clk2x
Data is launched at clk1x
rising edge with 1 cycle
latency from avid
Data is sampled at
clk2x rising edge
when phase 1x = 1
phase1x
clk1x
venc_dtv_avid
ygin/ubin/vrin
D
0
D
1
D
1
D
N-2
D
N-1
Active Video = DTV_AVID_H_STP-DTV_AVID_H_STA
venc_dtv_hs
Base V Counter
venc_dtv_fid
top field
DTV_VS_V_STP=12 (1/2H)
DTV_VS_V_STA=6 (1/2H)
DTV_AVID_V_STA0=34 (1/2H)
DTV_AVID_V_STP0=518 (1/2H)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
33
34
35
36
37
521 522 523 524
0V
Base FID
DTV_FID_V_STA0=14 (1/2H)
DTV_FID_F_STA0=0
venc_dtv_vs
517 518 519 520
515 516
venc_dtv_hs
Base V Counter
venc_dtv_fid
bottom field
DTV_VS_V_STP=12 (1/2H)
DTV_VS_V_STA=6 (1/2H)
DTV_AVID_V_STA1=33 (1/2H)
DTV_AVID_V_STP1=519 (1/2H)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
32
33
34
35
36
37
521 522 523 524
0V
Base FID
DTV_FID_V_STA1=12 (1/2H)
DTV_FID_F_STA1=1
venc_dtv_vs
517 518 519 520
515 516
venc_dtv_avid
venc_dtv_avid
Internal Modules
98
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Figure 1-44. Input I/F Vertical Timing
The VENC generates a venc_dtv_avid signal for data request purpose for the upstream module. Input
data is expected to arrive at the VENC one clk1x cycle (two clk2x cycles) after an avid assertion. The
supported input data format is RGB 4:4:4 or YCbCr 4:4:4. Input data is sampled at clk2x rising edge at
phase1x=1.
shows the timing chart of the input interface.
It is possible to sample the input data with an inversion. When the DIIV register is 1, the input data is
inverted before sampling.
Figure 1-45. Input Data Timing
