Texas Instruments DM38x DaVinci, User Manual

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Registers
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898 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.14.6 VIP_PARSER_fiq_mask Register (offset = 14h) [reset = 0h]
VIP_PARSER_fiq_mask is shown in Figure 1-568 and described in Table 1-486 .
Mask Bits for ARM FIQs. A 0 means the Host ARM will get an interrupt if the hardware sets one. A 1 in
the mask bitfield means that the hardware interrupt is masked and the ARM will not be interrupted.
Figure 1-568. VIP_PARSER_fiq_mask Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved PORT_B_CFG_DISA
BLE_COMPLETE_MA
SK
PORT_A_CFG_DISA
BLE_COMPLETE_MA
SK
PORT_B_ANC_PROT
OCOL_VIOLATION_
MASK
PORT_B_YUV_PROT
OCOL_VIOLATION_
MASK
PORT_A_ANC_PROT
OCOL_VIOLATION_
MASK
PORT_A_YUV_PROT
OCOL_VIOLATION_
MASK
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
PORT_B_SRC0_SIZE PORT_A_SRC0_SIZE PORT_B_DISCONN PORT_B_CONN PORT_A_DISCONN PORT_A_CONN OUTPUT_FIFO_PRT
B_ANC_OF
Reserved
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0h
7 6 5 4 3 2 1 0
OUTPUT_FIFO_PRT
B_YUV_OF
OUTPUT_FIFO_PRT
A_ANC_OF
Reserved OUTPUT_FIFO_PRT
A_YUV_OF
ASYNC_FIFO_PRTB_
OF
ASYNC_FIFO_PRTA_
OF
PRTB_VDET_MASK PRTA_VDET_MASK
R/W-0h R/W-0h R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-486. VIP_PARSER_fiq_mask Register Field Descriptions
Bit Field Type Reset Description
31-22 Reserved R 0h
21 PORT_B_CFG_DISABLE
_COMPLETE_MASK R/W 0h Port B Cfg Disable Complete Mask
20 PORT_A_CFG_DISABLE
_COMPLETE_MASK R/W 0h Port A Cfg Disable Complete Mask
19 PORT_B_ANC_PROTOC
OL_VIOLATION_MASK R/W 0h Port B ANC VPI Protocol Violation Mask
18 PORT_B_YUV_PROTOC
OL_VIOLATION_MASK R/W 0h Port B YUV VPI Protocol Violation Mask
17 PORT_A_ANC_PROTOC
OL_VIOLATION_MASK R/W 0h Port A ANC VPI Protocol Violation Mask
16 PORT_A_YUV_PROTOC
OL_VIOLATION_MASK R/W 0h Port A YUV VPI Protocol Violation Mask
15 PORT_B_SRC0_SIZE R/W 0h Video size detected on Port B does not match size programmed in
xtra_port_b register
14 PORT_A_SRC0_SIZE R/W 0h Video size detected on Port A does not match size programmed in
xtra_port_a register
13 PORT_B_DISCONN R/W 0h
Port B Link Disconnect Srcnum 0 Mask
12 PORT_B_CONN R/W 0h
Port B Link Connect Srcnum 0 Mask
11 PORT_A_DISCONN R/W 0h
Port A Link Disconnect Scrnum 0 Mask
10 PORT_A_CONN R/W 0h
Port A Link Connect Srcnum 0 Mask
9 OUTPUT_FIFO_PRTB_A
NC_OF R/W 0h
Output FIFO Port B Ancillary Overflow Mask
8 Reserved R 0h
7 OUTPUT_FIFO_PRTB_Y
UV_OF R/W 0h
Output FIFO Port B Luma Overflow Mask
6 OUTPUT_FIFO_PRTA_A
NC_OF R/W 0h
Output FIFO Port A Ancillary Overflow Mask