Texas Instruments DM38x DaVinci, User Manual

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Registers
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868 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.12.50 SD_VENC_dacsel Register (offset = 150h) [reset = 0h]
SD_VENC_dacsel is shown in Figure 1-545 and described in Table 1-461 .
DAC Output Signal Select
Figure 1-545. SD_VENC_dacsel Register
31 30 29 28 27 26 25 24
Reserved DA1E DA0E
R-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
DA1S DA0S
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-461. SD_VENC_dacsel Register Field Descriptions
Bit Field Type Reset Description
31-26 Reserved R 0h
25 DA1E R/W 0h
DAC1 enable
24 DA0E R/W 0h
DAC0 enable 0: DAC power down 1: DAC enable
23-8 Reserved R 0h
7-4 DA1S R/W 0h
DAC1 output select. See DAC0S.
3-0 DA0S R/W 0h
DAC0 output select. 0: CVBS 1: S-Video Y 2: S-Video; 3-15:
Reserved