Texas Instruments DM38x DaVinci, User Manual

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Registers
619 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.8.62 VPDMA_int2_channel4_int_mask Register (offset = 104h) [reset = 0h]
VPDMA_int2_channel4_int_mask is shown in Figure 1-362 and described in Table 1-274 .
Figure 1-362. VPDMA_int2_channel4_int_mask Register
31 30 29 28 27 26 25 24
INT_MASK_VIP2_MU
LT_ANCB_SRC3
INT_MASK_VIP2_MU
LT_ANCB_SRC2
INT_MASK_VIP2_MU
LT_ANCB_SRC1
INT_MASK_VIP2_MU
LT_ANCB_SRC0
INT_MASK_VIP2_MU
LT_ANCA_SRC15
INT_MASK_VIP2_MU
LT_ANCA_SRC14
INT_MASK_VIP2_MU
LT_ANCA_SRC13
INT_MASK_VIP2_MU
LT_ANCA_SRC12
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
INT_MASK_VIP2_MU
LT_ANCA_SRC11
INT_MASK_VIP2_MU
LT_ANCA_SRC10
INT_MASK_VIP2_MU
LT_ANCA_SRC9
INT_MASK_VIP2_MU
LT_ANCA_SRC8
INT_MASK_VIP2_MU
LT_ANCA_SRC7
INT_MASK_VIP2_MU
LT_ANCA_SRC6
INT_MASK_VIP2_MU
LT_ANCA_SRC5
INT_MASK_VIP2_MU
LT_ANCA_SRC4
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
INT_MASK_VIP2_MU
LT_ANCA_SRC3
INT_MASK_VIP2_MU
LT_ANCA_SRC2
INT_MASK_VIP2_MU
LT_ANCA_SRC1
INT_MASK_VIP2_MU
LT_ANCA_SRC0
INT_MASK_VIP2_MU
LT_PORTB_SRC15
INT_MASK_VIP2_MU
LT_PORTB_SRC14
INT_MASK_VIP2_MU
LT_PORTB_SRC13
INT_MASK_VIP2_MU
LT_PORTB_SRC12
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INT_MASK_VIP2_MU
LT_PORTB_SRC11
INT_MASK_VIP2_MU
LT_PORTB_SRC10
INT_MASK_VIP2_MU
LT_PORTB_SRC9
INT_MASK_VIP2_MU
LT_PORTB_SRC8
INT_MASK_VIP2_MU
LT_PORTB_SRC7
INT_MASK_VIP2_MU
LT_PORTB_SRC6
INT_MASK_VIP2_MU
LT_PORTB_SRC5
INT_MASK_VIP2_MU
LT_PORTB_SRC4
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-274. VPDMA_int2_channel4_int_mask Register Field Descriptions
Bit Field Type Reset Description
31 INT_MASK_VIP2_MULT_
ANCB_SRC3 R/W 0h
The interrupt for Video Input 2 Port B Ancillary Data Channel 3
should generate an interrupt on interrupt vpdma_int2. Write a 1 for
the interrupt event to trigger the interrupt signal.
30 INT_MASK_VIP2_MULT_
ANCB_SRC2 R/W 0h
The interrupt for Video Input 2 Port B Ancillary Data Channel 2
should generate an interrupt on interrupt vpdma_int2. Write a 1 for
the interrupt event to trigger the interrupt signal.
29 INT_MASK_VIP2_MULT_
ANCB_SRC1 R/W 0h
The interrupt for Video Input 2 Port B Ancillary Data Channel 1
should generate an interrupt on interrupt vpdma_int2. Write a 1 for
the interrupt event to trigger the interrupt signal.
28 INT_MASK_VIP2_MULT_
ANCB_SRC0 R/W 0h
The interrupt for Video Input 2 Port B Ancillary Data Channel 0
should generate an interrupt on interrupt vpdma_int2. Write a 1 for
the interrupt event to trigger the interrupt signal.
27 INT_MASK_VIP2_MULT_
ANCA_SRC15 R/W 0h
The interrupt for Video Input 2 Port A Ancillary Data Channel 15
should generate an interrupt on interrupt vpdma_int2. Write a 1 for
the interrupt event to trigger the interrupt signal.
26 INT_MASK_VIP2_MULT_
ANCA_SRC14 R/W 0h
The interrupt for Video Input 2 Port A Ancillary Data Channel 14
should generate an interrupt on interrupt vpdma_int2. Write a 1 for
the interrupt event to trigger the interrupt signal.
25 INT_MASK_VIP2_MULT_
ANCA_SRC13 R/W 0h
The interrupt for Video Input 2 Port A Ancillary Data Channel 13
should generate an interrupt on interrupt vpdma_int2. Write a 1 for
the interrupt event to trigger the interrupt signal.
24 INT_MASK_VIP2_MULT_
ANCA_SRC12 R/W 0h
The interrupt for Video Input 2 Port A Ancillary Data Channel 12
should generate an interrupt on interrupt vpdma_int2. Write a 1 for
the interrupt event to trigger the interrupt signal.
23 INT_MASK_VIP2_MULT_
ANCA_SRC11 R/W 0h
The interrupt for Video Input 2 Port A Ancillary Data Channel 11
should generate an interrupt on interrupt vpdma_int2. Write a 1 for
the interrupt event to trigger the interrupt signal.
22 INT_MASK_VIP2_MULT_
ANCA_SRC10 R/W 0h
The interrupt for Video Input 2 Port A Ancillary Data Channel 10
should generate an interrupt on interrupt vpdma_int2. Write a 1 for
the interrupt event to trigger the interrupt signal.
21 INT_MASK_VIP2_MULT_
ANCA_SRC9 R/W 0h
The interrupt for Video Input 2 Port A Ancillary Data Channel 9
should generate an interrupt on interrupt vpdma_int2. Write a 1 for
the interrupt event to trigger the interrupt signal.