Texas Instruments DM38x DaVinci, User Manual

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Registers
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580 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.8.50 VPDMA_int1_client1_int_mask Register (offset = D4h) [reset = 0h]
VPDMA_int1_client1_int_mask is shown in Figure 1-350 and described in Table 1-262 .
Figure 1-350. VPDMA_int1_client1_int_mask Register
31 30 29 28 27 26 25 24
Reserved INT_MASK_VIP2_AN
C_B
INT_MASK_VIP2_AN
C_A
INT_MASK_VIP1_AN
C_B
INT_MASK_VIP1_AN
C_A
INT_MASK_TRANS2_
LUMA
INT_MASK_TRANS2_
CHROMA
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
INT_MASK_TRANS1_
LUMA
INT_MASK_TRANS1_
CHROMA
INT_MASK_HDMI_W
RBK_OUT
INT_MASK_VPI_CTL INT_MASK_VBI_SDV
ENC
Reserved INT_MASK_NF_420_
UV_OUT
INT_MASK_NF_420_
Y_OUT
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
INT_MASK_NF_420_
UV_IN
INT_MASK_NF_420_
Y_IN
INT_MASK_NF_422_I
N
INT_MASK_GRPX3_
ST
INT_MASK_GRPX2_
ST
INT_MASK_GRPX1_
ST
INT_MASK_VIP2_UP
_UV
INT_MASK_VIP2_UP
_Y
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INT_MASK_VIP2_LO
_UV
INT_MASK_VIP2_LO
_Y
INT_MASK_VIP1_UP
_UV
INT_MASK_VIP1_UP
_Y
INT_MASK_VIP1_LO
_UV
INT_MASK_VIP1_LO
_Y
INT_MASK_GRPX3_
DATA
INT_MASK_GRPX2_
DATA
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-262. VPDMA_int1_client1_int_mask Register Field Descriptions
Bit Field Type Reset Description
31-30 Reserved R 0h
29 INT_MASK_VIP2_ANC_B R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.
28 INT_MASK_VIP2_ANC_A R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.
27 INT_MASK_VIP1_ANC_B R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.
26 INT_MASK_VIP1_ANC_A R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.
25 INT_MASK_TRANS2_LU
MA R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.
24 INT_MASK_TRANS2_CH
ROMA R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.
23 INT_MASK_TRANS1_LU
MA R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.
22 INT_MASK_TRANS1_CH
ROMA R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.
21 INT_MASK_HDMI_WRBK
_OUT R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.
20 INT_MASK_VPI_CTL R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.