Texas Instruments DM38x DaVinci, User Manual

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Internal Modules
235 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
– Bitmap-1 Offset4
– Bitmap-1 Offset5
– Bitmap-1 Offset6
– Bitmap-1 Offset7
• YUV Data Types:
– Y 4:4:4
– Y 4:2:2
– Y 4:2:0
– C 4:4:4
– C 4:2:2
– C 4:2:0
– YC 4:2:2
– YC4:4:4
– Cb 4:4:4
– Cb 4:2:2
– Cb 4:2:0
– CbY 4:2:2
– YC 4:2:2
– YCb 4:2:2
1.2.13.2 Memory Databus Write Order
The VPDMA L3 master port interfaces with the memory controller via a Quad Word (128 bit) data bus.
Words are placed in the Quad Word data bus in little endian order.
Table 1-72 shows the beginning or a
burst on the quad word data bus and the arrangement of each word address within the burst.
Table 1-72. Memory Databus Write Order
127 96 95 64 63 32 31 0
Quadword Addr 0 Word Addr 0x3 Word Addr 0x2 Word Addr 0x1 Word Addr 0x0
Quadword Addr 1 Word Addr 0x7 Word Addr 0x6 Word Addr 0x5 Word Addr 0x4
.....
.....
1.2.13.3 Descriptor
1.2.13.3.1 Data Transfer Descriptors
In order to set up data transfers from the VPDMA, a data transfer descriptor is added into a list. The fields
used for an Inbound and Outbound descriptor vary slightly. An outbound transfer can have two different
outbound transfers. The two transfers are the main data transfer and a write of an Inbound Descriptor. The
created inbound descriptor is formatted so it can be read back in directly to the next channel specified in
the original descriptor.