Texas Instruments DM38x DaVinci, User Manual

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G/Y[ :0] 9
B/Cb[ :0] 9
R/Cr[ :0] 9
ACT_VID
CLK1X
DA0 DA1 DA2 DA3 DAn
DB0
DC0 DC1 DC2 DC3 DCn
DB1 DB2
DB3
DBn
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Internal Modules
131 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
Figure 1-75 is the OSD-to-encoder data bus timing diagram. ACT_VID is the active video data
qualification signal. Encoder will capture data from OSD after one clock delay when the ACT_VID goes to
“high”.
The input 30-bit video data can also be in YCbCr 444 format. On chip processor will set the register bit
“Y_RGBn” in CFG0 register to select RGB or YCbCr color spaces.
Figure 1-75. Video Data Interface Between OSD and Encoder