DVO V Counter
top field
TVDETGP_V_STP=12 (1/2H)
TVDETGP_V_STA=6 (1/2H)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
523 524
0V
DVO FID
venc_tvdetgp
DVO V Counter
Bottom field
TVDETGP_V_STP=12 (1/2H)
TVDETGP_V_STA=6 (1/2H)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
523 524
0V
DVO FID
venc_tvdetgp
0
1715
0H
DVO H Counter
venc_tvdetgp
1
2
3
4
5
6
7
8
9
10
TVDETGP_H_STA=5
TVDETGP_H_STP=9
clk2x
DVO V Counter
Internal Modules
100
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.2.6.2.3.4 TV Detection Pulse Timing
The VENC supports a TVDET gate pulse generation to connect with the DAC which has the TV detect
feature. Its horizontal timing (see
) is configured by TVDETGP_H_STAand TVDETGP_H_STP
registers, and vertical timing (see
) is configured by TVDETGP_V_STA and TVDETGP_V_STP
registers.
Figure 1-48. TVDETGP Horizontal Timing
Figure 1-49. TVDETGP Vertical Timing
