EN logic
DLPA2005
VCORE
LS_OUT
VRST
VINC
VINL
VINR
DLPC150
VDD (252.9 mA)
VDDLP12
VCC_FLSH (1.0 mA)
VDD_PLL
VCC18 (12.62 mA)
VCC_INTF (1.5 mA)
RESETZ
P1P1V
TPS82671
(600 mA)
VOUT1
VIN
PROJ_ON
DLP2010NIR
VDDI (9.4mA)
VOFFSET (1.7 mA)
VDD (34.7mA)
VRESET (2 mA)
VBIAS (0.4 mA)
18V
-14V
P1P8V_SW
VINM
VINA
VBIAS
LS_IN
VOFS
VDD_PLLM (6 mA)
VDD_PLLD (6 mA)
PARKZ
RESETZ
INTZ
10V
P1P8V
TM4C129
VDD (117 mA)
VDDC
VDDA
VBAT
TPS63036
(500 mA)
VOUT1
VIN
EN
P3P3V
TPS81256
(400 mA)
VOUT1
VIN
EN
ADS1255
OPA2376
DVDD (2 mA)
AVDD (50 mA)
VCC (1 mA)
P5P0V
V-
REF5025
OPA350
VCC (8.5 mA)
VOUT1
VIN (1.2 mA)
V+
CC2564MODN
VDD_IO (1 mA)
VDD_IN (41.2 mA)
EN
BQ24250
BAT
IN
SYS
3.53 - 4.2V
VLED
SW4
LDO
TS
BAT
Conn
BAT +
TEMP
BAT -
STAT
VDPM
(4.36V)
ILM (1A)
150
ISET (1A)
249
1.5K
TPS386596
(Reset Sup)
RESETZ
RESETZ
VIN
SENSE1
SENSE2
SENSE4
MRZ
28.7K
10K
95.3K
10K
SENSE3
RESETZ
100K
2.5uF
Tiva
PJ7
EN = SYSPWR (~PROJ _ON + ~ INTz)
EN
logic
EN
logic
RESETz
INTz
SYSPWR
EN
PROJ_ON
TPS22904
VOUT1
VIN
EN
Tiva
PB2
P1P8V_BT
Emergency Shutdown Logic to allow
sufficient time for DLPA2005
to issue a Fast Park
PROJ_ON
Tiva PJ7
LS
char
ging
274k
107k
TPS81256
VOUT1
VIN
EN
PROJ_ON
PROJ_ON
LS
OPA567
VCC (300 mA)
V+
Tiva PD2
LS
EN
OUT
0.1
INA213
OUT
IN-
IN+
V-
V+
Power Management
Legend
DLP chipset
DLP
Analog
External Power Supply Requirements
•
The TPS81256 in the microcontroller board regulates the 5-V supply of the analog-to-digital converter
(ADS1255), transimpedance amplifiers circuits (OPA350 and OPA2276), and 2.5-V reference voltage
(REF5025) used in the detector board.
•
A second TPS81256 in the DLP controller board regulates the 5-V supply for the lamp driver (OPA567
and INA213). The lamp driver drives two parallel lamps at 5 V and 280 mA. Each lamp is rated to a
maximum 140 mA at 5 V.
•
The TPS386596 serves as reset supervisor to hold the system in reset whiles all the supplies reach
operational conditions. An external reset button issues a reset when the system has reached
operational conditions.
For detailed connections of these devices, refer to the DLP NIRscan Nano schematics.
Figure 4-1. DLP NIRscan Nano Power Block Diagram
shows the Tiva connections to the components on the microprocessor board and detector
board. The Tiva uses a 16-MHz external crystal as input to its on-board PLL to run the Tiva system at 120
MHz. A 32-kHz crystal supplies the clock to the Tiva's hibernation module and Bluetooth circuits. An
external 32MB of SDRAM stores the patterns that are streamed to the DLPC150 through the Tiva's LCD
interface. Tiva communicates to the HDC1000 and TMP006 sensors through its I2C6 and I2C7
peripherals. Both sensors generate a DRDY signal when a new value is available. This DRDY signals
interrupt Tiva when a new value is available through PP7 for HDC1000 and PP6 for TMP006. Tiva's
UART3 communicates with the CC2564MODN for Bluetooth transfers. The UART3 defaults to a 115200
baud transfer rate. Tiva's PH5 enables the Bluetooth circuits. Tiva interfaces to the microSD card through
32
DLP NIRscan Nano Hardware
DLPU030B – June 2015 – Revised July 2015
Copyright © 2015, Texas Instruments Incorporated