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EVM Operation

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3.3

The Output Operational Amplifier

The EVM includes an optional signal-conditioning circuit for the DAC output through an external
operational amplifier, U2. The output operational amplifier is set to unity gain configuration by default.
Nevertheless, the raw output of the DAC can be probed through the even pins of the output terminal, J4.

The inverting input of U2 can be tied to the gain resistor, R12 (via W15) or the DAC output (by shorting
pins 3 and 4 of the J3 header) or to any voltage source through J3-4.

The following sections describe the different configurations of the output amplifier, U2. This operational
amplifier can be used to serve as buffer to unload the DAC and also different signal conditioning and
amplification purposes desired.

This buffering circuit may present some slight distortion because of the feedback resistor and capacitor. If
this is the case, users can easily configure the feedback circuit to closely match the desired wave shape
by simply removing R6 and C12 and replacing it with the proper values. Additionally, C12 can be removed
altogether and R6 can be replaced with a 0-

Ω

resistor if desired.

3.3.1

Unity Gain Output

Table 2

shows the jumper setting for the unity gain configuration of the DAC output buffer in unipolar or

bipolar mode.

Table 2. Unity Gain Output Jumper Settings

Jumper Position

Reference

Unipolar

Bipolar

Function

J3

2-3

2-3

Routes the DAC output to the noninverting terminal of the output operational amplifier, U2.

W15

OPEN

OPEN

Disconnect the inverting input of the operational amplifier, U2, from gain resistor, R12.

W5

2-3

1-2

Negative rail of operational amplifier is tied to AGND or powered by V

SS

.

3.3.2

Output Gain of Two

Table 3

shows the proper jumper settings of the EVM for the 2× gain output of the DAC.

Table 3. Gain of Two Output Jumper Settings

Jumper Position

Reference

Unipolar

Bipolar

Function

J3

2-3

2-3

Routes the DAC output to the noninverting terminal of the operational amplifier, U2.

W15

CLOSED

CLOSED

Inverting input of the output operational amplifier, U2, is connected to gain resistor, R12, to
set for a gain of 2.

W5

2-3

1-2

Supplies power, V

SS

, to the negative rail of operational amplifier, U2, for bipolar supply mode

or ties it to AGND for unipolar supply mode.

3.3.3

Output Gain of Five With DAC V

OUT

Inverted

Table 4

shows the proper jumper settings of the EVM to achieve a gain of five with the output of the DAC

inverted.

Table 4. Jumper Settings for a Gain of Five With Inverted Output

Jumper Position

Reference

Unipolar

Bipolar

Function

J3

1-2 & 3-4

1-2 & 3-4

Output of DAC is inverted with a gain of five. Watch for clipping due to operational amplifier
headroom issue.

W15

OPEN

OPEN

Disconnect the inverting input of operational amplifier, U2, from the gain resistor, R12.

W5

2-3

1-2

Supplies power, V

SS

, to the negative rail of operational amplifier, U2, for bipolar supply

mode, or ties it to AGND for unipolar supply mode.

10

DAC8580/81 Evaluation Module

SLAU173A – December 2005 – Revised November 2009

Submit Documentation Feedback

Copyright © 2005–2009, Texas Instruments Incorporated

Summary of Contents for DAC8580

Page 1: ...t for the DAC8581 7 9 DNL Characteristic Plot for the DAC8581 7 10 DAC8580EVM Default Jumper Setting 9 11 DAC8581EVM Default Jumper Setting 9 12 DAC Output Waveform 11 13 MMB0 with DAC8581EVM Installed 14 14 Loading a DAC8581EVM Configuration 15 15 DAC8581EVM Frequency Amplitude and Update Rate Adjustments 16 16 DAC Output Update Options 17 List of Tables 1 DAC8580 81EVM Factory Default Jumper Set...

Page 2: ...om 4 5 V minimum to 18 V maximum and connect through the J1 1 and J1 3 terminals respectively if installed or through the J6 1 and J6 2 terminals All of the analog power supplies are referenced to analog ground through the J1 2 and J6 6 terminals The VCC supply sources the positive rail of the external output operational amplifier U2 as well as the REF02 reference source U3 and the buffer operatio...

Page 3: ...istic Figure 1 shows a block diagram of the DAC8580 81EVM Figure 1 DAC8580 81EVM Block Diagram 2 PCB Design and Performance This section discusses the layout design of the PCB describing the physical and mechanical characteristics of the EVM It shows the resulting performance of the EVM which can be compared to the device specification listed in the data sheet The list of components used on the mo...

Page 4: ...he digital traces in the digital section Minimize the length of the traces but use the biggest possible trace width allowable in the design These design practices can be seen in Figure 2 through Figure 7 The DAC8580 81EVM board is constructed on a four layer printed circuit board PCB using a copper clad FR 4 laminate material The PCB has a dimension of 43 1800 mm 1 7000 inch 82 5500 mm 3 2000 inch...

Page 5: ...Performance Figure 4 Layer 2 Ground Plane Figure 5 Layer 3 Power Plane 5 SLAU173A December 2005 Revised November 2009 DAC8580 81 Evaluation Module Submit Documentation Feedback Copyright 2005 2009 Texas Instruments Incorporated ...

Page 6: ...ester and tested using the Teradyne A580 connected to a personal computer The EVM board is tested for all codes of the device under test DUT and is allowed to settle before the measurement is recorded This process is repeated for all codes to generate the measurements for INL and DNL results 6 DAC8580 81 Evaluation Module SLAU173A December 2005 Revised November 2009 Submit Documentation Feedback C...

Page 7: ...st are shown in Figure 8 and Figure 9 Figure 8 INL Characteristic Plot for the DAC8581 Figure 9 DNL Characteristic Plot for the DAC8581 7 SLAU173A December 2005 Revised November 2009 DAC8580 81 Evaluation Module Submit Documentation Feedback Copyright 2005 2009 Texas Instruments Incorporated ...

Page 8: ...2x oversampling rate This is hardwired to DGND for the DAC8580 81EVM W8 CLOSE OSR2 is tied low configured for 2x oversampling rate This is hardwired to DGND for the DAC8580 81EVM W9 CLOSE RSTB is tied low so the DAC is configured for conventional operation Digital filter is disconnected This is hardwired to DGND for the DAC8580 81EVM W10 CLOSE BPB is tied low so the DAC is configured for conventio...

Page 9: ...serial data input The output can be monitored through the J4 header connector A TI Interface Board is also available for a specific TI DSP Starter Kit as well as an MSP430 based microprocessor as mentioned in Section 1 of this manual Using the interface board foregoes the task of building customized cables and allows easy configuration of a simple evaluation system This DAC EVM interfaces with any...

Page 10: ...ninverting terminal of the output operational amplifier U2 W15 OPEN OPEN Disconnect the inverting input of the operational amplifier U2 from gain resistor R12 W5 2 3 1 2 Negative rail of operational amplifier is tied to AGND or powered by VSS 3 3 2 Output Gain of Two Table 3 shows the proper jumper settings of the EVM for the 2 gain output of the DAC Table 3 Gain of Two Output Jumper Settings Jump...

Page 11: ...W1 Routes the 5 V power supply to DAC DVDD pin Disconnect the power supply to DAC DVDD pin Routes the 3 3 V power supply to DAC DVDD pin W4 Routes the onboard reference to the VREF pin of the DAC Disconnect the onboard reference supply to the VREF pin of the DAC Routes the user supplied external reference via TP1 to the VREF pin of the DAC W5 Negative supply rail of the output operational amplifie...

Page 12: ...or the DAC8581EVM Connect the BPB input pin of the DAC to ground This is hardwired to ground for the DAC8581EVM W14 The FSYNC pin of the DAC is driven by CS pin from J2 1 terminal The FSYNC pin of the DAC is driven by FSX pin from J2 7 terminal W15 Disconnect the inverting input pin of operational amplifier U2 from the gain resistor R12 Connect the inverting input pin of operational amplifier U2 t...

Page 13: ...MB0 modular motherboard The kit includes the DXP software for evaluation using any available USB port on a Microsoft Windows XP based computer DXP is a program that controls the digital input signals such as the clock CS and SDI Wave tables are built into the DSP software to allow sine ramp triangle and square wave signals to be generated by the DAC8581 Straight dc outputs can also be obtained The...

Page 14: ...closed before connecting the ac dc adapter to the DC In connector of the MMB0 This supply provides all power to the digital portion of the DAC8581EVM as well as all necessary power for the DSP Clean well regulated analog power for the DAC8581EVM should be supplied externally via J14 a six position screw terminal mounted in the lower left corner of the MMB0 board CAUTION When using external power s...

Page 15: ... DXP on a laptop or personal computer running Windows XP according to the detailed instruction in the DXP Users Guide TI document SBAU146 Run the DXP program by clicking on the DXP icon on your desktop or by browsing to your installation directory Before you can generate signals with DXP a DAC EVM configuration file must be loaded To load a configuration file select the desired DAC from the config...

Page 16: ...litude and Update Rate Adjustments Table 6 DAC8581EVM GPIO Options Function Detailed Description The MUTEB button controls the CLR pin of the DAC8581 By default the button is active causing CLR to be high and in normal operating mode Pressing the button places logic low on pin J2 14 of the DAC8581EVM When the CLR pin is low the MUTEB device is in clear mode The output displays 0V and does not upda...

Page 17: ...yer Ceramic Chip Capacitor 1206 TDK C3216COG2J102KT SMD 630V 0 30ppm ºC TC 10 Tol 5 7 2 1 0 1 TH W7 W8 W9 Modified 0 025 Square Post Header Samtec MTSW 102 08 T S 295 W10 W15 W16 W17 6 4 3 1 0 1 TH W1 W4 W5 Modified 0 025 Square Post Header Samtec MTSW 103 08 T S 295 W14 7 1 5 2 0 1 SMT P6 10 PIN Socket Strip 1 Samtec SSW 105 22 F D VS K 8 8 10 kΩ R1 R2 R3 R4 1 8W 1206 Thick Film Chip Resistor 1 P...

Page 18: ...et Bourns 3214W 203E 17 1 16 Bit DAC U1 High speed Low noise Voltage Output Texas DAC8580IPW DAC 1 Instruments DAC858IPW 18 2 3 1 0 138 TH J1 J5 3 Pin Terminal Block 1 On Shore Tech ED555 3DS 19 1 Difet Op Amp U2 8 SOP D Precision High speed Operational Texas OPA627AU Amplifier Instruments 20 1 5V Voltage U3 Precision Voltage Reference Texas REF02AU Reference Instruments 21 4 1 1 0 061D TH TP1 TP2...

Page 19: ...6 V Precision Voltage Texas REF3040AIDBZT Reference Reference 50ppm C 2 Instrument 27 10 To be determined C8 C13 C16 DO NOT INSTALL R18 R19 R20 R21 R22 R23 R24 28 7 Test point pins TP6 TP7 DO NOT INSTALL TP14 TP15 TP16 TP17 TP18 2 U4 is optional U4 can be substituted for U3 for external reference source 19 SLAU173A December 2005 Revised November 2009 DAC8580 81 Evaluation Module Submit Documentati...

Page 20: ... 1µF TP3 U2_ IN U2_ IN U2_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 17 19 18 J2 Serial Header TP4 AVDD 5V Analog DVDD 2 7V to 5 0V Digital AVSS 5V Analog 1 2 3 J1 1 2 3 J5 5VA VCC 1 2 3 4 5 6 7 8 9 10 J6 VSS 5VA 5VA 5VD 3 3VD 1 8VD 3 3VA GPIO0 GPIO1 SCL SDA R25 0 R26 0 GPIO2 GPIO3 GPIO0 GPIO1 GPIO2 GPIO3 R27 0 R28 0 GPIO4 GPIO5 GPIO4 GPIO5 R31 0 R32 0 R33 0 R38 0 R39 0 W1 3 3VD DVDD 6464408 R1...

Page 21: ...duct This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engineer or visit www ti com esh No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine process or combination in which such TI products o...

Page 22: ...ice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertis...

Page 23: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments DAC8581EVM ...

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