Texas Instruments DAC7731 User Manual Download Page 16 | Manualshive

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PCB Layout

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Figure 2 - 4. Layer 3 (Power Plane)

Figure 2 - 5. Layer 4 (Bottom Signal Plane)

Figure 2 - 6. Bottom Silkscreen

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Summary of Contents for DAC7731

Page 1: ...DAC7731 Evaluation Module March 2003 DAP EVMs User s Guide SLAU099 ...

Page 2: ...nt that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or end...

Page 3: ... handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR A...

Page 4: ...to the EVM Please consult the EVM User s Guide prior to connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 60 C The EVM is designed to operate properly with certain components above 60 C as long as the input and output ranges are m...

Page 5: ... This document contains the following chapters Chapter 1 EVM Overview Chapter 2 PCB Design and Performance Chapter 3 EVM Operation Information About Cautions and Warnings This book may contain cautions and warnings This is an example of a caution statement A caution statement describes a situation that could potentially damage your software or equipment This is an example of a warning statement A ...

Page 6: ... the Data Converter Application Team at dataconvapps list ti com Include in the subject heading the product you have questions or concerns with FCC Warning This equipment is intended for use in a laboratory test environment only It generates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FC...

Page 7: ...EVM Basic Functions 1 3 2 PCB Design and Performance 2 1 2 1 PCB Layout 2 2 2 2 EVM Performance 2 6 2 3 Bill of Materials 2 8 3 EVM Operation 3 1 3 1 Factory Default Settings 3 2 3 2 Host Processor Operation 3 3 3 2 1 Unity Gain Output 3 3 3 2 2 Output Gain of Two 3 4 3 2 3 Capacitive Load Drive 3 4 3 3 Jumper Setting 3 5 3 4 Schematic 3 6 ...

Page 8: ...Signal Plane 2 4 2 6 Bottom Silkscreen 2 4 2 7 Drill Drawing 2 5 2 8 DAC7731EVM Test Parameters 2 6 2 9 INL and DNL Characterization Graphs 2 7 Tables 2 1 Parts Lists 2 8 3 1 Factory Default Jumper Setting 3 2 3 2 Unity Gain Output Jumper Settings 3 3 3 3 Gain of Two Output Jumper Settings 3 4 3 4 Capacitive Load Drive Output Jumper Settings 3 4 3 5 Jumper Setting Functions 3 5 ...

Page 9: ...pter gives a general overview of the DAC7731 evaluation module EVM and describes some of the factors that must be considered when using the module Topic Page 1 1 Features 1 2 1 2 Power Requirements 1 2 1 3 EVM Basic Functions 1 3 Chapter 1 ...

Page 10: ...rovide the positive rail of the external output op amp while the negative rail can be selected between VSS and AGND via the W5 jumper The external op amp is installed as an option to provide output signal conditioning or boost capacitive load drive and for other output mode requirements To avoid potential damage to the EVM board make sure that the correct cables are connected to their respective t...

Page 11: ...ristics of the DAC7731 digital to analog converter Functional evaluation of the DAC device can be accomplished with the use of any microprocessor TI DSP with SPI capability or some sort of a waveform generator The headers J2 and P2 are the connectors provided which allow control signals and data required to interface a host processor or a waveform generator using a customized cable A specific adap...

Page 12: ...header to route the DAC output of each respective EVM so that the output signal does not stack up on top of the other Of course it is also possible to stack more than three EVMs as long as the W13 is left open and the output signal is monitored through this same header in each respective EVM A block diagram of the EVM is shown in Figure 1 1 Figure 1 1 EVM Block Diagram DAC Module J4 Output Buffer ...

Page 13: ...s of the EVM is presented in this chapter This section also shows the resulting performance of the EVM which can be compared to the device specification listed in the data sheet The list of components used on the module is also included in this section Topic Page 2 1 PCB Layout 2 2 2 2 EVM Performance 2 6 2 3 Bill of Materials 2 8 Chapter 2 ...

Page 14: ...ane is very important and are carefully considered in the layout process A solid plane is ideally preferred but sometimes impractical so when solid planes are not possible a split plane does the job as well When considering a split plane design analyze the component placement and carefully split the board into its analog and digital sections starting from the device under test The ground plane pla...

Page 15: ...PCB Layout 2 3 PCB Design and Performance Figure 2 1 Top Silkscreen Figure 2 2 Layer 1 Top Signal Plane Figure 2 3 Layer 2 Ground Plane ...

Page 16: ...PCB Layout 2 4 Figure 2 4 Layer 3 Power Plane Figure 2 5 Layer 4 Bottom Signal Plane Figure 2 6 Bottom Silkscreen ...

Page 17: ... the finished board 3 Laminate material Copper clad FR 4 4 Copper weight 1 oz finished 5 Finished thickness 0 062 0 010 6 MIN plating thickness in through holes 0 001 7 SMCBC HASL 8 LPI soldermask both sides using appropriate layer artwork color green 9 LPI silkscreen as required color white 10 Vender information to be incorporated on back side whenever possible 11 Minimum copper conductor width i...

Page 18: ...oftware The EVM board is tested for all codes of 65535 and the device under test DUT is allowed to settle for 1ms before the meter is read This process is repeated for all codes to generate the INL and DNL results and is shown in Figure 2 9 The parameters and results of the DAC7731 EVM characterization test can be seen in Figure 2 8 and Figure 2 9 Figure 2 8 DAC7731EVM Test Parameters ...

Page 19: ...EVM Performance 2 7 PCB Design and Performance Figure 2 9 INL and DNL Characterization Graphs ...

Page 20: ... 1 20 Pin 025 sq SMT socket 14 2 J1 J3 On Shore Technology ED555 3DS 3 Pin terminal connector 15 1 U1 Texas Instruments DAC7731 16 bit voltage output serial input DAC SSOP 24 16 1 U2 Texas Instruments OPA627AU 8 SOP D precision op amp 17 1 U3 Texas Instruments REF102AU 10 V 8 SOP D precision voltage reference 18 4 TP1 TP2 TP3 TP4 Mill max 2348 2 01 00 00 07 0 Turret terminal test point 19 1 W13 Sa...

Page 21: ... interface the EVM to a specific host processor Refer to the DAC7731 data sheet SBAS249 for information about its serial interface and other related topics The EVM board is factory tested and configured to operate in the bipolar output mode Topic Page 3 1 Factory Default Settings 3 2 3 2 Host Processor Operation 3 3 3 3 Jumper Setting 3 5 3 6 Schematics 3 7 Chapter 3 ...

Page 22: ...ternal voltage reference W4 OPEN Onboard external reference through U3 is disconnected W5 1 2 Negative supply rail of U2 op amp is supplied with 15 V W6 OPEN REFADJ pin is floated W7 CLOSE RFB2 pin is strapped to VOUT pin for DAC output feedback W8 CLOSE TEST pin is tied to DGND W9 OPEN SJ pin is floated W10 OPEN RFB1 is floated W13 3 4 Buffered output of DAC is channeled through to J4 6 W14 OPEN ...

Page 23: ...nterface card or the MSP430 motherboard But it is also used to monitor the different output configuration of the DAC through U2 easily by shorting the respective pins of W13 In addition it provides easy access for monitoring up to three DAC7731 EVMs in daisy chain or cascading fashion with the option of using U2 for each of the EVMs stacked together The following sections describe the different co...

Page 24: ...on option is to drive a wide range of capacitive load requirement However all op amps under certain conditions can become unstable depending on the op amp configuration gain and load value These are just a few factors that can affect op amps stability performance and should be considered when implementing In unity gain the OPA627 op amp U2 performs very well with very large capacitive loads Increa...

Page 25: ...ed reference to supply the DAC reference voltage 1 3 Routes the onboard 10 V reference through the adjustable pot to W3 W4 1 3 Routes the user supplied reference from TP1 or J4 20 through the adjustable pot to W3 1 3 Negative supply rail of op amp is powered by VSS for bipolar operation W5 1 3 Negative supply rail of op amp is tied to AGND for unipolar operation REFadj pin is not connected W6 REFa...

Page 26: ...SEL pin is pulled high and configures the DAC to mid scale when POR or reset is initiated W16 RSTSEL pin is pulled low and configures the DAC to min scale when POR or reset is initiated For use with DSP starter kit Disconnects the FSX line from the FSR line Default mode W17 For use with DSP starter kit Loops the FSX line back to the FSR line For use with DSP starter kit Disconnects the DX line fro...

Page 27: ...in RSTSEL RST LDAC CS 1 2 3 4 5 6 7 8 9 10 J6 C6 10µF C4 10µF C5 10µF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 J2 DAC7731 A 1 J PARGUIAN W2 W1 VSS W7 W10 R3 100K C8 1µF R1 10K R2 10K R7 0 5K 20K VDD W3 R4 10K W8 DAC_VOUT Sum_Junc Sum_Junc exREFin VSS VSS REFin REFin W6 W9 Tantalum REF_en REF_en 1 C13 0 1µF C14 10µF SDO 19 SCLK 21 SDI 18 VDD 12 REFin 3 REFout 2 Vref 5 DGND 13 CS 20 LDAC 1...

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