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DAC5668/88/89EVM Initial Power Up and Test
5.1.3
CDCM7005 Specific Controls
Tab Control (PLL, Output, Advanced):
Switches between the different CDCM7005 registers.
CDCM7005 Operation:
Select Buffer Mode when no VCXO is installed or the VCXO is disabled. In this case, the CDCM7005
operates as a buffer. Select PLL Mode when a VCXO is being used by the CDCM7005.
Send All:
Sends the current front panel registers to the device. This is generally only used when the EVM power
has recycled, or the device has been reset and the user wants to load the displayed settings to the
device.
6
DAC5668/88/89EVM Initial Power Up and Test
The steps described in this section show how to connect and configure the DAC5668/88/89EVM for
evaluation under the default settings.
1. Connect the DAC5668/88/89EVM digital connector (J2 and J7) to a digital test pattern generator
capable of providing 3.3-V or 1.8-V CMOS logic level inputs such as Texas Instruments TSW3100.
2. Use the DAC5668/88/89 EVM DAC_CLKOUT (J21) SMA connector to trigger the pattern generator. In
the case of the TSW3100 pattern generator, the trigger input is CMOS CLK (J73) SMA connector.
3. Connect the 1.8-V (J13/J14), 3.3-V (J15/J16) and 5-V (J10/J11) power supplies. Ensure that each
supply is not drawing more than 1 A of current. Turn on the power supplies. Press SW1 to reset the
board.
4. Provide a single-ended, 1-Vrms, 0-V, offset sine-wave signal to the DAC5668/88/89 EXT_VCXO (J20)
SMA connector. LED D3 should illuminate indicating that a signal has been detected. If not, verify that
the correct signal is being provided.
5. Connect a 0-dBm LO signal to the RF_LO_IN (J23) SMA connector.
6. Connect one end of the supplied USB cable to an available USB port on the host PC. Connect the
other end of the cable to J1 on the DAC5668/88/89EVM.
13
SLAU241A – June 2008 – Revised March 2010
DAC5668/88/89EVM
Copyright © 2008–2010, Texas Instruments Incorporated
