DAC31x2
J13
J12
J10
J11
J9
J13
J9
TSW3100
Ethernet
PC
+5 V
+5 V/GND
PSA
LO Source
CLK Source
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Testing and Configuration
2
Testing and Configuration
This section outlines the basic procedure for testing the DAC31x2EVM.
2.1
Test Set-Up
Figure 2
illustrates the test configuration for general testing of the DAC31x2 with the TSW3100 pattern
generation card.
Figure 2. DAC31x2EVM Test Setup
2.2
Test Set-Up Connections
Follow these procedures to properly connect the DAC31x2EVM and the TSW3100 pattern generator.
TSW3100 Pattern Generator:
•
Connect a 5-V power supply to J9, the 5V_IN jack of the TSW3100EVM.
•
Connect the PC Ethernet port to J13, the Ethernet port of the TSW3100. The cable should be a
standard crossover Cat5e Ethernet cable.
DAC31x2EVM:
•
Connect the J5 connector of DAC31x2EVM to connector J74 of the TSW3100EVM.
•
Connect 5 V and Ground to connectors J12 and J13 respectively.
•
Provide a 0.5-V
RMS
, 500-MHz (max) clock at J9, the CLOCK IN SMA port of the DAC31x2EVM.
•
Provide a 7-dBm, 350-MHz to 4-GHz local oscillator (LO) source at port J10 of the DAC31x2EVM. This
input provides the LO source to the TRF3703-33 modulators.
•
Connect the RF output port of (J11) to the spectrum analyzer.
DAC31x2EVM Jumpers:
Power distribution to the DAC31x2 and CDCP1803 devices on the EVM can be achieved through
low-dropout regulators (LDOs) or dc-dc converters. Jumpers JP24, JP25, JP26, and JP27 allow the
user to choose one of the power schemes from these two available options. The default setting of
these jumpers is shown; these settings use power management for the ICs through dc-dc switchers.
•
JP24 on pin {1,2}
•
JP25 on pin {1,2}
•
JP26 on pin {1,2}
•
JP27 on pin {1,2}
Jumper JP4 supplies power to the TRF3703-33 modulator. This jumper must be installed in order to use
the modulator.
3
SBOU096A – November 2010 – Revised January 2011
DAC31x2EVM
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