Texas Instruments Concerto F28M36 Series, Technical Reference Manual

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ARM Cortex M3
Access
Media
Controller
Physical
MAC
(Layer 2)
PHY
(Layer 1)
RJ45
Magnetics
Layer
Entity
Microcontroller
Introduction
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1418 SPRUHE8E – October 2012 – Revised November 2019
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M3 Ethernet Media Access Controller (EMAC)
19.1 Introduction
The EMAC module has the following features:
• Conforms to the IEEE 802.3-2002 specification
– 10BASE-T/100BASE-TX IEEE-802.3 compliant.
• Multiple operational modes
– Full- and half-duplex 100 Mbps
– Full- and half-duplex 10 Mbps
– Power-saving and power-down modes
• Highly configurable
– Programmable MAC address
– Promiscuous mode support
– CRC error-rejection control
– User-configurable interrupts
• IEEE 1588 Precision Time Protocol: Provides highly accurate time stamps for individual packets
• Efficient transfers using the Micro Direct Memory Access Controller ( μ DMA)
– Separate channels for transmit and receive
– Receive channel request asserted on packet receipt
– Transmit channel request asserted on empty transmit FIFO
19.2 EMAC Block Diagram
As shown in Figure 19-1 , the MAC layer corresponds to the OSI model layer 2. The MAC layer provides
transmit and receive processing for Ethernet frames. It also provides the interface to the physical layer
(PHY) via an internal media independent interface (MII). The PHY layer communicates with the Ethernet
bus.
Figure 19-1. Ethernet MAC
Figure 19-2 shows more detail of the internal structure of the EMAC and how the register set relates to
various functions.