Clock Control
139
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
System Control and Interrupts
Table 1-18. TIMERxTIMH Register Field Descriptions
Bits
Field
Description
15-0
TIMH
See description for TIMERxTIM.
Figure 1-18. TIMERxPRD Register (x = 0, 1, 2)
15
0
PRD
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 1-19. TIMERxPRD Register Field Descriptions
Bits
Field
Description
15-0
PRD
CPU-Timer Period Registers (PRDH:PRD): The PRD register holds the low 16 bits of the 32-bit period. The
PRDH register holds the high 16 bits of the 32-bit period. When the TIMH:TIM decrements to zero, the
TIMH:TIM register is reloaded with the period value contained in the PRDH:PRD registers, at the start of
the next timer input clock cycle (the output of the prescaler). The PRDH:PRD contents are also loaded into
the TIMH:TIM when you set the timer reload bit (TRB) in the Timer Control Register (TCR).
Figure 1-19. TIMERxPRDH Register (x = 0, 1, 2)
15
0
PRDH
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 1-20. TIMERxPRDH Register Field Descriptions
Bits
Field
Description
15-0
PRDH
See description for TIMERxPRD
Figure 1-20. TIMERxTCR Register (x = 0, 1, 2)
15
14
13
12
11
10
9
8
TIF
TIE
Reserved
FREE
SOFT
Reserved
R/W-0
R/W-0
R-0
R/W-0
R/W-0
R-0
7
6
5
4
3
0
Reserved
TRB
TSS
Reserved
R-0
R/W-0
R/W-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 1-21. TIMERxTCR Register Field Descriptions
Bits
Field
Value
Description
15
TIF
CPU-Timer Interrupt Flag
TIF indicates whether a timer overflow has happened since TIF was last cleared. TIF is
not cleared automatically and does not need to be cleared to enable the next timer
interrupt.
0
The CPU-Timer has not decremented to zero.
Writes of 0 are ignored.
1
This flag gets set when the CPU-timer decrements to zero.
Writing a 1 to this bit clears the flag.
