Register Descriptions
1373
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
M3 Universal Serial Bus (USB) Controller
18.5.30 USB Control and Status Endpoint 0 High Register (USBCSRH0), offset 0x103
The USB control and status endpoint 0 high 8-bit register (USBCSRH0) provides control and status bits
for endpoint 0.
Mode(s):
OTG A or Host
OTG B or Device
USBCSRH0 in OTG A/Host mode is shown in
and described in
Figure 18-36. USB Control and Status Endpoint 0 High Register (USBCSRH0) in OTG A/Host Mode
7
3
2
1
0
Reserved
DTWE
DT
FLUSH
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 18-39. USB Control and Status Endpoint 0 High Register (USBCSRH0) in OTG A/Host Mode
Field Descriptions
Bit
Field
Value
Description
7-3
Reserved
0
Reserved
2
DTWE
Data Toggle Write Enable. This bit is automatically cleared once the new value is written.
0
The DT bit cannot be written.
1
Enables the current state of the endpoint 0 data toggle to be written (see DT bit).
1
DT
Data Toggle. When read, this bit indicates the current state of the endpoint 0 data toggle.
If DTWE is set, this bit may be written with the required setting of the data toggle. If DTWE is Low, this
bit cannot be written. Care should be taken when writing to this bit as it should only be changed to
RESET USB endpoint 0.
0
FLUSH
Flush FIFO. This bit is automatically cleared after the flush is performed.
0
No effect
1
Flushes the next packet to be transmitted/read from the endpoint 0 FIFO. The FIFO pointer is reset and
the TXRDY/RXRDY bit is cleared.
Note:
This bit should only be set when TXRDY/RXRDY is set. At other times, it may cause data to be
corrupted.
USBCSRH0 in OTG B/Device mode is shown in
and described in
Figure 18-37. USB Control and Status Endpoint 0 High Register (USBCSRH0) in OTG B/Device
Mode
7
1
0
Reserved
FLUSH
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 18-40. USB Control and Status Endpoint 0 High Register (USBCSRH0) in OTG B/Device Mode
Field Descriptions
Bit
Field
Value
Description
7-1
Reserved
0
Reserved
0
FLUSH
Flush FIFO. This bit is automatically cleared after the flush is performed.
0
No effect
1
Flushes the next packet to be transmitted/read from the endpoint 0 FIFO. The FIFO pointer is reset and
the TXRDY/RXRDY bit is cleared.
Note:
This bit should only be set when TXRDY/RXRDY is set. At other times, it may cause data to be
corrupted.