Overview
1186
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
M3 Micro Direct Memory Access ( µDMA)
16.1 Overview
The µDMA controller provides the following features:
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ARM PrimeCell® 32-channel configurable µDMA controller
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Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer
modes
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Basic for simple transfer scenarios
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Ping-pong for continuous data flow
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Scatter-gather for a programmable list of arbitrary transfers initiated from a single request
•
Highly flexible and configurable channel operation
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Independently configured and operated channels
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Dedicated channels for supported on-chip modules
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Primary and secondary channel assignments
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One channel each for receive and transmit path for bidirectional modules
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Dedicated channel for software-initiated transfers
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Per-channel configurable bus arbitration scheme
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Optional software-initiated requests for any channel
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Two levels of priority
•
Design optimizations for improved bus access performance between µDMA controller and the
processor core
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µDMA controller access is subordinate to core access
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RAM striping
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Peripheral bus segmentation
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Data sizes of 8, 16, and 32 bits
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Transfer size is programmable in binary steps from 1 to 1024
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Source and destination address increment size of byte, half-word, word, or no increment
•
Maskable peripheral requests
16.2 Block Diagram
illustrates the µDMA block diagram.
