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For 2-bit delay:
Next frame-synchronization
pulse here or later is OK.

For 1-bit delay:
Next frame-synchronization
pulse here or later is OK.

For 0-bit delay:
Next frame-synchronization
pulse here or later is OK.

CLKR/CLKX

FSR/FSX

DR/DX

Last bit of
current frame

Earliest possible
time to begin transfer
of next frame

Multichannel Selection Modes

1101

SPRUHE8E – October 2012 – Revised November 2019

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Copyright © 2012–2019, Texas Instruments Incorporated

C28 Multichannel Buffered Serial Port (McBSP)

Figure 15-31. Proper Positioning of Frame-Synchronization Pulses

15.6 Multichannel Selection Modes

This section discusses the multichannel selection modes for the McBSP.

15.6.1 Channels, Blocks, and Partitions

A McBSP channel is a time slot for shifting in/out the bits of one serial word. Each McBSP supports up to
128 channels for reception and 128 channels for transmission.

In the receiver and in the transmitter, the 128 available channels are divided into eight blocks that each
contain 16 contiguous channels (see

through

) :

•

It is possible to have two receive partitions (A & B) and 8 transmit partitions (A – H).

•

McBSP can transmit/receive on selected channels.

•

Each channel partition has a dedicated channel-enable register. Each bit controls whether data flow is
allowed or prevented in one of the channels assigned to that partition.

•

There are three transmit multichannel modes and one receive multichannel mode.

Table 15-8. Block - Channel Assignment

Block

Channels

0

0 -15

1

16 - 31

2

32 - 47

3

48 - 63

4

64 - 79

5

80 - 95

6

96 - 111

7

112 - 127

«
...
1099
1100
1101
1102
1103
...
»

Summary of Contents for Concerto F28M36 Series

Page 1: ...Concerto F28M36x Technical Reference Manual Literature Number SPRUHE8E October 2012 Revised November 2019...

Page 2: ...dling 117 1 5 6 Control Subsystem NMI CNMI Module 117 1 6 Safety Features 120 1 6 1 Write Protection on Registers 120 1 6 2 Missing Clock Detection Logic 121 1 6 3 PLLSLIP Detection 124 1 6 4 Control...

Page 3: ...odule CSM Registers 255 1 13 9 Control Subsystem Code Security Module CSM Registers 271 1 13 10 CRC Register Description 275 1 13 11 Master Subsystem IPC Registers 277 1 13 12 Control Subsystem IPC Re...

Page 4: ...Masked Interrupt Status WDTMIS Register offset 0x014 337 3 3 7 Watchdog Test WDTTEST Register offset 0x418 338 3 3 8 Watchdog Lock WDTLOCK Register offset 0xC00 338 3 3 9 Watchdog Peripheral Identific...

Page 5: ...ntrol Registers 549 5 4 Flash Registers 550 5 4 1 Master Subsystem Flash Control Registers 554 5 4 2 Master Subsystem Flash ECC Error Log Registers 560 5 4 3 Control Subsystem Flash Control Registers...

Page 6: ...n Qualifier AQ Submodule 697 7 2 5 Dead Band Generator DB Submodule 713 7 2 6 PWM Chopper PC Submodule 720 7 2 7 Trip Zone TZ Submodule 724 7 2 8 Event Trigger ET Submodule 729 7 2 9 Digital Compare D...

Page 7: ...gger 851 8 7 4 Example 4 Time Difference Delta Operation Rising and Falling Edge Trigger 853 8 8 Application of the APWM Mode 855 8 8 1 Example 1 Simple PWM Generation Independent Channel s 855 9 C28...

Page 8: ...n 954 11 4 1 Arbitration when Accessing the Analog Subsystem 955 11 5 Channel Priority 955 11 5 1 Round Robin Mode 955 11 5 2 Channel 1 High Priority Mode 956 11 6 Address Pointer and Transfer Control...

Page 9: ...tion 999 12 3 SPI Registers and Waveforms 1001 12 3 1 SPI Control Registers 1001 12 3 2 SPI Example Waveforms 1010 13 C28 Serial Communications Interface SCI 1016 13 1 Enhanced SCI Module Overview 101...

Page 10: ...s of the McBSP 1074 15 1 2 McBSP Pins Signals 1075 15 1 3 McBSP Operation 1076 15 1 4 Data Transfer Process of McBSP 1077 15 1 5 Companding Compressing and Expanding Data 1077 15 2 Clocking and Framin...

Page 11: ...r Two Phases for the Receive Frame 1118 15 8 8 Set the Receive Word Length s 1119 15 8 9 Set the Receive Frame Length 1119 15 8 10 Enable Disable the Receive Frame Synchronization Ignore Function 1120...

Page 12: ...R1 and SRGR2 1168 15 12 8 Multichannel Control Registers MCR 1 2 1170 15 12 9 Pin Control Register PCR 1175 15 12 10 Receive Channel Enable Registers RCERA RCERB RCERC RCERD RCERE RCERF RCERG RCERH 11...

Page 13: ...ssignment DMACHMAP1 Register offset 0x514 1220 16 7 21 DMA Channel Map Assignment DMACHMAP2 Register offset 0x518 1221 16 7 22 DMA Channel Map Assignment DMACHMAP3 Register offset 0x51C 1222 16 7 23 D...

Page 14: ...as 1 7 EPIREADFIFO1 7 Registers offset 0x070 and 0x08C 1292 17 11 18 EPI FIFO Level Selects EPIFIFOLVL Register 0x200 1292 17 11 19 EPI Write FIFO Count EPIWFIFOCNT Register offset 0x204 1294 17 11 20...

Page 15: ...egister USBCONTIM offset 0x07A 1362 18 5 19 USB OTG VBUS Pulse Timing Register USBVPLEN offset 0x07B 1362 18 5 20 USB Full Speed Last Transaction to End of Frame Timing Register USBFSEOF offset 0x07D...

Page 16: ...offset 0x438 1408 18 5 58 USB VBUS Droop Control Interrupt Status and Clear Register USBVDCISC offset 0x43C 1409 18 5 59 USB ID Valid Detect Raw Interrupt Status Register USBIDVRIS offset 0x444 1410...

Page 17: ...4 Initialization and Configuration 1455 20 5 SSI Registers 1456 20 5 1 SSI Base Addresses 1456 20 5 2 SSI_REGS Registers 1457 21 M3 Universal Asynchronous Receivers Transmitters UARTs 1488 21 1 Intro...

Page 18: ...set 0xFF8 1520 21 7 29 UART PrimeCell Identification 3 UARTPCellID3 offset 0xFFC 1520 22 M3 Inter Integrated Circuit I2C Interface 1521 22 1 Introduction 1522 22 2 I2C Block Diagram 1522 22 3 Function...

Page 19: ...mes 1561 23 10 4 Configuration of a Single Receive Object for Remote Frames 1561 23 10 5 Configuration of a FIFO Buffer 1562 23 11 Message Handling 1562 23 11 1 Message Handler Overview 1562 23 11 2 R...

Page 20: ...600 23 15 21 IF3 Arbitration Register CAN IF3ARB 1600 23 15 22 IF3 Message Control Register CAN IF3MCTL 1601 23 15 23 IF3 Data A and Data B Registers CAN IF3DATA DATB 1602 23 15 24 IF3 Update Enable R...

Page 21: ...pt 128 133 Clear Enable DIS4 Register offset 0x190 1654 25 5 11 Interrupt 0 31 Set Pending PEND0 Register offset 0x200 1654 25 5 12 Interrupt 32 63 Set Pending PEND1 Register offset 0x204 1655 25 5 13...

Page 22: ...fset 0xD24 1677 25 6 12 Configurable Fault Status FAULTSTAT Register offset 0xD28 1680 25 6 13 Hard Fault Status HFAULTSTAT Register offset 0xD2C 1684 25 6 14 Memory Management Fault Address MMADDR Re...

Page 23: ...ord Match Flow 151 1 24 ECSL Password Match Flow 154 1 25 Messaging with IPC Flags and Interrupts 159 1 26 Flash Pump Allocation for Different States of Flash Pump Semaphore 163 1 27 Mastership of Clo...

Page 24: ...69 C28 NMI Flag Clear CNMIFLGCLR Register 209 1 70 C28 NMI Flag Force CNMIFLGFRC Register 210 1 71 C28 NMI Watchdog Counter CNMIWDCNT Register 210 1 72 C28 NMI Watchdog Period CNMIWDPRD Register 211...

Page 25: ...ntrol Register 2 SCGC2 240 1 116 Deep Sleep Mode Clock Gating Control Register 2 DCGC2 242 1 117 Run Mode Clock Gating Control Register 3 RCGC3 243 1 118 Sleep Mode Clock Gating Control Register 3 SCG...

Page 26: ...e Flag MTOCIPCFLG Register 281 1 167 M3 to C28 Core IPC Acknowledge CTOMIPCACK Register 283 1 168 C28 to M3 Core IPC Status CTOMIPCSTS Register 285 1 169 M3 Flash Semaphore Register 287 1 170 M3 Clock...

Page 27: ...WDTVALUE Register 335 3 4 Watchdog Control WDTCTL Register 336 3 5 Watchdog Interrupt Clear WDTICR Register 336 3 6 Watchdog Raw Interrupt Status WDTRIS Register 337 3 7 Watchdog Masked Interrupt Sta...

Page 28: ...ral Identification 2 GPIOPeriphID2 Register 375 4 30 GPIO Peripheral Identification 3 GPIOPeriphID3 Register 375 4 31 GPIO PrimeCell Identification 0 GPIOPCellID0 Register 376 4 32 GPIO PrimeCell Iden...

Page 29: ...4 79 GPIO Port A Data GPADAT Register 446 4 80 GPIO Port B Data GPBDAT Register 447 4 81 GPIO Port C Data GPCDAT Register 448 4 82 GPIO Port D Data GPDDAT Register 449 4 83 GPIO Port E Data GPEDAT Reg...

Page 30: ...ster Access Violation Flag Register MNMAVFLG 502 5 35 Non Master Access Violation Flag Clear Register MNMAVCLR 502 5 36 Master Access Violation Flag Register MMAVFLG 503 5 37 Master Access Violation F...

Page 31: ...r CMWRAVADDR 534 5 79 Master DMA Write Access Violation Address Register CMDMAWRAVADDR 534 5 80 Master CPU Fetch Access Violation Address Register CMFAVADDR 534 5 81 FMC Interface with Core Bank and P...

Page 32: ...573 5 129 Error Threshold Register ERR_THRESHOLD 573 5 130 Error Interrupt Flag Register ERR_INTFLG 574 5 131 Error Interrupt Flag Clear Register ERR_INTCLR 574 5 132 Data High Test Register FDATAH_TE...

Page 33: ...l Signal Interconnects 672 7 4 Time Base Submodule 680 7 5 Time Base Submodule Signals and Registers 682 7 6 Time Base Frequency and Period 684 7 7 Time Base Counter Synchronization Scheme 4 685 7 8 T...

Page 34: ...puts 732 7 44 Event Trigger Interrupt Generator 734 7 45 Event Trigger SOCA Pulse Generator 735 7 46 Event Trigger SOCB Pulse Generator 735 7 47 Digital Compare Submodule High Level Block Diagram 736...

Page 35: ...784 7 96 Counter Compare D Register CMPD 784 7 97 Compare B High Resolution Register CMPBHR 785 7 98 Compare B High Resolution Mirror Register CMPBHRM 785 7 99 Action Qualifier Output A Control Regist...

Page 36: ...vent Trigger Counter Initialization Register ETCNTINIT 824 8 1 Capture and APWM Modes of Operation 829 8 2 Counter Compare and PRD Effects on the eCAP Output in APWM Mode 830 8 3 Capture Function Diag...

Page 37: ...78 9 23 eQEP Position compare Control QPOSCTL Register 880 9 24 eQEP Capture Control QCAPCTL Register 881 9 25 eQEP Position Counter QPOSCNT Register 881 9 26 eQEP Position Counter Initialization QPOS...

Page 38: ...Select 2 Register ADCINTSOCSEL2 Address Offset 15h 920 10 32 ADC SOC Flag 1 Register ADCSOCFLG1 Address Offset 18h 920 10 33 ADC SOC Force 1 Register ADCSOCFRC1 Address Offset 1Ah 920 10 34 ADC SOC O...

Page 39: ...DST_WRAP_SIZE 977 11 24 Source Destination Wrap Count Register SCR DST_WRAP_COUNT 978 11 25 Source Destination Wrap Step Size Registers SRC DST_WRAP_STEP 978 11 26 Shadow Source Begin and Current Addr...

Page 40: ...Multiprocessor Communication Format 1022 13 5 Double Buffered WUT and TXSHF 1023 13 6 Address Bit Multiprocessor Communication Format 1024 13 7 SCI Asynchronous Communications Format 1025 13 8 SCI RX...

Page 41: ...ster I2CFFRX 1071 15 1 Conceptual Block Diagram of the McBSP 1076 15 2 McBSP Data Transfer Paths 1077 15 3 Companding Processes 1078 15 4 Law Transmit Data Companding Format 1078 15 5 A Law Transmit D...

Page 42: ...ing Edge and Sampled by the McBSP Receiver on a Falling Edge 1128 15 49 Frame of Period 16 CLKG Periods and Active Width of 2 CLKG Periods 1129 15 50 Data Clocked Externally Using a Rising Edge and Sa...

Page 43: ...et DMAUSEBURSTSET Register 1215 16 17 DMA Channel Useburst Clear DMAUSEBURSTCLR Register 1215 16 18 DMA Channel Request Mask Set DMAREQMASKSET Register 1216 16 19 DMA Channel Request Mask Clear DMAREQ...

Page 44: ...1 WR2CYC 1 1260 17 27 C28x Master and Control Subsystem Access to EPI 1260 17 28 EPI Configuration Register EPICFG offset 0x000 1265 17 29 EPI Main Baud Rate EPIBAUD Register offset 0x004 1266 17 30...

Page 45: ...USB Block Diagram 1317 18 2 Function Address Register USBFADDR 1337 18 3 Power Management Register USBPOWER in OTG A Host Mode 1338 18 4 Power Management Register USBPOWER in OTG B Device Mode 1338 18...

Page 46: ...9 USB Control and Status Endpoint n High Register USBCSRH n in OTG B Device Mode 1386 18 50 USB Maximum Receive Data Endpoint n Registers USBRXCOUNT n 1387 18 51 USB Host Transmit Configure Type Endpo...

Page 47: ...Management Register 2 PHY Identifier 1 MR2 Register 1442 19 24 Ethernet PHY Management Register 3 PHY Identifier 2 MR3 Register 1442 19 25 Ethernet PHY Management Register 4 Auto Negotiation Advertise...

Page 48: ...FLS Register 1507 21 17 UART Interrupt Mask UARTIM Register 1508 21 18 UART Raw Interrupt Status UARTRIS Register 1510 21 19 UART Masked Interrupt Status UARTMIS Register 1512 21 20 UART Interrupt Cle...

Page 49: ...atus I2CSCSR Register Read Only 1545 22 26 I2C Slave Control Status I2CSCSR Register Write Only 1546 22 27 I2C Slave Data I2CSDR Register 1546 22 28 I2C Slave Interrupt Mask I2CSIMR Register 1546 22 2...

Page 50: ...Register CAN IF1DATB offset 0x114 1598 23 42 IF2 Data A Register CAN IF2DATA offset 0x130 1598 23 43 IF2 Data B Register CAN IF2DATB offset 0x134 1599 23 44 IF3 Observation Register CAN IF3OBS offset...

Page 51: ...Interrupt 32 63 Active Bit ACTIVE1 Register 1661 25 27 Interrupt 64 95 Active Bit ACTIVE2 Register 1661 25 28 Interrupt 96 127 Active Bit ACTIVE3 Register 1662 25 29 Interrupt 128 133 Active Bit ACTIV...

Page 52: ...criptions 140 1 23 TIMERxTPRH Register Field Descriptions 141 1 24 Device Low Power Modes for Active Power Reduction 141 1 25 M3 Subsystem Low Power Modes 142 1 26 Low Power Modes Configuration 144 1...

Page 53: ...Input Output Software Reset Control SRGPIO Register Field Descriptions 199 1 70 Master Subsystem Wait In Reset MWIR Register Field Descriptions 201 1 71 C28 Wait In Reset CWIR Register Field Descript...

Page 54: ...120 Sleep Mode Clock Gating Control Register 0 SCGC0 Field Descriptions 233 1 121 Deep Sleep Mode Clock Gating Control Register 0 DCGC0 Field Descriptions 233 1 122 Run Mode Clock Gating Control Regis...

Page 55: ...scriptions 272 1 168 CSMCR Register Field Descriptions 272 1 169 ECSLKEY0 Register Field Descriptions 273 1 170 ECSLKEY1 Register Field Descriptions 273 1 171 EXEONLYR Register Field Description 274 1...

Page 56: ...GPTMTBPR Register Field Descriptions 327 2 19 GPTM Timer A Prescale Match GPTMTAPMR Register Field Descriptions 327 2 20 GPTM Timer B Prescale Match GPTMTBPMR Register Field Descriptions 328 2 21 GPTM...

Page 57: ...Register Field Descriptions 366 4 20 GPIO Analog Mode Select GPIOAMSEL Register Field Descriptions 366 4 21 GPIO Port Control GPIOPCTL Register Field Descriptions 367 4 22 GPIO Alternate Peripheral Se...

Page 58: ...elect 2 GPAQSEL2 Register Field Descriptions 429 4 71 GPIO Port B Qualification Select 1 GPBQSEL1 Register Field Descriptions 430 4 72 GPIO Port B Qualification Select 2 GPBQSEL2 Register Field Descri...

Page 59: ...P Input Signals 460 4 118 GPIO Low Power Mode Wakeup Select 1 GPIOLPMSEL1 Register Field Descriptions 461 4 119 GPIO Low Power Mode Wakeup Select 2 GPIOLPMSEL2 Register Field Descriptions 461 5 1 Mast...

Page 60: ...dress Register MNMDMAWRAVADDR Field Descriptions 505 5 49 Non Master CPU Fetch Access Violation Address Register MNMFAVADDR Field Descriptions 505 5 50 Master CPU Write Access Violation Address Regist...

Page 61: ...Bank Access Control Register FBAC Field Descriptions 555 5 96 Flash Bank Fallback Power Register FBFALLBACK Field Description 555 5 97 Flash Bank Pump Control Register FBPRDY Field Descriptions 556 5...

Page 62: ...riptions 575 5 141 Data Low Test Register FDATAL_TEST Field Descriptions 575 5 142 ECC Test Address Register FADDR_TEST Field Descriptions 575 5 143 ECC Test Register FECC_TEST Field Descriptions 576...

Page 63: ...EL Trigger Options 730 7 23 Event Trigger Submodule Registers 732 7 24 Digital Compare Submodule Registers 738 7 25 Time Base Period and Mirror 2 Register TBPRD TBPRDM2 Field Descriptions 770 7 26 Tim...

Page 64: ...eld Descriptions 802 7 66 Trip Zone Digital Compare Event Select Register TZDCSEL Field Descriptions 803 7 67 Digital Compare Trip Select DCTRIPSEL Field Descriptions 804 7 68 Digital Compare A Contro...

Page 65: ...osition compare QPOSCMP Register Field Descriptions 882 9 11 eQEP Index Position Latch QPOSILAT Register Field Descriptions 882 9 12 eQEP Strobe Position Latch QPOSSLAT Register Field Descriptions 883...

Page 66: ...931 10 32 ADC Start of Conversion Trigger Overflow Detect Register TRIGOVF Field Descriptions 932 10 33 ADC Start of Conversion Trigger Overflow Flag Clear Register TRIGOVFCLR Field Descriptions 933...

Page 67: ...eive Buffer Register SPIRXBUF Field Descriptions 1005 12 15 SPI Serial Transmit Buffer Register SPITXBUF Field Descriptions 1006 12 16 SPI Serial Data Register SPIDAT Field Descriptions 1006 12 17 SPI...

Page 68: ...KSTP on Clock Modes 1088 15 5 Choosing an Input Clock for the Sample Rate Generator with the SCLKME and CLKSM Bits 1088 15 6 Polarity Options for the Input to the Sample Rate Generator 1089 15 7 Input...

Page 69: ...Bits Used to Enable Disable Transmit Multichannel Selection 1138 15 53 Register Bit Used to Choose 1 or 2 Phases for the Transmit Frame 1138 15 54 Register Bits Used to Set the Transmit Word Length s...

Page 70: ...el Control Word Configuration for Peripheral Transmit Example 1203 16 11 Primary and Alternate Channel Control Structure Offsets for Channel 8 1204 16 12 Channel Control Word Configuration for Periphe...

Page 71: ...9 EPI General Purpose Signal Connections 1255 17 10 Control Subsystem Address Mapping 1261 17 11 External Peripheral Interface EPI Register Map M3 Base Address 0x400D_0000 C28x Base Address 0x7C00 12...

Page 72: ...ons 1315 18 1 Remainder MAXLOAD 4 1327 18 2 Actual Bytes Read 1327 18 3 Packet Sizes That Clear RXRDY 1327 18 4 Universal Serial Bus USB Controller Register Map 1329 18 5 Function Address Register USB...

Page 73: ...Endpoint n High Register USBTXCSRH n in OTG A Host Mode Field Descriptions 1379 18 47 USB Transmit Control and Status Endpoint n High Register USBTXCSRH n in OTG B Device Mode Field Descriptions 1380...

Page 74: ...Descriptions 1432 19 11 Ethernet MAC Threshold MACTHR Register Field Descriptions 1433 19 12 Ethernet MAC Management Control MACMCTL Register Field Descriptions 1434 19 13 Ethernet MAC Management Divi...

Page 75: ...0 UART Control UARTCTL Register Field Descriptions 1506 21 11 UART Interrupt FIFO Level Select UARTIFLS Register Field Descriptions 1507 21 12 UART Interrupt Mask UARTIM Register Field Descriptions 15...

Page 76: ...tatus I2CSMIS Register Field Descriptions 1548 22 21 I2C Slave Interrupt Clear I2CSICR Register Field Descriptions 1548 23 1 Programmable Ranges Required by CAN Protocol 1568 23 2 Message Object Field...

Page 77: ...5 10 SysTick Current Value Register STCURRENT Field Descriptions 1647 25 11 Interrupt 0 31 Set Enable EN0 Register Field Descriptions 1648 25 12 Interrupt 32 63 Set Enable 1 EN1 Register Field Descrip...

Page 78: ...Control APINT Register Field Descriptions 1671 25 44 System Control SYSCTRL Register Field Descriptions 1673 25 45 Configuration and Control CFGCTRL Register Field Descriptions 1674 25 46 System Handl...

Page 79: ...t uses the following conventions Hexadecimal numbers may be shown with the suffix h or the prefix 0x For example the following number is 40 hexadecimal decimal 64 40h or 0x40 Registers in this documen...

Page 80: ...onfigurable features in system control include reset control NMI operation power control clock control and low power modes For more information on the Viterbi Complex Math CRC Unit VCU please refer to...

Page 81: ...r default Non maskable interrupt XCLKIN PJ7_GPIO63 0 default 0 default Master default External oscillator input This pin feeds a clock from an external 3 3 V oscillator to the internal USB PLL module...

Page 82: ...ven high this pin is used as an interrupt to or from the emulator system and is defined as input output through the JTAG scan 1 2 System Control Functional Description The system control module provid...

Page 83: ...core configuration registers are CCNF0 CCNF1 CCNF2 CCNF3 and CCNF4 All these registers are defined in the Device Identification and Device Configuration registers subsection in the System Control Reg...

Page 84: ...the master subsystem whenever it is reset the entire device is reset including control and analog subsystems Software on the master subsystem can choose to reset the control subsystem and analog subsy...

Page 85: ...ecause a POR reset pulls the XRS pin low bit 0 is also set NOTE The power on reset also resets the JTAG controller While in most applications the POR generated reset has a long enough duration to also...

Page 86: ...n internal reset is asserted which pulls XRS low and this resets the whole device and appropriate bits in the MRESC register are set Note that on this device the watchdogs are available only on the ma...

Page 87: ...et resets the C28x CPU core and control subsystem All the GPIOs which were configured for the control subsystem will remain with the control subsystem and will be reset to their default state input GP...

Page 88: ...11 Shared Resources Reset Shared resources between the master and control subsystems IPC registers MTOC and CTOM message RAM configurable shared RAMs and the ACIB interface are reset by the shared res...

Page 89: ...T VALUES FLASH PUMP XRS CRESCNF REG DEVICECNF REG CRESSTS REG C28SYSRST C28NMIWD M3WDOGS ACIBRST M3RSNIN SOFTWARE JTAG CONTROLLER MRESC REG CONTAINS RESET CAUSES PERIPHERAL SOFTWARE RESETS ACIBRST SRC...

Page 90: ...us In addition to driving reset signals to other parts of the chip the master subsystem can also detect a C28SYSRST reset being set in the control subsystem by reading the CRES bit of the CRESSTS regi...

Page 91: ...CLK frequency Brings control and analog subsystems out of reset Since a POR reset also causes an XRS reset M Boot ROM clears both the POR and XRS bits bits 1 and 0 respectively in the MRESC register a...

Page 92: ...a debugger generated reset that is also output by the NVIC The M3RSNIN reset comes from the Cortex M3 subsystem to selectively reset the control subsystem from Cortex M3 software The C28x processor c...

Page 93: ...t ROM chapter for more details on the C Boot ROM procedure and supported IPC communication If there is an NMI during the execution time of C Boot ROM except for a Missing Clock NMI C Boot ROM acknowle...

Page 94: ...at EMU0 and EMU1 bits in the MWIR register and or the CWIR register are set to the WIR_MODE_YES value and run the boot ROM To achieve this the user can Set EMU0 and EMU1 pins on the device to the WIR_...

Page 95: ...E_YES value then the boot ROM continues its execution by exiting the WIR mode Although both the boot ROMs in the master subsystem and control subsystem continue to read the WIR mode register they do n...

Page 96: ...eptions that can occur in the system and trigger an NMI to the respective CPU core 1 5 1 Master Subsystem Nested Vectored Interrupt Controller Refer to the NVIC section of the Cortex M3 Peripherals ch...

Page 97: ...state transition attempt This exception is synchronous From the above exceptions the NMI and bus faults are generated by the digital subsystem whereas memory management errors are generated internally...

Page 98: ...ous errors that could occur in the entire system including all the subsystems and inform the main CPU core about the error An NMI exception to the M3 CPU on the master subsystem will be generated only...

Page 99: ...and Interrupts Figure 1 3 Master Subsystem NMI Sources and MNMIWD All the NMI sources except for the ACIBERR NMI shown in Figure 1 3 are enabled by default on reset There is no provision for the user...

Page 100: ...POR or XRS reset However the user application can configure PB7 for NMI operation give a warm reset and execute through boot ROM In which case this NMI could occur while M Boot ROM is executing Howev...

Page 101: ...ging the NMI and gracefully shutting down the system If none of the actions mentioned are taken then the MNMIWD counter keeps counting until the counter value reaches the MNMIWD period register value...

Page 102: ...d in the ROM vector table and when the PIE is enabled an NMI and ITRAP exceptions will use the handler s registers in the PIE vector table which is located in PIE RAM More details are explained in the...

Page 103: ...ng CPU interrupts are not multiplexed For the non multiplexed interrupts the PIE passes the request directly to the CPU For multiplexed interrupt sources each interrupt group in the PIE block has an a...

Page 104: ...October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated System Control and Interrupts Figure 1 5 CPU Level Interrupt Handling NOTE For mult...

Page 105: ...bsystem the interrupt vector table can be mapped to four distinct locations in memory In practice only the PIE vector table mapping is used This vector mapping is controlled by the following mode bits...

Page 106: ...modes are set to 1 on reset The ENPIE mode is forced to 0 on reset 2 The reset vector is always fetched from the boot ROM Table 1 11 Vector Table Mapping After Reset Operation Vector MAPS Reset Fetche...

Page 107: ...dback Copyright 2012 2019 Texas Instruments Incorporated System Control and Interrupts 1 5 4 3 Interrupt Sources Figure 1 7 shows how the various interrupt sources are multiplexed within the devices T...

Page 108: ...If the PIEIER registers are used to enable and then later disable an interrupt then the procedure described in Section 1 5 4 3 2 must be followed 1 5 4 3 2 Procedures for Enabling And Disabling Multi...

Page 109: ...rrupts INTM 0 6 Wait for any pending interrupt from the peripheral to be serviced by the empty ISR routine 7 Disable global interrupts INTM 1 8 Modify the PIE vector table to map the peripheral vector...

Page 110: ...to the PIEIERx register after an interrupt has been passed to the CPU In this case the PIE will respond as if a TRAP or INT instruction was executed unless there are other interrupts both pending and...

Page 111: ...ZINT EPWM12_TZINT MXINTA MRINTA Reserved Reserved SPITXINTA SPIRXINTA ePWM11 ePWM12 McBSP A McBSP A SPI A SPI A 0x0D9E 0x0D9C 0x0D9A 0x0D98 0x0D96 0x0D94 0x0D92 0x0D90 INT7 EPWM11_INT EPWM12_INT DINTC...

Page 112: ...00000D1E 2 CPU Data Logging Interrupt 19 lowest RTOSINT 16 0x0000 0D20 2 CPU Real Time OS Interrupt 4 EMUINT 17 0x0000 0D22 2 CPU Emulation Interrupt 2 NMI 18 0x0000 0D24 2 External Non Maskable Inter...

Page 113: ...7 4 INT3 5 52 0x0000 0D68 2 EPWM5_INT 7 5 INT3 6 53 0x0000 0D6A 2 EPWM6_INT 7 6 INT3 7 54 0x0000 0D6C 2 EPWM7_INT 7 7 INT3 8 55 0x0000 0D6E 2 EPWM8_INT 7 8 lowest PIE Group 4 Vectors MUXed into CPU I...

Page 114: ...000 0DB2 2 I2CINT2 A I2C A 12 2 INT8 3 90 0x0000 0DB4 2 Reserved 12 3 INT8 4 91 0x0000 0DB6 2 Reserved 12 4 INT8 5 92 0x0000 0DB8 2 Reserved 12 5 INT8 6 93 0x0000 0DBA 2 Reserved 12 6 INT8 7 94 0x0000...

Page 115: ...ers PIEIFR There are 12 PIEIFR registers one for each CPU interrupt in the PIE module INT1 INT12 PIE Interrupt Enable Registers PIEIER There are 12 PIEIER one for each CPU interrupt in the PIE module...

Page 116: ...en using the OR IER and AND IER instructions to modify IER bits make sure they do not modify the state of bit 15 RTOSINT unless a real time operating system is present When a hardware interrupt is ser...

Page 117: ...AP ISR gets executed before the INT12 5 ISR The user needs to take this into account when servicing the ITRAP Please refer to the Boot ROM chapter for details on how the boot ROM handles this exceptio...

Page 118: ...d CNMIWD As shown in Figure 1 9 any of the listed errors can trigger an NMI to the C28x CPU There is also an NMI Flag Force CNMIFLGFRC register to simulate an NMI error condition to aid in debug and d...

Page 119: ...This NMI is generated when a double bit error is detected by the memory wrapper logic 1 5 6 1 4 FLUNCERR NMI For information on the FLASH Uncorrectable Error NMI please refer to the Internal Memory c...

Page 120: ...r which if written with a value of 0xA5A5 A5A5 allows writes to all other PROTECTED registers defined in this specification The MWRALLOW register is only writable in M3 privileged mode 1 6 1 1 2 MLOCK...

Page 121: ...8 bit counter running with the OSCCLK source which keeps updating a reference clock count register 6 There are two programmable registers which contain programmable limits for missing clock condition...

Page 122: ...28 application software should configure the LPMCR registers to enter standby mode 2 Changing the clock limit values REFCLKLO and HI limit should be done after disabling the missing clock NMI using th...

Page 123: ...k to device 10MHz Internal Oscillator CLK 3 Disable missing clock counters 4 C28 side PWMs tripped based on configuration Input Clock Proper Yes CLOCKFAIL condition generated Disable missing clock cir...

Page 124: ...s are reserved for the PIE vector table one mapped at 0x0D00 and the other at 0x0E00 in C28 address space Writes with address 0x0Dxx will get duplicated onto the memory at 0x0E00 whereas writes to the...

Page 125: ...that the control subsystem is seeing a PIE vector address mismatch A while 1 loop is entered without further executing any code on the control subsystem If this exception on the control subsystem is...

Page 126: ...v VREGs generate the 1 2v VDD signal and 1 8v VDD signal from the 3 3 VDDIO input as needed to power the digital and analog subsystems on the device This is done by pulling the VREG12EN and VREG18EN p...

Page 127: ...L A resonator can also be used as an input clock source on the X1 X2 pins 1 8 1 2 GPIO_XCLKIN GPIO_XCLKIN is a clock input which is available when the PJ7_GPIO63 pin is used as a clock input This cloc...

Page 128: ...its support the fractional multiplier SPLLFMULT The value of SPLLIMULT 0 would default to PLLBYPASS mode where Fout Fref As an example if SPLLIMULT 36 and SPLLFMULT 2 it yields a multiplication factor...

Page 129: ...ilable in the master subsystem and explains how each clock is derived and the configuration registers involved Figure 1 11 Master Subsystem Clocks and Low Power Mode Configuration The internal PLLSYSC...

Page 130: ...iguration in addition to the M3 CPU clock being stopped An interrupt returns the M3 CPU to run mode by a request from the code Deep sleep mode is entered by first writing the deep sleep enable bit in...

Page 131: ...will be divided by the deep sleep divider only 1 8 4 Control Subsystem Clocking The input clock to the C28x processor is the C28CLKIN refer to Figure 1 12 which is the same as PLLSYSCLK coming from th...

Page 132: ...TE IN REVISION 0 OF SILICON XCLKOUT PLLSYSCLK DIVIDED DOWN BY 1 2 OR 4 C28SYSCLK C28x must control pin M3 must control pin Clock Control www ti com 132 SPRUHE8E October 2012 Revised November 2019 Subm...

Page 133: ...K are turned off Exit from Standby Mode is accomplished by one of 64 GPIOs from the GPIO_MUX block or MTOCIPCINT2 interrupt from the MTOC IPC peripheral The wakeup GPIO selected inside the GPIO_MUX bl...

Page 134: ...ontrol and Interrupts Figure 1 13 Control Subsystem Peripherals Clocking 1 8 4 5 Enabling Disabling Clocks to the Peripheral Modules The PCLKCR0 1 2 3 registers enable disable clocks to the various pe...

Page 135: ...locking control semaphore and can read write to the clocking control registers At this time these registers are READ ONLY for the master subsystem Registers which can be accessed by the subsystem whic...

Page 136: ...d with a proper divider value as a parameter based on user clock configuration requirements on the device during the application initialization process 1 8 6 1 MCIBSTATUS and CCIBSTATUS Both the maste...

Page 137: ...rated System Control and Interrupts 1 8 8 32 Bit CPU Timers 0 1 2 This section describes the three 32 bit CPU timers TIMER0 1 2 shown in Figure 1 14 CPU Timer 0 and CPU Timer 1 can be used in user app...

Page 138: ...od Register Figure 1 18 TIMER1PRDH 0x0C0B 1 CPU Timer 1 Period Register High Figure 1 19 TIMER1TCR 0x0C0C 1 CPU Timer 1 Control Register Figure 1 20 TIMER1TPR 0x0C0E 1 CPU Timer 1 Prescale Register Fi...

Page 139: ...The PRDH PRD contents are also loaded into the TIMH TIM when you set the timer reload bit TRB in the Timer Control Register TCR Figure 1 19 TIMERxPRDH Register x 0 1 2 15 0 PRDH R W 0 LEGEND R W Read...

Page 140: ...ivide down register TDDRH TDDR 4 TSS CPU Timer stop status bit TSS is a 1 bit flag that stops or starts the CPU timer 0 Reads of 0 indicate the CPU timer is running To start or restart the CPU timer s...

Page 141: ...Reduction PLL M3 CPU Master Subsystem C28 CPU Control Subsystem On decided by SYSCLKCTL register On Sleep mode Active M3 SS CLK full speed Active CLKIN CPUCLK SYSCLK on Active SYSCLK on Idle CLKIN on...

Page 142: ...to the DSLPCLKCFG register off On on off Any event for WFE Any interrupt for WFI The SLEEPDEEP bit of the System Control SYSCTRL register selects which sleep mode is used Refer to the SYSCTRL registe...

Page 143: ...have to execute system restore tasks after the processor wakes up and before executing an interrupt handler Entry to the interrupt handler can be delayed by setting the PRIMASK bit and clearing the F...

Page 144: ...2 1 9 1 2 1 Entering Low Power Mode The system enters low power mode upon execution of the IDLE instruction The low power mode bits LPM 1 0 of the CLPMCR0 register are only valid when the IDLE instruc...

Page 145: ...re two levels of protection are possible depending on where the program counter is currently pointing If code is currently running from inside secure memory only an access through JTAG is blocked that...

Page 146: ...to avoid introducing a security hole 1 10 1 1 Emulation Code Security Logic ECSL In addition to the CSM the emulation code security logic ECSL has been implemented using a 64 bit password for each zon...

Page 147: ...the device The user can enable the JTAG lock feature by programming the OTP_JTAGLOCK field with any value other than 1111 0xF at the OTPSEC location in OTP This feature takes effect only after the OT...

Page 148: ...r security may be desired once the application code is finalized Before such code is programmed in the flash memory a CSM password should be chosen to secure the zone Once a CSM password is in place f...

Page 149: ...lues Register Description 0x2F FFF0 Z2_CSMPSWD0 User Defined Low word 32 bit of the 128 bit CSM password for zone2 0x2F FFF4 Z2_CSMPSWD1 User Defined Second word 32 bit of the 128 bit CSM password for...

Page 150: ...ming solutions that use the flash API supplied by TI unlocking the CSM can be avoided by executing the flash programming algorithms from secure memory Custom environments defined by the application in...

Page 151: ...Fs Write the CSM Password of that zone into CSMKEY 0 1 2 3 registers Correct Password www ti com Code Security Module CSM 151 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback...

Page 152: ...icated to that zone are fully accessible immediately after this operation is completed NOTE Even if a zone is not protected with a password all password locations all ones the CSM will lock at reset T...

Page 153: ...E 1 0 0 0 SECURE 1 1 0 X SECURE 1 0 1 X NON SECURE 1 0 0 1 NON SECURE 1 10 3 4 Environments That Require ECSL Unlocking The following are the typical situations under which unsecuring memories can be...

Page 154: ...e unlocked Are ECSL PWL All Fs Write the ECSL Password of that zone into ECSLKEYx registers Correct Password Code Security Module CSM www ti com 154 SPRUHE8E October 2012 Revised November 2019 Submit...

Page 155: ...AG connection NOTE Even if a secure zone s ECSL is not locked with a password all password locations all ones the ECSL will be locked at reset Thus a dummy read operation must still be performed for t...

Page 156: ...by M3 software to compute CRC on data program data stored at memory locations which are addressible by the M3 subsystem The M3 flash bank and ROM are mapped to the code space which is only accessed by...

Page 157: ...Section 1 10 for more details Since zoneX X 1 2 software does not have access to data program data in zoneY Y 2 1 code running from zoneX cannot calculate CRC on data stored in zoneY memory Similarly...

Page 158: ...more information on these registers There is no hardware relationship between the IPC flags interrupts and the message RAMs Users can use them together to accomplish better communication techniques be...

Page 159: ...ion from the M3 to the C28x The MTOCIPCSET register has 32 bits each of which when set is capable of enabling a corresponding flag bit in the MTOCIPCFLG register on the M3 and a status bit in the MTOC...

Page 160: ...ET register has 32 bits each of which when set is capable of enabling a corresponding flag bit in the CTOMIPCFLG register on the C28x and a status bit in the CTOMIPCSTS register on the M3 For example...

Page 161: ...e C28x CPU has serviced the interrupt and reads the RAM from the predefined location and gathers the requested information 1 12 5 2 IPC With Flags Below is an example procedure for IPC usage when the...

Page 162: ...the MTOCIPCADDR register 2 After writing to these IPC message registers the M3 should raise an IPC request using either an MTOCIPC flag or interrupt 3 When the C28x gets this IPC request from the M3 C...

Page 163: ...he M3 by default the M3 should gain the pump by writing a value of 10 in the MPUMPREQUEST register when the M3 wants to erase program the M3 flash bank This prevents the C28x from grabbing the pump se...

Page 164: ...ne with configuring the clock settings and any operations that it wants to perform at that configured frequency it should release mastership of the clock configuration registers by writing a value of...

Page 165: ...NTERL 32 bit MIPCCOUNTERH 32 bit is clocked by the shared resources clock and is readable by the M3 and the C28x on their respective memory maps These counter registers are reset to zero on reset Beca...

Page 166: ...set the state of the LOCK configuration Note that all the addresses in the memory map which are not defined in the below table are reserved None of the reserved addresses nor any of the reserved bits...

Page 167: ...ontrol Register 0 4 0x120 MWRALLOW M3SYSRST DCGC1 Deep Sleep Mode Clock Gating Control Register 1 4 0x124 MWRALLOW M3SYSRST DCGC2 Deep Sleep Mode Clock Gating Control Register 2 4 0x128 MWRALLOW M3SYS...

Page 168: ...SYSRST MLOCK M3 Configuration Lock Register 4 0x4 MWRALLOW SRXRST READ ONLY Write 1 Master Subsystem Reset Registers 0x400F B8 C0 CRESCNF Control Subsystem Reset Configuration Control Register 4 0x0 M...

Page 169: ...Subsystem Device Configuration Registers 0x0886 0x400F B9 00 CCNF0 Control Subsystem Peripheral Configuration 0 Register 4 0x00 0x10 MWRALLOW XRS Yes CCNF1 Control Subsystem Peripheral Configuration...

Page 170: ...ster 0 2 0X1C EALLOW C28SYSRST PCLKCR1 C28 Peripheral Clock Control Register 1 2 0X1D EALLOW C28SYSRST LPMCR0 C28 LPM Control Register 0 2 0X1E EALLOW C28SYSRST PCLKCR3 C28 Peripheral Clock Control Re...

Page 171: ...0x80 M3SYSRST Z2_CSMCR Status Control Register for M3 Zone2 4 0x84 M3SYSRST Z1_GRABSEC TR Grab Flash Sectors Register for M3 Zone1 4 0x90 M3SYSRST Yes Z1_GRABRAM R Grab RAM blocks Register for M3 Zon...

Page 172: ...High Register clocked by shared resource clock 4 0x0E 0x1C SRXRST Yes CTOMIPCCOM C28 to M3 IPC Command Register 4 0x10 0x20 C28SYSRST SRXRST Yes for M3 CTOMIPCADD R C28 to M3 IPC Address Register 4 0x...

Page 173: ...d resource clock 4 0x0E 0x1C SRXRST Yes CTOMIPCCOM C28 to M3 IPC Command Register 4 0x10 0x20 C28SYSRST SRXRST CTOMIPCADD R C28 to M3 IPC Address Register 4 0x12 0x24 C28SYSRST SRXRST CTOMIPCDAT AW C2...

Page 174: ...S 0x50 F28M36x 15 0 REVID Current Rev ID of the device 1 13 2 2 Device Identification 1 DID1 Register Figure 1 29 Device Identification 1 DID1 Register 31 28 27 24 23 16 VER FAM PARTNO R 0x1 R 0x1 R x...

Page 175: ...TMP 2 Fully qualified TMS All other encodings are reserved 1 13 2 3 Device Configuration 1 DC1 Register Figure 1 30 Device Configuration 1 DC1 Register 31 29 28 27 16 Reserved WDT1 Reserved R x R x R...

Page 176: ...Reserved 30 EPI EPI Whether EPI is present or not depends on the device configuration 0 EPI is not present 1 EPI is present 29 20 Reserved Reserved 19 TIMER3 GPT Timer3 Whether GPT3 is present or not...

Page 177: ...2 is present 5 SSI1 SSI1 Whether SSI1 is present or not depends on the device configuration 0 SSI1 is not present 1 SSI1 is present 4 SSI0 SSI0 Whether SSI0 is present or not depends on the device con...

Page 178: ...or not depends on the device configuration 0 EMAC0 is not present 1 EMAC0 is present 27 25 Reserved Reserved 24 E1588 1588 Capable EMAC 0 Whether 1588 capable EMAC0 is present or not depends on the de...

Page 179: ...PIOE is present or not depends on the device configuration 0 GPIO PortE is not present 1 GPIO PortE is present 3 GPIOD GPIO PortD Whether GPIOD is present or not depends on the device configuration 0...

Page 180: ...1 USB0 PHY is present 3 2 Reserved Reserved 1 0 USB0 USB0 Controller Functionality USB functionality allowed in the device depends on device configuration 0x00 No USB functionality 0x01 Device Only 0...

Page 181: ...2 9 General Purpose Input Output Peripheral Present PPGPIO Register The General Purpose Input Output Peripheral Present PPGPIO register provides information regarding the availability of general purp...

Page 182: ...ash 0 GPIO Port M is not present 1 GPIO Port M is present 10 GPIOL GPIO Port L is present When set indicates GPIO Port L is present Whether GPIOL is present or not depends on the device configuration...

Page 183: ...GPIO Port B is present Whether GPIOB is present or not depends on the device configuration in OTP flash 0 GPIO Port B is not present 1 GPIO Port B is present 0 GPIOA GPIO Port A is present When set in...

Page 184: ...PI A is in Slave Mode 1 1 SSI3 Connected to SPI A SPI A is in Master Mode 1 13 2 12 Master Subsystem ACIB Status MCIBSTATUS Register Figure 1 39 Master Subystem ACIB Status MCIBSTATUS Register 15 8 CI...

Page 185: ...M3 boot software will read the part number from the OTP and load it into the PARTNO field of the DID1 register This register field is a replica on the C28 side of the PARTNO bits of the DID1 register...

Page 186: ...Read Write R Read only n value after reset Table 1 54 Control Subsystem Device Configuration DEVICECNF Register Field Descriptions Bit Field Value Description 31 20 Reserved Reserved 19 ENPROT Enable...

Page 187: ...ystem I2C module 0 I2C module is disabled 1 I2C module is enabled 3 1 Reserved Reserved 0 HRPWM HRPWM Module Configuration When set this enables the HRPWM module 0 HRPWM module is disabled 1 HRPWM mod...

Page 188: ...erved EPWM12 EPWM11 EPWM10 EPWM9 R 0 R x R x R x R x LEGEND R W Read Write R Read only n value after reset Table 1 57 Control Subsystem Peripheral Configuration 2 CCNF2 Register Field Descriptions Bit...

Page 189: ...gure 1 47 Control Subsystem Peripheral Configuration 3 CCNF3 Register 31 12 11 10 0 Reserved C28DMA Reserved R 0 R x R 0 LEGEND R W Read Write R Read only n value after reset Table 1 58 Control Subsys...

Page 190: ...ptions Bit Field Value Description 31 3 Reserved Reserved 2 0 FLASH C28 Flash Size Configuration 111 512KB 110 256KB 1 13 2 22 Master Subsystem Memory Configuration MEMCNF Register NOTE This register...

Page 191: ...CPU 0 RSn to C28 CPU is low causing a C28 CPU and C28 subsystem reset 1 RSn to C28 CPU is high bringing out the C28 CPU and subsystem out of reset 15 0 Reserved Reserved 1 13 3 2 Control Subsystem Res...

Page 192: ...Register Field Descriptions continued Bit Field Value Description 16 CNMIWDRST C28 Reset Cause Flag set by hardware when C28 NMIWD fired a reset to the C28 CPU and subsystem 0 C28 CPU was not reset by...

Page 193: ...ggered the M3 NMIWD M3 did not respond to the NMI and the M3 NMIWD fired a reset 29 M3BISTERRNMI M3 BIST Error NMI Unserviced 0 M3 did not respond to the NMI and the NMIWD fired a reset If 0 then ther...

Page 194: ...used a device reset 4 SW Software NVIC Reset 0 No NVIC software reset request that caused a device reset since the previous POR Writing a 0 to this bit clears it 1 SW reset request from the NVIC SYSRE...

Page 195: ...set and bringing it out of reset is done by software When a particular bit is set the module goes into reset and to bring the module out of reset software has to again write a 0 explicitly to the regi...

Page 196: ...being set 29 20 Reserved Reserved 19 TIMER3 TIMER3 S W Reset Control When this bit is set GPT3 is reset All internal data is lost and the registers are returned to their reset states This bit must be...

Page 197: ...d after being set 1 UART1 UART1 S W Reset Control When this bit is set UART1 is reset All internal data is lost and the registers are returned to their reset states This bit must be manually cleared a...

Page 198: ...registers are returned to their reset states This bit must be manually cleared after being set 4 GPIOE GPIOE SW Reset Control When this bit is set GPIOE is reset All internal data is lost and the regi...

Page 199: ...2 1 0 GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 69 General Purpose Input Output Soft...

Page 200: ...ol When this bit is set GPIOG is reset All internal data is lost and the registers are returned to their reset states This bit must be manually cleared after being set 5 GPIOF GPIOF SW Reset Control W...

Page 201: ...g this bit will give the state of the EMU1 pin on reset or when sampled 0 Has no effect 1 Forces the bit to 1 0 EMU0 Latched State of EMU0 Pin The state of EMU0 pin is latched on reset XRS AND POR or...

Page 202: ...ror event occurs Figure 1 61 M3NMI Configuration MNMICFG Register 31 16 Reserved R 0 15 10 9 8 1 0 Reserved ACIBERRE Reserved NMIE R 0 R W 0 R 0 R x LEGEND R W Read Write R Read only n value after res...

Page 203: ...MI Flag This bit indicates that an error condition was generated during NMI vector fetch from C28 PIE Once enabled the flag cannot be cleared by the user This bit can only be cleared by the user writi...

Page 204: ...5 4 3 2 1 0 C28PIENMIERR EXTGPIO C28BISTERR M3BISTERR Reserved CLOCKFAIL NMIINT R W 0 R W 0 R W 0 R W 0 R 0 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 74 M3NMI Flag Cl...

Page 205: ...erved ACIBERR C28NMIWDRST R 0 R W 0 R W 0 7 6 5 4 3 2 1 0 C28PIENMIERR EXTGPIO C28BISTERR M3BISTERR Reserved CLOCKFAIL Reserved R W 0 R W 0 R W 0 R W 0 R 0 0 R W 0 R 0 LEGEND R W Read Write R Read onl...

Page 206: ...t If the counter reaches the period value an NMIRS signal is fired which will then reset the full device See Section 1 3 for more details on the reset behavior The counter will reset to zero when it r...

Page 207: ...ed or disabled Note The ACIBERR NMI condition needs to be disabled at reset 0 ACIBERR NMI disabled 1 ACIBERR NMI enabled 5 C28BISTERR HW BIST Error NMI Flag This bit indicates if the time out error or...

Page 208: ...t clears the corresponding flag bit in the NMIFLG and NMISHDFLG registers Note 1 If hardware is trying to set a bit to 1 while software is trying to clear a bit to 0 on the same cycle hardware has pri...

Page 209: ...ways reads back 0 1 Clears the corresponding flag bit in the NMIFLG register 5 C28BISTERR C28 BIST Error Flag 0 Writes of 0 are ignored Always reads back 0 This can be used as a means to test the NMI...

Page 210: ...NMI mechanisms 1 Clears the corresponding flag bit in the NMIFLG register 1 CLOCKFAIL Clock Fail NMI Flag Force 0 Ignored always reads back 0 This can be used as a means to test the NMI mechanisms 1 C...

Page 211: ...Read Write R Read only n value after reset Table 1 84 PIE Control PIECTRL Register Field Descriptions Bits Field Value Description 15 1 PIEVECT These bits indicate the address within the PIE vector t...

Page 212: ...the bit and enables the PIE block to drive a pulse into the CPU interrupt input if an interrupt is pending for that group 1 13 5 13 3 PIE Interrupt Enable Registers There are twelve PIEIER registers...

Page 213: ...rtion of the interrupt processing Hardware has priority over CPU accesses to the PIEIFR registers 6 INTx 7 5 INTx 6 4 INTx 5 3 INTx 4 2 INTx 3 1 INTx 2 0 INTx 1 NOTE Never clear a PIEIFR bit An interr...

Page 214: ...perating system flag RTOSINT is the flag for RTOS interrupts 0 No RTOS interrupt is pending 1 At least one RTOS interrupt is pending Write a 0 to this bit to clear it to 0 and clear the interrupt requ...

Page 215: ...ending 1 At least one INT4 interrupt is pending Write a 0 to this bit to clear it to 0 and clear the interrupt request 2 INT3 Interrupt 3 flag INT3 is the flag for interrupts connected to CPU interrup...

Page 216: ...INT Real time operating system interrupt enable RTOSINT enables or disables the CPU RTOS interrupt 0 Level INT6 is disabled 1 Level INT6 is enabled 14 DLOGINT Data logging interrupt enable DLOGINT ena...

Page 217: ...BGIER is defined as a time critical interrupt When the CPU is halted in real time mode the only interrupts that are serviced are time critical interrupts that are also enabled in the IER If the CPU is...

Page 218: ...INT10 is enabled 8 INT9 Interrupt 9 enable INT9 enables or disables CPU interrupt level INT9 0 Level INT9 is disabled 1 Level INT9 is enabled 7 INT8 Interrupt 8 enable INT8 enables or disables CPU in...

Page 219: ...ved 0 ENABLE C28 XINT1 Enable 0 Interrupt disabled 1 Interrupt enabled 1 13 5 15 C28 External Interrupt 2 Configuration Register XINT2CR Figure 1 81 C28 External Interrupt 2 Configuration Register XIN...

Page 220: ...ng until the next valid interrupt edge is detected The counter must only be reset by the selected POLARITY edge as selected in the respective interrupt control register When the interrupt is disabled...

Page 221: ...g counter and will wrap around to zero when the max value is reached The counter is a read only register and can only be reset to zero by a valid interrupt edge or by the C28 SYSRSN reset 1 13 5 20 Sy...

Page 222: ...quency as PLLSYSCLK 1 C28 CPU CLKIN is turned off 1 13 6 Safety Control Registers 1 13 6 1 M3 Configuration Write Allow MWRALLOW Register Figure 1 88 M3 Configuration Write Allow MWRALLOW Register 31...

Page 223: ...ster 31 17 16 Reserved MCLKFLG R 0 0 R 0 15 8 7 0 Reserved REFCLKCNT R 0 0 R 0 0 LEGEND R W Read Write R Read only n value after reset Table 1 101 Missing Clock Status MCLKSTS Register Field Descripti...

Page 224: ...le reference clock input to the missing clock logic 1 Force reference clock off to the missing clock logic 1 13 6 5 Missing Clock Enable MCLKEN Register Figure 1 92 Missing Clock Enable MCLKEN Registe...

Page 225: ...by the PIE mismatch handler in C Boot ROM as mentioned in the safety features section of this chapter The user should initialize this register with the lower 16 bits of the application PIE mismatch ha...

Page 226: ...R W 0 0 LEGEND R W Read Write R Read only n value after reset Table 1 107 System PLL Multiplier SYSPLLMULT Register Field Descriptions Bit Field Value Description 31 10 Reserved Reserved 9 8 SPLLFMUL...

Page 227: ...Status SYSPLLSTS Register Figure 1 98 System PLL Lock Status SYSPLLSTS Register 31 2 1 0 Reserved SPLLSLIP S SYSPLLLO CKS R 0 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 1 10...

Page 228: ...Register Field Descriptions Bit Field Value Description 31 2 Reserved Reserved 1 0 XPLLCLKOUTDI V XPLLCLKOUT Divide Ratio This bit selects a clock divide ratio for the XPLLCLKOUT clock The configurat...

Page 229: ...LLCR register will be automatically forced to zero This prevents potential PLL overshoot The user will then have to write to the USBPLLCR register to configure the appropriate divisor ratio 0 X1 clock...

Page 230: ...switch to PLL bypass mode in the interrupt handler 0 USB PLL is not out of lock 1 USB PLL is out of lock 0 UPLLLOCKS USB PLL Lock Status This bit indicates whether the PLL is locked or not 0 USB PLL i...

Page 231: ...rs if the M3 CPU enters a sleep or deep sleep mode The RCGC registers are always used to control the clocks in run mode 0 The Run Mode Clock Gating Control RCGCx registers are used when the microcontr...

Page 232: ...aperture for Port C 0 Advanced Peripheral Bus APB This bus is the legacy bus 1 Advanced High Performance Bus AHB 1 PORT B PORT B AHB This bit defines the memory aperture for Port B 0 Advanced Peripher...

Page 233: ...set the module receives a clock and functions Otherwise it is unclocked and disabled If the module is unclocked reads or writes to the module generates bus faults 2 0 Reserved Reserved 1 13 7 15 Deep...

Page 234: ...it controls the clock gating for the TIMER2 module If set the module receives a clock and functions Otherwise it is unclocked and disabled If the module is unclocked reads or writes to the module gene...

Page 235: ...controls the clock gating for the UART2 module If set the module receives a clock and functions Otherwise it is unclocked and disabled If the module is unclocked reads or writes to the module generat...

Page 236: ...ts 11 8 Reserved Reserved 7 SSI3 SSI3 Clock Gating Control in Sleep Mode This bit controls the clock gating for the SSI3 module If set the module receives a clock and functions Otherwise it is unclock...

Page 237: ...he clock gating for the TIMER2 module If set the module receives a clock and functions Otherwise it is unclocked and disabled If the module is unclocked reads or writes to the module generates bus fau...

Page 238: ...Deep Sleep Mode This bit controls the clock gating for the UART2 module If set the module receives a clock and functions Otherwise it is unclocked and disabled If the module is unclocked reads or wri...

Page 239: ...a clock and functions Otherwise it is unclocked and disabled If the module is unclocked reads or writes to the module generates bus faults 5 GPIOF GPIOF Clock Gating Control in Run Mode This bit cont...

Page 240: ...his bit controls the clock gating for the DMA module If set the module receives a clock and functions Otherwise it is unclocked and disabled If the module is unclocked reads or writes to the module ge...

Page 241: ...Clock Gating Control in Sleep Mode This bit controls the clock gating for the GPIOC module If set the module receives a clock and functions Otherwise it is unclocked and disabled If the module is uncl...

Page 242: ...reads or writes to the module generates bus faults 12 9 Reserved Reserved 8 GPIOJ GPIOJ Clock Gating Control in Deep Sleep Mode This bit controls the clock gating for the GPIOJ module If set the modu...

Page 243: ...ck Gating Control Register 3 RCGC3 31 26 25 24 23 16 Reserved CAN1 CAN0 Reserved R 0 0 R W 0 R W 0 R 0 0 15 1 0 Reserved UART4 R 0 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1...

Page 244: ...24 23 16 Reserved CAN1 CAN0 Reserved R 0 0 R W 0 R W 0 R 0 0 15 1 0 Reserved UART4 R 0 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 130 Deep Sleep Mode Clock Gating Control Re...

Page 245: ...un mode 14 GPIOQ GPIOQ clock gating control in run mode 13 GPIOP GPIOP clock gating control in run mode 12 GPION GPION clock gating control in run mode 11 GPIOM GPIOM clock gating control in run mode...

Page 246: ...IOQ clock gating control in sleep mode 13 GPIOP GPIOP clock gating control in sleep mode 12 GPION GPION clock gating control in sleep mode 11 GPIOM GPIOM clock gating control in sleep mode 10 GPIOL GP...

Page 247: ...GPIOR GPIOR clock gating control in deep sleep mode 14 GPIOQ GPIOQ clock gating control in deep sleep mode 13 GPIOP GPIOP clock gating control in deep sleep mode 12 GPION GPION clock gating control in...

Page 248: ...Bit Field Value Description 31 27 Reserved Reserved 26 23 DSDIVOVRIDE Deep Sleep Divider Override Divider field override in deep sleep mode If Deep Sleep mode is enabled when the PLL is running the PL...

Page 249: ...cted clock source for CPU Timer 2 This selection is not affected by the missing clock detect circuit 0 0 0 1 default on reset 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reser...

Page 250: ...abled 3 Reserved Reserved 2 TBCLKSYNC ePWM Clock Sync When set PWM time bases of all modules start counting 1 Reserved Reserved 0 HRPWMENCLK HRPWM Clock Enable When set this enables the clock to the H...

Page 251: ...W 0 LEGEND R W Read Write R Read only n value after reset Table 1 138 Peripheral Clock Control Register 2 PCLKCR2 Register Field Descriptions Bit Field Value Description 15 9 Reserved Reserved 8 EQEP3...

Page 252: ...W 0 R W 1 R W 1 R W 1 7 0 Reserved R 0 0 LEGEND R W Read Write R Read only n value after reset Table 1 139 Peripheral Clock Control Register 3 PCLKCR3 Register Field Descriptions Bit Field Value Desc...

Page 253: ...ive to the C28 SYSCLKOUT 000 HSPCLK SYSCLKOUT 1 001 HSPCLK SYSCLKOUT 2 010 HSPCLK SYSCLKOUT 4 011 HSPCLK SYSCLKOUT 6 100 HSPCLK SYSCLKOUT 8 101 HSPCLK SYSCLKOUT 10 110 HSPCLK SYSCLKOUT 12 1 13 7 35 Lo...

Page 254: ...r Register CXCLK 15 2 1 0 Reserved XCLKOUTDIV R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 142 C28 XCLKOUT Divider Register CXCLK Field Descriptions Bit Field Value Descript...

Page 255: ...register 1 13 8 2 Z1_CSMKEY1 Register Figure 1 133 Z1_CSMKEY1 Register 31 0 CSMKEY R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 144 Z1_CSMKEY1 Register Field Descriptions Bit Fi...

Page 256: ...Description 31 0 ECSLKEY To disable ECSL logic active on the M3 zone1 write the same value in ECSLPSWD0 of zone1 to this register 1 13 8 6 Z1_ECSLKEY1 Register Figure 1 137 Z1_ECSLKEY1 Register 31 0...

Page 257: ...ister Figure 1 140 Z2_CSMKEY2 Register 31 0 CSMKEY R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 151 Z2_CSMKEY2 Register Field Descriptions Bit Field Value Description 31 0 CSMKE...

Page 258: ...14 13 12 11 10 9 8 FORCESEC Reserved ECSL ARMED CSM ARMED ECSL MATCH CSM MATCH ECSL ALLONE R 0 W 1 R 0 R 0 R 0 R x R x R x 7 6 5 4 0 CSM ALLONE ECSL ALLZERO CSM ALLZERO Reserved R x R x R x R 0 LEGEN...

Page 259: ...word of M3 Zone1 contains all 1 s 7 CSM ALLONE Shows the state of CSM Password programmed in Flash This is valid only when CSM_ARMED 1 0 CSM Passwords of M3 Zone1 does not contain all 1 s 1 CSM Passwo...

Page 260: ...ECSL MATCH Status bit indicate if ECSL is enabled or disabled for M3 zone2 This is valid only when ECSL_ARMED 1 0 M3 Zone2 ECSL is disabled 1 M3 Zone2 ECSL is enabled 9 CSM MATCH Status bit that refl...

Page 261: ...SECT 21 20 when a read is issued to the address location of Z1_GRABSECT in flash 00 Invalid M3 Flash Sector C is inaccessible 01 Request to allocate M3 Flash Sector C to M3 Zone1 10 Request to allocat...

Page 262: ...10 Request to allocate M3 Flash Sector I to M3 Zone1 11 Request to make M3 Flash Sector I Non Secure 7 6 GRABSECTJ Value in this field gets loaded from Z1_GRABSECT 7 6 when a read is issued to the ad...

Page 263: ...is inaccessible 01 Request to allocate M3 C1 RAM to M3 Zone1 10 Request to allocate M3 C1 RAM to M3 Zone1 11 Request to make M3 C1 RAM Non Secure 1 0 GRABRAM_C0 Value in this field gets loaded from Z...

Page 264: ...ssued to the address location of Z2_GRABSECT in flash 00 Invalid M3 Flash Sector E is inaccessible 01 Request to allocate M3 Flash Sector E to M3 Zone2 10 Request to allocate M3 Flash Sector E to M3 Z...

Page 265: ...SECT 3 2 when a read is issued to the address location of Z2_GRABSECT in flash 00 Invalid M3 Flash Sector L is inaccessible 01 Request to allocate M3 Flash Sector L to M3 Zone2 10 Request to allocate...

Page 266: ...Table 1 160 Z2_GRABRAMR Register Field Descriptions continued Bit Field Value Description 1 0 GRABRAM_C0 Value in this field gets loaded from Z2_GRABRAM 1 0 when a read is issued to the address locat...

Page 267: ...only is enabled for Sector C on Zone 1 1 Execute only is disabled for Sector C on Zone 1 10 EXEONLY_SECT D Execute only select register sector D 0 Execute only is enabled for Sector D on Zone 1 1 Exe...

Page 268: ...ter Figure 1 151 Z2_EXEONLYR Register 31 24 Reserved R 0 23 16 Reserved R 0 15 13 12 11 10 9 8 Reserved EXEONLY_SECTB EXEONLY_SECTC EXEONLY_SECTD EXEONLY_SECTE EXEONLY_SECTF R 0 R 0 R 0 R 0 R 0 R 0 7...

Page 269: ...elect register Sector K 0 Execute only is enabled for Sector K on Zone 2 1 Execute only is disabled for Sector K on Zone 2 2 EXEONLY_SECT L Execute only select register Sector L 0 Execute only is enab...

Page 270: ...belongs to M3 Zone2 11 8 M3Z1PSWDLOCK Value in this field gets loaded from OTPSECLOCK 11 8 when a read is issued to the OTPSECLOCK address location in OTP 0 M3 Zone1 CSM ECSL passwords can be accessed...

Page 271: ...gister 1 13 9 2 CSMKEY1 Register Figure 1 154 CSMKEY1 Register 31 0 CSMKEY R W 0 LEGEND R W Read Write R Read only n value after reset Table 1 165 CSMKEY1 Register Field Descriptions Bit Field Value D...

Page 272: ...clear bit 1 Clears the KEY registers and makes the control subsystem secure The password match flow described in Section 1 10 3 2 must be followed to unsecure zone1 again 14 11 Reserved Reserved 10 EC...

Page 273: ...hows the state of CSM Password programmed in Flash This is valid only when CSM_ARMED 1 0 CSM Passwords of control subsystem does not contain all 0 s 1 CSM Passwords of control subsystem contains all 0...

Page 274: ...n is disabled for C28x Flash Sector B only if it is allocated to the control subsystem 11 EXEONLY_SECT C Value in this field gets loaded from EXEONLY 11 11 when a read is issued to the EXEONLY address...

Page 275: ...ed to the control subsystem 1 Execute Only protection is disabled for C28x Flash Sector J only if it is allocated to the control subsystem 3 EXEONLY_SECT K Value in this field gets loaded from EXEONLY...

Page 276: ...e the polynomial used for CRC calculation 00 CRC8 Polynomial 0x07 01 CRC16 P1 Polynomial 0x8005 10 CRC16 P2 Polynomial 0x1021 11 CRC32 Polynomial 0x04C11DB7 1 13 10 2 CRCCONTROL Register Figure 1 162...

Page 277: ...ister it is readable in the MTOCIPCFLG and STS registers 29 IPC30 0 MTOCIPCSET Flag 30 M3 to C28 core IPC flag 30 set If a bit is set by writing a 1 then the corresponding bit in MTOCIPCFLG is set The...

Page 278: ...PC14 0 MTOCIPCSET Flag 14 M3 to C28 core IPC flag 14 set If a bit is set by writing a 1 then the corresponding bit in MTOCIPCFLG is set The status of this bit is not readable in this register it is re...

Page 279: ...re IPC flag 32 clear If a bit is cleared by writing a 1 then the corresponding bit in MTOCIPCFLG is cleared The status of this bit is not readable in this register it is readable in the MTOCIPCFLG and...

Page 280: ...sters 14 IPC15 0 MTOCIPCCLR Flag 15 M3 to C28 core IPC flag 15 clear If a bit is cleared by writing a 1 then the corresponding bit in MTOCIPCFLG is cleared The status of this bit is not readable in th...

Page 281: ...19 18 17 16 IPC24 IPC23 IPC22 IPC21 IPC20 IPC19 IPC18 IPC17 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 IPC16 IPC15 IPC14 IPC13 IPC12 IPC11 IPC10 IPC9 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 7 6 5 4...

Page 282: ...MTOCIPCCLR or MTOCIPCACK bit has not been written with a 1 15 IPC16 0 MTOCIPCFLG Flag 16 M3 to C28 core IPC flag 16 status The bit is 1 if the corresponding MTOCIPCSET bit has been written with a 1 an...

Page 283: ...5 IPC14 IPC13 IPC12 IPC11 IPC10 IPC9 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 7 6 5 4 3 2 1 0 IPC8 IPC7 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND R W Read Write R Read only n value a...

Page 284: ...16 IPC17 0 CTOMIPCACK Flag 17 C28 to M3 core IPC flag 17 acknowledge Writing a 1 to this bit clears the corresponding bit in CTOMIPCFLG and CTOMIPCSTS to 0 The status of this bit is not readable in t...

Page 285: ...knowledge Writing a 1 to this bit clears the corresponding bit in CTOMIPCFLG and CTOMIPCSTS to 0 The status of this bit is not readable in this register it is readable in the CTOMIPCFLG and STS regist...

Page 286: ...TOMIPCCLR or CTOMIPCACK bit has not been written with a 1 17 IPC18 0 CTOMIPCSTS Flag 18 C28 to M3 core IPC flag 18 status The bit is 1 if the corresponding CTOMIPCSET bit has been written with a 1 and...

Page 287: ...SET bit has been written with a 1 and CTOMIPCCLR or CTOMIPCACK bit has not been written with a 1 1 IPC2 0 CTOMIPCSTS Interrupt 2 C28 to M3 IPC interrupt 2 status flag The bit is 1 if the corresponding...

Page 288: ...of 00 10 11 gives ownership to the M3 A value of 01 gives ownership to the C28 The following are the only state transitions allowed on these bits 00 11 01 00 11 10 10 00 11 This can only happen from...

Page 289: ...0 CTOMIPCSET Flag 23 C28 to M3 core IPC flag 23 set If a bit is set by writing a 1 then the corresponding bit in CTOMIPCFLG is set The status of this bit is not readable in this register it is readabl...

Page 290: ...by writing a 1 then the corresponding bit in CTOMIPCFLG is set The status of this bit is not readable in this register it is readable in the CTOMIPCFLG and STS registers 4 IPC5 0 CTOMIPCSET Flag 5 C28...

Page 291: ...LR Flag 23 C28 to M3 core IPC flag 23 clear If a bit is cleared by writing a 1 then the corresponding bit in CTOMIPCFLG is cleared The status of this bit is not readable in this register it is readabl...

Page 292: ...t is cleared by writing a 1 then the corresponding bit in CTOMIPCFLG is cleared The status of this bit is not readable in this register it is readable in the CTOMIPCFLG and STS registers 4 IPC5 0 CTOM...

Page 293: ...bit has not been written with a 1 22 IPC23 0 CTOMIPCFLG Flag 23 C28 to M3 core IPC flag 23 status The bit is 1 if the corresponding CTOMIPCSET bit has been written with a 1 and CTOMIPCCLR or CTOMIPCA...

Page 294: ...8 to M3 core IPC flag 6 status The bit is 1 if the corresponding CTOMIPCSET bit has been written with a 1 and CTOMIPCCLR or CTOMIPCACK bit has not been written with a 1 4 IPC5 0 CTOMIPCFLG Flag 5 C28...

Page 295: ...23 M3 to C28 core IPC flag 23 acknowledge Writing a 1 to this bit clears the corresponding bit in MTOCIPCFLG and MTOCIPCSTS to 0 The status of this bit is not readable in this register it is readable...

Page 296: ...Flag 6 M3 to C28 core IPC flag 6 acknowledge Writing a 1 to this bit clears the corresponding bit in MTOCIPCFLG and MTOCIPCSTS to 0 The status of this bit is not readable in this register it is reada...

Page 297: ...bit has not been written with a 1 22 IPC23 0 MTOCIPCSTS Flag 23 M3 to C28 core IPC flag 23 status The bit is 1 if the corresponding MTOCIPCSET bit has been written with a 1 and MTOCIPCCLR or MTOCIPCA...

Page 298: ...TOCIPCSTS Flag 6 M3 to C28 core IPC flag 6 status The bit is 1 if the corresponding MTOCIPCSET bit has been written with a 1 and MTOCIPCCLR or MTOCIPCACK bit has not been written with a 1 4 IPC5 0 MTO...

Page 299: ...ship 1 13 12 7 C28 Clock Semaphore Register Figure 1 177 C28 Clock Semaphore Register 31 16 KEY R 0 W 15 4 3 2 1 0 KEY Reserved SEM R 0 W R 0 R W 0 LEGEND R W Read Write R Read only n value after rese...

Page 300: ...his is the low 32 bits of the free running 64 bit timestamp counter clocked by the shared resource clock 1 13 13 2 MIPCCOUNTERH Register Figure 1 179 MIPCCOUNTERH Register 31 0 COUNT R 0 LEGEND R W Re...

Page 301: ...W 0 LEGEND R W Read Write R Read only n value after reset Table 1 194 CTOMIPCDATAW Register Field Descriptions Bit Field Value Description 31 0 WDATA 0 C28 TO M3 IPC Data Write Registe This register i...

Page 302: ...ncorporated System Control and Interrupts Table 1 196 MTOCIPCCOM Register Field Descriptions Bit Field Value Description 31 0 COMMAND 0 M3 TO C28 IPC Command Register This register is defined and inte...

Page 303: ...0 LEGEND R W Read Write R Read only n value after reset Table 1 198 MTOCIPCDATAW Register Field Descriptions Bit Field Value Description 31 0 WDATA 0 M3 TO C28 IPC Data Write Register This register is...

Page 304: ...writes the boot status code that can be read by the M3 to report the boot condition of the C28 It is read write to the C28 CPU and read only to the M3 CPU 1 13 13 12 MTOCIPCBOOTMODE Register Figure 1...

Page 305: ...M blocks Each GPTM block provides two 16 bit timers counters referred to as Timer A and Timer B that can be configured to operate independently as timers or event counters or concatenated to operate a...

Page 306: ...e one shot timer 16 or 32 bit programmable periodic timer 16 bit general purpose timer with an 8 bit prescaler 32 bit real time clock RTC when using an external 32 768 KHz clock as the input 16 bit in...

Page 307: ...the most significant bits of the count 1 The prescaler is only available when the timers are used individually Table 2 2 General Purpose Timer Capabilities Mode Timer Use Count Direction Counter Size...

Page 308: ...he actual free running value of the timer at the time out event is loaded into the GPTMTnR register In this manner software can determine the time elapsed from the interrupt assertion to the ISR entry...

Page 309: ...unction is valid for both one shot and periodic modes Figure 2 2 Timer Daisy Chain 2 3 2 2 Real Time Clock Timer Mode In real time clock RTC mode the concatenated versions of the Timer A and Timer B r...

Page 310: ...rence between the value in the GPTMTnILR and GPTMTnPR registers and the GPTMTnMATCHR and GPTMTnPMR registers equals the number of edge events that must be counted When software writes the TnEN bit in...

Page 311: ...r event capture When the selected input event is detected the current timer counter value is captured in the GPTMTnR register and is available to be read by the microcontroller The GPTM then asserts t...

Page 312: ...tart state and is deasserted when the counter value equals the value in the GPTMTnMATCHR register Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the GPTMCT...

Page 313: ...the appropriate GPIO module must be enabled via the RCGC1 register see the System Control chapter To find out which GPIO port to enable refer to the PMCn fields in the GPIOPCTL register to assign the...

Page 314: ...ite the GPTM Configuration GPTMCFG register with a value of 0x0000 0004 3 In the GPTM Timer Mode GPTMTnMR register write the TnCMR field to 0x0 and the TnMR field to 0x3 4 Configure the type of event...

Page 315: ...d the timer start value into the GPTM Timer n Interval Load GPTMTnILR register 6 Load the GPTM Timer n Match GPTMTnMATCHR register with the match value 7 Set the TnEN bit in the GPTM Control GPTMCTL r...

Page 316: ...l order by address offset 2 6 1 GPTM Configuration GPTMCFG Register offset 0x000 The GPTM Configuration GPTMCFG register configures the global operation of the GPTM module The value written to this re...

Page 317: ...mer A GPTMTAR register 6 TAWOT GPTM Timer A Wait on Trigger 0 Timer A begins counting as soon as it is enabled 1 If Timer A is enabled TAEN is set in the GPTMCTL register Timer A does not begin counti...

Page 318: ...Bit Field Value Description 31 8 Reserved Reserved 7 TBSNAPS GPTM Timer B Snap Shot Mode 0 Snap shot mode is disabled 1 If Timer B is configured in the periodic mode the actual free running value of T...

Page 319: ...9 GPTM Control GPTMCTL Register 31 16 Reserved R 0 15 14 13 12 11 10 9 8 Reserved TBPWML Reserved TBEVENT TBSTALL TBEN R 0 R W 0 R 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 Reserved TAPWML Reserved RTCEN T...

Page 320: ...A Enable 0 Timer A is disabled 1 Timer A is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register 2 6 5 GPTM Interrupt Mask GPTMIMR Register offset 0x018 The GPTM I...

Page 321: ...M GPTM Timer A Time Out Interrupt Mask 0 Interrupt is disabled 1 Interrupt is enabled 2 6 6 GPTM Raw Interrupt Status GPTMRIS Register offset 0x01C The GPTM Raw Interrupt Status GPTMRIS register shows...

Page 322: ...TM RTC Raw Interrupt 0 The RTC event has not occurred 1 The RTC event has occurred 2 CAERIS GPTM Capture A Event Raw Interrupt 0 The Capture A event has not occurred 1 The Capture A event has occurred...

Page 323: ...OCINT bit in the GPTMICR register 7 5 Reserved 4 TAMMIS GPTM Timer A Mode Match Raw Interrupt 0 A Timer A Mode Match interrupt has not occurred or is masked 1 An unmasked Timer A Mode Match interrupt...

Page 324: ...MIS bit in the GPTMMIS register 7 5 Reserved Reserved 4 TAMCINT GPTM Timer A Mode Match Interrupt Clear Writing a 1 to this bit clears the TAMRIS bit in the GPTMRIS register and the TAMMIS bit in the...

Page 325: ...ved in both cases Figure 2 15 GPTM Timer A Interval Load GPTMTBILR Register 31 16 15 0 Reserved TBILR R 0 R W 1 LEGEND R W Read Write R Read only n value after reset Table 2 14 GPTM Timer A Interval L...

Page 326: ...ng with GPTMTBILR determines the duty cycle of the output PWM signal When a GPTM is configured to one of the 32 bit modes the contents of bits 15 0 in this register are loaded into the upper 16 bits o...

Page 327: ...BPR Register Field Descriptions Bit Field Value Description 31 8 Reserved Reserved 7 0 TBPSR 0x00 GPTM Timer B Prescale The register loads this value on a write A read returns the current value of the...

Page 328: ...the count Bits 31 24 always read as 0 To read the value of the prescaler in 16 bit One Shot and Periodic modes read bits 23 16 in the GPTMTAV register Figure 2 22 GPTM Timer A GPTMTAR Register 31 0 TA...

Page 329: ...egister In a 16 bit mode bits 15 0 contain the value of the counter and bits 23 16 contain the current free running value of the prescaler which is the upper 8 bits of the count Bits 31 24 always read...

Page 330: ...gister 31 16 15 0 Reserved TBV R W 1 LEGEND R W Read Write R Read only n value after reset Table 2 24 GPTM Timer B Value GPTMTBV Register Field Descriptions Bit Field Value Description 31 16 Reserved...

Page 331: ...Timers Chapter 3 SPRUHE8E October 2012 Revised November 2019 M3 Watchdog Timers This chapter discusses the functions of the Watchdog Timer 0 and Watchdog Timer 1 modules A watchdog timer can generate...

Page 332: ...ferent clock domain and therefore requires synchronizers As a result WDT1 has a bit defined in the watchdog timer control WDTCTL register to indicate when a write to a WDT1 register is complete Softwa...

Page 333: ...written with a timing gap between accesses Software must guarantee that this delay is inserted between back to back writes to WDT1 registers or between a write followed by a read to the registers The...

Page 334: ...eral Identification 1 0xFE8 WDTPeriphID2 R 0x0000 0018 Watchdog Peripheral Identification 2 0xFEC WDTPeriphID3 R 0x0000 0001 Watchdog Peripheral Identification 3 0xFF0 WDTPCellID0 R 0x0000 000D Watchd...

Page 335: ...WDTVALUE Register offset 0x004 The watchdog value WDTVALUE register contains the current count value of the timer Figure 3 3 Watchdog Value WDTVALUE Register 31 0 WDTVALUE R 0xFFFF FFFF LEGEND R W Re...

Page 336: ...es not have this restriction as it runs off the system clock and therefore does not have a WRC bit Figure 3 4 Watchdog Control WDTCTL Register 31 30 2 1 0 WRC Reserved RESEN ITEN R 1 R 0 R W 0 R W 0 L...

Page 337: ...on 31 1 Reserved Reserved 0 WDTRIS Watchdog raw interrupt status 0 The watchdog has not timed out 1 A watchdog time out event has occurred 3 3 6 Watchdog Masked Interrupt Status WDTMIS Register offset...

Page 338: ...served Reserved 3 3 8 Watchdog Lock WDTLOCK Register offset 0xC00 Writing 0x1ACC E551 to the watchdog lock WDTLOCK register enables write access to all other registers Writing any other value to the W...

Page 339: ...chdog peripheral identification WDTPeriphIDn registers are hard coded and the fields within the register determine the reset value Figure 3 11 Watchdog Peripheral Identification 5 WDTPeriphID5 Registe...

Page 340: ...atchdog peripheral identification WDTPeriphIDn registers are hard coded and the fields within the register determine the reset value Figure 3 14 Watchdog Peripheral Identification 0 WDTPeriphID0 Regis...

Page 341: ...watchdog peripheral identification WDTPeriphIDn registers are hard coded and the fields within the register determine the reset value Figure 3 17 Watchdog Peripheral Identification 3 WDTPeriphID3 Regi...

Page 342: ...hdog primecell identification WDTPCellIDn registers are hard coded and the fields within the register determine the reset value Figure 3 20 Watchdog PrimeCell Identification 2 WDTPCellID2 Register 31...

Page 343: ...of GPIO192 GPIO199 The GPIOCSELx register can be used to give the C28 core control of any GPIO If the M3 core has control of a GPIO the M3 muxing options can be used and if the C28 core has control o...

Page 344: ...the above nine GPIO blocks an additional eight GPIO blocks each corresponding to an individual GPIO port Port K Port L Port M Port N Port P Port Q Port R Port S are available on this device These port...

Page 345: ...PIO9 CCP2 CCP1 U1Tx SSI2Rx PB2_GPIO1 0 I2C0SCL CCP3 CCP0 USB0EPEN SSI2Clk CAN1Rx U4Rx PB3_GPIO1 1 I2C0SDA USB0PFLT SSI2Fss U1Rx PB4_GPIO1 2 U2Rx CAN0Rx U1Rx EPI0S23 CAN1Tx SSI1Tx PB5_GPIO1 3 CCP5 CCP6...

Page 346: ...SSI1Rx CCP2 EPI0S24 SSI3Clk U2Rx SSI1Clk PE3_GPIO2 7 CCP1 SSI1Tx CCP7 EPI0S25 SSI3Fss U2Tx SSI1Fss PE4_GPIO2 8 CCP3 U2Tx CCP2 MII_RXD0 U0Rx USB0EPEN PE5_GPIO2 9 CCP5 MII_TXER U0Tx USB0PFLT PE6_GPIO3 0...

Page 347: ...D3 SSI3Clk MII_TXD1 PH3_GPIO5 1 USB0EPEN ODMSE0 EPI0S0 MII_TXD2 SSI3Fss MII_TXD0 PH4_GPIO5 2 USB0PFLT ODPDAT EPI0S10 MII_TXD1 SSI1Clk U3Tx MII_COL PH5_GPIO5 3 EPI0S11 MII_TXD0 SSI1Fss U3Rx MII_PHYRS T...

Page 348: ...XCK SSI0Rx PK6_GPIO7 8 MII_TXER SSI0Clk PK7_GPIO7 9 MII_CRS SSI0Fss PL0_GPIO8 0 MII_RXD3 SSI1Tx PL1_GPIO8 1 MII_RXD2 SSI1Rx PL2_GPIO8 2 MII_RXD1 SSI1Clk PL3_GPIO8 3 MII_RXD0 SSI1Fss PL4_GPIO8 4 MII_CO...

Page 349: ...8 9 10 11 12 Alt 13 Alt 14 Alt 15 Alt PN4_GPIO1 00 U3Tx PN5_GPIO1 01 U3Rx PN6_GPIO1 02 U4Rx USB0EPEN PN7_GPIO1 03 U4Tx USB0PFLT PP0_GPIO1 04 I2C1SCL PP1_GPIO1 05 I2C1SDA PP2_GPIO1 06 I2C0SCL PP3_GPIO...

Page 350: ...eral Purpose Input Output GPIO Table 4 1 GPIO Pins and Alternate Functions continued GPIO Analog I O 1 2 3 4 5 6 7 8 9 10 11 12 Alt 13 Alt 14 Alt 15 Alt PR4_GPIO1 24 PR5_GPIO1 25 PR6_GPIO1 26 PR7_GPIO...

Page 351: ...O Mux also contains an alternate muxing mode The proper bits in the Alternate Peripheral Select GPIOAPSEL register must be set to access these muxing options The Digital Function GPIOPCTL register can...

Page 352: ...responding data register bit is driven out on the GPIO port 4 1 3 2 2 Data Register Operation To aid in the efficiency of software the GPIO ports allow for the modification of individual bits in the G...

Page 353: ...GPIOIBE or GPIOIEV the interrupts should be masked GPIOIM cleared Writing any value to an interrupt control register can generate a spurious interrupt if the corresponding bits are enabled 4 1 3 4 Mod...

Page 354: ...a rising edge interrupt is configured for pin 2 of a GPIO port It is recommended to configure the GPIOPCTL register before configuring the GPIOAFSEL register For example referring to the ControlSuite...

Page 355: ...B offers the same register map but provides better back to back access performance than the APB bus NOTE The GPIO registers in this chapter are duplicated in each GPIO block however depending on the b...

Page 356: ...GPIO Register Map Offset Name Type Reset Description 0x000 GPIODATA R W 0x0000 0000 GPIO Data 0X400 GPIODIR R W 0x0000 0000 GPIO Direction 0x404 GPIOIS R W 0x0000 0000 GPIO Interrupt Sense 0x408 GPIOI...

Page 357: ...he address bus bits 9 2 must be set Otherwise the bit values remain unchanged by the write Similarly the values read from this register are determined for each bit by the mask bit derived from the add...

Page 358: ...ection GPIODIR Register Field Descriptions Bit Field Value Description 31 8 Reserved Reserved 7 0 DIR GPIO Data Direction 0 Corresponding pin as an input 1 Corresponding pin as an output 4 1 6 3 GPIO...

Page 359: ...t Field Value Description 31 8 Reserved Reserved 7 0 IBE GPIO Interrupt Both Edges 0 Interrupt generation is controlled by the GPIO Interrupt Event GPIOIEV register 1 Both edges on the corresponding p...

Page 360: ...register is the raw interrupt status register A bit in this register is set when an interrupt condition occurs on the corresponding GPIO pin If the corresponding bit in the GPIO Interrupt Mask GPIOIM...

Page 361: ...terrupt condition on the corresponding pin has triggered an interrupt to the interrupt controller A bit is cleared by writing a 1 to the corresponding bit in the GPIOICR register 4 1 6 9 GPIO Interrup...

Page 362: ...bugger may be locked out of the part This issue can be avoided with a software routine that restores JTAG functionality based on an external or software trigger The GPIO commit control registers provi...

Page 363: ...criptions Bit Field Value Description 31 8 Reserved Reserved 7 0 ODE Output Pad Open Drain Enable 0 The corresponding pin is not configured as open drain 1 The corresponding pin is configured as open...

Page 364: ...put or output either GPIO or alternate function the corresponding GPIODEN bit must be set Important All GPIO pins are configured as GPIOs and tri stated by default GPIOAFSEL 0 GPIODEN 0 GPIOPUR 0 and...

Page 365: ...egister is locked and may not be modified 4 1 6 15 GPIO Commit GPIOCR Register offset 0x524 The GPIOCR register is the commit register The value of the GPIOCR register determines which bits of the GPI...

Page 366: ...eset value for the GPIOCR register is 0x0000 00FF for all GPIO pins with the exception of the NMI pin PB7 To ensure that the NMI pin is not accidentally programmed as the non maskable interrupt pin it...

Page 367: ...L 0 GPIODEN 0 GPIOPUR 0 and GPIOPCTL 0 A Power On Reset POR or asserting XRS puts the pins back to their default state Figure 4 20 GPIO Port Control GPIOPCTL Register 31 28 27 24 23 20 19 16 PMC7 PMC6...

Page 368: ...Alternate Peripheral Select GPIOAPSEL Register Field Descriptions Bit Field Value Description 31 8 Reserved Reserved 7 APSEL7 Alternate peripheral select 7 0 Alternate peripheral mode disabled 1 Alter...

Page 369: ...storage unless the GPIO Lock GPIOLOCK register has been unlocked and the appropriate bits of the GPIO Commit GPIOCR register have been set Figure 4 22 GPIO Core Select GPIOCSEL Register 31 16 Reserve...

Page 370: ...and GPIOPeriphID7 registers can conceptually be treated as one 32 bit register each register contains eight bits of the 32 bit register used by software to identify the peripheral Figure 4 23 GPIO Pe...

Page 371: ...and GPIOPeriphID7 registers can conceptually be treated as one 32 bit register each register contains eight bits of the 32 bit register used by software to identify the peripheral Figure 4 24 GPIO Pe...

Page 372: ...and GPIOPeriphID7 registers can conceptually be treated as one 32 bit register each register contains eight bits of the 32 bit register used by software to identify the peripheral Figure 4 25 GPIO Per...

Page 373: ...and GPIOPeriphID7 registers can conceptually be treated as one 32 bit register each register contains eight bits of the 32 bit register used by software to identify the peripheral Figure 4 26 GPIO Per...

Page 374: ...0 GPIOPeriphID0 Register Field Descriptions Bit Field Value Description 31 8 Reserved Reserved 7 0 PID0 GPIO Peripheral ID Register 7 0 Can be used by software to identify the presence of this periphe...

Page 375: ...by software to identify the presence of this peripheral 4 1 6 27 GPIO Peripheral Identification 3 GPIOPeriphID3 offset 0xFEC The GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 and GPIOPeriphID3 registers c...

Page 376: ...as one 32 bit register The register is used as a standard cross peripheral identification system Figure 4 32 GPIO PrimeCell Identification 1 GPIOPCellID1 Register 31 16 Reserved R 0 15 8 7 0 Reserved...

Page 377: ...ication 3 GPIOPCellID3 offset 0xFFC The GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 and GPIOPCellID3 registers are four 8 bit wide registers that can conceptually be treated as one 32 bit register The regi...

Page 378: ...n registers If selected for digital I O mode registers are provided to configure the pin direction via the GPxDIR registers You can also qualify the input signals to remove unwanted noise via the GPxQ...

Page 379: ...eripheral 2 output enable Peripheral 3 output enable 1 A www ti com C28 General Purpose Input Output GPIO 379 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2...

Page 380: ...Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated General Purpose Input Output GPIO Figure 4 36 GPIO32 GPIO33 Multiplexing Diagram A GPxDAT latch r...

Page 381: ...Output GPIO 381 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated General Purpose Input Output GPIO Figure 4 37 GPIO34 GPIO19...

Page 382: ...UX1 Reg 1 0 AIOxDIR 1 Input 0 Output 0 Input 1 Output AIODIR Reg Latch 0 C28 General Purpose Input Output GPIO www ti com 382 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback...

Page 383: ...SYNCIN ePWM 0 PU disabled reset value 1 PU enabled ADCEXTTRIG www ti com C28 General Purpose Input Output GPIO 383 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2...

Page 384: ...RL 0x5F90 2 GPIO B Control Register GPIO32 GPIO63 GPBQSEL1 0x5F92 2 GPIO B Qualifier Select 1 Register GPIO32 GPIO47 GPBQSEL2 0x5F94 2 GPIO B Qualifier Select 2 Register GPIO48 GPIO63 GPBMUX1 0x5F96 2...

Page 385: ...egister GPIO0 GPIO63 GPIOLPMSEL1 0x5FE8 2 LPM GPIO Select 1 Register GPIO0 GPIO31 GPIOLPMSEL2 0x5FEA 2 LPM GPIO Select 2 Register GPIO32 GPIO63 GPTRIP9SEL 0x5FF0 1 GPTRIP9 ECAP3 Input Select Register...

Page 386: ...tput in the GPADIR GPBDIR GPCDIR GPEDIR or AIODIR registers By default all GPIO pins are inputs To change the pin from input to output first load the output latch with the value to be driven by writin...

Page 387: ...GPACLEAR 0x5FC4 4 GPIO A Clear Register GPIO0 GPIO31 GPATOGGLE 0x5FC6 4 GPIO A Toggle Register GPIO0 GPIO31 GPBDAT 0x5FC8 4 GPIO B Data Register GPIO32 GPIO63 GPBSET 0x5FCA 4 GPIO B Set Register GPIO3...

Page 388: ...te of GPIO pins An example is shown below where two program statements attempt to drive two different GPIO pins that are currently low to a high state If Read Modify Write operations are used on the G...

Page 389: ...r each GPIO pin by configuring the GPxQSEL1 and GPxQSEL2 registers In the case of a GPIO input pin the qualification can be specified as only synchronize to SYSCLKOUT or qualification by a sampling wi...

Page 390: ...r The sampling period is configurable in groups of 8 input signals For example GPIO0 to GPIO7 use GPACTRL QUALPRD0 setting and GPIO8 to GPIO15 use GPACTRL QUALPRD1 Table 4 39 and Table 4 40 show the r...

Page 391: ...d in Table 4 39 Likewise for a six sample window the sampling window width is 5 sampling periods wide Table 4 41 and Table 4 42 show the calculations that can be used to determine the total sampling w...

Page 392: ...CLKOUT cycles or greater In other words the inputs should be stable for 5 x QUALPRD x 2 SYSCLKOUT cycles That would ensure 5 sampling periods for detection to occur Since external signals are driven a...

Page 393: ...ions The GPIO6 pin can be configured as follows GPAMUX1 13 12 Bit Setting Pin Functionality Selected If GPAMUX1 13 12 0 0 Pin configured as GPIO6 If GPAMUX1 13 12 0 1 Pin configured as EPWM4A O If GPA...

Page 394: ...nction in the GPxMUX1 2 registers or if no pin has been assigned Table 4 43 Default State of Peripheral Input Peripheral Input Description Default Input 1 TZ1 TZ3 Trip zone 1 3 1 EPWMSYNCI ePWM Synch...

Page 395: ...Reserved 27 26 GPIO13 EPWM7B O Reserved Reserved 29 28 GPIO14 EPWM8A O Reserved Reserved 31 30 GPIO15 EPWM8B O Reserved Reserved GPAMUX2 Register Bits GPAMUX2 bits 00 GPAMUX2 bits 01 GPAMUX2 bits 10 G...

Page 396: ...ed Reserved Reserved 21 20 GPIO42 Reserved Reserved Reserved 23 22 GPIO43 Reserved Reserved Reserved 25 24 GPIO44 Reserved Reserved Reserved 27 26 GPIO45 Reserved Reserved Reserved 29 28 GPIO46 Reserv...

Page 397: ...eserved 21 20 PK2_GPIO74 SPICLKA Reserved Reserved 23 22 PK3_GPIO75 SPISTEA Reserved Reserved 25 24 PK4_GPIO76 Reserved Reserved Reserved 27 26 PK5_GPIO77 Reserved Reserved Reserved 29 28 PK6_GPIO78 R...

Page 398: ...rved Reserved 21 20 PP2_GPIO106 EQEP1A Reserved Reserved 23 22 PP3_GPIO107 EQEP1B Reserved Reserved 25 24 PP4_GPIO108 EQEP1S Reserved Reserved 27 26 PP5_GPIO109 EQEP1I Reserved Reserved 29 28 PP6_GPIO...

Page 399: ...1 Peripheral Selection 2 Peripheral Selection 3 C28 GPEMUX1 Register Bits C28 GPEMUX1 bits 00 C28 GPEMUX1 bits 01 C28 GPEMUX1 bits 10 C28 GPEMUX1 bits 11 1 0 PS0_GPIO128 EPWM9A Reserved Reserved 3 2...

Page 400: ...on1 Peripheral Selection 2 and Peripheral Selection 3 AIOMUX1 Register bits AIOMUX1 bits 0 x AIOMUX1 bits 1 x 1 0 ADCINA0 I ADCINA0 I 3 2 ADCINA1 I ADCINA1 I 5 4 AIO2 I O ADCINA2 I COMP1A I 7 6 ADCINA...

Page 401: ...orated General Purpose Input Output GPIO Table 4 50 Analog MUX continued Default at Reset AIOx and Peripheral Selection1 Peripheral Selection 2 and Peripheral Selection 3 AIOMUX1 Register bits AIOMUX1...

Page 402: ...lue after reset 1 This register is EALLOW protected Table 4 51 GPIO Port A Multiplexing 1 GPAMUX1 Register Field Descriptions Bits Field Value Description 1 31 30 GPIO15 Configure the GPIO15 pin as 00...

Page 403: ...output B O 10 MCLKRA McBSP A receive clock I O 11 ECAP2 eCAP2 I O 13 12 GPIO6 Configure the GPIO6 pin as 00 GPIO6 General purpose I O 6 default 01 EPWM4A ePWM4 output A O 10 Reserved 11 EPWMSYNCO ePW...

Page 404: ...W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset 1 If reserved configurations are selected then the state of the pin will be undefined and the pin m...

Page 405: ...Reserved 15 14 GPIO23 Configure the GPIO23 pin as 00 GPIO23 General purpose I O 23 default I O 01 EQEP1I eQEP1 index I O 10 MFSXA McBSP A transmit frame synch I O 11 Reserved 13 12 GPIO22 Configure th...

Page 406: ...ble below Figure 4 44 GPIO Port B MUX 1 GPBMUX1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GPIO47 GPIO46 GPIO45 GPIO44 GPIO43 GPIO42 GPIO41 GPIO40 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W...

Page 407: ...eneral purpose I O 41 default 01 Reserved 10 Reserved 11 Reserved 17 16 GPIO40 Configure this pin as 00 GPIO 40 general purpose I O 40 default 01 Reserved 10 Reserved 11 Reserved 15 14 GPIO39 Configur...

Page 408: ...CIRXDA SCI A receive data I 11 ADCSOCAO ADC start of conversion A O 4 2 7 4 GPIO Port B MUX 2 GPBMUX2 Register The GPIO Port B MUX 2 GPBMUX2 register is shown and described in the figure and table bel...

Page 409: ...k 10 Reserved 11 EPWM7A ePWM7 output A O 19 18 GPIO57 Configure this pin as 00 GPIO 571 general purpose I O 57 default 01 SPISTEA SPI A slave transmit enable I O 10 Reserved 11 EQEP3I eQEP3 index I O...

Page 410: ...11 Reserved 1 0 GPIO48 Configure this pin as 00 GPIO 48 general purpose I O 48 default 01 ECAP5 eCAP5 I O 10 Reserved 11 Reserved 4 2 7 5 GPIO Port C MUX 1 GPCMUX1 Register The GPIO Port C MUX 1 GPCMU...

Page 411: ...00 GPIO 76 general purpose I O 76 GPIO default 01 Reserved 10 Reserved 11 Reserved 23 22 GPIO75 Configure this pin as 00 GPIO 75 general purpose I O 75 GPIO default 01 SPISTEA 10 Reserved 11 Reserved...

Page 412: ...is pin as 00 GPIO 68 general purpose I O 68 default 01 Reserved 10 Reserved 11 Reserved 7 6 GPIO67 Configure this pin as 00 GPIO 67 general purpose I O 67 default 01 EQEP1I 10 EQEP2B 11 Reserved 5 4 G...

Page 413: ...ter reset Table 4 56 GPIO Port C MUX 2 GPCMUX2 Register Field Descriptions Bit Field Value Description 31 30 GPIO95 Configure this pin as 00 GPIO 95 general purpose I O 95 GPIO default 01 Reserved 10...

Page 414: ...e this pin as 00 GPIO 87 general purpose I O 87 default 01 Reserved 10 Reserved 11 Reserved 13 12 GPIO86 Configure this pin as 00 GPIO 85 general purpose I O 86 default 01 Reserved 10 Reserved 11 Rese...

Page 415: ...W 0 R W 0 R W 0 R W 0 23 22 21 20 19 18 17 16 GPIO107 GPIO106 GPIO105 GPIO104 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 GPIO103 GPIO102 GPIO101 GPIO100 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 GPIO...

Page 416: ...105 general purpose I O 105 GPIO default 01 I2CSCLA 10 Reserved 11 Reserved 17 16 GPIO104 Configure this pin as 00 GPIO 104 general purpose I O 104 GPIO default 01 I2CSDAA 10 Reserved 11 Reserved 15...

Page 417: ...PIO Port D MUX 2 GPDMUX2 Register The GPIO Port D MUX 2 GPDMUX2 register is shown and described in the figure and table below Figure 4 49 GPIO Port D MUX 2 GPDMUX2 Register 31 30 29 28 27 26 25 24 GPI...

Page 418: ...3 general purpose I O 123 GPIO default 01 Reserved 10 Reserved 11 Reserved 21 20 GPIO122 Configure this pin as 00 GPIO 122 general purpose I O 122 GPIO default 01 Reserved 10 Reserved 11 Reserved 19 1...

Page 419: ...3 2 GPIO113 Configure this pin as 00 GPIO 113 general purpose I O 113 GPIO default 01 Reserved 10 EQEP2S 11 EQEP3B 1 0 GPIO112 Configure this pin as 00 GPIO 112 general purpose I O 112 GPIO default 01...

Page 420: ...6 GPIO131 Configure this pin as 00 GPIO 131 general purpose I O 131 GPIO default 01 EPWM10B 10 Reserved 11 Reserved 5 4 GPIO130 Configure this pin as 00 GPIO 130 general purpose I O 130 GPIO default...

Page 421: ...efault 01 Reserved 10 Reserved 11 COMP4OUT Comparator 4 output O 9 8 GPIO196 Configure this pin as 00 GPIO 196 general purpose I O 196 default 01 Reserved 10 Reserved 11 COMP3OUT Comparator 3 output O...

Page 422: ...2 disabled default 23 22 Reserved Any writes to these bit s must always have a value of 2 21 20 AIO10 00 or 01 AIO10 enabled 10 or 11 AIO10 disabled default 19 14 Reserved Any writes to these bit s mu...

Page 423: ...ve a value of 2 25 24 AIO28 00 or 01 AIO28 enabled 10 or 11 AIO28 disabled default 23 22 Reserved Any writes to these bit s must always have a value of 2 21 20 AIO26 00 or 01 AIO26 enabled 10 or 11 AI...

Page 424: ...ication samples relative to the period of SYSCLKOUT The number of samples is specified in the GPxQSELn registers Table 4 63 GPIO Port A Qualification Control GPACTRL Register Field Descriptions Bits F...

Page 425: ...pling period for pins GPIO56 to GPIO63 0x00 Sampling Period TSYSCLKOUT 2 0x01 Sampling Period 2 TSYSCLKOUT 0x02 Sampling Period 4 TSYSCLKOUT 0xFF Sampling Period 510 TSYSCLKOUT 23 16 QUALPRD2 Specifie...

Page 426: ...QUALPRD SYSCLKOUT 510 23 16 QUALPRD2 Specifies the qualification sampling period for GPIO80 to 87 0x00 QUALPRD SYSCLKOUT 0x01 QUALPRD SYSCLKOUT 2 0x02 QUALPRD SYSCLKOUT 4 0xFF QUALPRD SYSCLKOUT 510 15...

Page 427: ...d for GPIO104 to 111 0x00 QUALPRD SYSCLKOUT 0x01 QUALPRD SYSCLKOUT 2 0x02 QUALPRD SYSCLKOUT 4 0xFF QUALPRD SYSCLKOUT 510 7 0 QUALPRD0 Specifies the qualification sampling period for GPIO96 to 103 0x00...

Page 428: ...r 31 8 7 0 Reserved QUALPRDO R 0 R W 0 LEGEND R W Read Write R Read only n value after reset 1 TSYSCLKOUT indicates the period of SYSCLKOUT Table 4 68 GPIO Port G Qualification Control GPGCTRL Registe...

Page 429: ...no synchronization or qualification This option applies to pins configured as peripherals only If the pin is configured as a GPIO input then this option is the same as 0 0 or synchronize to SYSCLKOUT...

Page 430: ...onous no synchronization or qualification This option applies to pins configured as peripherals only If the pin is configured as a GPIO input then this option is the same as 0 0 or synchronize to SYSC...

Page 431: ...eld Value Description 31 30 GPIO79 Select input qualification type for GPIO79 00 Sync 01 Qualification 3 samples 10 Qualification 6 samples 11 Async no Sync or Qualification 29 28 GPIO78 Select input...

Page 432: ...6 samples 11 Async no Sync or Qualification 11 10 GPIO69 Select input qualification type for GPIO69 00 Sync 01 Qualification 3 samples 10 Qualification 6 samples 11 Async no Sync or Qualification 9 8...

Page 433: ...eld Value Description 31 30 GPIO95 Select input qualification type for GPIO95 00 Sync 01 Qualification 3 samples 10 Qualification 6 samples 11 Async no Sync or Qualification 29 28 GPIO94 Select input...

Page 434: ...6 samples 11 Async no Sync or Qualification 11 10 GPIO85 Select input qualification type for GPIO85 00 Sync 01 Qualification 3 samples 10 Qualification 6 samples 11 Async no Sync or Qualification 9 8...

Page 435: ...ld Value Description 31 30 GPIO111 Select input qualification type for GPIO111 00 Sync 01 Qualification 3 samples 10 Qualification 6 samples 11 Async no Sync or Qualification 29 28 GPIO110 Select inpu...

Page 436: ...6 samples 11 Async no Sync or Qualification 11 10 GPIO101 Select input qualification type for GPIO101 00 Sync 01 Qualification 3 samples 10 Qualification 6 samples 11 Async no Sync or Qualification 9...

Page 437: ...ield Value Description 31 30 GPIO127 Select input qualification type for GPIO127 00 Sync 01 Qualification 3 samples 10 Qualification 6 samples 11 Async no Sync or Qualification 29 28 GPIO126 Select in...

Page 438: ...amples 11 Async no Sync or Qualification 11 10 GPIO117 Select input qualification type for GPIO117 00 Sync 01 Qualification 3 samples 10 Qualification 6 samples 11 Async no Sync or Qualification 9 8 G...

Page 439: ...ld Value Description 31 16 Reserved Reserved 15 14 GPIO135 Select input qualification type for GPIO135 00 Sync 01 Qualification 3 samples 10 Qualification 6 samples 11 Async no Sync or Qualification 1...

Page 440: ...GPIO199 GPIO198 GPIO197 GPIO196 GPIO195 GPIO194 GPIO193 GPIO192 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset 1 This register is EALLOW protect...

Page 441: ...ral function The time between samples is specified in the GPECTRL register 10 Qualification using 6 samples Valid for pins configured as GPIO or a peripheral function The time between samples is speci...

Page 442: ...elow Figure 4 72 GPIO Port B Direction GPBDIR Register 31 30 29 28 27 26 25 24 GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 23 22 21 20 19 18...

Page 443: ...pin as output Reading the register returns the current value of the register setting 4 2 7 33 GPIO Port D Direction GPDDIR Register The GPIO Port D Direction GPDDIR register is shown and described in...

Page 444: ...ns the current value of the register setting 0 Configures the GPIO pin as an input default 1 Configures the GPIO pin as an output 4 2 7 35 GPIO Port G Direction GPGDIR Register The GPIO Port G Directi...

Page 445: ...is register 0 Enable the internal pullup on the specified pin 1 Disable the intenral pullup on the specified pin default 4 2 7 37 Analog I O DIR AIODIR Register The Analog I O DIR AIODIR register is s...

Page 446: ...t Figure 4 79 GPIO Port A Data GPADAT Register 31 30 29 28 27 26 25 24 GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 R W x R W x R W x R W x R W x R W x R W x R W x 23 22 21 20 19 18 17 16 G...

Page 447: ...R W x 7 6 5 4 3 2 1 0 GPIO39 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 GPIO32 R W x R W x R W x R W x R W x R W x R W x R W x LEGEND R W Read Write R Read only n value after reset Table 4 89 GPIO Port...

Page 448: ...R W x 7 6 5 4 3 2 1 0 GPIO71 GPIO70 GPIO69 GPIO68 GPIO67 GPIO66 GPIO65 GPIO64 R W x R W x R W x R W x R W x R W x R W x R W x LEGEND R W Read Write R Read only n value after reset Table 4 90 GPIO Port...

Page 449: ...x R W x R W x 7 6 5 4 3 2 1 0 GPIO103 GPIO102 GPIO101 GPIO100 GPIO99 GPIO98 GPIO97 GPIO96 R W x R W x R W x R W x R W x R W x R W x R W x LEGEND R W Read Write R Read only n value after reset Table 4...

Page 450: ...ort E Data GPEDAT Register Field Descriptions Bit Field Value Description 31 8 Reserved Any writes to these bit s must always have a value of 0 7 0 GPIO135 GPIO128 Each bit corresponds to one GPIO por...

Page 451: ...ort G Data GPGDAT Register Field Descriptions Bit Field Value Description 31 8 Reserved Any writes to these bit s must always have a value of 0 7 0 GPIO199 GPIO192 Each bit corresponds to one GPIO por...

Page 452: ...R W x R 0 R W x 7 6 5 4 3 2 1 0 Reserved AIO6 Reserved AIO4 Reserved AIO2 Reserved R 0 R W x R 0 R W x R 0 R W x R 0 LEGEND R W Read Write R Read only n value after resetR W x Table 4 94 Analog I O DA...

Page 453: ...n GPIO0 GPIO31 corresponds to one bit in this register 0 Writes of 0 are ignored This register always reads back a 0 1 Writing a 1 forces the respective output data latch to high If the pin is configu...

Page 454: ...B pin GPIO32 GPIO63 corresponds to one bit in this register 0 Writes of 0 are ignored This register always reads back a 0 1 Writing a 1 forces the respective output data latch to high If the pin is c...

Page 455: ...C pin GPIO95 GPIO64 corresponds to one bit in this register 0 Writes of 0 are ignored This register always reads back a 0 1 Writing a 1 forces the respective output data latch to high If the pin is c...

Page 456: ...ch GPIO port D pin GPIO127 GPIO96 corresponds to one bit in this register 0 Writes of 0 are ignored This register always reads back a 0 1 Writing a 1 forces the respective output data latch to high If...

Page 457: ...atch to high If the pin is configured as a GPIO output then it will be driven high If the pin is not configured as a GPIO output then the latch is set but the pin is not driven Table 4 108 GPIO Port E...

Page 458: ...is configured as a GPIO output then it will be driven high If the pin is not configured as a GPIO output then the latch is set but the pin is not driven Table 4 111 GPIO Port G Clear GPGCLEAR Register...

Page 459: ...ne bit in this register 0 Writes of 0 are ignored This register always reads back a 0 1 Writing a 1 forces the respective output data latch to high If the pin is configured as a AIO output then it wil...

Page 460: ...PxSEL Select GPIO input for GPTRIP signal 000000 Select the GPIO0 000001 Select the GPIO1 111110 Select the GPIO62 111111 Select the GPIO63 Note There are 12 GPTRIP select registers and each has a spe...

Page 461: ...o 1 the signal on the corresponding pin is able to wake the device from both HALT and STANDBY low power modes 4 2 7 54 GPIO Low Power Mode Wakeup Select 2 GPIOLPMSEL2 Register The GPIO Low Power Mode...

Page 462: ...ents Incorporated Internal Memory Chapter 5 SPRUHE8E October 2012 Revised November 2019 Internal Memory This chapter provides information on the RAM and flash memory modules Topic Page 5 1 RAM Control...

Page 463: ...ther defines and discusses the dedicated RAMs shared RAMs and MSG RAMs on this device 5 1 1 1 Dedicated RAM The M3 subsystem has two dedicated RAM blocks C0 and C1 Only the Cortex M3 CPU has access to...

Page 464: ...ister When an Sx RAM block is owned by the M3 subsyteam the M3 CPU and DMA have full access to that RAM block whereas the C28x CPU and DMA have only read access to that RAM block no fetch write access...

Page 465: ...rbitration scheme used is a mix of round robin and fixed priority Arbitration between individual masters is done based on the round robin scheme whereas arbitration between different accesses from the...

Page 466: ...ast latency on the re locatable NVIC vector table accesses for exception accesses user should allocate the vector tables in a dedicated RAM block In case of bit band writes from the M3 CPU it is possi...

Page 467: ...en fetch accesses are allowed based on the mastership from a CPU it can be further protected by setting the FETCHPROTx bit of the specific register to 1 If fetch access is done by CPU to memory where...

Page 468: ...DMA write protection violation If a write protection violation occurs on M3 write is ignored and the dmaerr interrupt gets generated If a write violation occurs on C28x write is ignored and an access...

Page 469: ...the controller corrects the data and writes into memory but incase of uncorrectable error appropriate error get generated 5 1 1 7 2 Error Handling For each correctable error the count in the correcta...

Page 470: ...rror duing fetch on C28x CPU there is possibility of getting ITRAP before NMI since garbage instructions enters into C28x pipeline before NMI gets generated During debug accesses RD WR correctable as...

Page 471: ...6 bits of data 15 9 Not Used 16 Parity for address 31 17 Not Used 5 1 1 9 RAM Initialization To ensure that read fetch byte write in case of M3 uDMA from uninitialized RAM locations do not cause ECC o...

Page 472: ...Register 4 4 0x38 PROTECTED M3 CxRTESTINIT1 Cx RAM TEST and INIT Register 1 4 0x40 PROTECTED M3 MSxRTESTINIT1 M3 Sx RAM TEST and INIT Register 1 4 0x50 PROTECTED M3 MTOCRTESTINIT MTOC MSG RAM TEST an...

Page 473: ...Non Master DMA Write Access Violation Address Register MNMFAVADDR 4 0x78 M3 Non Master CPU Fetch Access Violation Address Register MMWRAVADDR 4 0x80 M3 Master CPU Write Access Violation Address Regis...

Page 474: ...28x C28x Corrected Error Threshold Exceeded Force Register CCECLR 4 0x18 C28x C28x Corrected Error Threshold Exceeded Flag Clear Register CCEIE 4 0x1A C28x C28x Single Error Interrupt Enable Register...

Page 475: ...Write R Read only n value after reset Table 5 13 Cx DEDRAM Configuration Register 1 CxDRCR1 Field Descriptions Bit Field Value Description 31 11 Reserved Reserved 10 CPUWRPROTC1 CPU Write Protection C...

Page 476: ...0 M3 CPU Write allowed to C5 RAM Block 1 M3 CPU Write not allowed to C5 RAM Block 25 DMAWRPROTC5 0 M3 uDMA Write allowed to C5 RAM Block 1 M3 uDMA Write not allowed to C5 RAM Block 24 FETCHPROTC5 0 M...

Page 477: ...FETCHPROTC 7 R 0 R W 0 R W 0 R W 0 7 3 2 1 0 Reserved CPUWRPROT C6 DMAWRPROT C6 FETCHPROTC 6 R 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 5 15 Cx SHRAM Configurat...

Page 478: ...3 CxSRCR3 Figure 5 7 Cx SHRAM Configuration Register 3 CxSRCR3 31 30 29 28 27 26 25 24 Reserved CPUWRPROT C13 DMAWRPROT C13 FETCHPROTC 13 R 0 R W 0 R W 0 R W 0 23 22 21 20 19 18 17 16 Reserved CPUWRPR...

Page 479: ...m C11 RAM Block 1 M3 CPU Fetch not allowed from C11 RAM Block 7 3 Reserved Reserved 2 CPUWRPROTC10 0 M3 CPU Write allowed to C10 RAM Block 1 M3 CPU Write not allowed to C10 RAM Block 1 DMAWRPROTC10 0...

Page 480: ...M3 uDMA Write allowed to C15 RAM Block 1 M3 uDMA Write not allowed to C15 RAM Block 8 FETCHPROTC15 0 M3 CPU Fetch allowed from C15 RAM Block 1 M3 CPU Fetch not allowed from C15 RAM Block 7 3 Reserved...

Page 481: ...5 RAM block M3 CPU DMA accesses are allowed based on the setting of protection bits in the MSxSRCR register 1 C28 subsystem is master for S5 RAM block C28 CPU DMA accesses are allowed based on the set...

Page 482: ...UWRPROT S2 DMAWRPROT S2 FETCHPROTS 2 R 0 R W 0 R W 0 R W 0 15 11 10 9 8 Reserved CPUWRPROT S1 DMAWRPROT S1 FETCHPROTS 1 R 0 R W 0 R W 0 R W 0 7 3 2 1 0 Reserved CPUWRPROT S0 DMAWRPROT S0 FETCHPROTS 0...

Page 483: ...te allowed to S1 RAM block 1 M3 CPU write not allowed to S1 RAM block 9 DMAWRPROTS1 DMA Write Protection S1 0 M3 DMA write allowed to S1 RAM block 1 M3 DMA write not allowed to S1 RAM block 8 FETCHPRO...

Page 484: ...UWRPROTS7 CPU Write Protection S7 0 M3 CPU write allowed to S7 RAM block 1 M3 CPU write not allowed to S7 RAM block 25 DMAWRPROTS7 DMA Write Protection S7 0 M3 DMA write allowed to S7 RAM block 1 M3 D...

Page 485: ...CHPROTS5 CPU Fetch Protection S5 0 M3 CPU Fetch allowed from S5 RAM block 1 M3 CPU Fetch not allowed from S5 RAM block 7 3 Reserved Reserved 2 CPUWRPROTS4 CPU Write Protection S4 0 M3 CPU write allowe...

Page 486: ...MSGRCR Figure 5 12 M3TOC28_MSG_RAM Configuration Register MTOCMSGRCR 31 2 1 0 Reserved DMAWRPROT Rsvd R 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 5 21 M3TOC28_MSG_RAM Con...

Page 487: ...data an address ECC parity bits 5 ECCPARTESTC2 Enable Disable RAMTEST Feature for C2 RAM Block 0 RAMTEST feature is disabled for C2 RAM block 1 RAMTEST feature is enabled for C2 RAM block ECC parity l...

Page 488: ...master for S7 memory 13 ECCPARTESTS6 Enable Disable RAMTEST Feature for S6 RAM Block if M3 Subsystem is Master for S6 RAM Block 0 RAMTEST feature is disabled for S6 RAM block 1 RAMTEST feature is enab...

Page 489: ...ory accesses 4 RAMINITS2 RAM Initialization S2 Any reads to this bit will return a 0 0 No action taken 1 Initialize all address locations of S2 RAM block with data 0x0 and corresponding data an addres...

Page 490: ...W Read Write R Read only n value after reset Table 5 24 MTOC_MSG_RAM Test and Initialization Register MTOCRTESTINIT Field Descriptions Bit Field Value Description 31 2 Reserved Reserved 1 ECCPARTEST...

Page 491: ...sed by M3 CPU This status bit gets cleared when the RAMINIT bit is set for C3 RAM block 5 Reserved Reserved 4 RAMINITDONEC2 RAM Initialization Process Status when RAMINIT is Set for C2 RAM Block RAM i...

Page 492: ...TDONES6 RAM Initialization Process Status when RAMINIT is Set for S6 RAM Block 0 RAM initialization is not finished for S6 RAM block 1 RAM initialization is done for S6 RAM block S6 RAM can be accesse...

Page 493: ...is status bit gets cleared when the RAMINIT bit is set for S2 RAM block 3 Reserved Reserved 2 RAMINITDONES1 RAM Initialization Process Status when RAMINIT is Set for S1 RAM Block 0 RAM initialization...

Page 494: ...ck 5 2 2 M3 RAM Error Registers 5 2 2 1 M3 CPU Uncorrectable Write Error Address Register MCUNCWEADDR Figure 5 19 M3 CPU Uncorrectable Write Error Address Register MCUNCWEADDR 31 0 MCUNCWEADDR R 0 LEG...

Page 495: ...ld Value Description 31 0 MCUNCREADDR This register contains the address where uncorrectable error occurs during M3 CPU data read or fetch Only the address coresponding to the last error is stored 5 2...

Page 496: ...ield Value Description 31 0 MCPUCREADDR This register contains the address where correctable error occurs during M3 CPU data read or fetch Only the address coresponding to the last error is stored 5 2...

Page 497: ...e read error occurred Once this bit is set it can be cleared by setting the corresponding error clear bit in the MUECLR register 2 M3CPURE M3 CPU Uncorrectable Read Error Status Flag 0 No M3 CPU uncor...

Page 498: ...riptions Bit Field Value Description 31 4 Reserved Reserved 3 UDMARE M3 DMA Uncorrectable Read Error Force Any reads to this bit will return a 0 Setting this bit to 1 will set the M3 DMA uncorrectable...

Page 499: ...rectable read error flag 1 UDMAWE M3 DMA Uncorrectable Write Error Clear Any reads to this bit will return a 0 0 No effect 1 Clears the M3 DMA uncorrectable write error flag 0 M3CPUWE M3 CPU Uncorrect...

Page 500: ...erved MCEFLG R 0 M3 R 0 LEGEND R W Read Write R Read only n value after reset Table 5 39 M3 Corrected Error Threshold Exceeded Flag Register MCEFLG Field Descriptions Bit Field Value Description 31 1...

Page 501: ...served 0 MCECLR M3 Corrected Error Threshold Reached Error Flag Clear Any reads to this bit will return a 0 Writing a 1 to this bit clears the M3 corrected error threshold reached flag It will also cl...

Page 502: ...ion did not occur 1 Non master DMA write access violation has occurred The M3 DMA tried to write into an Sx RAM block for which C28x subsystem is the master In this case writes are ignored Once this b...

Page 503: ...0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 5 45 Master Access Violation Flag Register MMAVFLG Field Descriptions Bit Field Value Description 31 3 Reserved Reserved 2 CPUWRIT...

Page 504: ...Clears the corresponding master CPU write access violation flag 1 DMAWRITE Master DMA Write Access Violation Clear 0 No effect 1 Clears the corresponding master DMA write access violation flag 0 CPUFE...

Page 505: ...gister MNMFAVADDR Figure 5 40 Non Master CPU Fetch Access Violation Address Register MNMFAVADDR 31 0 NMCPUFAVADDR R 0 LEGEND R W Read Write R Read only n value after reset Table 5 49 Non Master CPU Fe...

Page 506: ...CMDMAWRAVADDR Field Descriptions Bit Field Value Description 31 0 MDMAWRAVADDR Master DMA Write Access Violation Address This holds the address at which M3 DMA attempted a write access and the master...

Page 507: ...Read only n value after reset Table 5 53 Lx DEDRAM Configuration Register 1 LxDRCR1 Field Descriptions Bit Field Value Description 31 11 Reserved Reserved 10 CPUWRPROTL1 CPU Write Protection L1 0 C28...

Page 508: ...Description 31 11 Reserved Reserved 10 CPUWRPROTL3 CPU Write Protection L3 0 C28x CPU write allowed to L3 RAM block 1 C28x CPU write not allowed to L3 RAM block 9 DMAWRPROTL3 DMA Write Protection L3...

Page 509: ...5 RAM block M3 CPU DMA accesses are allowed based on the setting of protection bits in the MSxSRCR register 1 C28 subsystem is master for S5 RAM block C28 CPU DMA accesses are allowed based on the set...

Page 510: ...T S2 DMAWRPROT S2 FETCHPROTS 2 R 0 R W 0 R W 0 R W 0 15 11 10 9 8 Reserved CPUWRPROT S1 DMAWRPROT S1 FETCHPROTS 1 R 0 R W 0 R W 0 R W 0 7 3 2 1 0 Reserved CPUWRPROT S0 DMAWRPROT S0 FETCHPROTS 0 R 0 R...

Page 511: ...from S1 RAM block 1 C28x CPU Fetch not allowed from S1 RAM block 7 3 Reserved Reserved 2 CPUWRPROTS0 CPU Write Protection S0 0 C28x CPU write allowed to S0 RAM block 1 C28x CPU write not allowed to S0...

Page 512: ...AWRPROTS6 DMA Write Protection S6 0 C28x DMA write allowed to S6 RAM block 1 C28x DMA write not allowed to S6 RAM block 16 FETCHPROTS6 CPU Fetch Protection S6 0 C28x CPU Fetch allowed from S6 RAM bloc...

Page 513: ...GRCR Figure 5 49 C28TOC28_MSG_RAM Configuration Register CTOMMSGRCR 31 2 1 0 Reserved DMAWRPROT Rsvd R 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 5 58 C28TOC28_MSG_RAM Con...

Page 514: ...ECC parity logic is bypassed for memory accesses 4 RAMINIT CTOMMSGRAM RAM Initialization for CTOM_MSG_RAM Block Any reads to this bit will return a 0 0 No action taken 1 Initialize all address locati...

Page 515: ...data an address ECC parity bits 5 ECCPARTESTL2 Enable Disable RAMTEST Feature for L2 RAM Block 0 RAMTEST feature is disabled for L2 RAM block 1 RAMTEST feature is enabled for L2 RAM block ECC parity...

Page 516: ...ess locations of S7 RAM block with data 0x0 and corresponding data an address ECC parity bits Applicable only if C28x subsystem is master for S7 memory 13 ECCPARTESTS6 Enable Disable RAMTEST Feature f...

Page 517: ...e is disabled for S2 RAM block 1 RAMTEST feature is enabled for S2 RAM block ECC parity logic is bypassed for memory accesses 4 RAMINITS2 RAM Initialization S2 Any reads to this bit will return a 0 0...

Page 518: ...atus when RAMINIT is Set for CTOM_MSG_RAM Block RAM initialization is not finished for CTOM_MSG_RAM block 0 RAM initialization is done for CTOM_MSG_RAM block CTOM_MSG_RAM can be accessed by M3 CPU DMA...

Page 519: ...n be accessed by M3 CPU This status bit gets cleared when the RAMINIT bit is set for C3 RAM block 5 Reserved Reserved 4 RAMINITDONEC 2 RAM Initialization Process Status when RAMINIT is Set for C2 RAM...

Page 520: ...INITDONES 6 RAM Initialization Process Status when RAMINIT is Set for S6 RAM Block 0 RAM initialization is not finished for S6 RAM block 1 RAM initialization is done for S6 RAM block S6 RAM can be acc...

Page 521: ...his status bit gets cleared when the RAMINIT bit is set for S2 RAM block 3 Reserved Reserved 2 RAMINITDONES 1 RAM Initialization Process Status when RAMINIT is Set for S1 RAM Block 0 RAM initializatio...

Page 522: ...r Address Register CDUNCREADDR Figure 5 57 C28x DMA Uncorrectable Read Error Address Register CDUNCREADDR 31 0 CDUNCREADDR R 0 LEGEND R W Read Write R Read only n value after reset Table 5 66 C28x DMA...

Page 523: ...red 5 2 4 5 C28x Uncorrectable Error Flag Register CUEFLG Figure 5 60 C28x Uncorrectable Error Flag Register CUEFLG 31 16 Reserved R 0 15 2 1 0 Reserved C28DMARE C28CPURE R 0 R 0 R 0 LEGEND R W Read W...

Page 524: ...rectable read error flag status 0 C28CPURE C28x CPU Uncorrectable Read Error Force Any reads to this bit will return a 0 Setting this bit to 1 will set the C28x CPU uncorrectable read error flag statu...

Page 525: ...g C28x CPU or DMA reads this counter increments by 1 After increment if this counter value becomes equal to the value configured in the CCETRES register correctable error interrupt gets generated if i...

Page 526: ...rror Count Reached Flag This status flag is set when corrected error count on C28x CPU or DMA accesses becomes equal to the C28x CPU DMA corrected error threshold Once this bit is set it can be cleare...

Page 527: ...ved 0 CCECLR C28x Corrected Error Threshold Reached Error Flag Clear Any reads to this bit will return a 0 Writing a 1 to this bit clears the C28x corrected error threshold reached flag It will also c...

Page 528: ...C28x CPU tried to write into an Sx RAM block for which M3 subsystem is the master Once this bit is set it can be cleared by setting the corresponding error clear bit in the CNMAVCLR register 1 DMAWRI...

Page 529: ...0 CPUFETCH Non Master CPU Fetch Access Violation Force Any reads to this bit will return a 0 0 No effect 1 Sets the CPUFETCH flag in the CNMAVFLG register 5 2 4 16 Non Master Access Violation Flag Cle...

Page 530: ...violation did not occur 1 Master DMA write access violation has occurred The C28x DMA tried to write into a RAM Block for which DMAWRPROT is set to 1 In this case writes are ignored Once this bit is s...

Page 531: ...r Access Violation Force Register CMAVFRC Field Descriptions continued Bit Field Value Description 1 DMAWRITE Master DMA Write Access Violation Force Any reads to this bit will return a 0 0 No effect...

Page 532: ...after reset Table 5 83 Master Access Violation Flag Clear Register CMAVCLR Field Descriptions Bit Field Value Description 31 3 Reserved Reserved 2 CPUWRITE Master CPU Write Access Violation Clea Any...

Page 533: ...igure 5 76 Non Master DMA Write Access Violation Address Register CNMDMAWRAVADDR 31 0 NMDMAWRAVADDR R 0 LEGEND R W Read Write R Read only n value after reset Table 5 85 Non Master DMA Write Access Vio...

Page 534: ...VADDR Figure 5 79 Master DMA Write Access Violation Address Register CMDMAWRAVADDR 31 0 NMDMAWRAVADDR R 0 LEGEND R W Read Write R Read only n value after reset Table 5 88 Master DMA Write Access Viola...

Page 535: ...ever the semaphore must be managed when the API is used Dedicated flash module controller FMC in the master subsystem and the control subsystem 128 bits bankwidth can be programmed at a time along wit...

Page 536: ...che prefetch mechanisms must always be disabled if they are enabled After the initialization of wait states is done cache prefetch mechanisms can be enabled as needed 5 3 4 Flash Bank OTP and Pump The...

Page 537: ...tem interfaces with the C28x flash module controller C28x FMC which in turn interfaces with the C28x flash bank and shared pump to perform erase program operations as well as to read data execute code...

Page 538: ...on versus access time Faster access times are associated with higher power modes of operation At one extreme the power control logic could attempt to reduce power consumption by putting the banks and...

Page 539: ...low formula RWAIT SYSCLK FCLK 1 round up to the next highest integer or 1 whichever is larger where SYSCLK is the system operating frequency FCLK is flash clock frequency FCLK should be FCLKmax allowe...

Page 540: ...nce of small loop code execution an 8 level deep 128 bit wide 8 x 128 direct mapped program cache has been implemented in the FMC Whenever instructions in cache are fetched for CPU processing the flas...

Page 541: ...chanism For data space accesses the program cache and prefetch mechanism are bypassed If an instruction prefetch is already in progress when a data read operation is initiated then the data read will...

Page 542: ...ress of the access from flash is automatically aligned to a 128 bit boundary such that the instruction location is within the 128 bits to be fetched With flash prefetch mode enabled the 128 bits read...

Page 543: ...ocation is within the 128 bits to be read from the bank By default this data cache is disabled and can be enabled by setting DATA_CACHE_EN bit in the FRD_INTF_CTRL register Some other points to keep i...

Page 544: ...ogram ECC check bits This command is implemented by the following Flash API functions Fapi_issueProgrammingCommand The Program function provides the options to program data without ECC data along with...

Page 545: ...ead margin mode 2 Follow the procedure above to enter read margin mode 5 3 10 Error Correction Code ECC Protection M3 FMC and C28x FMC contain an embedded single error correction and double error dete...

Page 546: ...ble bit data error or address error occurred If the SECDED logic finds a single bit error in the address field then it is considered to be a non correctable error NOTE Since ECC is calculated for an e...

Page 547: ...a single bit error occurs the SINGLE_ERR_INT flag is set and an interrupt C28FLSINGERR on C28x PIE and M3 Flash Single Error on M3 NVIC have to be enabled for interrupts if needed is fired The SINGLE...

Page 548: ...DATAL_TEST This is because ECC test mode registers FDATAH_TEST FDATAL_TEST FECC_TEST are multiplexed with data from the flash Hence the CPU should not read fetch from flash when ECC test mode is enabl...

Page 549: ...ss ranges inclusive given below in M3 Flash cannot be used for program code or data but must be programmed to 0x00 when the Code Security Password is programmed in M3 Flash If security is not a concer...

Page 550: ...x core and by initializing MWRALLOW with 0xA5A5A5A5 on Cortex M3 Write access to flash registers is disabled when the EDIS instruction is executed on the C28x core For Cortex M3 write access to flash...

Page 551: ...R 0x10 MWRALLOW M3SYSRSTn ERR_STATUS_ CLR Error Status Clear Register 4 R W0 1 0x14 MWRALLOW M3SYSRSTn ERR_CNT Error Counter Register 4 R 0x18 MWRALLOW M3SYSRSTn ERR_THRESHO LD Error Threshold Registe...

Page 552: ...4 R W 0x026 EALLOW C28SYSRSTn FMAC Flash Module Access Control Register 4 R 0x028 EALLOW C28SYSRSTn FMSTAT Flash Module Status Register Used with Flash API Refer to Flash Application Programming Inter...

Page 553: ...lag Clear Register 4 R W0 1 0x12 EALLOW C28SYSRSTn FDATAH_TEST Data High Test Register 4 R W 0x14 EALLOW C28SYSRSTn FDATAL_TEST Data Low Test Register 4 R W 0x16 EALLOW C28SYSRSTn FADDR_TEST ECC Test...

Page 554: ...its indicate how many waitstates are added to a flash read access The RWAIT value can be set anywhere from 0 to 0xF For a flash access data is returned in RWAIT 1 M3 SYSCLK cycles Note The required wa...

Page 555: ...determined by the FBFALLBACK register This value must be greater than 1 when the fallback mode is not ACTIVE Note The prescaled clock used for the BAGP down counter is a clock divided by 16 from input...

Page 556: ...wait for both the pump and the bank to be ready before attempting an access 0 M3 bank is not ready 1 M3 bank is in active power mode and is ready for access 5 4 1 6 Flash Bank Pump Control Register 1...

Page 557: ...2 Field Descriptions Bit Field Value Description 31 16 Reserved Reserved 15 0 PAGP Pump Active Grace Period This register contains the starting count value for the PAGP mode down counter Any access to...

Page 558: ...apper registers can be written from code running from zone1 security zone 10 M3 Flash Wrapper registers can be written from code running from zone2 security zone State Transitions 00 11 01 code runnin...

Page 559: ...served DATA_CACHE _EN PROG_CACHE _EN R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 5 102 Flash Read Interface Control Register FRD_INTF_CTRL Field Descriptions Bit Field...

Page 560: ...disable ECC 5 4 2 2 Single Error Address Register SINGLE_ERR_ADDR Figure 5 96 Single Error Address Register SINGLE_ERR_ADDR 31 0 ERR_ADDR R 0 LEGEND R W Read Write R Read only n value after reset Tabl...

Page 561: ...that a single bit error occurred and the corrected value was 0 Cleared by writing a 1 to FAIL_0_CLR bit of ERR_STATUS_CLR register 5 4 2 5 Error Position Register ERR_POS Figure 5 99 Error Position Re...

Page 562: ...il on 0 clear Writing a 1 to this bit will clear the FAIL_0 bit of ERR_STATUS register Writes of 0 have no effect 5 4 2 7 Error Counter Register ERR_CNT Figure 5 101 Error Counter Register ERR_CNT 31...

Page 563: ...4 2 9 Error Interrupt Flag Register ERR_INTFLG Figure 5 103 Error Interrupt Flag Register ERR_INTFLG 31 16 Reserved R 0 15 2 1 0 Reserved UNC_ERR_ INT_FLG SINGLE_ERR_ INT_FLG R 0 R 0 R 0 LEGEND R W Re...

Page 564: ...INGLE_ERR_INT_CLR Single bit error interrupt flag clear Writing a 1 to this bit will clear SINGLE_ERR_INT_FLG Writes of 0 have no effect 5 4 2 11 Data High Test Register FDATAH_TEST Figure 5 105 Data...

Page 565: ...4 2 14 ECC Test Register FECC_TEST Figure 5 108 ECC Test Register FECC_TEST 31 8 7 0 Reserved ECC R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 5 116 ECC Test Register FECC_TES...

Page 566: ...the selected ECC block 5 4 2 18 ECC Status Register FECC_STATUS Figure 5 112 ECC Status Register FECC_STATUS 31 16 Reserved R 0 15 9 8 7 2 1 0 Reserved CHK_ERR ERR_POS UNC_ERR SINGLE_ERR R 0 R 0 R 0 R...

Page 567: ...its indicate how many waitstates are added to a flash read access The RWAIT value can be set anywhere from 0 to 0xF For a flash access data is returned in RWAIT 1 C28 SYSCLK cycles Note The required w...

Page 568: ...termined by the FBFALLBACK register This value must be greater than 1 when the fallback mode is not ACTIVE Note The prescaled clock used for the BAGP down counter is a clock divided by 16 from input C...

Page 569: ...the C28x bank is ready for Flash access before the access is attempted Note User should wait for both the pump and the bank to be ready before attempting an access 0 C28x bank is not ready 1 C28x ban...

Page 570: ...ntains the starting count value for the PAGP mode down counter Any access to flash memory causes the counter to reload with the PAGP value After the last access to flash memory the down counter delays...

Page 571: ...nable Register ECC_ENABLE Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 0 ENABLE ECC enable A value of 0xA would enable ECC Any other value would disable ECC 5 4 4 2 SIngle...

Page 572: ...ingle bit error occurred and the corrected value was 0 Cleared by writing a 1 to FAIL_0_CLR bit of ERR_STATUS_CLR register 5 4 4 5 Error Position Register ERR_POS Figure 5 126 Error Position Register...

Page 573: ...of 0 have no effect 5 4 4 7 Error Counter Register ERR_CNT Figure 5 128 Error Counter Register ERR_CNT 31 16 15 0 Reserved ERR_CNT R R W 0 LEGEND R W Read Write R Read only n value after reset Table 5...

Page 574: ...orrectable error occurs this bit is set and the UNC_ERR_INT interrupt is fired When UNC_ERR_INT_CLR bit of ERR_INTCLR register is written a value of 1 this bit is cleared 0 SINGLE_ERR_INT_FLG Single b...

Page 575: ..._TEST Field Descriptions Bit Field Value Description 31 0 FDATAL Low double word of selected 64 bit data User configurable bits 31 0 of the selected data blocks in ECC test mode 5 4 4 13 ECC Test Addr...

Page 576: ...RL Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 ECC_SELECT ECC block select 0 Selects the ECC block on bits 63 0 of bank data 1 Selects the ECC block on bits 127 64 of ban...

Page 577: ...alue Description 31 9 Reserved Reserved 8 CHK_ERR Test mode ECC single bit error indicator When 1 indicates that the single bit error is in check bits When 0 indicates that the single bit error is in...

Page 578: ...r 2019 ROM Code and Peripheral Booting This chapter describes the booting functionality of the master M3 and control C28 subsystems Topic Page 6 1 Introduction 579 6 2 Device Boot Sequence 579 6 3 Dev...

Page 579: ...flash memories The control subsystem is held in reset on power up and M Boot ROM brings the control subsystem out of reset C Boot ROM after performing the needed device initialization puts the C28x CP...

Page 580: ...re boot from Cortex M3 USB 0 1 0 1 6 2 4 Boot to OTP 0 1 1 0 7 2 4 Boot to Master Subsystem Flash memory 0 1 1 1 8 Not supported Defaults to Boot to Flash 1 0 0 0 9 4 Boot from Master Subsystem serial...

Page 581: ...ot mode Master subsystem initialization Control subsystem initialization Control subsystem WIR mode handling Enter IDLE mode Wakeup on IPC Interrupt POR XRSn POR XRSn www ti com Device Boot Flow Diagr...

Page 582: ...es the stack pointer from the first location in this table and the reset vector is fetched from address 0x00000004 in the table As long as boot ROM is executing the NVIC base address is set to its def...

Page 583: ...ase in M Boot ROM So if any of these errors occur during M Boot ROM execution they end up triggering a Hard Fault Exception SysTickIntHandler is the function used by Ethernet bootloaders for timing du...

Page 584: ...esets User applications can reuse this memory location after it reads the device boot status or it can leave this location reserved if there is a need to preserve boot status between resets Note that...

Page 585: ...location 0x0068100C is equal to 0x00000000 or equal to 0xFFFFFFFF or fall outside the available master subsystem flash memory address range then M Boot ROM defaults to M_BOOT_ROM_Z1_FLASH_ENTRY_POINT...

Page 586: ...15 1 2 for more details on SSI0 boot load protocol 6 5 7 8 M Boot ROM I2C0 Master Boot Mode Entry Point When using this boot mode there is a provision for the user to provide an entry point to tell M...

Page 587: ...eral Boot Function Name for pin Direction GPIO s used Pin Mux Assignment Peripheral Mode Alternate Mode Core Select Serial Boot Mode UART0 UART0_RX Input PA0_GPIO0 1 0 default Master default boot mode...

Page 588: ...Alternate 12 Master default MII_TXER Output PG7_GPIO47 3 0 default Master default MII_RXDV Input PG3_GPIO43 Alternate 12 Master default MII_MDIO Bi Directional PE6_GPIO30 Alternate 12 Master default M...

Page 589: ...Master default MII_COL Input PL4_GPIO84 Alternate 12 Master default MII_CRS Input PK7_GPIO79 Alternate 12 Master default MII_PHYINTR n Input PL6_GPIO86 Alternate 12 Master default MII_PHYRSTn Output...

Page 590: ...y boot mode selected as per If boot mode is boot_to_flash Call mbrom_start_app M_BOOT_ROM_Z1_FLASH_ENTRY_POINT or user programmed entry point If boot mode is boot_from_serial ConfigureDevice PickInter...

Page 591: ...OM_OTP_ENTRY_POINT If no valid boot mode is selected Call mbrom_start_app M_BOOT_ROM_Z1_FLASH_ENTRY_POINT or user programmed entry point 6 5 10 3 MBROM_START_APP ENTRY_POINT_ADDRESS Reset device confi...

Page 592: ...tion sequence RAM_INIT all M3 RAM s POR Branch to TO OTP HWBIST Reset Handler Go to APP M3 HWBIST RESET ZERO out BootROM Reserved C2 RAM NOT POR Adjust stack pointer to C2 RAM Reset Cause POR XRSn Ena...

Page 593: ..._START_ADDRESS Initialize CAN0 for 20MHz input clock or user selected i p clk 250Kbps standards Boot commands Download process CAN Boot Start Parallel IO loader and download application to RAM Paralle...

Page 594: ...edback Copyright 2012 2019 Texas Instruments Incorporated ROM Code and Peripheral Booting NOTE Boot to OTP option is not shown in this flow chart but it is similar to boot to RAM option The boot ROM u...

Page 595: ...ERR NMI If set M BootROM detected a M3 BIST ERR NMI If set M BootROM detected a Missing clock NMI 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 www ti com M Boot ROM Description 595 SPRUHE8E October 2012 Rev...

Page 596: ...and M3SSDIVSEL dividers are configured for divide by 1 operation as explained in Section 6 5 8 above 6 5 14 M Boot ROM Exceptions Handling Table 6 7 shows how M Boot ROM handles different possible exc...

Page 597: ...sical connections and signaling used to transfer the bytes of the protocol When serial boot mode is selected M Boot ROM polls each of these interfaces sequentially for the boot mode commands and boots...

Page 598: ...to ensure reliable communications with the update program The packets are always acknowledged or not acknowledged by the communicating devices The packets use the same format for receiving and sending...

Page 599: ...cCommand 1 Program Address 31 24 ucCommand 2 Program Address 23 16 ucCommand 3 Program Address 15 8 ucCommand 4 Program Address 7 0 ucCommand 5 Program Size 31 24 ucCommand 6 Program Size 23 16 ucComm...

Page 600: ...ta The format of the command is as follows unsigned char ucCommand 9 ucCommand 0 COMMAND_SEND_DATA ucCommand 1 Data 0 ucCommand 2 Data 1 ucCommand 3 Data 2 ucCommand 4 Data 3 ucCommand 5 Data 4 ucComm...

Page 601: ...d NakPacket Once the update is complete the application can be started by issuing a COMMAND_RUN command or COMMAND_RESET command 6 5 15 1 5 1 Packet Handling The bootloader uses the SendPacket functio...

Page 602: ...equency of the microcontroller running the bootloader 6 5 15 1 5 2 3 UART Transport The UART handling functions are UARTSend UARTReceive and UARTFlush The device communicating with the bootloader is r...

Page 603: ...e 4 and Boot Mode 12 are both exactly same except that they use different IOs for the EMAC The IOs used by both these modes are listed in Table 6 1 EMAC boot mode needs to configure the management clo...

Page 604: ...oader will not reconfigure the CAN clocks or bit timing and will assume that they have been configured as expected by the application running on device The bootloader assumes that the application has...

Page 605: ...wnload Size 7 0 ucData 5 Download Size 15 8 ucData 6 Download Size 23 16 ucData 7 Download Size 31 24 3 LM_API_UPD_SEND_DATA 0x1F020080 This command should only follow a LM_API_UPD_DOWNLOAD command or...

Page 606: ...end a valid packet to another device including waiting for the acknowledge or not acknowledge from the other device Received packets use the same format as sent packets The bootloader uses the PacketR...

Page 607: ...8 bits long and follows the same data flow as outlined in Section 6 6 15 1 The exception is that the C2000 hex utility hex file generated for the master subsystem boot has the least significant byte L...

Page 608: ...block Addr 31 16 CC DD Destination address of second block Addr 15 0 Addr 0xAABBCCDD AA BB First word of the second block in the source being loaded n n 1 AA BB Last word of the last block of the sour...

Page 609: ...9 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated ROM Code and Peripheral Booting Figure 6 7 Parallel GPIO Mode Overview Fi...

Page 610: ...012 2019 Texas Instruments Incorporated ROM Code and Peripheral Booting Figure 6 8 Parallel GPIO Mode Host Transfer Flow Figure 6 9 shows the flow used to read a single word of data from the parallel...

Page 611: ...or MSB of data www ti com M Boot ROM Description 611 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated ROM Code and Periphera...

Page 612: ...T_ROM_RAM_ENTRY_POINT 6 5 15 7 M Boot ROM I2C0 Master Boot Mode In this mode M Boot ROM configures I2C0 peripheral as master and tries to boot from an I2C slave at address 0x52 The pins used in this b...

Page 613: ...entry point as explained in Section 6 5 7 9 The function call sequence below gives details of the flow when OTP boot mode is selected on the device ResetIsr mbrom_init_device mbrom_master_system_init...

Page 614: ...of computationally intensive real time applications can achieve execution speeds considerably faster than what are currently available without having to rewrite existing code The functions listed in...

Page 615: ...gh precision functions the TI IQmath Library can shorten significantly your DSP application development time The IQmath library accesses the tables through the IQmathTables and the IQmathTablesRam lin...

Page 616: ...Raphson square root algorithm By using a more accurate estimate the convergence is quicker and hence cycle time is faster Normalized Arctan Table IQ Math Table Table size 452 words Q format Q30 Conten...

Page 617: ...11 12 2011 0x003FFF7C 0x003FFFBD Checksum 6 6 1 4 C Boot ROM PIE Vector Mismatch Handler As explained in the Control Subsystem PIE Vector Address Validity Check section of the System Control and Inter...

Page 618: ...t vector located at 0x3F FFC0 The reset vector is factory programmed to point to the InitBoot function stored in the boot ROM This function starts the boot load process PIE and all the peripheral inte...

Page 619: ...ined further below in this chapter After PIE is enabled the NMI ITRAP and any enabled peripheral interrupt vectors are fetched from the PIE Vector table as shown in table 0 13 below C Boot ROM enables...

Page 620: ...INT9 1 96 INT9 8 103 0x00000DC0 0x00000DCE cbrom_pie_isr_not_supported PIE GROUP10 INT10 1 104 INT10 8 111 0x00000DD0 0x00000DDE cbrom_pie_isr_not_supported PIE GROUP11 INT11 1 112 0x00000DE0 cbrom_mt...

Page 621: ...m I2C interface BOOT_FROM_PARALLEL 0x00000006 On receiving this command C Boot ROM boots from the control subsystem GPIO The master subsystem application must follow the below procedure to let the con...

Page 622: ...n C Boot ROM branches to location 0x00000000 in M0 RAM User applications which use this option must have their main function located at this address or have a branch to main instruction at this locati...

Page 623: ...tation Feedback Copyright 2012 2019 Texas Instruments Incorporated ROM Code and Peripheral Booting 6 6 6 C Boot ROM GPIO Assignment for Boot Modes Table 6 17 gives information on the GPIOs used for ea...

Page 624: ...em D2 Input PA2_GPIO2 0 default Control Subsystem D3 Input PA3_GPIO3 0 default Control Subsystem D4 Input PA4_GPIO4 0 default Control Subsystem D5 Input PA5_GPIO5 0 default Control Subsystem D6 Input...

Page 625: ...CSM initialization sequence Refer to the Security Module section in the System Control and Interrupts chapter Initialize boot environment local and global variables initialization for boot C Boot ROM...

Page 626: ...OCIPCINT1 Interrupt Service Routine Enable PIE Go to IDLE mode Wake up to handle IPC interrupts C28X CSM sequence RAM_INIT all C28x RAM s Zero Init C Boot ROM stack Not BIST RESET POR Enable NMI Reset...

Page 627: ...it is a valid command handles the command 6 6 9 1 Procedure for Master Subsystem Application to Send IPC Commands to C Boot ROM and Wait for Response The procedure for the master subsystem application...

Page 628: ...uccessfully Read the Result in MTOCIPCDATAR register Command was NOT serviced successfully Read the Error code MTOCIPCDATAR 15 0 register Refer to C Boot ROM NAK status table MTOCIPCCLR 31 1 to clear...

Page 629: ...er the command Service the command Clear MTOCIPCFLG 31 if the command was successfully processed if the command was invalid or cannot execute the command because of any reason MTOCIPCFLG 31 is not cle...

Page 630: ...CIPCACK 0 1 MTOCIPCDATAR C_BOOTROM_NAK_STATUS_CMD _NOT_SET_PROPERLY Command Completed successfully ACK the Command Handling another IPC FALSE MTOCIPCACK 0 1 MTOCIPCACK 31 1 Control Subsystem in IDLE M...

Page 631: ...s after write 0x00 Command success address data 3 MASTER_IPC_MTOC_CLEA R_BITS_16 Address of the 16 bit register Data in MTOCIPCDATAW 15 0 Data read back after write 0x00 Command success address data 4...

Page 632: ...ill jump to the address in ADDR register and starts executing the code from that address PIE will be enabled when this branch occurs it is up to the application to disable and reload PIE interrupt han...

Page 633: ...M_NAK_STATUS_CM D_NOT_SET_PROPERLY tells corresponding system that control system has received a command but the IPCFLG 0 and IPCFLG 31 both are not set 3 CONTROL_SYSTEM_NAK_STATUS_AL READY_BUSY_WITH_...

Page 634: ...20 C Boot ROM Boot Status Values Value MTOCIPCBOOTSTS 15 0 Description 0 C_BOOTROM_BOOTSTS_CTOM_IGNORE Invalid status tells corresponding system that control system has not filled in a valid value yet...

Page 635: ...as a spurious PIE interrupt or if there was a PIE vector address mismatch exception The events that trigger C Boot ROM to send these IPC Messages are explained in Section 6 6 12 and Table 6 21 In this...

Page 636: ...miss another IPC status message from C Boot ROM 6 6 13 C Boot Reset Cause Handling Table 6 22 shows the actions taken by C Boot ROM for each of the Reset Causes that will reset control subsystem Table...

Page 637: ...C message Wait in While 1 loop for reset from master C28RAMUNCERR C28 RAM Uncorrectable Error NMI Flag cbrom_handle_nmi Clear NMI Flags Save error status in CTOMBOOTSTS register send IPC message to ma...

Page 638: ...its Note that not all bootloaders will accept both 8 and 16 bit streams Please refer to the detailed information on each loader for the valid data stream width For an 8 bit data stream the key value i...

Page 639: ...r future use 10 Entry point PC 22 16 11 Entry point PC 15 0 12 Block size number of words of the first block of data to load If the block size is 0 this indicates the end of the source program Otherwi...

Page 640: ...0005 0002 0x0002 2nd block consists of 2 16 bit words 003F 8000 0x003F8000 2nd block will be loaded starting at 0x3F8000 7700 7625 Data loaded 0x7700 0x7625 0000 0x0000 Size of 0 indicates end of data...

Page 641: ...10 words or 20 bytes in the block MSB block size 25 26 LSB MSW destination address first block Addr 23 16 MSB MSW destination address first block Addr 31 24 27 28 LSB LSW destination address first blo...

Page 642: ...completed the following memory values will have been initialized as follows Location Value 0x3F9010 0x0001 0x3F9011 0x0002 0x3F9012 0x0003 0x3F9013 0x0004 0x3F9014 0x0005 0x3F8000 0x7700 0x3F8001 0x76...

Page 643: ...Description 643 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated ROM Code and Peripheral Booting Figure 6 15 Bootloader Bas...

Page 644: ...a function that is initialized by each of the loaders to properly read data from that port For example when the SPI loader is evoked the GetWordData function pointer is initialized to point to the SPI...

Page 645: ...ure of the SCI port is used to lock baud rates with the host For this reason the SCI loader is very flexible and you can use a number of different baud rates to communicate with the device After each...

Page 646: ...Read MSB Echoback MSB to host Return MSB LSB C Boot ROM Description www ti com 646 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incor...

Page 647: ...tings FIFO enabled 8 bit character internal SPICLK master mode and talk mode clock phase 1 polarity 0 using the slowest baud rate If the download is to be performed from an SPI port on another device...

Page 648: ...an 8 bit data stream 0x08AA The least significant byte of this word is the byte read first and the most significant byte is the next byte fetched This is true of all word transfers on the SPI If the k...

Page 649: ...m reset GPIO19 Set chip enable high Enable EEPROM Send read command and start at EEPROM address 0x0000 Read KeyValue Jump to Flash Read LOSPCP value Change LOSPCP Change SPIBRR Read SPIBRR value Read...

Page 650: ...conventional I2C EEPROM protocol as described in this section with a 16 bit base address architecture Figure 6 23 EEPROM Device at Address 0x50 The I2C loader uses following pins SDAA on GPIO 32 SCLA...

Page 651: ...o run the I2C at a 50 percent duty cycle at 100 kHz bit rate standard I2C mode when the system clock is 10 MHz These registers can be modified after receiving the first few bytes from the EEPROM This...

Page 652: ...5 LSB I2CCLKH 7 0 6 MSB I2CCLKH 15 8 7 LSB I2CCLKL 7 0 8 MSB I2CCLKL 15 8 Data for this section 17 LSB Reserved for future use 18 MSB Reserved for future use 19 LSB Upper half of entry point PC 20 MS...

Page 653: ...e is 8 bits long and follows the same data flow as outlined in Figure 6 27 Figure 6 27 Overview of Parallel GPIO Bootloader Operation The control subsystem communicates with the external host device b...

Page 654: ...second block Addr 31 16 DD CC Destination address of second block Addr 15 0 BB AA First word of the second block in the source being loaded n n 1 BB AA Last word of the last block of the source being...

Page 655: ...RUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated ROM Code and Peripheral Booting Figure 6 29 Parallel GPIO Mode Overview Figur...

Page 656: ...r Flow Figure 6 31 shows the flow used to read a single word of data from the parallel port 8 bit data stream The 8 bit routine shown in Figure 6 31 discards the upper 8 bits of the first read from th...

Page 657: ...31 8 Bit Parallel GetWord Function 6 7 Guidelines for Boot ROM Application Writers This section provides guidelines to write a master subsystem application in order to kick start a peripheral bootloa...

Page 658: ...trol Subsytem RAM INIT Proceedure Assign Boot Mode IOs to Control Subsytem Assign Boot Mode IOs to Control Subsytem Assign Boot Mode IOs to Control Subsytem MTOCIPCBOOTM ODE BOOT_FROM_PAR ALLEL MTOCIP...

Page 659: ...loaders 6 8 1 1 Building the Binary Image for an Application Using Code Composr Studio When using the CCS IDE to build code to RUN on the Concerto platform the binary bootable image is automatically g...

Page 660: ...er M Boot ROM Serial EMAC and CAN boot modes are compatible to respective boot modes in Stellaris devices The snapshots below show how the LM Flash programmer utility available on the web can be used...

Page 661: ...right 2012 2019 Texas Instruments Incorporated ROM Code and Peripheral Booting Figure 6 35 LM FLASH Programmer Interface Selection Screen 6 8 1 2 1 Using the LM FLASH Programmer to Send Data to the M...

Page 662: ...below and select the bin file built as explained in Section 6 8 1 1 The Program Address Offset in the snapshot below is the LOAD address for M Boot ROM to load the application The same address is the...

Page 663: ...e 6 37 LM FLASH Programmer Binary Image Selection Screen 6 8 1 2 2 Using the LM FLASH Programmer to Send Data to the M BOOT ROM EMAC Interface Ethernet Bootload Option 1 Select the Ethernet option as...

Page 664: ...and Peripheral Booting Figure 6 38 LM FLASH Programmer EMAC Interface Selection Screen 2 Select the program tab as shown below and select the binary image file built as shown in Section 6 8 1 1 Note...

Page 665: ...e key value reserved bits entry point address block start address block length and terminating value The contents of the boot table vary slightly depending on the boot mode and the options selected wh...

Page 666: ...loader table as the GPIO port 8 bit mode gpio16 Specify the source of the bootloader table as the GPIO port 16 bit mode bootorg value Specify the source address of the bootloader table lospcp value Sp...

Page 667: ...motor control switch mode power supply control uninterruptible power supplies UPS and other forms of power conversion The ePWM peripheral performs a digital to analog DAC function where the duty cycle...

Page 668: ...SOC events to be generated by additional counter compares CMPC and CMPD Event Trigger Module Enhancements Prescaling logic to issue interrupt requests and ADC start of conversion expanded upto every 1...

Page 669: ...hronization scheme that allows them to operate as a single system when required Additionally this synchronization scheme can be extended to the capture peripheral modules eCAP The number of modules is...

Page 670: ...OCA2 SOCAx Pulse Stretch 32 SYSCLKOUT Cycles Active Low Output SOCB1 SOCB2 SOCBx EPWM1SYNCI GPTRIP6 PIEERR ECCDBLERR ePWM2A ePWM2B ePWMxA ePWMxB EQEPnERR PIEERR ECCDBLERR PIEERR ECCDBLERR 28x RAM Flas...

Page 671: ...Each module on a device can be configured to either use or ignore any of the trip zone signals The TZ1 to TZ3 trip zone signals can be configured as asynchronous inputs through the GPIO peripheral us...

Page 672: ...24 CMPA Shadow 24 Introduction www ti com 672 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Enhanced Pulse Width Modu...

Page 673: ...C28 Enhanced Pulse Width Modulator ePWM Module 7 1 2 Register Mapping The complete ePWM module control and status register set is grouped by submodule as shown in Table 7 1 Each register set is duplic...

Page 674: ...CMPAHR 0x08 1 Yes Extension for HRPWM Counter Compare A Register 2 CMPA 0x09 1 Yes Counter Compare A Register CMPB 0x0A 1 Yes Counter Compare B Register Action Qualifier Submodule Registers AQCTLA 0x...

Page 675: ...Compare Filter Control Register DCCAPCTL 0x34 1 Yes Digital Compare Capture Control Register DCFOFFSET 0x35 1 Writes Digital Compare Filter Offset Register DCFOFFSETCNT 0x36 1 Digital Compare Filter O...

Page 676: ...Mirror 2 Register 3 CMPAM2 0x65 1 Yes Counter Compare A Mirror 2 Register 3 CMPBHRM 0x66 1 Yes Counter Compare B Mirror High Resolution Register 2 CMPBM 0x67 1 Yes Counter Compare B Mirror Register 2...

Page 677: ...x50 Active TI_Internal DBRED 0x10 Active Active DBREDM 0x51 Active Active DBREDHR 0x52 Active TI_Internal DBFED 0x11 Active Active DBFEDM 0x53 Active Active CMPC 0x69 Active Active CMPD 0x6B Active Ac...

Page 678: ...y an emulator Specify the source for the synchronization output of the ePWM module Synchronization input signal Time base counter equal to zero Time base counter equal to counter compare B CMPB No out...

Page 679: ...ycle Enable the trip zone to initiate an interrupt Bypass the trip zone module entirely Programmable option for Cycle by cycle trip clear Event trigger ET Enable the ePWM events that will trigger an i...

Page 680: ...module has its own time base submodule that determines all of the event timing for the ePWM module Built in synchronization logic allows the time base of multiple ePWM modules to work together as a s...

Page 681: ...e which ePWM instances include this feature Table 7 4 Time Base Submodule Registers Register Name Address Offset Shadowed Description TBCTL 0x00 No Time Base Control Register TBSTS 0x01 No Time Base S...

Page 682: ...Signal Description EPWMxSYNCI Time base synchronization input Input pulse used to synchronize the time base counter with the counter of ePWM module earlier in the synchronization chain An ePWM periphe...

Page 683: ...ontrolled by the time base period TBPRD register and the mode of the time base counter Figure 7 6 shows the period Tpwm and frequency Fpwm relationships for the up count down count and up down count t...

Page 684: ...adow register buffers or provides a temporary holding location for the active register It has no direct effect on any control hardware At a strategic point in time the shadow register s content is tra...

Page 685: ...me Base Clock Synchronization The TBCLKSYNC bit in the peripheral clock enable registers allows all users to globally synchronize all enabled ePWM modules to the time base clock TBCLK When set all ena...

Page 686: ...figured to generate synchronization pulses which have the same affect as EPWMxSYNCI This feature enables the ePWM module to be automatically synchronized to the time base of another ePWM module Lead o...

Page 687: ...ster is configured so that CMPA CMPAHR are linked to ePWM1 then a write to CMPA CMPAHR in ePWM 1 will simultaneously write the same value to CMPA CMPAHR in ePWM3 If ePWM4 also has its CMPA CMPAHR regi...

Page 688: ...PHS value TBPRD value ePWM Submodules www ti com 688 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Enhanced Pulse Wid...

Page 689: ...CTR_dir CTR zero CNT_max CTR PRD www ti com ePWM Submodules 689 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Enhance...

Page 690: ...x COMPxOUT GPTRIP PIEERR ECCDBLERR TZ1 TZ3 to GPIO MUX 28x RAM Flash ECC 0x0000 0xFFFF TBCTR 15 0 UP DOWN UP DOWN UP DOWN TBPHS value TBPRD value EPWMxSYNCI CTR_dir CTR zero CNT_max CTR PRD ePWM Submo...

Page 691: ...the active PWM cycle 7 2 3 2 Controlling and Monitoring the Counter Compare Submodule The counter compare submodule operation is controlled and monitored by the registers shown in Table 7 6 1 This reg...

Page 692: ...sync A EPWMxSYNCI TBCTL SWFSYNC 0 CMPCTL2 LOADDMODE CTR PRD CTR Zero Event Trigger and Interrupt ET SOCA SOCB EPWMxINT Counter Compare A Counter Compare B Counter Compare C Counter Compare D ePWM Subm...

Page 693: ...ic points This prevents corruption or spurious operation due to the register being asynchronously modified by software The memory address of the active register and the shadow register is identical Wh...

Page 694: ...If the shadow register is enabled then the content of the shadow register is transferred to the active register on one of the following events as specified by the CMPCTL2 LOADCMODE CMPCTL2 LOADDMODE...

Page 695: ...Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Enhanced Pulse Width Modulator ePWM Module Figure 7 14 Counter Compare Event Waveforms in Up Count Mode NOTE An EPWMxSYNCI external syn...

Page 696: ...e CTR CMPB EPWMxSYNCI ePWM Submodules www ti com 696 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Enhanced Pulse Wid...

Page 697: ...2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Enhanced Pulse Width Modulator ePWM Module Figure 7 16 Counter Compare Events In Up Down Count Mode TBCTL PHSD...

Page 698: ...er submodule is responsible for the following Qualifying and generating actions set clear toggle based on the following events CTR PRD Time base counter equal to the period TBCTR TBPRD CTR Zero Time b...

Page 699: ...re controlled via the set of registers shown in Table 7 8 Figure 7 19 Action Qualifier Submodule Inputs and Outputs For convenience the possible input events are summarized again in Table 7 9 Table 7...

Page 700: ...n still trigger interrupts and ADC start of conversion See the Event trigger Submodule description in Section 7 2 8 for details Actions are specified independently for either output EPWMxA or EPWMxB A...

Page 701: ...count CBD Counter equals CMPB on up count CBU 6 Lowest Counter equals CMPA on down count CAD Counter equals CMPA on up count CBU Table 7 11 shows the action qualifier priority for up count mode In th...

Page 702: ...two load modes is described below Shadow Mode The shadow mode for the AQCTLA is enabled by setting the AQCTLR SHDWAQAMODE bit and the shadow register for AQCTLB is enabled by setting the AQCTLR SHDWA...

Page 703: ...1 10 01 00 AQCTLR LDAQAMODE 01 10 00 CTR PRD CTR Zero DCAEVT1 sync A DCBEVT1 sync A EPWMxSYNCI TBCTL SWFSYNC AQCTLR SHDWAQAMODE AQCTLA 16 Active Reg AQCTLA 16 Shadow Reg 16 www ti com ePWM Submodules...

Page 704: ...ation Load CMPA CMPB on period and use the period action to clear the PWM and a compare up action to set the PWM Modulate the compare value from 0 to TBPRD to achieve 50 0 PWM duty When using up count...

Page 705: ...or ePWM Module Figure 7 23 Up Down Count Mode Symmetrical Waveform The PWM waveforms in Figure 7 24 through Figure 7 29 show some common action qualifier configurations The C code samples in Example 7...

Page 706: ...to 0000 Example 7 1 contains a code sample showing initialization and run time for the waveforms in Figure 7 24 Example 7 1 Code Sample for Figure 7 24 Initialization Time EPwm1Regs TBPRD 600 Period 6...

Page 707: ...dge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Active Low A PWM period TBPRD 1 TTBCLK B Duty modulation for EPWMxA is set by CMPA and is active low that is the low time duty...

Page 708: ...SCLKOUT EPwm1Regs TBCTL bit CLKDIV TB_DIV1 EPwm1Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm1Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm1Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on TBCTR Zero EPwm1Regs CMP...

Page 709: ...nter EPwm1Regs TBCTL bit CTRMODE TB_COUNT_UP EPwm1Regs TBCTL bit PHSEN TB_DISABLE Phase loading disabled EPwm1Regs TBCTL bit PRDLD TB_SHADOW EPwm1Regs TBCTL bit SYNCOSEL TB_SYNC_DISABLE EPwm1Regs TBCT...

Page 710: ...e headers Example 7 4 Code Sample for Figure 7 27 Initialization Time EPwm1Regs TBPRD 600 Period 2 600 TBCLK counts EPwm1Regs CMPA half CMPA 400 Compare A 400 TBCLK counts EPwm1Regs CMPB 500 Compare B...

Page 711: ...for the waveforms in Figure 7 28 Use the code in Example 7 5 to define the headers Example 7 5 Code Sample for Figure 7 28 Initialization Time EPwm1Regs TBPRD 600 Period 2 600 TBCLK counts EPwm1Regs C...

Page 712: ...e waveforms in Figure 7 29 Use the code in Example 7 5 to define the headers Example 7 6 Code Sample for Figure 7 29 Initialization Time EPwm1Regs TBPRD 600 Period 2 600 TBCLK counts EPwm1Regs CMPA ha...

Page 713: ...7 2 5 1 Purpose of the Dead Band Submodule The Action qualifier AQ Module section discussed how it is possible to generate the required dead band by having full control over edge placement using both...

Page 714: ...cycle value on PWMxA is less than this phase shift amount PWMxA s falling edge has precedence over the delayed rising edge for PWMxB It is recommended to make sure the duty cycle value of the current...

Page 715: ...lection The input signals to the dead band module are the EPWMxA and EPWMxB output signals from the action qualifier In this section they will be referred to as EPWMxA In and EPWMxB In Using the DBCTL...

Page 716: ...y changing the input signal source The modes shown in Table 7 15 fall into the following categories Mode 1 Bypass both falling edge delay FED and rising edge delay RED Allows you to fully disable the...

Page 717: ...escription DBCTL DEDB MODE DBCTL OUTSWAP S8 S6 S7 EPWMxA and EPWMxB signals are as defined by OUT MODE bits 0 0 0 EPWMxA A path as defined by OUT MODE bits 0 0 1 EPWMxB A path as defined by OUT MODE b...

Page 718: ...w AL RED FED Period ePWM Submodules www ti com 718 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Enhanced Pulse Width...

Page 719: ...BRED TTBCLK Where TTBCLK is the period of TBCLK the prescaled version of SYSCLKOUT For convenience delay values for various TBCLK options are shown in Table 7 17 Table 7 17 Dead Band Delay Values in S...

Page 720: ...bmodules This capability is important if you need pulse transformer based gate drivers to control the power switching elements 7 2 6 1 Purpose of the PWM Chopper Submodule The key functions of the PWM...

Page 721: ...E8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Enhanced Pulse Width Modulator ePWM Module Figure 7 34 PWM Chopper Submodule...

Page 722: ...or period of the first pulse is given by T1stpulse TSYSCLKOUT 8 OSHTWTH Where TSYSCLKOUT is the period of the system clock SYSCLKOUT and OSHTWTH is the four control bits value from 1 to 16 Figure 7 3...

Page 723: ...and associated circuitry Saturation is one such consideration To assist the gate drive designer the duty cycles of the second and subsequent pulses have been made programmable These sustaining pulses...

Page 724: ...mux TZ4 is sourced from an inverted EQEPxERR signal on those devices with an EQEP module TZ5 is connected to the system clock fail logic and TZ6 is sourced from the EMUSTOP output from the CPU These s...

Page 725: ...the ePWM module If the pulse width is less than this the trip condition may not be latched by CBC or OST latches The asynchronous trip makes sure that if clocks are missing for any reason the outputs...

Page 726: ...als which source the DCAH DCAL and DCBH DCBL signals are selected via the DCTRIPSEL register and can be either trip zone input pins or analog comparator COMPxOUT signals For more information on the di...

Page 727: ...follows TZSEL OSHT1 1 enables TZ1 as a one shot event source for ePWM2 TZCTL TZA 1 EPWM2A will be forced high on a trip event TZCTL TZB 1 EPWM2B will be forced high on a trip event Scenario B A cycle...

Page 728: ...WMxA from PC submodule EPWMxA TZCTL TZA DCAEVT1 DCAEVT2 EPWMA Trip Logic DCAEVT1 force DCAEVT2 force EPWMxB from PC submodule EPWMxB TZCTL TZB DCBEVT1 DCBEVT2 EPWMB Trip Logic DCBEVT1 force DCBEVT2 fo...

Page 729: ...le Figure 7 40 Trip Zone Submodule Interrupt Logic 7 2 8 Event Trigger ET Submodule The key functions of the event trigger submodule are Receives event inputs generated by the time base counter compar...

Page 730: ...er submodule s operational highlights Each ePWM module has one interrupt request line connected to the PIE and two start of conversion signals connected to the ADC module As shown in Figure 7 42 ADC s...

Page 731: ...dule Table 7 22 TRIGxSEL Trigger Options continued TRIGxSEL Bits Trigger Source Peripheral 01110 EPWM4SOCA EPWM4 01111 EPWM4SOCB 10000 EPWM4SYNC 10001 EPWM5SOCA EPWM5 10010 EPWM5SOCB 10011 EPWM5SYNC 1...

Page 732: ...gister ETCLR 0x1C No Event Trigger Clear Register ETFRC 0x1D No Event Trigger Force Register ETCLRM 0x70 No Event Trigger Clear Register Mirror ETINTPS 0x50 No Event Trigger Interrupt Pre Scale Regist...

Page 733: ...e counter equal to the compare D register CMPD when the timer is incrementing Time base counter equal to the compare D register CMPD when the timer is decrementing The number of events that have occur...

Page 734: ...made in ETCNTINITCTL INTINITEN When ETCNTINITCTL INTINITEN is set then it enables initialization of INTCNT2 counter with contents of ETCNTINIT INTINIT on a SYNC event or software force determined by...

Page 735: ...EPWMxSYNCI ETCNTINITCTL SOCAINITEN 0 1 101 0 1 110 0 1 111 0 1 ETSEL SOCASELCMP 0 1 ETINTPS SOCAPRD2 ETPS SOCPSSEL ETPS SOCPSSEL ETSOCPS SOCACNT2 0 1 CTR Zero CTR PRD CTRU CMPA CTRU CMPC CTRD CMPA CTR...

Page 736: ...and TZ1 TRIPIN2 and TZ2 TRIPIN3 TRIPIN4 TRIPIN5 TRIPIN6 TRIPIN7 TRIPIN8 TRIPIN9 TRIPIN10 TRIPIN11 TRIPIN12 TRIPIN14 ECCDBLERR TRIPIN15 PIEERR GPTRIP GPIO MUX DCAEVT1 soc DCBEVT1 soc DCBEVT1 force DCBE...

Page 737: ...pare DC submodule compares signals external to the ePWM module for instance COMPxOUT signals from the analog comparators to directly generate PWM events actions which then feed to the event trigger tr...

Page 738: ...e external trip inputs which feed into the OR gate individually selectable and not go through the combinational input by using the DCTRIPSEL register 7 2 9 3 Controlling and Monitoring the Digital Com...

Page 739: ...ILT event signals can generate a force to the trip zone module a TZ interrupt an ADC SOC or a PWM sync signal force signal DCAEVT1 2 force signals force trip zone conditions which either directly infl...

Page 740: ...Clear TZCLR DCAEVT1 DCAEVT1 inter TZEINT DCAEVT1 TZFLG DCAEVT1 DCAEVT1 force 1 0 Sync TBCLK Async 1 0 DCACTL EVT1SRCSEL DCEVTFILT DCAEVT1 DCACTL EVT1FRCSYNCSEL TZFRC DCAEVT1 ePWM Submodules www ti co...

Page 741: ...The diagrams below show how the DCBEVT1 DCBEVT2 or DCEVTFLT signals are processed to generate the digital compare B event force interrupt soc and sync signals Figure 7 51 DCBEVT1 Event Triggering Figu...

Page 742: ...out all event occurrences on the signal while it is active will be aligned to either a CTR PRD pulse or a CTR 0 pulse configured by the DCFCTL PULSESEL bits An offset value in TBCLK counts is program...

Page 743: ...n 1 Window n 1 TBCLK CTR PRD or CTR 0 BLANKWDW BLANKWDW BLANKWDW www ti com ePWM Submodules 743 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Ins...

Page 744: ...Key Configuration Capabilities The key configuration choices available to each module are as follows Options for SyncIn Load own counter with phase register on an incoming sync strobe enable EN switc...

Page 745: ...olling Multiple Buck Converters With Independent Frequencies One of the simplest power converter topologies is the buck A single ePWM module configured as a master can control two buck stages with the...

Page 746: ...En EPWM4A 3 X Buck 1 Vout1 Vin1 EPWM1A Buck 2 Vin2 EPWM2A Vout2 Buck 4 Buck 3 Vin3 EPWM4A Vin4 EPWM3A Vout3 Vout4 SyncIn SyncIn SyncIn Applications to Power Topologies www ti com 746 SPRUHE8E October...

Page 747: ...B A I P I P I P I Indicates this event triggers an ADC start of conversion www ti com Applications to Power Topologies 747 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Cop...

Page 748: ...L bit CTRMODE TB_COUNT_UP Asymmetrical mode EPwm2Regs TBCTL bit PHSEN TB_DISABLE Phase loading disabled EPwm2Regs TBCTL bit PRDLD TB_SHADOW EPwm2Regs TBCTL bit SYNCOSEL TB_SYNC_DISABLE EPwm2Regs CMPCT...

Page 749: ...ocumentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Enhanced Pulse Width Modulator ePWM Module 7 3 4 Controlling Multiple Buck Converters With Same Frequencies If synchronizat...

Page 750: ...B CA CA CA CA CB CB CB CB Applications to Power Topologies www ti com 750 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C...

Page 751: ...bit CAD AQ_CLEAR EPwm1Regs AQCTLB bit CBU AQ_SET set actions for EPWM1B EPwm1Regs AQCTLB bit CBD AQ_CLEAR EPWM Module 2 config EPwm2Regs TBPRD 600 Period 1200 TBCLK counts EPwm2Regs TBPHS half TBPHS...

Page 752: ...ntrol of multiple switching elements can also be addressed with these same ePWM modules It is possible to control a Half H bridge stage with a single ePWM module This control can be extended to multip...

Page 753: ...CB CA A CB CA Z A CB CA Z A CB Z CA A CB Z CA www ti com Applications to Power Topologies 753 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instru...

Page 754: ...Pwm2Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm2Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm2Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero...

Page 755: ...X En EPWM3B EPWM3A Phase reg CTR CMPB CTR zero 4 Slave SyncOut X EPWM4A EPWM4B En SyncOut CTR zero CTR CMPB Phase reg Phase reg CTR CMPB CTR zero Slave 6 5 Slave X En SyncIn EPWM6B EPWM6A SyncOut X EP...

Page 756: ...P CA CA CA CA CA CA CA CA CA CA Applications to Power Topologies www ti com 756 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorpor...

Page 757: ..._SHADOW EPwm2Regs TBCTL bit SYNCOSEL TB_SYNC_IN sync flow through EPwm2Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm2Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm2Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on C...

Page 758: ...S multiple PWM modules can address another class of power topologies that rely on phase relationship between legs or stages for correct operation As described in the TB module section a PWM module can...

Page 759: ...module 1 configured as the master To work the phase relationship between adjacent modules must be F 120 This is achieved by setting the slave TBPHS registers 2 and 3 with values of 1 3 and 2 3 of the...

Page 760: ...SyncOut X EPWM3B Phase reg Slave En SyncIn EPWM3A 1 2 3 VIN EPWM2B EPWM2A EPWM3A EPWM3B VOUT 0 120 120 240 Applications to Power Topologies www ti com 760 SPRUHE8E October 2012 Revised November 2019...

Page 761: ...I Z I A P CA CA A P CA CA A P CA CA www ti com Applications to Power Topologies 761 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Inc...

Page 762: ...OW EPwm2Regs TBCTL bit SYNCOSEL TB_SYNC_IN sync flow through EPwm2Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm2Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm2Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Ze...

Page 763: ...change the phase value on a cycle by cycle basis This feature lends itself to controlling a class of power topologies known as phase shifted full bridge or zero voltage switched full bridge Here the c...

Page 764: ...transition Z CA Z I Z I Z I Z CB A CA CB A Z Z CB A CA Z Z CB A CA Applications to Power Topologies www ti com 764 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright...

Page 765: ...de EPwm2Regs TBCTL bit PHSEN TB_ENABLE Slave module EPwm2Regs TBCTL bit PRDLD TB_SHADOW EPwm2Regs TBCTL bit SYNCOSEL TB_SYNC_IN sync flow through EPwm2Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm2Regs CMP...

Page 766: ...nal of the comparator Alternatively an external reference could be connected at this input The comparator output is an input to the Digital compare sub module The ePWM module is configured in such a w...

Page 767: ...EVT2FRCSYNCSEL DC_EVT_ASYNC Take async path Enable DCAEVT2 as a one shot trip source Note DCxEVT1 events can be defined as one shot DCxEVT2 events can be defined as cycle by cycle EPwm1Regs TZSEL bit...

Page 768: ...former En SyncIn SyncOut CNT Zero CNT CMPB X X Phase Reg Master 1 Ext Sync In optional EPWM1A EPWM1B NOTE X indicates value in phase register is a don t care Applications to Power Topologies www ti co...

Page 769: ...es as a double buffer EPwm1Regs CMPCTL bit SHDWBMODE CC_SHADOW Shadow mode Operates as a double buffer EPwm1Regs AQCTLA bit ZRO AQ_SET Set PWM1A on Zero EPwm1Regs AQCTLA bit CAU AQ_CLEAR Clear PWM1A o...

Page 770: ...e register will be loaded from the shadow register when the time base counter equals zero If TBCTL PRDLD 1 then the shadow is disabled and any write or read will go directly to the active register tha...

Page 771: ...he hardware Likewise reads return the active value Figure 7 78 Time Base Period High Resolution Mirror Register TBPRDHRM 15 8 TBPRDHR R W 0 7 0 Reserved R 0 LEGEND R W Read Write R Read only n value a...

Page 772: ...gister TBPHSHR TBPHSHRM 15 8 TBPHSHR R W 0 7 0 Reserved R 0 LEGEND R W Read Write R Read only n value after reset Table 7 30 Time Base Phase High Resolution Register and Mirror Register TBPHSHR TBPHSH...

Page 773: ...re the synchronization event In the up count and down count modes this bit is ignored 0 Count down after the synchronization event 1 Count up after the synchronization event 12 10 CLKDIV Time base Clo...

Page 774: ...d by the TBCTL2 PRDLDSYNC bit A write read to the TBPRD register accesses the shadow register 2 PHSEN Counter Register Load From Phase Register Enable 0 Do not load the time base counter TBCTR from th...

Page 775: ...t Synchronization Latched Status Bit 0 Writing a 0 will have no effect Reading a 0 indicates no external synchronization event has occurred 1 Reading a 1 on this bit indicates that an external synchro...

Page 776: ...on period feature Note This bit and the TBCTL PHSEN bit must be set to 1 when high resolution period control is enabled for up down count mode even if TBPHSHR 0x00 1 Reserved Reserved 0 HRPE High Reso...

Page 777: ...e reserved and do nothing i e register is linked to itself 15 12 CMPCLINK CMPC Link Bits Writes to the CMPC register in the ePWM module selected by the following bit selections results in a simultaneo...

Page 778: ...ultaneous write to the current ePWM module s CMPA CMPAHR registers 0010 ePWM1 0011 ePWM2 0100 ePWM3 0101 ePWM4 0110 ePWM5 0111 ePWM6 1000 ePWM7 1001 ePWM8 1010 ePWM9 All other values are reserved and...

Page 779: ...cy 01 Shadow to Active Load of CMPA CMPAHR occurs both according to LOADAMODE bits and when SYNC occurs 10 Shadow to Active Load of CMPA CMPAHR occurs only when a SYNC is received 11 Reserved Note Thi...

Page 780: ...Counter Compare Control Register CMPCTL2 Field Descriptions Bit Field Value Description 15 14 Reserved 0 Reserved 13 12 LOADDSYNC Shadow to Active CMPD Register Load on SYNC event 00 Shadow to Active...

Page 781: ...adow Select Mode 00 Load on CTR Zero Time base counter equal to zero TBCTR 0x0000 01 Load on CTR PRD Time base counter equal to period TBCTR TBPRD 10 Load on either CTR Zero or CTR PRD 11 Freeze no lo...

Page 782: ...L SHDWAMODE 0 then the shadow is enabled and any write or read will automatically go to the shadow register In this case the CMPCTL LOADAMODE bit field determines which event will load the active regi...

Page 783: ...directly to the active register that is the register actively controlling the hardware Figure 7 93 Counter Compare B Register CMPBM 15 0 CMPB R W 0 LEGEND R W Read Write R Read only n value after res...

Page 784: ...ow register Before a write the CMPCTL SHDWBFULL bit can be read to determine if the shadow register is currently full If CMPCTL SHDWBMODE 1 then the shadow register is disabled and any write or read w...

Page 785: ...97 Compare B High Resolution Register CMPBHR 15 8 CMPBHR R W 0 7 0 Reserved R 0 LEGEND R W Read Write R Read only n value after reset Table 7 47 Compare B High Resolution Register CMPBHR Field Descrip...

Page 786: ...nal will be forced low 9 8 CBU Action when the counter equals the active CMPB register and the counter is incrementing 00 Do nothing action disabled 01 Clear force EPWMxA output low 10 Set force EPWMx...

Page 787: ...eld Descriptions Bit Field Value Description 15 12 Reserved Reserved 11 10 CBD Action when the counter equals the active CMPB register and the counter is decrementing 00 Do nothing action disabled 01...

Page 788: ...ow Figure 7 101 Action Qualifier Software Force Register and Mirror Register AQSFRC AQSFRCM 15 8 Reserved R 0 7 6 5 4 3 2 1 0 RLDCSF OTSFB ACTSFB OTSFA ACTSFA R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W...

Page 789: ...Reserved CSFB CSFA R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 7 52 Action Qualifier Continuous Software Force Register and Mirror Register AQCSFRC AQCSFRCM Field Descr...

Page 790: ...bits and when SYNC occurs 10 Shadow to Active Load of AQCTLA occurs only when a SYNC is received 11 Reserved Note This bit is valid only if AQCTLR SHDWAQAMODE 1 7 Reserved 0 Reserved 6 SHDWAQBMOD E A...

Page 791: ...te When this bit is set to 1 user should always either set OUT_MODE bits such that Apath InA OR OUTSWAP bits such that OutA Bpath otherwise OutA will be invalid 13 12 OUTSWAP Dead Band Output Swap Con...

Page 792: ...g edge delayed signal 10 EPWMxA In from the action qualifier is the source for rising edge delayed signal EPWMxB In from the action qualifier is the source for falling edge delayed signal 11 EPWMxB In...

Page 793: ...7 56 Dead Band Generator Falling Edge Delay and Mirror Register DBFED DBFEDM Field Descriptions Bit Field Value Description 15 14 Reserved Reserved 13 0 DEL Falling Edge Delay Count 14 bit counter Fi...

Page 794: ...Edge Delay High Resolution Register DBFEDHR Field Descriptions Bit Field Value Description 15 9 DBFEDHR 00 7Fh These 7 bits contain the high resolution portion least significant 7 bits of the dead ba...

Page 795: ...e by 3 4 16 MHz at 100 MHz SYSCLKOUT 011 Divide by 4 3 12 MHz at 100 MHz SYSCLKOUT 100 Divide by 5 2 50 MHz at 100 MHz SYSCLKOUT 101 Divide by 6 2 08 MHz at 100 MHz SYSCLKOUT 110 Divide by 7 1 78 MHz...

Page 796: ...ck Copyright 2012 2019 Texas Instruments Incorporated C28 Enhanced Pulse Width Modulator ePWM Module Table 7 59 PWM Chopper Control Register PCCTL Bit Descriptions continued Bit Field Value Descriptio...

Page 797: ...ip zone 6 TZ6 Select 0 Disable TZ6 as a one shot trip source for this ePWM module 1 Enable TZ6 as a one shot trip source for this ePWM module 12 OSHT5 Trip zone 5 TZ5 Select 0 Disable TZ5 as a one sho...

Page 798: ...1 Enable TZ2 as a CBC trip source for this ePWM module 0 CBC1 Trip zone 1 TZ1 Select 0 Disable TZ1 as a CBC trip source for this ePWM module 1 Enable TZ1 as a CBC trip source for this ePWM module Fig...

Page 799: ...pedance state 01 Force EPWMxA to a high state 10 Force EPWMxA to a low state 11 Do nothing no action is taken on EPWMxA Figure 7 112 Trip Zone Enable Interrupt Register TZEINT 15 8 Reserved R 0 7 6 5...

Page 800: ...dicates a trip event has occurred for the event defined for DCAEVT1 2 OST Latched Status Flag for A One Shot Trip Event 0 No one shot trip event has occurred 1 Indicates a trip event has occurred on a...

Page 801: ...has no effect This bit always reads back 0 1 Writing 1 clears the DCBEVT2 event trip condition 5 DCBEVT1 Clear Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect This bit always reads...

Page 802: ...eads back 0 1 Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG DCBEVT1 bit 4 DCAEVT2 Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect This bit always reads...

Page 803: ...110 reserved 111 reserved 8 6 DCBEVT1 Digital Compare Output B Event 1 Selection 000 Event disabled 001 DCBH low DCBL don t care 010 DCBH high DCBL don t care 011 DCBL low DCBH don t care 100 DCBL hi...

Page 804: ...ut 0001 TRIPIN2 and TZ2 input 0010 TRIPIN3 and TZ3 input 0011 TRIPIN4 1011 TRIPIN12 1100 Reserved 1101 TRIPIN14 1110 TRIPIN15 1111 Trip combination input all trip inputs selected by DCBLTRIPSEL regist...

Page 805: ...4 3 2 1 0 Reserved EVT1SYNCE EVT1SOCE EVT1FRC SYNCSEL EVT1SRCSEL R 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 7 68 Digital Compare A Control Register DCACTL...

Page 806: ...ct 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal 7 4 Reserved Reserved 3 EVT1SYNCE DCBEVT1 SYNC Enable Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled 2 EVT1SOCE DCBEVT1 SOC Ena...

Page 807: ...11 Source Is DCBEVT2 Signal Figure 7 121 Digital Compare Capture Control Register DCCAPCTL 15 8 Reserved R 0 7 2 1 0 Reserved SHDWMODE CAPE R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value a...

Page 808: ...0 LEGEND R W Read Write R Read only n value after reset Table 7 73 Digital Compare Filter Offset Register DCFOFFSET Field Descriptions Bit Field Value Description 15 0 OFFSET 0000 FFFFh Blanking Windo...

Page 809: ...started The blanking window can cross a PWM period boundary Figure 7 126 Digital Compare Filter Window Counter Register DCFWINDOWCNT 15 8 Reserved R 0 7 0 WINDOWCNT R 0 LEGEND R W Read Write R Read on...

Page 810: ...8 TRIPIN9 TRIP Input 9 0 Trip Input 9 not selected as combinational ORed input 1 Trip Input 9 selected as combinational ORed input to DCAH mux 7 TRIPIN8 TRIP Input 8 0 Trip Input 8 not selected as co...

Page 811: ...selected as combinational ORed input to DCAL mux 10 TRIPIN11 TRIP Input 11 0 Trip Input 11 not selected as combinational ORed input 1 Trip Input 11 selected as combinational ORed input to DCAL mux 9...

Page 812: ...ved 14 TRIPIN15 TRIP Input 15 0 Trip Input 15 not selected as combinational ORed input 1 Trip Input 15 selected as combinational ORed input to DCBH mux 13 TRIPIN14 TRIP Input 14 0 Trip Input 14 not se...

Page 813: ...8 Reserved TRIPIN15 TRIPIN14 Reserved TRIPIN12 TRIPIN11 TRIPIN10 TRIPIN9 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 TRIPIN8 TRIPIN7 TRIPIN6 TRIPIN5 TRIPIN4 TRIPIN3 TRIPIN2 TRIPIN1 R...

Page 814: ...ip Input 6 not selected as combinational ORed input 1 Trip Input 6 selected as combinational ORed input to DCBL mux 4 TRIPIN5 TRIP Input 5 0 Trip Input 5 not selected as combinational ORed input 1 Tri...

Page 815: ...ze x16 Description GPTRIP1SEL 0x5FE0 1 GPTRIP1 TZ1n Input Select Register GPIO0 GPIO63 GPTRIP2SEL 0x5FE1 1 GPTRIP2 TZ2n ADCEXTTRIG Input Select Register GPIO0 GPIO63 GPTRIP3SEL 0x5FE2 1 GPTRIP3 TZ3n I...

Page 816: ...s Incorporated C28 Enhanced Pulse Width Modulator ePWM Module Table 7 83 GPIO Trip Input Select Register GPTRIPxSEL Field Descriptions Bit Field Value Description 15 6 Reserved Reserved 5 0 GPTRIPxSEL...

Page 817: ...s incrementing or CMPC when the timer is incrementing 101 Enable event time base counter equal to CMPA when the timer is decrementing or CMPC when the timer is decrementing 110 Enable event time base...

Page 818: ...mux 4 SOCASELCMP EPWMxSOCA Compare Register Selection Options 0 Enable event time base counter equal to CMPA when the timer is incrementing Enable event time base counter equal to CMPA when the timer...

Page 819: ...A Event EPWMxSOCA Period Select These bits determine how many selected ETSEL SOCASEL events need to occur before an EPWMxSOCA pulse is generated To be generated the pulse must be enabled ETSEL SOCAEN...

Page 820: ...alue that is equal to the current counter value will trigger an interrupt if it is enabled and the status flag is cleared and INTCNT will also be cleared to 0 Writing an INTPRD value that is LESS than...

Page 821: ...nt Figure 7 135 Event Trigger SOC Pre Scale Register ETSOCPS 15 12 11 8 SOCBCNT2 SOCBPRD2 R 0 0 R W 0 0 7 4 3 0 SOCACNT2 SOCAPRD2 R 0 0 R W 0 0 LEGEND R W Read Write R Read only n value after reset Ta...

Page 822: ...OCA Reserved INT R 0 R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 7 88 Event Trigger Flag Register ETFLG Field Descriptions Bit Field Value Description 15 4 Reserved Res...

Page 823: ...o be generated Figure 7 138 Event Trigger Force Register ETFRC 15 8 Reserved R 0 7 4 3 2 1 0 Reserved SOCB SOCA Reserved INT R 0 R W 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after r...

Page 824: ...Has no effect 1 Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT SOCAINIT on a SYNC event or software force 13 INTINITEN EPWMxINT Counter 2 Initialization Enable 0 Has no effect 1...

Page 825: ...1 8 SOCBINIT EPWMxSOCB Counter 2 Initialization Bits 0000 1111 The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force 7 4 SOCAINIT EPWMxSO...

Page 826: ...heral clock is enabled it may be possible that interrupt flags may be set due to spurious events due to the ePWM registers not being properly initialized The proper procedure for initializing the ePWM...

Page 827: ...nt The eCAP module described in this reference guide is a Type 0 eCAP See the TMS320C28xx 28xxx DSP Peripheral Reference Guide SPRU566 for a list of all devices with a eCAP module of the same type to...

Page 828: ...ime stamps in a four deep circular buffer Absolute time stamp capture Difference Delta mode time stamp capture All above resources dedicated to a single input pin When not used in capture mode the ECA...

Page 829: ...it is not being used for input captures The counter operates in count up mode providing a time base for asymmetrical pulse width modulation PWM waveforms The CAP1 and CAP2 registers become the active...

Page 830: ...0 31 clear clear CTR 0 31 set set Capture Mode Description www ti com 830 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated...

Page 831: ...4 APRD shadow 32 32 MODE SELECT ECCTL2 SYNCI_EN SYNCOSEL SWSYNC ECCTL2 CAP APWM Edge Polarity Select ECCTL1 CAPxPOL ECCTL1 EVTPS ECCTL1 CAPLDEN CTRRSTx ECCTL2 RE ARM CONT ONESHT STOP_WRAP Registers EC...

Page 832: ...e Function Waveforms 8 4 2 Edge Polarity Select and Qualifier Four independent edge polarity rising edge falling edge selection MUXes are used one for each capture event Each edge up to 4 is event qua...

Page 833: ...ng prepares the eCAP module for another capture sequence Also re arming clears to zero the Mod4 counter and permits loading of CAP1 4 registers again providing the CAPLDEN bit is set In continuous mod...

Page 834: ...1 and CAP2 during APWM operation 8 4 6 Interrupt Control An Interrupt can be generated on capture events CEVT1 CEVT4 CTROVF or APWM events CTR PRD CTR CMP A counter overflow event FFFFFFFF 00000000 is...

Page 835: ...mit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Enhanced Capture eCAP Module Note The CEVT1 CEVT2 CEVT3 CEVT4 flags are only active in capture mode ECCTL2 CAP APWM 0...

Page 836: ...rs CAP3 CAP4 This emulates immediate mode Writing to the shadow registers CAP3 CAP4 will invoke the shadow mode During initialization you must write to the active registers for both period and compare...

Page 837: ...1 T 1 F T www ti com Capture Mode Description 837 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Enhanced Capture eCAP...

Page 838: ...hat can be programmed for phase lag lead This register shadows TSCTR and is loaded into TSCTR upon either a SYNCI event or S W force via a control bit Used to achieve phase control synchronization wit...

Page 839: ...31 0 CAP4 R W 0 LEGEND R W Read Write R Read only n value after reset Table 8 6 Capture 4 Register CAP4 Field Descriptions Bit s Field Description 31 0 CAP4 In CMP mode this is a time stamp capture r...

Page 840: ...reset counter on Capture Event 3 absolute time stamp 1 Reset counter after Event 3 time stamp has been captured used in difference mode operation 4 CAP3POL Capture Event 3 Polarity select 0 Capture Ev...

Page 841: ...a one forces a TSCTR shadow load of current ECAP module and any ECAP modules down stream providing the SYNCO_SEL bits are 0 0 After writing a 1 this bit returns to a zero Note Selection CTR PRD is mea...

Page 842: ...r Capture Event 3 in one shot mode Wrap after Capture Event 3 in continuous mode 11 Stop after Capture Event 4 in one shot mode Wrap after Capture Event 4 in continuous mode Notes STOP_WRAP is compare...

Page 843: ...source 1 Enable counter Overflow as an Interrupt source 4 CEVT4 Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source 1 Capture Event 4 Interrupt Enable 3 CEVT3 Capture Ev...

Page 844: ...r Overflow Status Flag This flag is active in CAP and APWM mode 0 Indicates no event occurred 1 Indicates the counter TSCTR has made the transition from FFFFFFFF 00000000 4 CEVT4 Capture Event 4 Statu...

Page 845: ...reads back a 0 1 Writing a 1 clears the CEVT3 flag condition 2 CEVT2 Capture Event 2 Status Flag 1 Writing a 0 has no effect Always reads back a 0 0 Writing a 1 clears the CEVT2 flag condition 1 CEVT1...

Page 846: ...0 8 6 Register Mapping Table 8 13 shows the eCAP module control and status register set Table 8 13 Control and Status Register Set Name Offset Size x16 Description Time Base Module Registers TSCTR 0x...

Page 847: ..._SYNCIN 0x0 define EC_CTR_PRD 0x1 define EC_SYNCO_DIS 0x2 CAP APWM mode bit define EC_CAP_MODE 0x0 define EC_APWM_MODE 0x1 APWMPOL bit define EC_ACTV_HI 0x0 define EC_ACTV_LO 0x1 Generic define EC_DIS...

Page 848: ...ECCTL1 bit CTRRST2 EC_ABS_MODE ECap1Regs ECCTL1 bit CTRRST3 EC_ABS_MODE ECap1Regs ECCTL1 bit CTRRST4 EC_ABS_MODE ECap1Regs ECCTL1 bit CAPLDEN EC_ENABLE ECap1Regs ECCTL1 bit PRESCALE EC_DIV1 ECap1Regs...

Page 849: ...2012 2019 Texas Instruments Incorporated C28 Enhanced Capture eCAP Module 8 7 2 Example 2 Absolute Time Stamp Operation Rising and Falling Edge Trigger In Figure 8 24 the eCAP operating mode is almos...

Page 850: ...E ECap1Regs ECCTL1 bit CTRRST2 EC_ABS_MODE ECap1Regs ECCTL1 bit CTRRST3 EC_ABS_MODE ECap1Regs ECCTL1 bit CTRRST4 EC_ABS_MODE ECap1Regs ECCTL1 bit CAPLDEN EC_ENABLE ECap1Regs ECCTL1 bit PRESCALE EC_DIV...

Page 851: ...re mode TSCTR counts up without resetting and Mod4 counter wraps around is used In Delta time mode TSCTR is Reset back to Zero on every valid event Here Capture events are qualified as Rising edge onl...

Page 852: ...LTA_MODE ECap1Regs ECCTL1 bit CTRRST2 EC_DELTA_MODE ECap1Regs ECCTL1 bit CTRRST3 EC_DELTA_MODE ECap1Regs ECCTL1 bit CTRRST4 EC_DELTA_MODE ECap1Regs ECCTL1 bit CAPLDEN EC_ENABLE ECap1Regs ECCTL1 bit PR...

Page 853: ...ration Rising and Falling Edge Trigger In Figure 8 26 the eCAP operating mode is almost the same as in previous section except Capture events are qualified as either Rising or Falling edge this now gi...

Page 854: ...TRRST2 EC_DELTA_MODE ECap1Regs ECCTL1 bit CTRRST3 EC_DELTA_MODE ECap1Regs ECCTL1 bit CTRRST4 EC_DELTA_MODE ECap1Regs ECCTL1 bit CAPLDEN EC_ENABLE ECap1Regs ECCTL1 bit PRESCALE EC_DIV1 ECap1Regs ECCTL2...

Page 855: ...evel of the period Alternatively if the APWMPOL bit is configured for active low then the compare value represents the off time Note here values are in hexadecimal h notation 8 8 1 Example 1 Simple PW...

Page 856: ...cumentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Enhanced Capture eCAP Module Example 8 1 Code Snippet for APWM Mode continued Set Duty cycle that is compare value Run Time...

Page 857: ...ne the differences between types and for a list of device specific differences within a type The enhanced quadrature encoder pulse eQEP module is used for direct interface with a linear or rotary incr...

Page 858: ...ive direction information the lines on the disk are read out by two different photo elements that look at the disk pattern with a mechanical shift of 1 4 the pitch of a line pair between them This shi...

Page 859: ...shaft encoders include robotics and even computer input in the form of a mouse Inside your mouse you can see where the mouse ball spins a pair of axles a left right and an up down axle These axles are...

Page 860: ...speeds one approach is to use Equation 2 at low speed and have the DSP software switch over to Equation 1 when the motor speed rises above some specified threshold 9 2 Description This section provid...

Page 861: ...QEP eQEP Module 9 2 2 Functional Description The eQEP peripheral contains the following major functional units as shown in Figure 9 4 Programmable input qualification for each pin part of the GPIO MUX...

Page 862: ...0 0x0000 eQEP Watchdog Period Register QDECCTL 0x14 1 0 0x0000 eQEP Decoder Control Register QEPCTL 0x15 1 0 0x0000 eQEP Control Register QCAPCTL 0x16 1 0 0x0000 eQEP Capture Control Register QPOSCTL...

Page 863: ...QDF EQEPA EQEPB www ti com Quadrature Decoder Unit QDU 863 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Enhanced QE...

Page 864: ...and accordingly updates the direction information in QEPSTS QDF bit Table 9 2 and Figure 9 6 show the direction decoding logic in truth table and state machine form Both edges of the QEPA and QEPB si...

Page 865: ...count operation QEPA input is fed to the QA input of the quadrature decoder and the QEPB input is fed to the QB input of the quadrature decoder Reverse counting is enabled by setting the SWAP bit in...

Page 866: ...some systems the position counter is accumulated continuously for multiple revolutions and the position counter value provides the position information with respect to the known reference An example...

Page 867: ...upt flag QFLG PCE are set if the latched value is not equal to 0 or QPOSMAX The position counter error flag QEPSTS PCEF is updated on every index event marker and an interrupt flag QFLG PCE will be se...

Page 868: ...reset to the value in the QPOSMAX register on the next eQEP clock Note that this is done only on the first occurrence and subsequently the position counter value is not reset on an index event rather...

Page 869: ...tion counter accumulated the correct number of counts between index events As an example the 1000 line encoder must count 4000 times when moving in the same direction between the index events The inde...

Page 870: ...ounter can be initialized using following events Index event Strobe event Software initialization Index Event Initialization IEI The QEPI index input can be used to trigger the initialization of the p...

Page 871: ...sition compare Unit In shadow mode you can configure the position compare unit QPOSCTL PCLOAD to load the shadow register value into the active register on the following events and to generate the pos...

Page 872: ...the position compare unit generates a programmable position compare sync pulse output on the position compare match In the event of a new position compare match while a previous position compare pulse...

Page 873: ...n unit position events will be correct if the following conditions are met No more than 65 535 counts have occurred between unit position events No direction change between unit position events The ca...

Page 874: ...vised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Enhanced QEP eQEP Module Figure 9 15 eQEP Edge Capture Unit NOTE The QCAPCTL UPPS prescaler sho...

Page 875: ...Calculation Equations 4 where v k Velocity at time instant k x k Position at time instant k x k 1 Position at time instant k 1 T Fixed unit time or inverse of velocity calculation rate X Incremental p...

Page 876: ...rol system The eQEP watchdog timer is clocked from SYSCLKOUT 64 and the quadrate clock event pulse resets the watchdog timer If no quadrature clock event is detected until a period match QWDPRD QWDTMR...

Page 877: ...nterrupt events is enabled the flag bit is 1 and the INT flag bit is 0 The interrupt service routine will need to clear the global interrupt flag bit and the serviced event via the interrupt clear reg...

Page 878: ...input to the quadrature decoder reversing the counting direction 0 Quadrature clock inputs are not swapped 1 Quadrature clock inputs are swapped 9 IGATE Index pulse gating option 0 Disable gating of...

Page 879: ...ing edge of the QEPS signal 11 Clockwise Direction Initializes the position counter on the rising edge of QEPS strobe Counter Clockwise Direction Initializes the position counter on the falling edge o...

Page 880: ...and QCPRDLAT registers on unit time out 1 UTE eQEP unit timer enable 0 Disable eQEP unit timer 1 Enable unit timer 0 WDE eQEP watchdog enable 0 Disable the eQEP watchdog timer 1 Enable the eQEP watch...

Page 881: ...LK SYSCLKOUT 32 CAPCLK SYSCLKOUT 64 CAPCLK SYSCLKOUT 128 3 0 UPPS Unit position event prescaler 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 11xx UPEVNT QCLK 1 UPEVNT QCLK 2 UPEVNT QCLK...

Page 882: ...n 31 0 QPOSMAX This register contains the maximum position counter value Writes to this register should always be full 32 bit writes Figure 9 28 eQEP Position compare QPOSCMP Register 31 0 QPOSCMP R W...

Page 883: ...QEP Unit Timer QUTMR Register 31 0 QUTMR R W 0 LEGEND R W Read Write R Read only n value after reset Table 9 14 eQEP Unit Timer QUTMR Register Field Descriptions Bits Name Description 31 0 QUTMR This...

Page 884: ...eral watch dog timer When the watchdog timer value matches the watchdog period value a watchdog timeout interrupt is generated Figure 9 36 eQEP Interrupt Enable QEINT Register 15 12 11 10 9 8 Reserved...

Page 885: ...erved Reserved Figure 9 37 eQEP Interrupt Flag QFLG Register 15 12 11 10 9 8 Reserved UTO IEL SEL PCM R 0 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 PCR PCO PCU WTO QDC PHE PCE INT R 0 R 0 R 0 R 0 R 0 R 0 R 0 R...

Page 886: ...terrupt generated 1 Set on simultaneous transition of QEPA and QEPB 1 PCE Position counter error interrupt flag 0 No interrupt generated 1 Position counter error 0 INT Global interrupt status flag 0 N...

Page 887: ...PHE Clear quadrature phase error interrupt flag 0 No effect 1 Clears the interrupt flag 1 PCE Clear position counter error interrupt flag 0 No effect 1 Clears the interrupt flag 0 INT Global interrupt...

Page 888: ...terrupt 0 No effect 1 Force the interrupt 2 PHE Force quadrature phase error interrupt 0 No effect 1 Force the interrupt 1 PCE Force position counter error interrupt 0 No effect 1 Force the interrupt...

Page 889: ...e occurred between the capture position event 1 FIMF First index marker flag 0 Sticky bit cleared by writing 1 1 Set by first occurrence of index pulse 0 PCEF Position counter error flag This bit is n...

Page 890: ...QEP capture timer value can be latched into this register on two events viz unit timeout event reading the eQEP position counter Figure 9 44 eQEP Capture Period Latch QCPRDLAT Register 15 0 QCPRDLAT R...

Page 891: ...ADC and the Comparator function described here is a Type 0 Comparator See the TMS320C28xx 28xxx DSP Peripheral Reference Guide SPRU566 for a list of all devices with modules of the same type to determ...

Page 892: ...l 10 bit DACs The analog subsystem is accessed by the analog common interface bus ACIB The ACIB is responsible for transferring triggers initiated by the control subsystem to the analog subsystem and...

Page 893: ...ter accesses across the ACIB are handled as data read and write operations Trigger and interrupt signals are specially encoded by the ACIB for lower latency behavior ACIB buffers on both the digital a...

Page 894: ...sed November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated Analog Subsystem The ACIB buffer can store a single write operation from the digital subsystem in ord...

Page 895: ...4 7 0 Digital Buffer Analog Buffer Sync Stall Clock Bus 7 0 Size R W Addr 15 8 Addr 7 0 Word 1 15 8 Word 1 7 0 Read Stall Ready Ready 2 3 Cycle Sync Stall Word 2 15 8 Word 2 7 0 Digital Buffer Analog...

Page 896: ...a total of up to 16 analog input channels See the device datasheet for the specific number of channels available The converter can be configured to run with an internal bandgap reference to create tru...

Page 897: ...ion Contrary to previous ADC types this ADC is not sequencer based Instead it is SOC based The term SOC is the configuration set defining the single conversion of a single channel In that set there ar...

Page 898: ...one of the SOCs using its ADCSOCxCTL register It makes no difference which SOC we choose so we ll use SOC0 It also makes no difference which ADC trigger we choose so we ll use ADC trigger 1 The faste...

Page 899: ...2 will show up in ADCRESULT1 The result of the conversion on channel ADCINA3 will show up in ADCRESULT2 The channel converted and the trigger have no bearing on where the result of the conversion show...

Page 900: ...OCxCTL register has a 6 bit field ACQPS that determines the sample and hold S H window size The value written to this field is one less than the number of cycles desired for the sampling window for th...

Page 901: ...nfigured to convert any of the available ADCIN input channels When an SOC is configured for sequential sampling mode the four bit CHSEL field of the ADCSOCxCTL register defines which channel to conver...

Page 902: ...ty When multiple SOC flags are set at the same time one of two forms of priority determines the order in which they are converted The default priority method is round robin In this scheme no SOC has a...

Page 903: ...SOC2 SOC12 triggers rcvd simultaneously SOC12 is first on round robin wheel SOC12 configured channel is converted while SOC2 stays pending RRPOINTER changes to point to SOC 12 SOC2 configured channel...

Page 904: ...0 SOC 4 SOC 8 SOC 2 SOC 14 SOC 6 SOC 10 SOC 15 SOC 1 SOC 3 SOC 5 SOC 7 SOC 9 SOC 11 SOC 13 RRPOINTER default 32 A High Priority SOC 12 SOC 0 SOC 4 SOC 8 SOC 2 SOC 14 SOC 6 SOC 10 SOC 15 SOC 1 SOC 3 S...

Page 905: ...ill be sampled simultaneously assuming priority Immediately after the ADCINA2 channel will be converted and its value will be stored in the ADCRESULT0 register Depending on the ADCCTL1 INTPULSEPOS set...

Page 906: ...ly supported 3 Enable the ADC by setting bit 14 ADCENABLE of the ADCCTL1 register 4 Before performing the first conversion a delay of 1 millisecond after step 2 is required Alternatively steps 1 throu...

Page 907: ...ng for the results will not be affected and the full dynamic range of the ADC will be maintained for any trim value Calling the Device_cal function writes the ADCOFFTRIM register with the factory cali...

Page 908: ...d VREFLO must be tied to ground in this mode This is done internally on some devices 10 3 10 2 External Reference Voltage To convert the voltage presented as a ratiometric signal the external VREFHI V...

Page 909: ...the ADCRESULT registers are found in the AdcResult register file not AdcRegs Table 10 5 ADC Configuration and Control Registers AdcRegs and AdcResult Register Name Address Offset Size x16 Description...

Page 910: ...the device reset pin is pulled low or after a power on reset This is a one time effect bit meaning this bit is self cleared immediately after it is set to 1 Read of this bit always returns a 0 0 No e...

Page 911: ...tly processing or was last ADC SOC executed 1xh Invalid value 7 ADCPWDN ADC power down active low This bit controls the power up and power down of all the analog circuitry inside the analog core excep...

Page 912: ...ptions are shown below Figure 10 19 ADC Interrupt Flag Register ADCINTFLG Address Offset 04h 15 9 8 Reserved R 0 7 6 5 4 3 2 1 0 ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 ADCINT2 ADCINT1 R 0 R 0...

Page 913: ...G bit was previously set or not Figure 10 21 ADC Interrupt Overflow Register ADCINTOVF Address Offset 06h 15 9 8 Reserved R 0 7 6 5 4 3 2 1 0 ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 ADCINT2 AD...

Page 914: ...et 08h 15 14 13 12 8 Reserved INT2CONT INT2E INT2SEL R 0 R W 0 R W 0 R W 0 7 6 5 4 0 Reserved INT1CONT INT1E INT1SEL R 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Figure...

Page 915: ...rupt Enable 0 ADCINTy is disabled 1 ADCINTy is enabled 12 8 INTySEL ADCINTy EOC Source Select 00h EOC0 is trigger for ADCINTy 01h EOC1 is trigger for ADCINTy 02h EOC2 is trigger for ADCINTy 03h EOC3 i...

Page 916: ...or ADCINTx 08h EOC8 is trigger for ADCINTx 09h EOC9 is trigger for ADCINTx 0Ah EOC10 is trigger for ADCINTx 0Bh EOC11 is trigger for ADCINTx 0Ch EOC12 is trigger for ADCINTx 0Dh EOC13 is trigger for A...

Page 917: ...was last round robin SOC to convert SOC15 is highest round robin priority 0Fh SOC15 was last round robin SOC to convert SOC0 is highest round robin priority 1xh Invalid value 20h Reset value to indica...

Page 918: ...ts of CHSEL field define channel to be converted EOC12 associated with SOC12 EOC13 associated with SOC13 SOC12 s result placed in ADCRESULT12 register SOC13 s result placed in ADCRESULT13 1 Simultaneo...

Page 919: ...en the ADC is actively converting SOC2 or SOC3 0 Single sample mode set for SOC2 and SOC3 All bits of CHSEL field define channel to be converted EOC2 associated with SOC2 EOC3 associated with SOC3 SOC...

Page 920: ...OC12 SOC11 SOC10 SOC9 SOC8 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 SOC7 SOC6 SOC5 SOC4 SOC3 SOC2 SOC1 SOC0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset...

Page 921: ...0 LEGEND R W Read Write R Read only n value after reset Table 10 19 ADC SOC Overflow 1 Register ADCSOCOVF1 Field Descriptions Bit Field Value Description 15 0 SOCx x 15 to 0 SOCx Start of Conversion...

Page 922: ...egister Field Descriptions Bit Field Value Description 15 11 TRIGSEL SOCx Trigger Source Select Configures which trigger will set the respective SOCx flag in the ADCSOCFLG1 register to intiate a conve...

Page 923: ...Sequential Sampling Mode SIMULENx 0 0h ADCINA0 1h ADCINA1 2h ADCINA2 3h ADCINA3 4h ADCINA4 5h ADCINA5 6h ADCINA6 7h ADCINA7 8h ADCINB0 9h ADCINB1 Ah ADCINB2 Bh ADCINB3 Ch ADCINB4 Dh ADCINB5 Eh ADCINB6...

Page 924: ...ers for which trigger source will be tied to each ADC trigger 10 3 11 6 ADC Calibration Registers NOTE The following ADC Calibration Registers are EALLOW protected Figure 10 37 ADC Reference Gain Trim...

Page 925: ...Result Registers are found in Peripheral Frame 0 PF0 In the header files the ADCRESULTx registers are located in the AdcxResult register file not AdcxRegs The ADC Result Registers can also be accessed...

Page 926: ...ol System Lock Register 1 CCIBSTATUS 41h 1 Control System ACIB Status Register CCLKCTL 42h 1 Control System Clock Control 1 TRIGOVF 50h 1 ADC Trigger Overflow Detect TRIGOVFCLR 51h 1 ADC Trigger Overf...

Page 927: ...DC Interrupt Overflow Detect Register INTOVF Field Descriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 ADCINT8 ADCINT8 Overflow Flag Status 0 No overflow 1 Overflow detected 6 ADCINT7...

Page 928: ...ADC Interrupt Overflow Clear Register INTOVFCLR Field Descriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 ADCINT8 ADCINT8 Overflow Flag Clear 0 No action 1 Clears overflow flag 6 ADCIN...

Page 929: ...0 LEGEND R W Read Write R Read only n value after reset Table 10 29 Control System Lock Register CLOCK Field Descriptions Bit Field Value Description 15 8 PSWD 0 FFh Write protection password The CCL...

Page 930: ...ad Write R Read only n value after reset Table 10 30 Control System ACIB Status Register CCIBSTATUS Field Descriptions Bit Field Value Description 15 8 ASYSCLKCNT 0 FFh 8 bit ACIB Bus Clock Counter Th...

Page 931: ...Figure 10 45 Control System Clock Control Register CCLKCTL 15 8 Reserved R 0 7 3 2 0 Reserved CLKDIV R 0 R W h LEGEND R W Read Write R Read only n value after reset Table 10 31 Control System Clock C...

Page 932: ...cription 15 8 Reserved 0 Reserved 7 TRIG8 Indicates if overflow occurred on respective ADC trigger 0 No overflow 1 Overflow detected 6 TRIG7 Indicates if overflow occurred on respective ADC trigger 0...

Page 933: ...Field Descriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 TRIG8 Clears ADC trigger overflow flag in TRIGOVF register 0 No action 1 Clears overflow flag 6 TRIG7 Clears ADC trigger overf...

Page 934: ...erved 4 0 TRIGxSEL Analog Trigger TRIGx MUX Input Select 00000 No selection Disabled 00001 TINT0 CPU Timer 0 00010 TINT1 CPU Timer 1 00011 TINT2 CPU Timer 2 00100 ADCEXTTRIG C28 GPIO MUX 00101 EPWM1SO...

Page 935: ...CLKs 1 ADCCLK Analog Input SOC1 Sample Window SOC0 Sample Window SOC2 Sample Window A www ti com Analog to Digital Converter ADC 935 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Fe...

Page 936: ...se EOC2 Pulse 2 ADCCLKs Analog Input SOC1 Sample Window SOC0 Sample Window SOC2 Sample Window A Analog to Digital Converter ADC www ti com 936 SPRUHE8E October 2012 Revised November 2019 Submit Docume...

Page 937: ...1 ADCCLK 2 ADCCLKs 2 ADCCLKs Analog Input B SOC0 Sample B Window SOC2 Sample B Window Analog Input A SOC0 Sample A Window SOC2 Sample A Window A A www ti com Analog to Digital Converter ADC 937 SPRUH...

Page 938: ...sult 0 A and Result 0 B latched on their respective cycles does not include the additional cycles required for the C28x and M3 subsystems to read the ADC result registers using the ACIB 10 4 Comparato...

Page 939: ...ock The truth table for the comparator is shown in Table 10 35 Figure 10 54 Comparator Table 10 35 Comparator Truth Table Voltages Output Voltage A Voltage B 1 Voltage B Voltage A 0 There is no defini...

Page 940: ...l Domain Manipulation At the output of the comparator there are two more functional blocks that can be used to influence the behavior of the comparator output They are 1 Inverter circuit Controlled by...

Page 941: ...000 1 Comparator Control 1 Reserved 0x0000 0001 1 Reserved COMPSTS 0x0000 0002 1 Comparator Output Status Reserved 0x0000 0003 1 Reserved Reserved 0x0000 0004 1 Reserved Reserved 0x0000 0005 1 Reserve...

Page 942: ...comparator is passed 1 COMPSOURCE Source select for comparator inverting input 0 Inverting input of comparator connected to internal DAC 1 Inverting input connected to external pin 0 COMPDACEN Compar...

Page 943: ...stemClock unsigned short ClockDivider unsigned short AnalogClockEnable unsigned short AnalogConfigReg unsigned short AnalogClockMask unsigned short AnalogClockDisable unsigned short AnalogConfigReg un...

Page 944: ...tion 10 5 2 10 5 1 3 AnalogClockDisable Function The AnalogClockDisable function disables the clock to each Analog Subsystem peripheral This function requires two input parameters Valid define values...

Page 945: ...log Config 1 Register for correct values bit 3 should be set analogclock2 ReadAnalogClockStatus AnalogConfig2 Check Analog Config 2 Register for correct values bits 15 3 0 should be set EDIS NOTE Bits...

Page 946: ...to Enable ADC1 ADC2_ENABLE 0x8000 Mask to Enable ADC2 COMP1_ENABLE 0x0001 Mask to Enable COMP1 COMP2_ENABLE 0x0002 Mask to Enable COMP2 COMP3_ENABLE 0x0004 Mask to Enable COMP3 COMP4_ENABLE 0x0008 Mas...

Page 947: ...LE Enable ADC 2 COMP1 and COMP4 analogclock1 ReadAnalogClockStatus AnalogConfig1 Check Analog Config 1 Register for correct values bit 3 should be set analogclock2 ReadAnalogClockStatus AnalogConfig2...

Page 948: ...without intervention from the CPU thereby freeing up bandwidth for other system functions Additionally the DMA has the capability to orthogonally rearrange the data as it is transferred as well as pi...

Page 949: ...source there is no mechanism within the module itself to start memory transfers periodically The interrupt trigger source for each of the six DMA channels can be configured separately and each channel...

Page 950: ...Diagram 11 2 2 Peripheral Interrupt Event Trigger Sources The peripheral interrupt event trigger can be independently configured as one twenty nine different sources for each of the six DMA channels I...

Page 951: ...channel Once the burst transfer starts the flag is cleared If a new interrupt trigger is generated while a burst is in progress the burst will complete before responding to the new interrupt trigger...

Page 952: ...ADC Start of Conversion A ADC Start of Conversion B ePWM5 ADC Start of Conversion A ADC Start of Conversion B ePWM6 ADC Start of Conversion A ADC Start of Conversion B ePWM7 ADC Start of Conversion A...

Page 953: ...ce A read of a McBSP DRR register stalls the DMA bus for one cycle during the read portion of the transfer as shown in Figure 11 4 Figure 11 3 4 Stage Pipeline DMA Transfer Figure 11 4 4 Stage Pipelin...

Page 954: ...transfer is completed with one DMA burst The cycles required for this transfer is 16 256 64 150 37 5 2 256 32 1 272 Cycles 11 4 CPU Arbitration Typically DMA activity is independent of the CPU activi...

Page 955: ...DMA accessing the same RAM block concurrently thus avoiding any stalls or corruption issues 11 4 1 Arbitration when Accessing the Analog Subsystem The DMA read cycles to the analog subsystem must pass...

Page 956: ...H3 burst will be serviced followed by CH5 burst Now while the CH5 burst is being serviced the DMA receives a request from CH1 CH3 and CH6 The burst from CH6 will start after the completion of the CH5...

Page 957: ...each word is transferred the signed value contained in the appropriate source or destination BURST_STEP register is added to the active SRC DST_ADDR register During the transfer loop after each burst...

Page 958: ...The TRANSFER_COUNT register keeps track of how many bursts of data the channel has transferred and when it reaches zero the DMA transfer is complete Source Destination Wrap Size SRC DST_WRAP_SIZE Thi...

Page 959: ...hen ONESHOT mode is enabled the DMA will continuously transfer bursts of data on the given channel until the TRANSFER_COUNT value is zero This could potentially hog the bandwidth of a peripheral and c...

Page 960: ...ve DST_ADDR BURST_COUNT ADDR BURST_STEP BURST_ COUNT 0 No BURSTSTS 0 TRANSFER_ COUNT 0 Yes No WRAP_ COUNT 0 Yes No BEG_ADDR WRAP_STEP ADDR BEG_ADDR WRAP_COUNT WRAP_SIZE WRAP_COUNT TRANSFER_COUNT ONESH...

Page 961: ...BEG_ADDR WRAP_STEP ADDR BEG_ADDR The active registers get updated when a sync error occurs The shadow registers remain unchanged Specifically BEG_ADDR_SHADOW remains unchanged ADDR_SHADOW remains unch...

Page 962: ...end of transfer MODE CHx CHINTE PERx_INT CONTROL CHx ERRCLR MODE CHx OVERNITE Overrun Detection Feature www ti com 962 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyrig...

Page 963: ...ion 11 8 9 0x1024 SRC_BURST_STEP Source Burst Step Size Register Section 11 8 10 0x1025 DST_BURST_STEP Destination Burst Step Size Register Section 11 8 11 0x1026 TRANSFER_SIZE Transfer Size Register...

Page 964: ...hown in Figure 11 8 and described in Table 11 3 Figure 11 8 DMA Control Register DMACTRL 15 8 Reserved R 0 7 2 1 0 Reserved PRIORITY RESET HARD RESET R 0 R0 S 0 R0 S 0 LEGEND R0 S Read 0 Set R Read on...

Page 965: ...ice reset Writes of 0 are ignored and this bit always reads back a 0 For a soft reset a bit is provided for each channel to perform a gentler reset Refer to the channel control registers If the DMA wa...

Page 966: ...HALT points in Figure 11 6 for possible halt states 1 DMA is unaffected by emulation suspend run free 14 0 Reserved Reserved 11 8 3 Revision Register REVISION The revision register REVISION is shown...

Page 967: ...1 Priority Control Register 1 PRIORITYCTRL1 15 1 0 Reserved CH1 PRIORITY R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 11 6 Priority Control Register 1 PRIORITYCTRL1 Field Desc...

Page 968: ...rved 6 4 ACTIVESTS_SH ADOW Active Channel Status Shadow Bits These bits are only useful when CH1 is enabled as a higher priority channel When CH1 is serviced the ACTIVESTS bits are copied to the shado...

Page 969: ...for details 13 12 Reserved Reserved 11 CONTINUOUS Continuous Mode Bit If this bit is set to 1 then DMA re initializes when TRANSFER_COUNT is zero and waits for the next interrupt event trigger If thi...

Page 970: ...it Value Interrupt Sync Peripheral 0 None None No peripheral connection 1 ADCINT1 None ADC 2 ADCINT2 None 3 XINT1 None External Interrupts 4 XINT2 None 5 XINT3 None 6 Reserved None No peripheral conne...

Page 971: ...to 1 when a DMA burst transfer begins and the BURST_COUNT is initialized with the BURST_SIZE This bit is cleared to zero when BURST_COUNT reaches zero This bit is also cleared to 0 when either the HA...

Page 972: ...it completes current read write access and places the channel into a default state as follows RUNSTS 0 TRANSFERSTS 0 BURSTSTS 0 BURST_COUNT 0 TRANSFER_COUNT 0 SRC_WRAP_COUNT 0 DST_WRAP_COUNT 0 This is...

Page 973: ...ed Reserved 4 0 BURSTSIZE These bits specify the burst transfer size 0 Transfer 1 word in a burst 1 Transfer 2 words in a burst 31 Transfer 32 words in a burst 11 8 9 BURST_COUNT Register The burst co...

Page 974: ...11 17 Source Burst Step Size Register SRC_BURST_STEP 15 0 SRCBURSTSTEP R W 0 LEGEND R W Read Write R Read only n value after reset Table 11 12 Source Burst Step Size Register SRC_BURST_STEP Field Desc...

Page 975: ...cify the destination address post increment decrement step size while processing a burst of data 0x0FFF Add 4095 to address 0x0002 Add 2 to address 0x0001 Add 1 to address 0x0000 No address change 0xF...

Page 976: ...to transfer 0xFFFF 65535 bursts left to transfer The above values represent the state of the counter at the HALT conditions 11 8 14 Source Transfer Step Size Register SRC_TRANSFER_STEP EALLOW Protect...

Page 977: ...t of data 0x0FFF Add 4095 to address 0x0002 Add 2 to address 0x0001 Add 1 to address 0x0000 No address change 0xFFFF Sub 1 from address 0xFFFE Sub 2 from address 0xF000 Sub 4096 from address Only valu...

Page 978: ...ft 0x0002 2 burst left 0xFFFF 65535 burst left The above values represent the state of the counter at the HALT conditions 11 8 18 Source Destination Wrap Step Size Registers SRC DST_WRAP_STEP EALLOW P...

Page 979: ...nly n value after reset Table 11 21 Shadow Source Begin and Current Address Pointer Registers SRC_BEG_ADDR_SHADOW DST_BEG_ADDR_SHADOW Field Descriptions Bit Field Value Description 31 22 Reserved Rese...

Page 980: ...Read only n value after reset Table 11 23 Shadow Destination Begin and Current Address Pointer Registers SRC_ADDR_SHADOW DST_ADDR_SHADOW Field Descriptions Bit Field Value Description 31 22 Reserved R...

Page 981: ...o 16 bits to be shifted into and out of the device at a programmed bit transfer rate The SPI is normally used for communications between the DSP controller and external peripherals or another controll...

Page 982: ...s used on the SPI pins See the device specific data sheet for more details Data word length one to sixteen data bits Four clocking schemes controlled by clock polarity and clock phase bits include Fal...

Page 983: ...ng at address 7040h NOTE All registers in this module are 16 bit registers that are connected to Peripheral Frame 2 When a register is accessed the register data is in the lower byte 7 0 and the upper...

Page 984: ...er RX FIFO _0 RX FIFO _1 RX FIFO _15 TX FIFO registers TX FIFO _0 TX FIFO _1 TX FIFO _15 RX FIFO registers 16 16 16 TX Interrupt Logic RX Interrupt Logic SPIFFOVF FLAG SPIFFRX 15 16 TX FIFO Interrupt...

Page 985: ...0x0000 7047 1 SPI Serial Input Buffer Register SPITXBUF 0x0000 7048 1 SPI Serial Output Buffer Register SPIDAT 0x0000 7049 1 SPI Serial Data Register SPIFFTX 0x0000 704A 1 SPI FIFO Transmit Register S...

Page 986: ...is shifted into the other end of the shift register SPIPRI SPI priority register Contains bits that specify interrupt priority and determine SPI operation on the XDS emulator during program suspensio...

Page 987: ...es Data written to SPIDAT or SPITXBUF initiates data transmission on the SPISIMO pin MSB most significant bit first Simultaneously received data is shifted through the SPISOMI pin into the LSB least s...

Page 988: ...o the serial data line an inactive high signal causes the slave SPI serial shift register to stop and its serial output pin to be put into the high impedance state This allows many slave devices to be...

Page 989: ...ware 12 1 5 2 Data Format Four bits SPICCR 3 0 specify the number of bits 1 to 16 in the data character This information directs the state control logic to count the number of bits received or transmi...

Page 990: ...the master SPI device To determine what value to load into SPIBRR you must know the device system clock LSPCLK frequency which is device specific and the baud rate at which you will be operating Exam...

Page 991: ...K PHASE and CLOCK POLARITY differs between manufacturers For proper operation select the desired waveform to determine the PHASE and POLARITY settings Table 12 3 SPI Clocking Scheme Selection Guide SP...

Page 992: ...T bit to 1 to release the SPI from the reset state Step 4 Write to SPIDAT or SPITXBUF this initiates the communication process in the master Step 5 Read SPIRXBUF after the data transmission has comple...

Page 993: ...9h and the slave reads 8Dh from their respective SPIRXBUF After the user s software masks off the unused bits the master receives 09h and the slave receives 0Dh K Master clears the slave SPISTE signal...

Page 994: ...words shifting out with a delay of 255 SPI clocks between each words The programmable delay facilitates glueless interface to various slow SPI peripherals such as EEPROMs ADC DAC etc 8 FIFO status bit...

Page 995: ...ISISOx SPI slave in slave out pin and SPISIMOx is no longer used by the SPI The table below indicates the pin function differences between 3 wire and 4 wire SPI mode for a master and slave SPI Table 1...

Page 996: ...to configure the SPI module for 3 wire mode the TRIWIRE bit SPIPRI 0 must be set to 1 After initialization there are several considerations to take into account when transmitting and receiving data in...

Page 997: ...e in master mode when transmitting the slave receives the data it transmits and must clear this junk data from its receive buffer Example 12 6 3 Wire Slave Mode Transmit Uint16 data Uint16 dummy SpiaR...

Page 998: ...supported using the 2 SPI configuration with the STEINV bit See your device specific data sheet electricals for SPI timing requirements With the SPI clock phase configured such that the CLOCK POLARIT...

Page 999: ...Three different modes are available not connected default M3 SSI3 master connected to C28 SPI A slave and M3 SSI3 slave connected to C28 SPI A master For a detailed description of the SERPLOOP regist...

Page 1000: ...on section of the M3 Synchronous Serial Interface SSI chapter 2 Enable the corresponding loopback mode by setting SERPLOOP SSI3TOSPIA 0x3 on the M3 subsystem 3 Enable and configure the C28 SPI module...

Page 1001: ...s bit is set 6 CLOCK POLARITY Shift Clock Polarity This bit controls the polarity of the SPICLK signal CLOCK POLARITY and CLOCK PHASE SPICTL 3 control four clocking schemes on the SPICLK pin See Secti...

Page 1002: ...writes have no effect 4 Overrun INT ENA Overrun Interrupt Enable Setting this bit causes an interrupt to be generated when the RECEIVER OVERRUN Flag bit SPISTS 7 is set by hardware Interrupts generate...

Page 1003: ...INT FLAG 1 2 TX BUF FULL FLAG 2 Reserved R C 0 R C 0 R C 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 12 11 SPI Status Register SPIST Field Descriptions Bit Field Value Descriptio...

Page 1004: ...egister SPIBRR Address 7044h 7 6 5 4 3 2 1 0 Reserved SPI BIT RATE 6 SPI BIT RATE 5 SPI BIT RATE 4 SPI BIT RATE 3 SPI BIT RATE 2 SPI BIT RATE 1 SPI BIT RATE 0 R 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 LE...

Page 1005: ...SPIRXEMU enables the emulator to emulate the true operation of the SPI more accurately It is recommended that you view SPIRXEMU in the normal emulator run mode 12 3 1 6 SPI Serial Receive Buffer Regis...

Page 1006: ...gister Data written to SPIDAT is shifted out MSB on subsequent SPICLK cycles For every bit MSB shifted out of the SPI a bit is shifted into the LSB end of the shift register Figure 12 20 SPI Serial Da...

Page 1007: ...o and hold in reset 1 Re enable Transmit FIFO operation 12 8 TXFFST4 0 Transmit FIFO status 00000 Transmit FIFO is empty 00001 Transmit FIFO has 1 word 00010 Transmit FIFO has 2 words 00011 Transmit F...

Page 1008: ...RX FIFO interrupt based on RXFFIL match greater than or equal to will be disabled 1 RX FIFO interrupt based on RXFFIL match greater than or equal to will be enabled 4 0 RXFFIL4 0 Receive FIFO interru...

Page 1009: ...ransmitting from where it had stopped fourth bit in this case and will transmit 8 bits from that point The SCI module operates differently 1 0 If the emulation suspend occurs before the start of a tra...

Page 1010: ...Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Serial Peripheral Interface SPI 12 3 2 SPI Example Waveforms Figure 12 25 CLOCK POLARITY 0 CL...

Page 1011: ...r 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Serial Peripheral Interface SPI Figure 12 26 CLOCK POLARITY 0 CLOCK PHASE 1 All data t...

Page 1012: ...SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Serial Peripheral Interface SPI Figure 12 27 CLOCK POLARITY 1 CLOCK PHA...

Page 1013: ...2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Serial Peripheral Interface SPI Figure 12 28 CLOCK POLARITY 1 CLOCK PHASE 1 All data tr...

Page 1014: ...014 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Serial Peripheral Interface SPI Figure 12 29 SPISTE Behavior in Mas...

Page 1015: ...15 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Serial Peripheral Interface SPI Figure 12 30 SPISTE Behavior in Slav...

Page 1016: ...een the CPU and other asynchronous peripherals that use the standard non return to zero NRZ format The SCI receiver and transmitter each have a 16 level deep FIFO for reducing servicing overhead and e...

Page 1017: ...bit Data word length programmable from one to eight bits Optional even odd no parity bit One or two stop bits Four error detection flags parity overrun framing and break detection Two wake up multipr...

Page 1018: ...TXINT SCIFFTX 14 RX FIFO _15 SCIRXBUF 7 0 Receive Data Buffer register SCIRXBUF 7 0 RX FIFO_1 RX FIFO _0 8 RX FIFO registers SCICTL1 0 RX Interrupt Logic RXINT RX FIFO Interrupt SCIFFRX 15 RXFFOVF RX...

Page 1019: ...ers Name Address Range Size x16 Description 1 2 SCICCR 0x0000 7750 1 SCI B Communications Control Register SCICTL1 0x0000 7751 1 SCI B Control Register 1 SCIHBAUD 0x0000 7752 1 SCI B Baud Register Hig...

Page 1020: ...se protocols allow efficient data transfer between multiple processors The SCI offers the universal asynchronous receiver transmitter UART communications mode for interfacing with many popular periphe...

Page 1021: ...lker sends contains an address byte that is read by all listeners Only listeners with the correct address can be interrupted by the data bytes that follow the address byte The listeners with an incorr...

Page 1022: ...n address 2 A software routine is entered through the interrupt and checks the incoming address This address byte is checked against its device address byte stored in memory 3 If the check shows that...

Page 1023: ...start signal of exactly one frame time during a sequence of block transmissions 1 Write a 1 to the TXWAKE bit 2 Write a data word content not important a don t care to the SCITXBUF register transmit...

Page 1024: ...ediately since both TXSHF and WUT are both double buffered 3 Leave the TXWAKE bit set to 0 to transmit non address frames in the block NOTE As a general rule the address bit format is typically used f...

Page 1025: ...racter Figure 13 8 SCI RX Signals in Communication Modes 1 Data arrives on the SCIRXD pin start bit detected 2 Bit RXENA is brought low to disable the receiver Data continues to be assembled in RXSHF...

Page 1026: ...t flag which is a logical OR of the FE OE BRKDT and PE conditions The transmitter and receiver have separate interrupt enable bits When not enabled the interrupts are not asserted however the conditio...

Page 1027: ...will work normally with TXINT RXINT interrupts as the interrupt source for the module 3 FIFO enable FIFO mode is enabled by setting the SCIFFEN bit in the SCIFFTX register SCIRST can reset the FIFO m...

Page 1028: ...FIFOs resumes operation from start once these bits are set to one 9 Programmable interrupt levels Both transmit and receive FIFO can generate CPU interrupts The interrupt trigger is generated wheneve...

Page 1029: ...LR bit bit 14 2 Initialize the baud register to be 1 or less than a baud rate limit of 500 Kbps 3 Allow SCI to receive either character A or a from a host at the desired baud rate If the first charact...

Page 1030: ...ed by setting the UART4TOSCIA bit in the M3 SERPLOOP register For a complete description of the SERPLOOP register refer to the System Control and Interrupt chapter Figure 13 11 UART and SCI Connection...

Page 1031: ...0000 7054 1 SCI A Control Register 2 SCIRXST 0x0000 7055 1 SCI A Receive Status Register SCIRXEMU 0x0000 7056 1 SCI A Receive Emulation Data Buffer Register SCIRXBUF 0x0000 7057 1 SCI A Receive Data B...

Page 1032: ...alculation if parity is enabled For characters of less than eight bits the remaining unused bits should be masked out of the parity calculation 0 Parity disabled no parity bit is generated during tran...

Page 1033: ...Thus after a system reset re enable the SCI by writing a 1 to this bit Clear this bit after a receiver break detect BRKDT flag bit SCIRXST bit 5 SW RESET affects the operating flags of the SCI but it...

Page 1034: ...EP is not cleared when the address byte is detected 0 Sleep mode disabled 1 Sleep mode enabled 1 TXENA SCI transmitter enable Data is transmitted through the SCITXD pin only when TXENA is set If reset...

Page 1035: ...egister SCILBAUD Address 7053h 7 6 5 4 3 2 1 0 BAUD7 BAUD6 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1 BAUD10 LSB R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after rese...

Page 1036: ...r both are loaded with data 1 Transmitter buffer and shift registers are both empty 5 2 Reserved 1 RX BK INT ENA Receiver buffer break interrupt enable This bit controls the interrupt request caused b...

Page 1037: ...ceipt of a character after the break is detected In order to receive more characters the SCI must be reset by toggling the SW RESET bit or by a system reset 0 No break condition 1 Break condition occu...

Page 1038: ...ator EMU because it can continuously read the data received for screen updates without clearing the RXRDY flag SCIRXEMU is cleared by a system reset This is the register that should be used in an emul...

Page 1039: ...ers less than eight bits long The transfer of data from this register to the TXSHF transmitter shift register sets the TXRDY flag SCICTL2 7 indicating that SCITXBUF is ready to receive another set of...

Page 1040: ...FFIL4 0 The maximum value that can be assigned to these bits to generate an interrupt cannot be more than the depth of the TX FIFO The default value of these bits after reset is 00000b Users should se...

Page 1041: ...status bits RXFFST4 0 are greater than or equal to the FIFO level bits RXFFIL4 0 The maximum value that can be assigned to these bits to generate an interrupt cannot be more than the depth of the RX F...

Page 1042: ...f 256 baud clock cycles In FIFO mode the buffer TXBUF between the shift register and the FIFO should be filled only after the shift register has completed shifting of the last bit This is required to...

Page 1043: ...Register SCIPRI Field Descriptions Bit Field Value Description 7 5 Reserved Reads return zero writes have no effect 4 3 SOFT and FREE These bits determine what occurs when an emulation suspend event...

Page 1044: ...nected by way of an I2C bus External components attached to this 2 wire serial bus can transmit receive 1 to 8 bit data to from the device through the I2C module This guide assumes the reader is famil...

Page 1045: ...19 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Inter Integrated Circuit Module 14 1 Introduction to the I2C Module The I2C module supports any slave or master...

Page 1046: ...of the device A device connected to the I2C bus can also be considered as the master or the slave when performing data transfers A master device is the device that initiates a data transfer on the bus...

Page 1047: ...another master Interrupt generation logic so that an interrupt can be sent to the CPU FIFO interrupt generation logic so that FIFO access can be synchronized to data reception and data transmission in...

Page 1048: ...e IRS 1 has no effect The master clock appears on the SCL pin when the I2C module is configured to be a master on the I2C bus This clock controls the timing of communication between the I2C module and...

Page 1049: ...er mode The I2C module is a slave and transmits data to a master This mode can be entered only from the slave receiver mode the I2C module must first receive a command from the master When you are usi...

Page 1050: ...START and STOP Conditions After a START condition and before a subsequent STOP condition the I2C bus is considered busy and the bus busy BB bit of I2CSTR is 1 Between a STOP condition and the next ST...

Page 1051: ...s receives data from the slave An extra clock cycle dedicated for acknowledgment ACK is inserted after each byte If the ACK bit is inserted by the slave after the first byte from the master it is foll...

Page 1052: ...bit addressing 10 bit addressing and free data formats Figure 14 10 shows a repeated START condition in the 7 bit addressing format Figure 14 10 Repeated START Condition in This Case 7 Bit Addressing...

Page 1053: ...lave slows down a fast master and the slow device creates enough time to store a received byte or to prepare a byte to be transmitted Figure 14 11 Synchronization of Two I2C Clock Generators During Ar...

Page 1054: ...enable bit is 1 the request is forwarded to the CPU as an I2C interrupt The I2C interrupt is one of the maskable interrupts of the CPU As with any maskable interrupt request if it is properly enabled...

Page 1055: ...an arbitration contest with another master transmitter As an alternative to using ALINT the CPU can poll the AL bit of I2CSTR SCDINT Stop condition detected A STOP condition was detected on the I2C bu...

Page 1056: ...e and transmit shift registers I2CRSR and I2CXSR are accessible to the CPU Table 14 4 I2C Module Registers Name Address Description I2COAR 0x7900 I2C own address register I2CIER 0x7901 I2C interrupt e...

Page 1057: ...C module is master If SCL is low when the breakpoint occurs the I2C module stops immediately and keeps driving SCL low whether the I2C module is the transmitter or the receiver If SCL is high the I2C...

Page 1058: ...ARDY bit interrupt can be used to determine when the I2CDXR or FIFO is ready for more data or when the data has all been sent and the CPU is allowed to write to the STP bit 6 DLB Digital loopback mode...

Page 1059: ...e RM STT and STP Bits of I2CMDR RM STT STP Bus Activity 1 Description 0 0 0 None No activity 0 0 1 P STOP condition 0 1 0 S A D n D START condition slave address n data bytes n value in I2CCNT 0 1 1 S...

Page 1060: ...Effects of the Digital Loopback Mode DLB Bit 14 5 2 I2C Extended Mode Register I2CEMDR The I2C extended mode register is shown in Figure 14 16 and described in Table 14 8 Figure 14 16 I2C Extended Mod...

Page 1061: ...1 A Data 2 A Data 3 nA P Left in I2CDXR Interrupt XRDY XSMT I2CDXR I2CXSR b BC 0 Interrupt XRDY XSMT I2CDXR I2CXSR b BC 1 Slave Transmitter www ti com I2C Module Registers 1061 SPRUHE8E October 2012...

Page 1062: ...s slave interrupt enable bit 0 Interrupt request disabled 1 Interrupt request enabled 5 SCD Stop condition detected interrupt enable bit 0 Interrupt request disabled 1 Interrupt request enabled 4 XRDY...

Page 1063: ...e the paragraph following the table for more information 0 Bus free BB is cleared by any one of the following events The I2C module receives or transmits a STOP bit bus free The I2C module is reset 1...

Page 1064: ...RXFFINT instead 0 I2CDRR not ready RRDY is cleared by any one of the following events I2CDRR is read by the CPU Emulator reads of the I2CDRR do not affect this bit RRDY is manually cleared To clear th...

Page 1065: ...is detected on the I2C bus Follow these steps before initiating the first data transfer with I2C 1 After taking the I2C peripheral out of reset by setting the IRS bit to 1 wait a certain period to det...

Page 1066: ...orted range of values for the module clock frequency Table 14 12 lists the bit descriptions For more details about the module clock see Section 14 1 3 IPSC must be initialized while the I2C module is...

Page 1067: ...iption 15 0 ICCL Clock low time divide down value To produce the low time duration of the master clock the period of the module clock is multiplied by ICCL d d is 5 6 or 7 as described in Section 14 5...

Page 1068: ...0 Reserved These reserved bit locations are always read as zeros A value written to this field has no effect 9 0 SAR In 7 bit addressing mode XA 0 in I2CMDR 00h 7Fh Bits 6 0 provide the 7 bit slave ad...

Page 1069: ...ata counter is 1 65535 14 5 11 I2C Data Receive Register I2CDRR I2CDRR see Figure 14 28 and Table 14 19 is a 16 bit register used by the CPU to read received data The I2C module can receive a data byt...

Page 1070: ...1 Figure 14 30 I2C Transmit FIFO Register I2CFFTX 15 14 13 12 11 10 9 8 Reserved I2CFFEN TXFFRST TXFFST4 TXFFST3 TXFFST2 TXFFST1 TXFFST0 R 0 R W 0 R W 0 R 0 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 TXFFINT TXF...

Page 1071: ...2CFFRX is a 16 bit register that contains the control and status bits for the receive FIFO mode of operation on the I2C peripheral The bit fields are shown in Figure 14 31 and described in Table 14 22...

Page 1072: ...NT flag does generate an interrupt when set 4 0 RXFFIL4 0 Receive FIFO interrupt level These bits set the status level that will set the receive interrupt flag When the RXFFST4 0 bits reach a value eq...

Page 1073: ...s one high speed multichannel buffered serial port McBSP that allows direct interface to codecs and other devices in a system Topic Page 15 1 Overview 1074 15 2 Clocking and Framing Data 1079 15 3 Fra...

Page 1074: ...ese registers are needed to hold the most significant bits The frame and clock loopback is implemented at chip level to enable CLKX and FSX to drive CLKR and FSR If the loop back is enabled the CLKR a...

Page 1075: ...the input clock of the sample rate generator MCLKXA I O Supplying or reflecting the transmit clock supplying the input clock of the sample rate generator MDRA I Serial data receive pin MDXA O Serial...

Page 1076: ...d November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated C28 Multichannel Buffered Serial Port McBSP 15 1 2 1 McBSP Generic Block Diagram The McBSP consists of...

Page 1077: ...nchronization the transmitter begins shifting bits from XSR1 to the DX pin For more details about transmission see Section 15 3 6 15 1 4 2 Data Transfer Process for Word Length of 20 24 or 32 Bits If...

Page 1078: ...sing law compression the 14 data bits must be left justified in DXR1 and that the remaining two low order bits are filled with 0s as shown in Figure 15 4 Figure 15 4 Law Transmit Data Companding Forma...

Page 1079: ...length bits are set to 0 indicating that 8 bit words are to be transferred serially If either phase of the frame does not have an 8 bit word length the McBSP assumes the word length is eight bits and...

Page 1080: ...ame synchronization occur 15 2 4 Generating Transmit and Receive Interrupts The McBSP can send receive and transmit interrupts to the CPU to indicate specific events in the McBSP To facilitate detecti...

Page 1081: ...packets are transmitted contiguously with no inactivity between bits Figure 15 8 McBSP Operating at Maximum Packet Frequency If there is a 1 bit data delay as shown in this figure the frame synchroniz...

Page 1082: ...N1 for phase 1 RWDLEN2 for phase 2 Transmission 1 XPHASE 0 XFRLEN1 XWDLEN1 Transmission 2 XPHASE 1 XFRLEN1 and XFRLEN2 XWDLEN1 for phase 1 XWDLEN2 for phase 2 15 3 2 Single Phase Frame Example Figure...

Page 1083: ...CLKXP 0 Receive data sampled on falling edge of internal CLKR transmit data clocked on rising edge of internal CLKX FSRP FSXP 0 Active high frame sync signal R X DATDLY 01b Data delay of 1 clock cycle...

Page 1084: ...rd length see Section 15 8 8 Set the Receive Word Length s 4 When a full word is received the McBSP copies the contents of the receive shift register s to the receive buffer register s provided that R...

Page 1085: ...d the transmitter ready bit XRDY is cleared in SPCR2 to indicate that the transmitter is not ready for new data If the word length is 16 bits or smaller only DXR1 is used If the word length is larger...

Page 1086: ...interrupt The McBSP can send a receive interrupt request to CPU based upon a selected condition in the receiver of the McBSP a condition selected by the RINTM bits of SPCR1 XINT Transmit interrupt Th...

Page 1087: ...ives CLKG and FSG programmability The three stages provide Clock divide down The source clock is divided according to the CLKGDV bits of SRGR1 to produce CLKG Frame period divide down CLKG is divided...

Page 1088: ...loopback mode disabled CLKR is an output pin driven by the sample rate generator output clock CLKG DLB 1 Digital loopback mode enabled CLKR is an output pin driven by internal CLKX The source for CLK...

Page 1089: ...the source to the sample rate generator the rising edge of CLKSRG see Figure 15 17 generates CLKG and FSG The first divider stage of the sample rate generator creates the output clock from the input c...

Page 1090: ...figuration of the sample rate generator If the sample rate generator is using an external input clock and GSYNC 1 in SRGR2 FSG pulses in response to an inactive to active transition on the FSR pin Thu...

Page 1091: ...nput FSR has appropriate timing so that it can be sampled by the falling edge of CLKG it can be used instead by setting FSXM 0 and connecting FSR to FSX externally The sample rate generator clock driv...

Page 1092: ...et the transmitter XRST 0 in SPCR2 If GRST 0 due to a device reset CLKG is driven by the CPU clock divided by 2 and FSG is driven inactive low If GRST 0 due to program code CLKG and FSG are driven low...

Page 1093: ...ion pulse RSYNCERR 1 This occurs during reception when RFIG 0 and an unexpected frame synchronization pulse occurs An unexpected frame synchronization pulse is one that begins the next frame transfer...

Page 1094: ...d is shifted into the RSR1 NOTE If both DRRs are needed word length larger than 16 bits the CPU or the DMA controller must read from DRR2 first and then from DRR1 As soon as DRR1 is read the next RBR...

Page 1095: ...nexpected Receive Frame Synchronization Pulse Section 15 5 3 1 shows how the McBSP responds to any receive frame synchronization pulses including an unexpected pulse Section 15 5 3 2 and Section 15 5...

Page 1096: ...ate generator If a frame synchronization pulse starts the transfer of a new frame before the current frame is fully received this pulse is treated as an unexpected frame synchronization pulse and the...

Page 1097: ...cribed in the section on McBSP transmission page Section 15 3 6 the transmitter must copy the data previously written to the DXR s by the CPU or DMA controller into the XSR s and then shift each bit f...

Page 1098: ...d then load DXR1 As soon as DXR1 is loaded the contents of both DXRs are copied to the transmit shift registers XSRs If DXR2 is not loaded first the previous content of DXR2 is passed to the XSR2 XEMP...

Page 1099: ...ulse Section 15 5 5 1 shows how the McBSP responds to any transmit frame synchronization pulses including an unexpected pulse Section 15 5 5 2 and Section 15 5 5 3 show examples of a frame synchroniza...

Page 1100: ...r of a new frame before the current frame is fully transmitted this pulse is treated as an unexpected frame synchronization pulse and the transmitter sets the transmit frame synchronization error bit...

Page 1101: ...the McBSP 15 6 1 Channels Blocks and Partitions A McBSP channel is a time slot for shifting in out the bits of one serial word Each McBSP supports up to 128 channels for reception and 128 channels fo...

Page 1102: ...nel enable register If the appropriate multichannel selection mode is on each bit in the register controls whether data flow is allowed or prevented in one of the channels that is assigned to that par...

Page 1103: ...selection modes described in Section 15 6 7 the channels in this partition are controlled by transmit channel enable register A XCERA Assign an odd numbered block 1 3 5 or 7 to transmit partition B wi...

Page 1104: ...tion B is active the CPU changes the block assignment for partition A Whenever partition A is active the CPU changes the block assignment for partition B Figure 15 33 Reassigning Channel Blocks Throug...

Page 1105: ...be disabled When RMCM 1 the receive multichannel selection mode is enabled In this mode Channels can be individually enabled or disabled The only channels enabled are those selected in the appropriate...

Page 1106: ...he DX pin in channel 0 2 Places the DX pin in the high impedance state in channels 1 14 3 Shifts data to the DX pin in channel 15 4 Places the DX pin in the high impedance state in channels 16 38 5 Sh...

Page 1107: ...5 6 7 3 Using Interrupts Between Block Transfers When a multichannel selection mode is used an interrupt request can be sent to the CPU at the end of every 16 channel block at the boundary between par...

Page 1108: ...DY DXR1 to XSR1 copy W1 W3 DX W1 Internal FSX a XMCM 00b All channels enabled and unmasked W3 W2 W1 W0 XRDY DX Internal FSX DXR1 to XSR1 copy W0 Write to DXR1 W1 DXR1 to XSR1 copy W1 Write to DXR1 W2...

Page 1109: ...the SPI protocol When the McBSP is configured in clock stop mode the transmitter and receiver are internally synchronized so that the McBSP functions as an SPI master or slave device The transmit cloc...

Page 1110: ...d receives data on the falling edge of MCLKR CLKXP 0 CLKRP 0 CLKSTP 11b Low inactive state with delay The McBSP transmits data one half cycle ahead of the rising edge of CLKX and receives data on the...

Page 1111: ...LKRP 0 A If the McBSP is the SPI master CLKXM 1 SIMO DX If the McBSP is the SPI slave CLKXM 0 SIMO DR B If the McBSP is the SPI master CLKXM 1 SOMI DR If the McBSP is the SPI slave CLKXM 0 SOMI DX Fig...

Page 1112: ...tor is released from reset wait two sample rate generator clock periods for the McBSP logic to stabilize If the CPU services the McBSP transmit and receive buffers then you can immediately enable the...

Page 1113: ...ry time data is transferred from DXR1 to XSR1 FSXP 1 The FSX pin is active low XDATDLY 01b This setting provides the correct setup time on the FSX signal RDATDLY 01b When the McBSP functions as the SP...

Page 1114: ...Table 15 17 Bit Values Required to Configure the McBSP as an SPI Slave Required Bit Setting Description CLKSTP 10b or 11b The clock stop mode without or with a clock delay is selected CLKXP 0 or 1 The...

Page 1115: ...er perform the following procedure 1 Place the McBSP receiver in reset see Section 15 8 2 2 Program McBSP registers for the desired receiver operation see Section 15 8 1 3 Take the receiver out of res...

Page 1116: ...disabled and in the reset state 1 The serial port receiver is enabled 15 8 2 1 Reset Considerations The serial port can be reset in the following two ways 1 The DSP reset XRS signal driven low places...

Page 1117: ...MCLKX transmit clock 15 8 5 Enable Disable the Clock Stop Mode The CLKSTP bits determine whether the clock stop mode is on CLKSTP is described in Table 15 22 Table 15 22 Register Bits Used to Enable D...

Page 1118: ...e of MCLKR CLKXP 1 CLKRP 1 15 8 6 Enable Disable the Receive Multichannel Selection Mode The RMCM bit determines whether the receive multichannel selection mode is on RMCM is described in Table 15 24...

Page 1119: ...al word in phase 2 of the frame RWDLEN2 000 8 bits RWDLEN2 001 12 bits RWDLEN2 010 16 bits RWDLEN2 011 20 bits RWDLEN2 100 24 bits RWDLEN2 101 32 bits RWDLEN2 11X Reserved 15 8 8 1 Word Length Bits Ea...

Page 1120: ...e number of words or logical time slots or channels per frame synchronization pulse Program the RFRLEN fields with w minus 1 where w represents the number of words per phase For the example if you wan...

Page 1121: ...nchronization pulse when R X FIG 0 In the case of reception the reception of B is aborted B is lost and a new data word C in this example is received after the appropriate data delay This condition is...

Page 1122: ...ncoded according to the specified companding law A law or law When companding is chosen for the receiver expansion occurs during the process of copying data from RBR1 to DRR1 The receive data is decod...

Page 1123: ...pulse is detected or sampled with respect to an edge of internal serial clock CLK R X Thus on the following cycle or later depending on the data delay value data may be received or transmitted However...

Page 1124: ...s in DRR 1 2 RJUST 11 Reserved 15 8 13 1 Sign Extension and the Justification RJUST in SPCR1 selects whether data in RBR 1 2 is right or left justified with respect to the MSB in DRR 1 2 and whether u...

Page 1125: ...ame synchronization pulses This generates an interrupt even when the receiver is in its reset state This is done by synchronizing the incoming frame synchronization pulse to the CPU clock and sending...

Page 1126: ...ing the receive frame synchronization signal are connected internally through multiplexers to the corresponding transmit signals SPCR1 12 11 CLKSTP Clock stop mode R W 00 CLKSTP 0Xb Clock stop mode di...

Page 1127: ...de When FSR and FSX are inputs FSXM FSRM 0 external frame synchronization pulses the McBSP detects them on the internal falling edge of clock internal MCLKR and internal CLKX respectively The receive...

Page 1128: ...erator can produce a clock signal CLKG and a frame synchronization signal FSG If the sample rate generator is supplying receive or transmit frame synchronization you must program the bit fields FPER a...

Page 1129: ...ame 15 8 17 Set the Receive Clock Mode Table 15 40 shows the settings for bits used to set receive clock mode Table 15 40 Register Bits Used to Set the Receive Clock Mode Register Bit Name Function Ty...

Page 1130: ...he CLKRP bit In the digital loopback mode DLB 1 the transmit clock signal is used as the receive clock signal Also in the clock stop mode the internal receive clock signal MCLKR and the internal recei...

Page 1131: ...SP and FSRP FSXP 1 the external active low frame synchronization signals are inverted before being sent to the receiver internal FSR and transmitter internal FSX Similarly if internal synchronization...

Page 1132: ...CLKGDV is odd or equal to 0 the CLKG duty cycle is 50 When CLKGDV is an even value 2p representing an odd divide down the high state duration is p 1 cycles and the low state duration is p cycles 15 8...

Page 1133: ...LKME 0 Sample rate generator clock derived from LSPCLK default CLKSM 1 SCLKME 1 Sample rate generator clock derived from MCLKR pin CLKSM 0 SCLKME 1 Sample rate generator clock derived from MCLKX pin C...

Page 1134: ...sample rate generator must be driven by an input clock signal derived from the CPU clock or from an external clock on the CLKX or MCLKR pin If you use a pin choose a polarity for that pin by using the...

Page 1135: ...te generator is reset If GRST 0 due to a device reset CLKG is driven by the CPU clock divided by 2 and FSG is driven low inactive If GRST 0 due to program code CLKG and FSG are both driven low inactiv...

Page 1136: ...SPCR1 15 DLB Digital loopback mode R W 0 DLB 0 Digital loopback mode is disabled DLB 1 Digital loopback mode is enabled 15 9 4 1 Digital Loopback Mode In the digital loopback mode the receive signals...

Page 1137: ...l port operation In the clock stop mode the receive clock is tied internally to the transmit clock and the receive frame synchronization signal is tied internally to the transmit frame synchronization...

Page 1138: ...el enable registers XCERs The XMCME bit determines whether 32 channels or 128 channels are selectable in XCERs XMCM 11b This mode is used for symmetric transmission and reception All channels are disa...

Page 1139: ...frame phase 2 R W 000 XWDLEN2 000b 8 bits XWDLEN2 001b 12 bits XWDLEN2 010b 16 bits XWDLEN2 011b 20 bits XWDLEN2 100b 24 bits XWDLEN2 101b 32 bits XWDLEN2 11Xb Reserved 15 9 8 1 Word Length Bits Each...

Page 1140: ...111 1111 128 words in phase 2 15 9 9 1 Selected Frame Length The transmit frame length is the number of serial words in the transmit frame Each frame can have one or two phases depending on the value...

Page 1141: ...urrent frame is fully transmitted this pulse is treated as an unexpected frame synchronization pulse When XFIG 1 normal transmission continues with unexpected frame synchronization signals ignored Whe...

Page 1142: ...in either law or A law format The companding standard employed in the United States and Japan is law The European companding standard is referred to as A law The specifications for law and A law log P...

Page 1143: ...least significant bit LSB to be transferred first If you set XCOMPAND 01b in XCR2 the bit ordering of 8 bit words is reversed LSB first before being sent from the serial port Similar to companding thi...

Page 1144: ...d because receive data is sampled on the first falling edge of MCLKR where an active high internal FSR is detected However data transmission must begin on the rising edge of the internal CLKX clock th...

Page 1145: ...le 15 61 Register Bits Used to Set the Transmit Interrupt Mode Register Bit Name Function Type Reset Value SPCR2 5 4 XINTM Transmit interrupt mode R W 00 XINTM 00 XINT generated when XRDY changes from...

Page 1146: ...also shows the effect of each bit setting on the FSX pin The polarity of the signal on the FSX pin is determined by the FSXP bit Table 15 63 How FSXM and FSGM Select the Source of Transmit Frame Synch...

Page 1147: ...All frame synchronization signals internal FSR internal FSX that are internal to the serial port are active high If the serial port is configured for external frame synchronization FSR FSX are inputs...

Page 1148: ...ion pulse on FSG Range for FWID 1 1 to 256 CLKG cycles 15 9 17 1 Frame Synchronization Period and Frame Synchronization Pulse Width The sample rate generator can produce a clock signal CLKG and a fram...

Page 1149: ...pin is determined by the CLKXP bit Table 15 67 How the CLKXM Bit Selects the Transmit Clock and the Corresponding Status of the MCLKX pin CLKXM in PCR Source of Transmit Clock MCLKX pin Status 0 Inter...

Page 1150: ...P and FSRP FSXP 1 the external active low frame synchronization signals are inverted before being sent to the receiver internal FSR and transmitter internal FSX Similarly if internal synchronization F...

Page 1151: ...continues running and an overrun error is possible Table 15 69 McBSP Emulation Modes Selectable with FREE and SOFT Bits of SPCR2 FREE SOFT McBSP Emulation Mode 0 0 Immediate stop mode reset condition...

Page 1152: ...GRST 1 pins MFSRx and MFSXx are in an inactive state when RRST 0 and XRST 0 respectively even if they are outputs driven by FSG This ensures that when only one portion of the McBSP is in reset the oth...

Page 1153: ...ady bit RRDY The transmitter is in its reset state The transmit interrupt XINT will be triggered by the transmit frame sync error bit XSYNCERR PCR 0900h Transmit frame synchronization is generated int...

Page 1154: ...b 1 word frame R X WDLEN1 101b 32 bit word Two 16 bit data words are transferred to and from the McBSP by the CPU or DMA controller Thus two reads from DRR2 and DRR1 and two writes to DXR2 and DXR1 ar...

Page 1155: ...ng at the maximum packet frequency Here each frame only has a single 8 bit word Notice the frame synchronization pulse that initiates each frame transfer for reception and for transmission For recepti...

Page 1156: ...Transmit Channel Enable Register Partition A XCERB 0x5011 R W 0x0000 McBSP Transmit Channel Enable Register Partition B PCR 0x5012 R W 0x0000 McBSP Pin Control Register RCERC 0x5013 R W 0x0000 McBSP R...

Page 1157: ...sabled the data copied from RBR 1 2 to DRR 1 2 is justified and bit filled according to the RJUST bits 15 12 3 Data Transmit Registers DXR 1 2 For transmission the CPU or the DMA controller writes dat...

Page 1158: ...DLB Digital loopback mode bit DLB disables or enables the digital loopback mode of the McBSP 0 Disabled Internal DR is supplied by the MDRx pin Internal FSR and internal MCLKR can be supplied by their...

Page 1159: ...McBSP sends a receive interrupt RINT request to the CPU when the RRDY bit changes from 0 to 1 indicating that receive data is ready to be read the content of RBR 1 2 has been copied to DRR 1 2 Regardl...

Page 1160: ...A controller 0 Receiver not ready When the content of DRR1 is read RRDY is automatically cleared 1 Receiver ready New data can be read from DRR 1 2 Important If both DRRs are required word length larg...

Page 1161: ...u can use FRST to take the frame synchronization logic into and out of its reset state This bit has a negative polarity FRST 0 indicates the reset state 0 If you read a 0 the frame synchronization log...

Page 1162: ...d by the McBSP If XINTM 11b the McBSP sends a transmit interrupt XINT request to the CPU when XSYNCERR is set The flag remains set until you write a 0 to it or reset the transmitter If XINTM 11b writi...

Page 1163: ...chronization ignore function RFIG Choose a receive data delay RDATDLY 15 12 5 1 Receive Control Register 1 RCR1 The receive control register 1 RCR1 is shown in Figure 15 69 and described in Table 15 7...

Page 1164: ...RWDLEN2 RCOMPAND RFIG RDATDLY R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 15 76 Receive Control Register 2 RCR2 Field Descriptions Bit Field Value Description...

Page 1165: ...ization ignore bit If a frame synchronization pulse starts the transfer of a new frame before the current frame is fully received this pulse is treated as an unexpected frame synchronization pulse For...

Page 1166: ...8 12 16 20 24 or 32 bits per word in the frame If a dual phase frame is selected XFRLEN1 determines the number of serial words in phase 1 of the frame and XFRLEN2 in XCR2 determines the number of wor...

Page 1167: ...FRLEN1 determines the number of serial words in phase 1 of the frame and XFRLEN2 in XCR2 determines the number of words in phase 2 of the frame The 7 bit XFRLEN fields allow up to 128 words per phase...

Page 1168: ...nization and before the transmission of the first bit of the frame For more details see Section 15 9 12 0 0 bit data delay 1h 1 bit data delay 2h 2 bit data delay 3h Reserved do not use Table 15 81 Fr...

Page 1169: ...f 1 to 256 CLKG cycles 0 FWID 255 1 FWID 1 256 CLKG cycles The period between the frame synchronization pulses on FSG is defined by the FPER bits 7 0 CLKGDV 0 FFh Divide down value for CLKG The sample...

Page 1170: ...ple rate generator is taken from the MCLKR pin depending on the value of the SCLKME bit of PCR SCLKME CLKSM Input Clock For Sample Rate Generator 0 0 Reserved 1 0 Signal on MCLKR pin 1 The input clock...

Page 1171: ...ite R Read only n value after reset Table 15 84 Multichannel Control 1 Register MCR1 Field Descriptions Bit Field Value Description 15 10 Reserved 0 Reserved bits not available for your use They are r...

Page 1172: ...6 through 31 1h Block 3 channels 48 through 63 2h Block 5 channels 80 through 95 3h Block 7 channels 112 through 127 6 5 RPABLK 0 3h Receive partition A block bits RPABLK is only applicable if channel...

Page 1173: ...ally disabled enabled or masked unmasked for transmission XMCM is nonzero 0 2 partition mode Only partitions A and B are used You can control up to 32 channels in the transmit multichannel selection m...

Page 1174: ...ese conditions the McBSP transmitter can transmit or withhold data in any of the 32 channels that are assigned to partitions A and B of the transmitter See the description for XPBBLK bits 8 7 for more...

Page 1175: ...0 R W 0 R W 0 R W 0 R W 0 7 6 4 3 2 1 0 SCLKME Reserved FSXP FSRP CLKXP CLKRP R W 0 R 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 15 86 Pin Control Register...

Page 1176: ...nal master clock 8 CLKRM Receive clock mode bit The role of CLKRM and the resulting effect on the MCLKR pin depend on whether the McBSP is in the digital loopback mode DLB 1 The polarity of the signal...

Page 1177: ...enable register These memory mapped registers are only used when the receiver is configured to allow individual enabling and disabling of the channels RMCM 1 For more details about the way these regis...

Page 1178: ...hannel n 15 RCERB Channels m to m 15 RCE0 Channel m RCE1 Channel m 1 RCE2 Channel m 2 The block of channels is chosen with the RPBBLK bits RCE15 Channel m 15 128 RMCME 1 RCERA Block 0 RCE0 Channel 0 R...

Page 1179: ...l Enable Registers XCERA XCERH 15 14 13 12 11 10 9 8 XCE15 XCE14 XCE13 XCE12 XCE11 XCE10 XCE9 XCE8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 XCE7 XCE6 XCE5 XCE4 XCE3 XCE2 XCE1 XC...

Page 1180: ...to unmask channels for transmission Table 15 91 Use of the Transmit Channel Enable Registers Number of Selectable Channels Block Assignments Channel Assignments XCERx Block Assigned Bit in XCERx Chan...

Page 1181: ...l 111 XCERH Block 7 XCE0 Channel 112 XCE1 Channel 113 XCE2 Channel 114 XCE15 Channel 127 15 12 12 Interrupt Generation McBSP registers can be programmed to receive and transmit data through DRR2 DRR1...

Page 1182: ...nsmit Interrupt Generation McBSP module data transmit and error conditions generate two sets of interrupt signals One set is used for the CPU and the other set is for DMA Figure 15 81 Transmit Interru...

Page 1183: ...icates with various types of Codecs with variable word size Apart from this mode the McBSP uses time division multiplexed TDM data stream while communicating with other McBSPs or serial devices The mu...

Page 1184: ...cBSP Table 15 96 McBSP Mode Selection continued Register Bits Used for Mode Selection MCR1 bit 9 0 MCR2 bit 9 1 0 No McBSP Word Size RMCME RMCM XMCME XMCM Mode and Function Description XCERs 1 1 1 10...

Page 1185: ...asks from the Cortex M3 processor allowing for more efficient use of the processor and the available bus bandwidth The DMA controller can perform transfers between memory and peripherals It has dedica...

Page 1186: ...nfigured and operated channels Dedicated channels for supported on chip modules Primary and secondary channel assignments One channel each for receive and transmit path for bidirectional modules Dedic...

Page 1187: ...act on the rest of the system The bus architecture has been optimized to greatly enhance the ability of the processor core and the DMA controller to efficiently share the on chip bus thus improving pe...

Page 1188: ...annel is used then the interrupt occurs on the interrupt vector for the peripheral Table 16 1 DMA Channel Assignment Mapping DMACHALT Encoding 0 1 DMACHMAPx Encoding 0 1 2 DMA Channel First Assignment...

Page 1189: ...g all the channels making a request and services the DMA channel with the highest priority Once a transfer begins it continues for a selectable number of transfers before rearbitrating among the reque...

Page 1190: ...example perhaps the nature of the data is such that it only makes sense when transferred together as a single unit rather than one piece at a time The single request can be disabled by using the DMA C...

Page 1191: ...er mode The control word and each field are described in detail in Section 16 6 The DMA controller updates the transfer size and transfer mode fields as the transfer is performed At the end of a trans...

Page 1192: ...to Basic mode except that once a transfer request is received the transfer runs to completion even if the DMA request is removed This mode is suitable for software triggered transfers Generally Auto...

Page 1193: ...Instruments Incorporated M3 Micro Direct Memory Access DMA Figure 16 2 Example of Ping Pong DMA Transaction 16 3 6 5 Memory Scatter Gather Memory Scatter Gather mode is a complex mode used when data...

Page 1194: ...MA controller using this method a set of arbitrary transfers can be performed based on a single DMA request Figure 16 3 and Figure 16 4 show an example of operation in Memory Scatter Gather mode This...

Page 1195: ...ler C 4 WORDS SRCA 16 WORDS SRCB SRC DST ITEMS 16 Unused SRC DST ITEMS 1 1 WORD SRCC 4 DESTA 16 DESTB 1 DESTC DST A B TASK A TASK B TASK C SRC DST ITEMS 12 SRC DST ITEMS n Task List in Memory 2 1 3 So...

Page 1196: ...opies task B configuration to the channel s controller copies task C configuration to the channel s alternate control structure alternate control structure Then using the channel s alternate control s...

Page 1197: ...of arbitrary locations whenever the peripheral is ready to transfer data Figure 16 5 and Figure 16 6 show an example of operation in Peripheral Scatter Gather mode This example shows a gather operati...

Page 1198: ...locations in memory into a peripheral data register 2 Application sets up MA tasklist in memory which contains the pointers and control configuration for three D DMA copy tasks 3 Application sets up t...

Page 1199: ...channel s controller copies task C configuration to the channel s alternate control structure alternate control structure Then using the channel s alternate control structure the Then using the chann...

Page 1200: ...gle request and or burst request signal that is asserted when the peripheral is ready to transfer data see Table 16 2 The request signal can be disabled or enabled using the DMA Channel Request Mask S...

Page 1201: ...6 shows the dedicated interrupt assignments for the DMA controller Table 16 6 DMA Interrupt Assignments Interrupt Assignment 46 DMA Software Transfer 47 DMA Error Note Software should always do a RMW...

Page 1202: ...ast address for the transfer inclusive 1 Program the source end pointer at offset 0x1E0 to the address of the source buffer 0x3FC 2 Program the destination end pointer at offset 0x1E4 to the address o...

Page 1203: ...register using DMA channel 7 The control structure for channel 7 is at offset 0x070 of the channel control table The channel control structure for channel 7 is located at the offsets shown in Table 1...

Page 1204: ...heral interrupts are enabled then the peripheral interrupt handler receives an interrupt when the entire transfer is complete 16 4 4 Configuring a Peripheral for Ping Pong Receive This example configu...

Page 1205: ...0x284 to the address of ping pong buffer B 0x3F The primary control word at offset 0x088 and the alternate control word at offset 0x288 are initially programmed the same way Program the primary channe...

Page 1206: ...field is 0 this means buffer A is complete If buffer A is complete then Process the newly received data in buffer A or signal the buffer processing code that buffer A has data available Reprogram the...

Page 1207: ...0x030 DMAALTSET R W 0x0000 0000 DMA Channel Primary Alternate Set 0x034 DMAALTCLR WO DMA Channel Primary Alternate Clear 0x038 DMAPRIOSET R W 0x0000 0000 DMA Channel Priority Set 0x03C DMAPRIOCLR WO D...

Page 1208: ...y and ROM are located on a separate internal bus it is not possible to transfer data from the Flash memory or ROM with the DMA controller NOTE The offset specified is from the base address of the cont...

Page 1209: ...ameters of a DMA transfer NOTE The offset specified is from the base address of the control structure in system memory not the DMA module base address Figure 16 9 DMA Channel Control Word DMACHCTL Reg...

Page 1210: ...rd Increment by 16 bit locations 0x2 Word Increment by 32 bit locations 0x3 No increment Address remains set to the value of the Source Address End Pointer DMASRCENDP for the channel 25 24 SRCSIZE Sou...

Page 1211: ...emory Scatter Gather 0x5 Alternate Memory Scatter Gather 0x6 Peripheral Scatter Gather 0x7 Alternate Peripheral Scatter Gather XFERMODE Bit Field Values Stop Channel is stopped or configuration data i...

Page 1212: ...ee Basic mode for details See Section 16 3 6 6 Alternate Peripheral Scatter Gather This value must be used in the alternate channel control data structure when the DMA controller operates in Periphera...

Page 1213: ...egister controls the configuration of the DMA controller Figure 16 11 DMA Configuration DMACFG Register 31 1 0 Reserved MASTEN W W LEGEND R W Read Write R Read only n value after reset Table 16 18 DMA...

Page 1214: ...t Field Value Description 31 0 ADDR Alternate Channel Address Pointer This field provides the base address of the alternate channel control structures 16 7 5 DMA Channel Wait on Request Status DMAWAIT...

Page 1215: ...ransfer If there are fewer items remaining to transfer than the arbitration burst size the DMA controller automatically clears the corresponding SET n bit allowing the remaining items to transfer usin...

Page 1216: ...t 0 corresponds to channel 0 A bit can only be cleared by setting the corresponding CLR n bit in the DMAREQMASKCLR register 0 The peripheral associated with channel n is enabled to request DMA transfe...

Page 1217: ...n 31 0 CLR n Clear Channel n Enable Clear Note The controller disables a channel when it completes the DMA cycle 0 No effect 1 Setting a bit clears the corresponding SET n bit in the DMAENASET registe...

Page 1218: ...that channel n is using the primary control structure 16 7 15 DMA Channel Priority Set DMAPRIOSET offset 0x038 Each bit of the DMAPRIOSET register represents the corresponding DMA channel Setting a b...

Page 1219: ...MAERRCLR Register 31 1 0 Reserved ERRCLR R 0 R W 1C 0 LEGEND R W Read Write R Read only n value after reset Table 16 33 DMA Bus Error Clear DMAERRCLR Register Field Descriptions Bit Field Value Descri...

Page 1220: ...d Assignment 3 Reserved 23 20 0 Channel 5 First Assignment 1 Channel 5 Second Assignment 2 Channel 5 Third Assignment 3 Reserved 19 16 0 Channel 4 First Assignment 1 Channel 4 Second Assignment 2 Chan...

Page 1221: ...signment 3 Reserved 23 20 0 Channel 13 First Assignment 1 Channel 13 Second Assignment 2 Channel 13 Third Assignment 3 Reserved 19 16 0 Channel 12 First Assignment 1 Channel 12 Second Assignment 2 Cha...

Page 1222: ...gnment 3 Reserved 23 20 0 Channel 21 First Assignment 1 Channel 21 Second Assignment 2 Channel 21 Third Assignment 3 Reserved 19 16 0 Channel 20 First Assignment 1 Channel 20 Second Assignment 2 Chann...

Page 1223: ...ignment 3 Reserved 23 20 0 Channel 29 First Assignment 1 Channel 29 Second Assignment 2 Channel 29 Third Assignment 3 Reserved 19 16 0 Channel 28 First Assignment 1 Channel 28 Second Assignment 2 Chan...

Page 1224: ...served 7 0 PID1 DMA Peripheral ID Register 15 8 Can be used by software to identify the presence of this peripheral 16 7 25 DMA Peripheral Identification 2 DMAPeriphID2 offset 0xFE8 The DMAPeriphIDn r...

Page 1225: ...scriptions Bit Field Value Description 31 8 Reserved Reserved 7 0 PID4 DMA Peripheral ID Register Can be used by software to identify the presence of this peripheral 16 7 28 DMA PrimeCell Identificati...

Page 1226: ...0 Reserved CID2 R 0 R 05 LEGEND R W Read Write R Read only n value after reset Table 16 45 DMA PrimeCell Identification 2 DMAPCellID2 Register Field Descriptions Bit Field Value Description 31 8 Reser...

Page 1227: ...Peripheral Interface EPI This chapter discusses the function of the external peripheral interface EPI Topic Page 17 1 Introduction 1228 17 2 EPI Block Diagram 1229 17 3 Functional Description 1229 17...

Page 1228: ...le also provides custom GPIOs however unlike regular GPIOs the EPI module uses a FIFO in the same way as a communication mechanism and is speed controlled using clocking Synchronous Dynamic Random Acc...

Page 1229: ...hat can use a FIFO with speed control by using either the internal write FIFO WFIFO or the non blocking read FIFO NBRFIFO The WFIFO can hold four words of data that are written to the external interfa...

Page 1230: ...vailable The NBRFIFO can be configured to interrupt the processor or trigger the DMA based on fullness using the EPIFIFOLVL register By using the trigger interrupt method the DMA or processor can keep...

Page 1231: ...ides the best possible transfer rate For blocking reads the DMA software channel or another unused channel is used for memory to memory transfers or memory to peripheral where some other peripheral is...

Page 1232: ...d to when the first operation is allowed The SDRAM controller begins the SDRAM initialization sequence as soon as the mode is selected and enabled via the EPICFG register It is important that the GPIO...

Page 1233: ...EPI0S10 A10 D10 EPI0S11 A11 D11 EPI0S12 A12 2 D12 EPI0S13 BA0 D13 EPI0S14 BA1 D14 EPI0S15 D15 EPI0S16 DQML EPI0S17 DQMH EPI0S18 CAS EPI0S19 RAS EPI0S20 EPI0S27 not used EPI0S28 WE EPI0S29 CS EPI0S30...

Page 1234: ...running at higher speeds the bus interface can run only as fast as half speed and the COUNT0 field must be configured to at least 0x0001 17 6 4 Non Blocking Read Cycle Figure 17 2 shows a non blocking...

Page 1235: ...programmed CAS latency of 2 the Write command with the column address on the EPI0S 15 0 signals follows after two clock cycles When writing to SDRAMs the Write command is presented with the first half...

Page 1236: ...GH and WRHIGH bits in the EPI Host Bus n Configuration EPIHBnCFGn register The ALE can be changed to an active low chip select signal CS through the EPIHBnCFGn register The ALE is best used for Host B...

Page 1237: ...h ALE EPI0S27 is used as CS1 and EPI0S26 is used as CS0 Whether CS0 or CS1 is asserted is determined by the most significant address bit for a respective external address map 0x4 ALE with Single CS Co...

Page 1238: ...00 or 0x8000 0000 N A N A Dual chip select 0x0 0x1 or 0x2 0x1 ECADR defined address range 0x1000 0000 EPADR defined address range 0xA000 0000 or 0xC000 0000 N A N A Dual chip select 0x1 or 0x2 0x0 0x1...

Page 1239: ...ss space is doubled For example 28 bits of address accesses 512 MB in this mode Table 17 5 shows the capabilities of the HB8 and HB16 modes as well as the available address bits with the possible comb...

Page 1240: ...Yes 8 2 256 B HB16 0x1 1 0x0 1 0 No 11 1 4 KB HB16 0x1 1 0x0 1 1 Yes 9 2 256 B HB16 0x1 1 0x1 4 0 No 19 1 1 MB HB16 0x1 1 0x1 4 1 Yes 17 2 128 KB HB16 0x1 1 0x2 4 0 No 10 1 2 KB HB16 0x1 1 0x2 4 1 Yes...

Page 1241: ...B8 Signal MODE ADNOMUX Cont Read HB8 Signal MODE XFIFO EPI0S0 X AD0 D0 D0 EPI0S1 X AD1 D1 D1 EPI0S2 X AD2 D2 D2 EPI0S3 X AD3 D3 D3 EPI0S4 X AD4 D4 D4 EPI0S5 X AD5 D5 D5 EPI0S6 X AD6 D6 D6 EPI0S7 X AD7...

Page 1242: ...CS0 CS0 0x3 ALE ALE 0x4 0x5 CS0 CS0 0x6 ALE ALE EPI0S31 X Clock 3 Clock 3 Clock 3 EPIOS32 X iRDY iRDY iRDY EPIOS33 0x0 X X X 0x1 X X X 0x2 X X X 0x3 X X X 0x4 X X X 0x5 CS3 CS3 X 0x6 X EPI0S34 0x0 X X...

Page 1243: ...E ADMUX 3 HB16 Signal MODE ADNOMUX B16 Signal MODE XFIFO EPI0S0 X X AD0 D0 D0 EPI0S1 X X AD1 D1 D1 EPI0S2 X X AD2 D2 D2 EPI0S3 X X AD3 D3 D3 EPI0S4 X X AD4 D4 D4 EPI0S5 X X AD5 D5 D5 EPI0S6 X X AD6 D6...

Page 1244: ...EL0 BSEL0 0x1 0 A26 A10 1 BSEL0 BSEL0 0x2 0 A26 A10 1 BSEL1 BSEL1 0x3 X CS0 CS0 0x4 0 A26 A10 1 BSEL1 BSEL1 0x5 0 A26 A10 1 BSEL1 BSEL1 0x6 X CS0 CS0 0x7 0 A10 1 BSEL1 EPI0S27 0x0 0 A27 A11 FFULL 1 BS...

Page 1245: ...A15 EPI0S41 0x0 0x4 X 0x5 X A16 0x6 X 0x7 X A16 EPI0S42 0x0 0x4 X 0x5 0 A17 1 A9 0x6 X 0x7 0 A17 1 A9 EPI0S43 0x0 0x4 X 0x5 0 A18 1 A10 0x6 X 0x7 0 A18 1 A10 The RDYEN in the EPIHBnCFG enables the mon...

Page 1246: ...12 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated External Peripheral Interface EPI Figure 17 7 shows how to connect the EPI signals to a16 bit...

Page 1247: ...9 A10 A11 A12 A13 A14 A15 EPI16 EPI17 EPI0 EPI1 EPI2 EPI3 EPI4 EPI5 EPI6 EPI7 EPI8 EPI9 EPI10 EPI11 EPI12 EPI13 EPI14 EPI15 EPI28 EPI29 EPI26 EPI25 EPI24 A 0 15 EPI_16_BUS EPI_16_BUS A0 A1 A2 A3 A4 A5...

Page 1248: ...d the SRAM This sub mode is provided for compatibility with existing devices that support data transfers without a latch that is CPLDs In general the de muxed sub mode should normally be used The ALE...

Page 1249: ...blocking read latency from the processor or DMA The WORD bit in the EPIHBnCFG2 register can be set to use memory more efficiently By default the EPI controller uses data bits 7 0 for Host Bus 8 acces...

Page 1250: ...erface EPI Figure 17 9 Host Bus Write Cycle MODE 0x1 WRHIGH 0 RDHIGH 0 ALEHIGH 1 Figure 17 10 shows a write cycle with the address and data signals multiplexed MODE field is 0x0 in the EPIHBnCFG regis...

Page 1251: ...g the address pins The data pins are changed by the SRAM after the address pins change Figure 17 12 Continuous Read Mode Accesses FIFO mode accesses are the same as normal read and write accesses exce...

Page 1252: ...iods by configuring 20 pins to be inputs configuring the COUNT0 field in the EPIBAUD register to some divider and then using non blocking reads Implementing a very wide ganged PWM PCM with fixed frequ...

Page 1253: ...ptured on the second cycle when RD is not asserted allowing more setup time for data For writes the output may be in one or two cycles In the two cycle case the address if any is emitted on the first...

Page 1254: ...ipheral Interface EPI states are read back With the EPI controller the non blocking interface may also be used to perform reads based on a fixed time rule via the EPIBAUD clock rate Table 17 9 shows h...

Page 1255: ...I0S4 D4 D4 D4 D4 EPI0S5 D5 D5 D5 D5 EPI0S6 D6 D6 D6 D6 EPI0S7 D7 D7 D7 D7 EPI0S8 A0 D8 D8 D8 EPI0S9 A1 D9 D9 D9 EPI0S10 A2 D10 D10 D10 EPI0S11 A3 D11 D11 D11 EPI0S12 A4 D12 D12 D12 EPI0S13 A5 D13 D13...

Page 1256: ...I0S29 WR EPI0S28 Address Data General Purpose Mode www ti com 1256 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated External...

Page 1257: ...simply the logical OR of the WR and RD strobes so the FRAME signal is high during every read or write access See Figure 17 18 Figure 17 18 FRAME Signal Operation FRM50 0 and FRMCNT 0 If the FRMCNT fie...

Page 1258: ...corporated External Peripheral Interface EPI Figure 17 21 FRAME Signal Operation FRM50 1 and FRMCNT 0 When FRMCNT 1 the FRAME signal transitions on the rising edge of the WR or RD strobes for every ot...

Page 1259: ...until after iRDY has been sampled High again Data is sampled on the subsequent rising edge If iRDY is sampled Low at the start of the data phase as shown in Figure 17 24 the FRAME RD Address and Data...

Page 1260: ...rce between master subsystem M3 and DMA and control subsystem C28x and DMA All masters can access external devices via EPI simultaneously Access to each master is granted based on round robin arbitrat...

Page 1261: ...ime period for which C28x wants to grab the EPI Once C28x grabs the EPI by setting the GRAB bit a free running counter CEPIRTWCNT starts incrementing If C28x software does not release the EPI access b...

Page 1262: ...Address C28x Offset Address Acronym Type Reset Description 0x000 0x000 EPICFG R W 0x0000 0000 EPI Configuration Register 0x004 0x002 EPIBAUD R W 0x0000 0000 EPI Main Baud Rate Register 0x010 0x008 EPI...

Page 1263: ...0x108 EPIIM R W 0x0000 0000 EPI Interrupt Mask Register 0x214 0x10A EPIRIS R 0x0000 0004 EPI Raw Interrupt Status Register 0x218 0x10C EPIMIS R 0x0000 0000 EPI Masked Interrupt Status Register 0x21C...

Page 1264: ...n Size x8 Offset x16 Protection CEPIRTWCFG C28 EPI Real Time Window Config Register 4 0x00 EALLOW CEPIRTWCNT C28 EPI Real Time Window Counter Register 4 0x02 None CEPIRTWPRD C28 EPI Real Time Window P...

Page 1265: ...rved INTDIV Reserved BLKEN MODE R 0 R W 0 R 0 R W 0 R W 0x0 LEGEND R W Read Write R Read only n value after reset Table 17 14 EPI Configuration Register EPICFG Field Descriptions Bit Field Value Descr...

Page 1266: ...k as follows If COUNTn 0 EPIClockFreq SystemClockFreq otherwise EPIClockFreq SystemClockFreq Countn 2 1 2 where the symbol around COUNTn 2 is the floor operator meaning the largest integer less than o...

Page 1267: ...to the COUNTn field and the system clock as follows If COUNTn 0 EPIClockFreq SystemClockFreq otherwise EPIClockFreq SystemClockFreq Countn 2 1 2 where the symbol around COUNTn 2 is the floor operator...

Page 1268: ...0 Reserved SLEEP Reserved SIZE R 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 17 17 EPI SDRAM Configuration EPISDRAMCFG Register Field Descriptions Bit Field Value Des...

Page 1269: ...our chip selects with and without the use of ALE If an alternative to chip selects are required a chip enable can be handled in one of three ways 1 Manually control via GPIOs 2 Associate one or more u...

Page 1270: ...S032 is high the current access is stalled 0 No effect 26 24 Reserved Reserved 23 XFFEN External FIFO FULL Enable 0 No effect 1 An external FIFO full signal can be used to control write cycles If this...

Page 1271: ...rising edge of RD Oen or the falling edge of RD Each wait state adds two EPI clock cycles to the access time The RDWSM bit in the EPIHB8TIME register can decrease the number of wait states by 1 EPI c...

Page 1272: ...chip selects with and without the use of ALE If an alternative to chip selects are required a chip enable can be handled in one of three ways 1 Manually control via GPIOs 2 Associate one or more upper...

Page 1273: ...gnal can be used to control write cycles If this bit is set and the FFULL full signal is high XFIFO writes are stalled 22 XFEEN External FIFO EMPTY Enable 0 No effect 1 An external FIFO empty signal c...

Page 1274: ...ME register can decrease the number of wait states by 1 EPI clock cycle for greater granularity This field is not applicable in BURST mode 0x0 Active RD is 2 EPI clocks 0x1 Active RD is 4 EPI clocks 0...

Page 1275: ...custom interfaces of any speed The configuration allows for choice of an output clock free running or gated a framing signal with frame size a ready input to stretch transactions read and write strobe...

Page 1276: ...orced to be set 0 Data is output on the same EPI clock cycle as the address 1 Writes are two EPI clock cycles long with address on one EPI clock cycle with the WR strobe asserted and data written on t...

Page 1277: ...ines the size of the data bus starting at EPI0S0 Subsets of these numbers can be created by clearing the AFSEL bit for the corresponding GPIOs Note that size 32 may not be used with clock frame addres...

Page 1278: ...ved WRHIGH RDHIGH ALEHIGH Reserved R 0 R W 0 R W 0 R W 1 R 0 15 14 13 12 11 10 9 8 Reserved R 0 7 6 5 4 3 2 1 0 WRWS RDWS Reserved MODE R W 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value...

Page 1279: ...rther configurations including quad chip select 0x0 ALE Configuration EPI0S30 is used as an address latch ALE The ALE signal is generally used when the address and data are muxed HB8MODE field in the...

Page 1280: ...his field adds wait states to the data phase of CS1 accesses the address phase is not affected The effect is to delay the rising edge of RD OE or the falling edge of RD Each wait state encoding adds 2...

Page 1281: ...7 16 Reserved WRHIGH RDHIGH ALEHIGH Reserved BURST R 0 R W 0 R W 0 R W 1 R 0 R W 0 15 8 Reserved R 0 7 6 5 4 3 2 1 0 WRWS RDWS Reserved MODE R W 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n v...

Page 1282: ...chip selects and an ALE combined with two chip selects These bits are also used in combination with the CSCFGEXT bit for further configurations including quad chip select 0x0 ALE Configuration EPI0S30...

Page 1283: ...t states to the data phase of CS1 accesses the address phase is not affected The effect is to delay the rising edge of RD OE or the falling edge of RD Each wait state encoding adds 2 EPI clock cycles...

Page 1284: ...ust be reinitialized Figure 17 37 EPI General Purpose Configuration 2 EPIGPCFG2 Register offset 0x014 31 30 0 WORD Reserved R W 0 R 0 LEGENR W 0D R W Read Write R Read only n value after reset Table 1...

Page 1285: ...is not 0x0 then CS0 is asserted for the address range defined by ECADR and CS1 is asserted for either address range defined by EPADR If the ECADR field is 0x1 EPADR field is 0x0 and the ERADR field is...

Page 1286: ...mode CS2 maps to 0xA000 0000 and CS3 maps to 0xC000 0000 3 2 ERSZ External RAM Size This field selects the size of mapped RAM If the size of the external memory is larger a bus fault occurs If the si...

Page 1287: ...PIRSIZE0 Register offset 0x020 and EPI Read Size 1 EPIRSIZE1 Register offset 0x030 31 2 1 0 Reserved SIZE R 0x0000 000 R W 0x3 LEGEND R W Read Write R Read only n value after reset Table 17 25 EPI Rea...

Page 1288: ...n Blocking Read Data 1 EPIRPSTD1 Register offset 0x028 and 0x038 This register sets up a non blocking read via the external interface A non blocking read is started by writing to this register with th...

Page 1289: ...erface is not busy At that point the corresponding EPIRADDRn register indicates how many values were read Figure 17 41 EPI Non Blocking Read Data 0 EPIRPSTD0 Register offset 0x028 and EPI Non Blocking...

Page 1290: ...ot gating the clock 1 The external device is gating the clock iRDY is low Attempts to read or write in this situation are stalled until the clock is enabled or the counter times out as specified by th...

Page 1291: ...the EPIRPSTD0 register is active If the NBRBUSY bit is clear then neither EPIRPSTDx register is active 1 The EPIRPSTD1 register is active 17 11 16 EPI Read FIFO Count EPIRFIFOCNT Register offset 0x06C...

Page 1292: ...e DMA The NBRFIFO select triggers on fullness such that it triggers on match or above more full in order for the processor or the DMA to extract the read data The WFIFO triggers on emptiness such that...

Page 1293: ...be generated when a read is attempted and the WFIFO is not empty The read is still stalled during the time the WFIFO drains but this error notifies the application that this excess delay has occurred...

Page 1294: ...WFIFOCNT 0 ext_ram mydata The above code ensures that writes to the address mapped location do not occur unless the WFIFO has room Although polling makes the code wait spinning in the loop it does not...

Page 1295: ...rrupt source to trigger an interrupt to the interrupt controller a mask value of 0 prevents the interrupt source from triggering an interrupt Figure 17 48 EPI Interrupt Mask EPIIM Register offset 0x21...

Page 1296: ...DRIS ERRRIS R 0x000 R 0 R 0 R 1 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 17 35 EPI Raw Interrupt Status EPIRIS Register Field Descriptions Bit Field Value Description 31 5 R...

Page 1297: ...write has no effect The values returned are the ANDing of the EPIIM and EPIRIS registers If a bit is set in this register the interrupt is sent to the interrupt controller Figure 17 50 EPI Masked Inte...

Page 1298: ...the NBRFIFO is below the range specified by the trigger level or the interrupt is masked 1 The number of valid entries in the NBRFIFO is within the range specified by the trigger level the RDFIFO fiel...

Page 1299: ...nd reading back immediately pipelined by the processor returns the old register contents One cycle is needed between write and read Figure 17 51 EPI Error Interrupt Status and Clear EPIEISC Register o...

Page 1300: ...G2 0 The address latch strobe for CS2 accesses is ADV active Low 1 The address latch strobe for CS2 accesses is ALE active High 18 8 Reserved Reserved 7 6 WRWS CS2 Write Wait States This field is used...

Page 1301: ...t 0x308 NOTE The MODE field in the EPICFG register determines which configuration is enabled For EPIHB16CFG3 to be valid the MODE field must be 0x3 Figure 17 53 EPI Host Bus 16 Configuration 3 Registe...

Page 1302: ...s 0x2 Active WR is 6 EPI clocks 0x3 Active WR is 8 EPI clocks 5 2 Reserved Reserved 1 0 MODE CS2 Host Bus Sub Mode This field determines which Host Bus 8 sub mode to use for CS2 in multiple chip selec...

Page 1303: ...arity This field is used if the CSBAUD bit is enabled in the EPIHB8CFG2 register This field is not applicable in BURST mode 0x0 Active WR is 2 EPI clocks 0x1 Active WR is 4 EPI clocks 0x2 Active WR is...

Page 1304: ...active Low 1 The READ strobe for CS3 accesses is RD active High 19 ALEHIGH CS3 ALE Strobe Polarity This field is used if the CSBAUD bit is enabled in EPIHB16CFG2 0 The address latch strobe for CS3 acc...

Page 1305: ...This mode is not practical in HB16 mode for normal SRAMs because there are generally not enough address bits available 0x3 Reserved 17 11 29 EPI Host Bus 8 Timing Extension EPIHB8TIME offset 0x310 NO...

Page 1306: ...6 Timing Extension EPIHB16TIME offset 0x310 NOTE The MODE field in the EPICFG register determines which configuration is enabled For EPIHB16TIME to be valid the MODE field must be 0x3 Figure 17 57 EPI...

Page 1307: ...Host Bus 8 Timing Extension EPIHB8TIME2 offset 0x314 NOTE The MODE field in the EPICFG register determines which configuration is enabled For EPIHB8TIME2 to be valid the MODE field must be 0x2 Figure...

Page 1308: ...Bus 16 Timing Extension EPIHB16TIME2 offset 0x314 NOTE The MODE field in the EPICFG register determines which configuration is enabled For EPIHB16TIME2 to be valid the MODE field must be 0x3 Figure 1...

Page 1309: ...33 EPI Host Bus 8 Timing Extension EPIHB8TIME3 offset 0x318 NOTE The MODE field in the EPICFG register determines which configuration is enabled For EPIHB8TIME3 to be valid the MODE field must be 0x2...

Page 1310: ...16 Timing Extension EPIHB16TIME3 Register offset 0x318 NOTE The MODE field in the EPICFG register determines which configuration is enabled For EPIHB16TIME3 to be valid the MODE field must be 0x3 Figu...

Page 1311: ...ost Bus 8 Timing Extension EPIHB8TIME4 Register offset 0x31C NOTE The MODE field in the EPICFG register determines which configuration is enabled For EPIHB8TIME4 to be valid the MODE field must be 0x2...

Page 1312: ...t Bus 16 Timing Extension EPIHB16TIME4 Register 0x31C NOTE The MODE field in the EPICFG register determines which configuration is enabled For EPIHB16TIME4 to be valid the MODE field must be 0x3 Figur...

Page 1313: ...R W 0 LEGEND R W Read Write R Read only n value after reset Table 17 50 CEPIRTWCFG Register Field Descriptions Bit FiKEY Value Description 31 4 KEY This field should have value of 0x9EDCB4A to enable...

Page 1314: ...egister Figure 17 67 CEPISTATUS Register 31 16 Reserved R 0 15 2 3 2 1 0 Reserved MEMPROTER R RTWTIMEOUT R 0 R W 1 R W 1 LEGEND R W Read Write R Read only n value after reset Table 17 53 CEPISTATUS Re...

Page 1315: ...M3 uDMA C28x DMA have RD WR permission 01 Only Master subsystem has WR permission to CS2 region Control subsystem has only RD permission 10 Only control subsystem has WR permission to CS2 region Mast...

Page 1316: ...PEND and RESUME signaling Thirty two endpoints comprised of two hard wired for control transfers one endpoint for IN and one endpoint for OUT plus 30 endpoints defined by firmware along with a dynamic...

Page 1317: ...endpoint memory one endpoint may be defined for double buffered 1023 byte isochronous packet size VBUS droop and valid ID detection and interrupt Efficient transfers using direct memory access control...

Page 1318: ...on the USB controller s endpoint 0 18 2 1 1 Endpoints When operating as a Device the USB controller provides two dedicated control endpoints IN and OUT and 30 configurable endpoints 15 IN and 15 OUT...

Page 1319: ...iate transmit endpoint interrupt signaled to indicate that another packet can now be loaded into the transmit FIFO The state of the FIFONE bit in the USBTXCSRLn register at this point indicates how ma...

Page 1320: ...to some error If the Host controller makes a request and the Device controller is not ready the USB controller sends a busy response NAK to all requests until it is ready 18 2 1 1 4 Additional Action...

Page 1321: ...SPEND mode If the SUSPEND interrupt has been enabled in the USB Interrupt Enable USBIE register an interrupt is generated at this time When in SUSPEND mode the PHY also goes into SUSPEND mode When RES...

Page 1322: ...supported both for point to point communication and for operation through a hub The USB controller automatically carries out the necessary transaction translation needed to allow a low speed or full s...

Page 1323: ...leared The AUTOCL bit in the USBRXCSRHn register can be used to have RXRDY automatically cleared when a maximum sized packet has been unloaded from the FIFO The AUTORQ bit in USBRXCSRHn causes the REQ...

Page 1324: ...ion is started if the transaction is found on the first scheduler cycle of a frame and if the interval counter for that endpoint has counted down to zero As a result only one interrupt or isochronous...

Page 1325: ...When a device is detected a connect interrupt is generated The speed of the device that has been connected can be determined by reading the USBDEVCTL register where the FSDEV bit is set for a full spe...

Page 1326: ...device of the OTG setup wishes to start a session it either raises VBUS above the Session Valid threshold if it is the A device or if it is the B device it pulses the data line then pulses VBUS Depen...

Page 1327: ...ltiples of the size of the USB FIFO Both read and write transfers of the USB FIFOs using DMA must be configured in this manner For example if the USB endpoint is configured with a FIFO size of 64 byte...

Page 1328: ...rtion of the USB controller in a system that also provides Host functionality the power to VBUS must be disabled to allow the external Host controller to supply power Usually the USB0EPEN signal is us...

Page 1329: ...00 USB General Interrupt Status Section 18 5 7 0x00B USBIE 1 2 R W 0x06 USB Interrupt Enable Section 18 5 8 0x00C USBFRAME 1 2 RO 0x0000 USB Frame Value Section 18 5 9 0x00E USBEPIDX 1 2 R W 0x00 USB...

Page 1330: ...ection 18 5 24 0x09C USBRXFUNCADDR3 2 R W 0x00 USB Receive Functional Address Endpoint 3 Section 18 5 25 0x09E USBRXHUBADDR3 2 R W 0x00 USB Receive Hub Address Endpoint 3 Section 18 5 26 0x09F USBRXHU...

Page 1331: ...oint 11 Section 18 5 23 0x0DB USBTXHUBPORT11 2 R W 0x00 USB Transmit Hub Port Endpoint 11 Section 18 5 24 0x0DC USBRXFUNCADDR11 2 R W 0x00 USB Receive Functional Address Endpoint 11 Section 18 5 25 0x...

Page 1332: ...MAXP2 1 2 R W 0x0000 USB Maximum Receive Data Endpoint 2 Section 18 5 36 0x126 USBRXCSRL2 1 2 R W 0x00 USB Receive Control and Status Endpoint 2 Low Section 18 5 37 0x127 USBRXCSRH2 1 2 R W 0x00 USB R...

Page 1333: ...nd Status Endpoint 6 High Section 18 5 38 0x168 USBRXCOUNT6 1 2 RO 0x0000 USB Receive Byte Count Endpoint 6 Section 18 5 39 0x16A USBTXTYPE6 2 R W 0x00 USB Host Transmit Configure Type Endpoint 6 Sect...

Page 1334: ...ction 18 5 41 0x1AC USBRXTYPE10 2 R W 0x00 USB Host Configure Receive Type Endpoint 10 Section 18 5 42 0x1AD USBRXINTERVAL10 2 R W 0x00 USB Host Receive Polling Interval Endpoint 10 Section 18 5 43 0x...

Page 1335: ...18 5 41 0x1EC USBRXTYPE14 2 R W 0x00 USB Host Configure Receive Type Endpoint 14 Section 18 5 42 0x1ED USBRXINTERVAL14 2 R W 0x00 USB Host Receive Polling Interval Endpoint 14 Section 18 5 43 0x1F0 U...

Page 1336: ...Interrupt Status Section 18 5 51 0x414 USBDRIM 1 2 R W 0x0000 0000 USB Device RESUME Interrupt Mask Section 18 5 52 0x418 USBDRISC 1 2 W1C 0x0000 0000 USB Device RESUME Interrupt Status and Clear Sec...

Page 1337: ...egister is clear this register must be written with the address received through a SET_ADDRESS command which is then used for decoding the function address in subsequent token packets Mode s OTG B or...

Page 1338: ...aling on the bus 2 RESUME RESUME signaling The bit should be cleared by software 20 ms after being set 0 Ends RESUME signaling on the bus 1 Enables RESUME signaling when the Device is in SUSPEND mode...

Page 1339: ...3 RESET RESET signaling 0 Ends RESET signaling on the bus 1 Enables RESET signaling on the bus 2 RESUME RESUME signaling The bit should be cleared by software 10 ms a maximum of 15 ms after being set...

Page 1340: ...Transmit Interrupt Status Register USBTXIS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R...

Page 1341: ...rupt is asserted 5 EP5 TX Endpoint 5 Interrupt 0 No interrupt 1 The Endpoint 5 transmit interrupt is asserted 4 EP4 TX Endpoint 4 Interrupt 0 No interrupt 1 The Endpoint 4 transmit interrupt is assert...

Page 1342: ...P2 EP1 Rsvd R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 18 9 USB Receive Interrupt Status Register USBRXIS Field Descrip...

Page 1343: ...0 No interrupt 1 The Endpoint 6 receive interrupt is asserted 5 EP5 RX Endpoint 5 Interrupt 0 No interrupt 1 The Endpoint 5 receive interrupt is asserted 4 EP4 RX Endpoint 4 Interrupt 0 No interrupt...

Page 1344: ...ontroller when the EP14 bit in the USBTXIS register is set 13 EP13 TX Endpoint 13 Interrupt Enable 0 The EP13 transmit interrupt is suppressed and not sent to the interrupt controller 1 An interrupt i...

Page 1345: ...n the USBTXIS register is set 3 3P3 TX Endpoint 3 Interrupt Enable 0 The EP3 transmit interrupt is suppressed and not sent to the interrupt controller 1 An interrupt is sent to the interrupt controlle...

Page 1346: ...ler when the EP14 bit in the USBRXIS register is set 13 EP13 RX Endpoint 13 Interrupt Enable 0 The EP13 receive interrupt is suppressed and not sent to the interrupt controller 1 An interrupt is sent...

Page 1347: ...ot sent to the interrupt controller 1 An interrupt is sent to the interrupt controller when the EP4 bit in the USBRXIS register is set 3 3P3 RX Endpoint 3 Interrupt Enable 0 The EP3 receive interrupt...

Page 1348: ...R Read only n value after reset Table 18 12 USB General Interrupt Status Register USBIS in OTG A Host Mode Field Descriptions Bit Field Value Description 7 VBUSERR VBUS Error 0 No interrupt 1 VBUS ha...

Page 1349: ...vice Mode Field Descriptions Bit Field Value Description 7 6 Reserved 0 Reserved 5 DISCON Session Disconnect 0 No interrupt 1 The device has been disconnected from the host 4 Reserved 0 Reserved 3 SOF...

Page 1350: ...0 The SESREQ interrupt is suppressed and not sent to the interrupt controller 1 An interrupt is sent to the interrupt controller when the SESREEQ bit in the USBIS register is set 5 DISCON Enable Disc...

Page 1351: ...egister is set 4 Reserved 0 Reserved 3 SOF Start of frame 0 The SOF interrupt is suppressed and not sent to the interrupt controller 1 An interrupt is sent to the interrupt controller when the SOF bit...

Page 1352: ...t received frame number 18 5 10 USB Endpoint Index Register USBEPIDX offset 0x00E Each endpoint s buffer can be accessed by configuring a FIFO size and starting address The endpoint index 16 bit regis...

Page 1353: ...the USB controller to enter Host mode when the SESSION bit is set regardless of whether the USB controller is connected to any peripheral The state of the USB0DP and USB0DM signals is ignored The USB...

Page 1354: ...Incorporated M3 Universal Serial Bus USB Controller Table 18 19 USB Test Mode Register USBTEST in OTG B Device Mode Field Descriptions continued Bit Field Value Description 5 FORCEFS Force Full Speed...

Page 1355: ...ently byte halfword or word aligned However the last transfer may contain fewer bytes than the previous transfers in order to complete an odd byte or odd word transfer Depending on the size of the FIF...

Page 1356: ...e Description 7 DEV Device mode 0 The USB controller is operating on the OTG A side of the cable 1 The USB controller is operating on the OTG B side of the cable Only valid while a session is in progr...

Page 1357: ...Start End When operating as an OTG A device 0 When cleared by software this bit ends a session 1 When set by software this bit starts a session When operating as an OTG A device 0 The USB controller...

Page 1358: ...r Device USBTXFIFOSZ is shown in Figure 18 19 and described in Table 18 22 Figure 18 19 USB Transmit Dynamic FIFO Sizing Register USBTXFIFOSZ 7 5 4 3 0 Reserved DPB SZ R 0 R W 0 R 0 LEGEND R W Read Wr...

Page 1359: ...Figure 18 20 and described in Table 18 23 Figure 18 20 USB Receive Dynamic FIFO Sizing Register USBRXFIFOSZ 7 5 4 3 0 Reserved DPB SZ R 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after res...

Page 1360: ...s of the selected transmit endpoint FIFOs Mode s OTG A or Host OTG B or Device USBTXFIFOADDR is shown in Figure 18 21 and described in Table 18 24 Figure 18 21 USB Transmit FIFO Start Address Register...

Page 1361: ...ss of the selected receive endpoint FIFOs Mode s OTG A or Host OTG B or Device USBRXFIFOADDR is shown in Figure 18 22 and described in Table 18 25 Figure 18 22 USB Receive FIFO Start Address Register...

Page 1362: ...wait required to allow for the user s connect disconnect filter in units of 533 3 ns The default corresponds to 2 667 s 3 0 WTID Ch The wait ID field configures the delay required from the enable of t...

Page 1363: ...speed end of frame gap field is used during full speed transactions to configure the gap between the last transaction and the End of Frame EOF in units of 533 3 ns The default corresponds to 63 46 s 1...

Page 1364: ...Rx must be defined for each transmit endpoint that is used Note USBTXFUNCADDR0 is used for both receive and transmit for endpoint 0 For the specific offset for each register see Table 18 4 Mode s OTG...

Page 1365: ...ds the address of the USB 2 0 hub through which the target associated with the endpoint is accessed Note USBTXHUBADDR0 is used for both receive and transmit for endpoint 0 For the specific offset for...

Page 1366: ...b This register records the port of the USB 2 0 hub through which the target associated with the endpoint is accessed Note USBTXHUBPORT0 is used for both receive and transmit for endpoint 0 For the sp...

Page 1367: ...USBRXFUNCADDRx must be defined for each receive endpoint that is used Note USBTXFUNCADDR0 is used for both receive and transmit for endpoint 0 For the specific offset for each register see Table 18 4...

Page 1368: ...the endpoint is accessed Note USBTXHUBADDR0 is used for both receive and transmit for endpoint 0 For the specific offset for each register see Table 18 4 Mode s OTG A or Host The USBRXHUBADDR n regist...

Page 1369: ...Each register records the port of the USB 2 0 hub through which the target associated with the endpoint is accessed Note USBTXHUBPORT0 is used for both receive and transmit for endpoint 0 For the spec...

Page 1370: ...ter must not exceed the FIFO size for the transmit endpoint and must not exceed half the FIFO size if double buffering is required If this register is changed after packets have been sent from the end...

Page 1371: ...e set at the same time as the TXRDY or REQPKT bit is set This bit is automatically cleared when the STATUS stage is over 5 REQPKT Request Packet This bit is cleared when the RXRDY bit is set 0 No requ...

Page 1372: ...has not ended or ended after the DATAEND bit was set 1 A control transaction has ended before the DATAEND bit has been set The EP0 bit in the USBTXIS register is also set in this situation This bit i...

Page 1373: ...of the endpoint 0 data toggle If DTWE is set this bit may be written with the required setting of the data toggle If DTWE is Low this bit cannot be written Care should be taken when writing to this bi...

Page 1374: ...eceive Byte Count Endpoint 0 Register USBCOUNT0 Field Descriptions Bit Field Value Description 7 Reserved 0 Reserved 6 0 COUNT 0 FIFO Count COUNT is a read only value that indicates the number of rece...

Page 1375: ...mber of frames selected is 2 m 1 where m is the value set in the register with valid values of 2 16 If the Host receives NAK responses from the target for more frames than the number represented by th...

Page 1376: ...t 1 Writing a 1 to this bit clears the DT bit in the USBTXCSRH n register 5 STALLED Endpoint Stalled Software must clear this bit 0 A STALL handshake has not been received 1 Indicates that a STALL han...

Page 1377: ...RL n in OTG B Device Mode Field Descriptions Bit Field Value Description 7 Reserved 0 Reserved 6 CLRDT Clear Data Toggle 0 No effect 1 Writing a 1 to this bit clears the DT bit in the USBTXCSRH n regi...

Page 1378: ...B Device Mode Field Descriptions continued Bit Field Value Description 0 TXRDY Transmit Packet Ready This bit is cleared automatically when a data packet has been transmitted The EPn bit in the USBTX...

Page 1379: ...ually 6 Reserved 0 Reserved 5 MODE Mode Note This bit only has an effect when the same endpoint FIFO is used for both transmit and receive transactions 0 Enables the endpoint direction as RX 1 Enables...

Page 1380: ...tomatically set when data of the maximum packet size value in USBTXMAXP n is loaded into the transmit FIFO If a packet of less than the maximum packet size is loaded then the TXRDY bit must be set man...

Page 1381: ...ansfers in full speed operation The total amount of data represented by the value written to this register must not exceed the FIFO size for the transmit endpoint and must not exceed half the FIFO siz...

Page 1382: ...1 A STALL handshake has been received The EPn bit in the USBRXIS register is also set 5 REQPKT Request Packet This bit is cleared when the RXRDY bit is set 0 No request 1 Requests an IN transaction 4...

Page 1383: ...d Value Description 7 CLRDT Clear Data Toggle 0 No effect 1 Writing a 1 to this bit clears the DT bit in the USBRXCSRH n register 6 STALLED Endpoint Stalled Software must clear this bit 0 A STALL hand...

Page 1384: ...can be loaded into the receive FIFO 0 RXRDY Receive Packet Ready If the AUTOCLR bit in the USBRXCSRH n register is set then the this bit is automatically cleared when a packet of USBRXMAXP n bytes has...

Page 1385: ...regardless of the value of the MAXLOAD field in the USBRXMAXP n register see Section 18 2 4 6 AUTORQ Auto Request Note This bit is automatically cleared when a short packet is received 0 No effect 1...

Page 1386: ...4 byte chunks regardless of the value of the MAXLOAD field in the USBRXMAXP n register see Section 18 2 4 6 ISO Isochronous Transfers 0 Enables the receive endpoint for isochronous transfers 1 Enable...

Page 1387: ...for the combined packet Note The value returned changes as the FIFO is unloaded and is only valid while the RXRDY bit in the USBRXCSRLn register is set For the specific offset for each register see Ta...

Page 1388: ...bed in Table 18 54 Figure 18 51 USB Host Transmit Configure Type Endpoint n Register USBTXTYPE n 7 6 5 4 3 0 SPEED PROTO TEP R W 0 R W 0 R W 0 LEGEND R W Read Write n value after reset Table 18 54 USB...

Page 1389: ...mbers Transfer Type Speed Valid Values m Interpretation Interrupt Low speed or Full speed 0x01 0xFF The polling interval is m frames Isochronous Full speed 0x01 0x10 The polling interval is 2 m 1 fram...

Page 1390: ...bed in Table 18 57 Figure 18 53 USB Host Configure Receive Type Endpoint n Register USBRXTYPE n 7 6 5 4 3 0 SPEED PROTO TEP R W 0 R W 0 R W 0 LEGEND R W Read Write n value after reset Table 18 57 USB...

Page 1391: ...mbers Transfer Type Speed Valid Values m Interpretation Interrupt Low speed or Full speed 0x01 0xFF The polling interval is m frames Isochronous Full speed 0x01 0x10 The polling interval is 2 m 1 fram...

Page 1392: ...n about IN transactions as a host see Section 18 2 2 2 Note Multiple packets combined into a single bulk packet within the FIFO count as one packet For the specific offset for each register see Table...

Page 1393: ...egister USBRXDPKTBUFDIS Field Descriptions Bit Field Value Description 15 EP15 EP15 RX Double Packet Buffer Disable 0 Disables double packet buffering 1 Enables double packet buffering 14 EP14 EP14 RX...

Page 1394: ...Packet Buffer Disable 0 Disables double packet buffering 1 Enables double packet buffering 4 EP4 EP4 RX Double Packet Buffer Disable 0 Disables double packet buffering 1 Enables double packet bufferin...

Page 1395: ...e Register USBTXDPKTBUFDIS Field Descriptions Bit Field Value Description 15 EP15 EP15 RX Double Packet Buffer Disable 0 Disables double packet buffering 1 Enables double packet buffering 14 EP14 EP14...

Page 1396: ...Packet Buffer Disable 0 Disables double packet buffering 1 Enables double packet buffering 4 EP4 EP4 RX Double Packet Buffer Disable 0 Disables double packet buffering 1 Enables double packet bufferi...

Page 1397: ...0 Reserved 0 Reserved 9 8 PFLTACT Power Fault Action This bit field specifies how the USB0EPEN signal is changed when detecting a USB power fault 0h Unchanged USB0EPEN is controlled by the combination...

Page 1398: ...own By adding the high impedance state system designers can bias the power supply enable to the disabled state using a large resistor 100 k and later configure and drive the output signal to enable th...

Page 1399: ...external power interface Mode s OTG A or Host OTG B or Device USBEPCRIS is shown in Figure 18 59 and described in Table 18 64 Figure 18 59 USB External Power Control Raw Interrupt Status Register USBE...

Page 1400: ...l power interface Mode s OTG A or Host OTG B or Device USBEPCIM is shown in Figure 18 59 and described in Table 18 64 Figure 18 60 USB External Power Control Interrupt Mask Register USBEPCIM 31 1 0 Re...

Page 1401: ...hown in Figure 18 61 and described in Table 18 66 Figure 18 61 USB External Power Control Interrupt Status and Clear Register USBEPCISC 31 1 0 Reserved PF R 0 R 0 LEGEND R W Read Write R Read only n v...

Page 1402: ...sponding interrupt prior to masking A write has no effect Mode s OTG A or Host OTG B or Device USBDRRIS is shown in Figure 18 62 and described in Table 18 67 Figure 18 62 USB Device RESUME Raw Interru...

Page 1403: ...Mode s OTG A or Host OTG B or Device USBDRIM is shown in Figure 18 63 and described in Table 18 68 Figure 18 63 USB Device RESUME Raw Interrupt Status Register USBDRRIS 31 1 0 Reserved RESUME R 0 R 0...

Page 1404: ...SBDRISC is shown in Figure 18 64 and described in Table 18 69 Figure 18 64 USB Device RESUME Interrupt Status and Clear Register USBDRISC 31 0 Reserved RESUME R 0 R W1C LEGEND R W Read Write R Read on...

Page 1405: ...alue must still be monitored to assure that if the Host removes VBUS the self powered Device disables the D D pull up resistors This function can be accomplished by connecting a standard GPIO to VBUS...

Page 1406: ...level 4 75 V but not below AValid 2 0 V for 65 microseconds without signaling a VBUSERR interrupt in the controller Without this any glitch on VBUS would force the USB Host controller to remove power...

Page 1407: ...5 microseconds Mode s OTG A or Host USBVDCRIS is shown in Figure 18 67 and described in Table 18 72 Figure 18 67 USB VBUS Droop Control Raw Interrupt Status Register USBVDCRIS 31 1 0 Reserved VD R 0 R...

Page 1408: ...p Mode s OTG A or Host USBVDCIM is shown in Figure 18 68 and described in Table 18 73 Figure 18 68 USB VBUS Droop Control Raw Interrupt Status Register USBVDCIM 31 1 0 Reserved VD R 0 R W 0 LEGEND R W...

Page 1409: ...BVDCISC is shown in Figure 18 69 and described in Table 18 74 Figure 18 69 USB VBUS Droop Control Raw Interrupt Status Register USBVDCISC 31 1 0 Reserved VD R 0 R W1 C LEGEND R W Read Write R Read onl...

Page 1410: ...ID value is valid Mode s OTG specific functions USBIDVRIS is shown in Figure 18 70 and described in Table 18 75 Figure 18 70 USB ID Valid Detect Raw Interrupt Status Register USBIDVRIS 31 1 0 Reserved...

Page 1411: ...ection Mode s OTG specific functions USBIDVIM is shown in Figure 18 71 and described in Table 18 76 Figure 18 71 USB ID Valid Detect Interrupt Mask Register USBIDVIM 31 1 0 Reserved ID R 0 R W 0 LEGEN...

Page 1412: ...Figure 18 72 and described in Table 18 77 Figure 18 72 USB ID Valid Detect Interrupt Status and Clear Register USBIDVISC 31 8 0 Reserved ID R 0 R W1 C 0 LEGEND R W Read Write R Read only n value afte...

Page 1413: ...21 20 19 18 17 16 Reserved DMACTX DMACRX R 0 R W 0 R W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMABTX DMABRX DMAATX DMAARX R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset...

Page 1414: ...dpoint 1 RX 2h Endpoint 2 RX 3h Endpoint 3 RX 4h Endpoint 4 RX 5h Endpoint 5 RX 6h Endpoint 6 RX 7h Endpoint 7 RX 8h Endpoint 8 RX 9h Endpoint 9 RX Ah Endpoint 10 RX Bh Endpoint 11 RX Ch Endpoint 12 R...

Page 1415: ...oint 1 RX 2h Endpoint 2 RX 3h Endpoint 3 RX 4h Endpoint 4 RX 5h Endpoint 5 RX 6h Endpoint 6 RX 7h Endpoint 7 RX 8h Endpoint 8 RX 9h Endpoint 9 RX Ah Endpoint 10 RX Bh Endpoint 11 RX Ch Endpoint 12 RX...

Page 1416: ...EL Field Descriptions continued Bit Field Value Description 3 0 DMAARX DMA A RX Select specifies the RX mapping of the first USB endpoint on DMA channel 0 primary assignment 0h Reserved 1h Endpoint 1...

Page 1417: ...3 Ethernet Media Access Controller EMAC The Ethernet Media Access Controller EMAC conforms to IEEE 802 3 specifications and fully supports 10BASE T and 100BASE TX standards Topic Page 19 1 Introductio...

Page 1418: ...CRC error rejection control User configurable interrupts IEEE 1588 Precision Time Protocol Provides highly accurate time stamps for individual packets Efficient transfers using the Micro Direct Memory...

Page 1419: ...scribe the operation of the MAC layer including an overview of the Ethernet frame format the MAC layer FIFOs Ethernet transmission reception options packet timestamps and Ethernet MAC address format 1...

Page 1420: ...destination address source address length type and data including pad fields using the CRC 32 algorithm The Ethernet MAC computes the FCS value one nibble at a time For transmitted frames this field...

Page 1421: ...Options At the MAC layer the transmitter can be configured for both full duplex and half duplex operation by using the DUPLEX bit in the MACTCTL register Note that in 10BASE T half duplex mode the tra...

Page 1422: ...ter Timer A of GPT3 stores the transmit time and Timer B stores the receive time One other General Purpose Timer can be set up as a 16 bit free running timer to synchronize the receiver and transmitte...

Page 1423: ...er mode should be used See the Micro Direct Memory Access DMA chapter for more details about programming the DMA controller 19 4 Initialization and Configuration The following sections describe the ha...

Page 1424: ...ntation PHY registers MR0 MR6 are not located on the microcontroller These registers are located on IEEE 802 3 compliant Ethernet external PHYs These registers are defined for software ease of use See...

Page 1425: ...gister offset 0x000 The MACRIS MACIACK register is the interrupt status and acknowledge register On a read this register gives the current status value of the corresponding interrupt prior to masking...

Page 1426: ...The packet was transmitted and that the TX FIFO is empty This bit is cleared by writing a 1 to it 1 TXER Transmit Error 0 No interrupt 1 An error was encountered on the transmitter The possible error...

Page 1427: ...n 0 The FOV interrupt is suppressed and not sent to the interrupt controller 1 An interrupt is sent to the interrupt controller when the FOV bit in the MACRIS MACIACK register is set 2 TXEMPM Mask Tra...

Page 1428: ...dress 1 Enables Promiscuous mode which accepts all valid frames regardless of the specified Destination Address 1 AMUL Enable Multicast Frames 0 Disables the reception of multicast frames 1 Enables th...

Page 1429: ...ss Controller EMAC Table 19 6 Ethernet MAC Transmit Control MACTCTL Register Field Descriptions continued Bit Field Value Description 1 PADEN Enable packet padding 0 Disables automatic padding 1 Enabl...

Page 1430: ...hieve the indicated length Attempting to write the next frame into the TX FIFO before transmission of the first has completed results in the data being lost Bytes may not be randomly accessed in eithe...

Page 1431: ...Individual Address 0 MACIA0 Register 31 24 23 16 MACOCT4 MACOCT3 R W 0 R W 0 15 8 7 0 MACOCT2 MACOCT1 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 19 9 Ethernet MAC Individ...

Page 1432: ...is compared against the incoming Destination Address fields to determine whether the frame should be received Figure 19 11 Ethernet MAC Individual Address 0 MACIA1 Register 31 16 Reserved R 0 15 8 7 0...

Page 1433: ...itten while a value of 0x02 makes the wait equal to 68 bytes of written data In general early transmission starts when Number of Bytes 4 THRESH x 8 1 Reaching the threshold level has the same effect a...

Page 1434: ...ing the same cycle that the START bit is set Figure 19 13 Ethernet MAC Management Control MACMCTL Register 31 8 7 3 2 1 0 Reserved REGADR Reserved WRITE START R 0 R W 0 R 0 R W 0 R W 0 LEGEND R W Read...

Page 1435: ...ck divider 80h The DIV bits are used to set the clock divider for the MDC clock used to transmit data between the MAC and external PHY layers 19 6 11 Ethernet MAC Management Address Register MACMAR of...

Page 1436: ...19 Texas Instruments Incorporated M3 Ethernet Media Access Controller EMAC Table 19 15 Ethernet MAC Management Transmit Data MACMTXD Register Field Descriptions Bit Field Value Description 31 16 Reser...

Page 1437: ...lds the number of frames that are currently in the RX FIFO When NPR is 0 there are no frames in the RX FIFO and the RXINT bit is clear When NPR is any other value at least one frame is in the RX FIFO...

Page 1438: ...Request MACTR Register Field Descriptions Bit Field Value Description 31 1 Reserved Reserved 0 NEWTX New Transmission 0 The transmission has completed 1 Initiates an Ethernet transmission once the pac...

Page 1439: ...are designed to initialize the Ethernet external PHY to a normal operational mode without configuration Figure 19 21 Ethernet PHY Management Register 0 Control MR0 Register 15 14 13 12 11 10 9 8 RESET...

Page 1440: ...Field Value Description 9 RANEG Restart Auto Negotiation 0 No effect 1 Restarts the auto negotiation process 8 DUPLEX Set Duplex Mode 0 Enables the Half Duplex mode of operation Note that in 10BASE T...

Page 1441: ...Ethernet PHY is not capable of supporting 10BASE T Full Duplex mode 1 The Ethernet PHY is capable of supporting 10BASE T Full Duplex mode 11 10T_H 10BASE T Half Duplex Mode 0 The Ethernet PHY is not...

Page 1442: ...long with the OUI 5 0 field in MR3 makes up the Organizationally Unique Identifier indicating the PHY manufacturer 19 7 4 Ethernet PHY Management Register 3 PHY Identifier 2 MR3 Register address 0x03...

Page 1443: ...ult condition has been encountered 1 Indicates to the link partner that a Remote Fault condition has been encountered 12 9 Reserved Reserved 8 A3 Technology Ability Field 3 0 The Ethernet PHY does not...

Page 1444: ...ld Descriptions Bit Field Value Description 15 NP Next Page 0 The link partner s Ethernet PHY is not capable of Next Page exchanges 1 The link partner s Ethernet PHY is capable of Next Page exchanges...

Page 1445: ...PANEGA R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 19 26 Ethernet PHY Management Register 6 Auto Negotiation Expansion MR6 Register Field Descriptions Bit Field...

Page 1446: ...SPRUHE8E October 2012 Revised November 2019 M3 Synchronous Serial Interface SSI This chapter describes synchronous serial interface SSI modules Refer to the device datasheet for the number of instance...

Page 1447: ...bit rate and prescaler Separate transmit and receive FIFOs each 16 bits wide and 8 locations deep Programmable data frame size from 4 to 16 bits Internal loopback test mode for diagnostic debug testin...

Page 1448: ...nversion on data received from a peripheral device The CPU accesses data control and status information The transmit and receive paths are buffered with internal FIFO memories allowing up to eight 16...

Page 1449: ...DR register and data is stored in the FIFO until it is read out by the transmission logic When configured as a master or a slave parallel data is written into the transmit FIFO prior to serial convers...

Page 1450: ...e to turn off the SSI module clock or enter sleep mode In addition because transmitted data and received data complete at exactly the same time the interrupt can also indicate that read data is ready...

Page 1451: ...f the Freescale SPI format is that the inactive state and phase of the SSIClk signal are programmable through the SPO and SPH bits in the SSICR0 control register 20 3 4 1 1 SPO Clock Polarity Bit When...

Page 1452: ...ister and does not allow it to be altered if the SPH bit is clear Therefore the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral d...

Page 1453: ...ed onto the SSIRx line of the master The master SSITx output pad is enabled One half period later valid master data is transferred to the SSITx line Once both the master and slave data have been set t...

Page 1454: ...MACTL register When DMA operation is enabled the SSI asserts a DMA request on the receive or transmit channel when the associated FIFO can transfer data For the receive channel a single transfer reque...

Page 1455: ...clock prescale divisor by writing the SSICPSR register 4 Write the SSICR0 register with the following configuration Serial clock rate SCR Desired clock phase polarity if using Freescale SPI mode SPH a...

Page 1456: ...t 2012 2019 Texas Instruments Incorporated M3 Synchronous Serial Interface SSI 20 5 SSI Registers This section describes the Synchronous Serial Interface registers 20 5 1 SSI Base Addresses Table 20 1...

Page 1457: ...perties Go FC4h SSIPC SSI Peripheral Configuration Go FD0h SSIPeriphID4 SSI Peripheral Identification 4 Go FD4h SSIPeriphID5 SSI Peripheral Identification 5 Go FD8h SSIPeriphID6 SSI Peripheral Identif...

Page 1458: ...inued Access Type Code Description i j k l m n When these variables are used in a register name an offset or an address they refer to the value of a register array where the register is part of a grou...

Page 1459: ...2 254 programmed in the SSICPSR register and SCR is a value from 0 255 Reset type PER RESET 7 SPH R W 0h SSI Serial clock PHase This bit is only applicable to the Freescale SPI Format The control bit...

Page 1460: ...SSI Table 20 4 SSICR0 Register Field Descriptions continued Bit Field Type Reset Description 3 0 DSS R W 0h SSI Data Size Select Value Data Size 0x0 0x2 Reserved 0x3 4 bit data 0x4 5 bit data 0x5 6 b...

Page 1461: ...W 0h High Speed Clock Enable High speed clock enable is available only when operating as a master Value Description 0 Use Input Clock 1 Use High Speed Clock Note For proper functionality of high spee...

Page 1462: ...W 0h SSI Synchronous Serial Port Enable Value Description 0 SSI operation is disabled 1 SSI operation is enabled This bit must be cleared before any control registers are reprogrammed The bit HSCLKEN...

Page 1463: ...27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DATA R 0h R W 0h Table 20 6 SSIDR Register Field Descriptions Bit Field Type Reset Description 31 16 RESERVED R 0h Re...

Page 1464: ...eld Type Reset Description 31 5 RESERVED R 0h Reserved 4 BSY R 0h SSI Busy Bit Value Description 0 The SSI is idle 1 The SSI is currently transmitting and or receiving a frame or the transmit FIFO is...

Page 1465: ...20 8 Return to the Summary Table SSI Clock Prescale Figure 20 14 SSICPSR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED CPSDVSR R 0h R W 0h Ta...

Page 1466: ...type PER RESET 5 DMATXIM R W 0h SSI Transmit DMA Interrupt Mask Value Description 0 The transmit DMA interrupt is masked 1 The transmit DMA interrupt is not masked Reset type PER RESET 4 DMARXIM R W...

Page 1467: ...ICR register Reset type PER RESET 5 DMATXRIS R 0h SSI Transmit DMA Raw Interrupt Status Value Description 0 No interrupt 1 The transmit DMA has completed This bit is cleared when a 1 is written to the...

Page 1468: ...TRIS R 0h SSI Receive Time Out Raw Interrupt Status Value Description 0 No interrupt 1 The receive time out has occurred This bit is cleared when a 1 is written to the RTIC bit in the SSI Interrupt Cl...

Page 1469: ...it in the SSI Interrupt Clear SSIICR register Reset type PER RESET 5 DMATXMIS R 0h SSI Transmit DMA Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked 1 An unmasked...

Page 1470: ...cleared when the receive FIFO is less than half full Reset type PER RESET 1 RTMIS R 0h SSI Receive Time Out Masked Interrupt Status Value Description 0 An interrupt has not occurred or is masked 1 An...

Page 1471: ...h End of Transmit Interrupt Clear Writing a 1 to this bit clears the EOTRIS bit in the SSIRIS register and the EOTMIS bit in the SSIMIS register Reset type PER RESET 5 DMATXIC R 0 W1S 0h SSI Transmit...

Page 1472: ...29 28 27 26 25 24 RESERVED R 0h 23 22 21 20 19 18 17 16 RESERVED R 0h 15 14 13 12 11 10 9 8 RESERVED R 0h 7 6 5 4 3 2 1 0 RESERVED TXDMAE RXDMAE R 0h R W 0h R W 0h Table 20 13 SSIDMACTL Register Fiel...

Page 1473: ...SIPV Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED MAJOR MINOR R 0h R 4h R 0h Table 20 14 SSIPV Register Field Descriptions Bit Field Type Res...

Page 1474: ...11 10 9 8 RESERVED R 0h 7 6 5 4 3 2 1 0 RESERVED FSSHLDFRM MODE HSCLK R 0h R 1h R 0h R 1h Table 20 15 SSIPP Register Field Descriptions Bit Field Type Reset Description 31 5 RESERVED R 0h Reserved 3 F...

Page 1475: ...5 2 13 SSIPC Register Offset FC4h reset 0h SSIPC is shown in Figure 20 22 and described in Table 20 16 Return to the Summary Table SSI Peripheral Configuration Figure 20 22 SSIPC Register 31 30 29 28...

Page 1476: ...and described in Table 20 17 Return to the Summary Table SSI Peripheral Identification 4 Figure 20 23 SSIPeriphID4 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5...

Page 1477: ...and described in Table 20 18 Return to the Summary Table SSI Peripheral Identification 5 Figure 20 24 SSIPeriphID5 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5...

Page 1478: ...nd described in Table 20 19 Return to the Summary Table SSI Peripheral Identification 6 Figure 20 25 SSIPeriphID6 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4...

Page 1479: ...nd described in Table 20 20 Return to the Summary Table SSI Peripheral Identification 7 Figure 20 26 SSIPeriphID7 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4...

Page 1480: ...and described in Table 20 21 Return to the Summary Table SSI Peripheral Identification 0 Figure 20 27 SSIPeriphID0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5...

Page 1481: ...and described in Table 20 22 Return to the Summary Table SSI Peripheral Identification 1 Figure 20 28 SSIPeriphID1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5...

Page 1482: ...nd described in Table 20 23 Return to the Summary Table SSI Peripheral Identification 2 Figure 20 29 SSIPeriphID2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4...

Page 1483: ...nd described in Table 20 24 Return to the Summary Table SSI Peripheral Identification 3 Figure 20 30 SSIPeriphID3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4...

Page 1484: ...and described in Table 20 25 Return to the Summary Table SSI PrimeCell Identification 0 Figure 20 31 SSIPCellID0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4...

Page 1485: ...and described in Table 20 26 Return to the Summary Table SSI PrimeCell Identification 1 Figure 20 32 SSIPCellID1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4...

Page 1486: ...and described in Table 20 27 Return to the Summary Table SSI PrimeCell Identification 2 Figure 20 33 SSIPCellID2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4...

Page 1487: ...and described in Table 20 28 Return to the Summary Table SSI PrimeCell Identification 3 Figure 20 34 SSIPCellID3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4...

Page 1488: ...ed November 2019 M3 Universal Asynchronous Receivers Transmitters UARTs This chapter discusses the features and functions of the Universal Asynchronous Receiver Transmitter UART module Topic Page 21 1...

Page 1489: ...e characteristics 5 6 7 or 8 data bits Even odd stick or no parity bit generation detection 1 or 2 stop bit generation IrDA serial IR SIR encoder decoder providing Programmable use of IrDA Serial Infr...

Page 1490: ...and serial to parallel conversions It is similar in functionality to a 16C550 UART but is not register compatible The UART is configured for transmit and or receive via the TXE and RXE bits of the UAR...

Page 1491: ...or multiplying it by 64 and adding 0 5 to account for rounding errors UARTFBRD DIVFRAC integer BRDF 64 0 5 The UART generates an internal baud rate reference clock at 8x or 16x the baud rate referred...

Page 1492: ...he SIR block uses the UnTx and UnRx pins for the SIR protocol These signals should be connected to an infrared transceiver to implement an IrDA SIR physical layer link The SIR block can receive and tr...

Page 1493: ...affected data Note that the UART does not support automatic retransmission in this case 21 3 6 LIN Support The UART module offers hardware support for the LIN protocol as either a master or a slave Th...

Page 1494: ...s empty full and overrun conditions The UARTFR register contains empty and full flags TXFE TXFF RXFE and RXFF bits and the UARTRSR register shows overrun status via the OE bit The trigger points at wh...

Page 1495: ...enever there is at least one empty location in the transmit FIFO The burst request is asserted whenever the transmit FIFO contains fewer characters than the FIFO trigger level The single and burst DMA...

Page 1496: ...must be enabled by setting the UART0 UART1 or UART2 bits in the RCGC1 register see the System Control and Interrupts chapter The clock to the appropriate GPIO module must be enabled via the RCGC2 reg...

Page 1497: ...UARTCTL register Write the integer portion of the BRD to the UARTIBRD register Write the fractional portion of the BRD to the UARTFBRD register Write the desired serial parameters to the UARTLCRH reg...

Page 1498: ...0000 UART Peripheral Identification 6 0xFDC UARTPeriphID7 RO 0x0000 0000 UART Peripheral Identification 7 0xFE0 UARTPeriphID0 RO 0x0000 0060 UART Peripheral Identification 0 0xFE4 UARTPeriphID1 RO 0x...

Page 1499: ...word transmission time defined as start data parity and stop bits 9 PE UART Parity Error In FIFO mode this error is associated with the character at the top of the FIFO 0 No parity error has occurred...

Page 1500: ...FO was full resulting in data loss 2 BE UART Break Error This bit is cleared to 0 by a write to UARTECR In FIFO mode this error is associated with the character at the top of the FIFO When a break occ...

Page 1501: ...Flag Register UARTFR Field Descriptions Bit Field Value Description 31 8 Reserved Reserved 7 TXFE UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH r...

Page 1502: ...rs UARTs Table 21 5 UART Flag Register UARTFR Field Descriptions continued Bit Field Value Description 3 BUSY UART Busy This bit is set as soon as the transmit FIFO becomes non empty regardless of whe...

Page 1503: ...cepted as valid pulses NOTE Zero is an illegal value Programming a zero value results in no IrLPBaud16 pulses being generated Figure 21 11 UART IrDA Low Power Register UARTILPR 31 8 7 0 Reseved ILPDVS...

Page 1504: ...egister is the line control register Serial parameters such as data length parity and stop bit selection are implemented in this register When updating the baud rate divisor UARTIBRD and or UARTIFRD t...

Page 1505: ...signal after completing transmission of the current character For the proper execution of the break command software must set this bit for at least two frames character periods 21 7 8 UART Control Reg...

Page 1506: ...TRIS register 0 The TXRIS bit is set when the transmit FIFO condition specified in UARTIFLS is met 1 The TXRIS bit is set only after all transmitted data including stop bits have cleared the serialize...

Page 1507: ...FIFOs trigger an interrupt at the half way mark Figure 21 16 UART Interrupt FIFO Level Select UARTIFLS Register 31 16 Reserved R 0 15 6 5 3 2 0 Reserved RXIFLSEL TXIFLSEL R 0 R W 2 R W 2 LEGEND R W Re...

Page 1508: ...LME1RIS interrupt is suppressed and not sent to the interrupt controller 1 An interrupt is sent to the interrupt controller when the LME1RIS bit in the UARTRIS register is set 13 LMSBIM LIN Mode Sync...

Page 1509: ...ontinued Bit Field Value Description 5 TXIM UART Transmit Interrupt Mask 0 The TXRIS interrupt is suppressed and not sent to the interrupt controller 1 An interrupt is sent to the interrupt controller...

Page 1510: ...the UARTICR register 0 No interrupt 1 The timer value at the 5th falling edge of the LIN Sync Field has been captured 14 LME1RIS LIN Mode Edge 1 Raw Interrupt Status This bit is cleared by writing a...

Page 1511: ...No interrupt 1 A receive time out has occurred 5 TXRIS UART Transmit Raw Interrupt Status This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register 0 No interrupt 1 If the EOT bit in...

Page 1512: ...s This bit is cleared by writing a 1 to the LME1IC bit in the UARTICR register 0 An interrupt has not occurred or is masked 1 An unmasked interrupt was signaled due to the 1st falling edge of the LIN...

Page 1513: ...sked 1 An unmasked interrupt was signaled due to a receive time out 5 TXMIS UART Transmit Masked Interrupt Status This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register 0 An interr...

Page 1514: ...bit clears the LME1RIS bit in the UARTRIS register and the LME1MIS bit in the UARTMIS register 13 LMSBMIC LIN Mode Sync Break Interrupt Clear Writing a 1 to this bit clears the LMSBRIS bit in the UART...

Page 1515: ...hen a receive error occurs 1 TXDMAE Transmit DMA Enable 0 DMA for the transmit FIFO is disabled 1 DMA for the transmit FIFO is enabled 0 RXDMAE Receive DMA Enable 0 DMA for the receive FIFO is disable...

Page 1516: ...6 Reserved Reserved 15 0 TSS Timer Snap Shot This field contains the value of the free running timer when either the Sync Edge 5 or the Sync Edge 1 was detected 21 7 17 UART LIN Timer UARTLTIM offset...

Page 1517: ...phIDn registers are hard coded and the fields within the registers determine the reset values Figure 21 26 UART Peripheral Identification 5 UARTPeriphID5 Register 31 8 7 0 Reserved PID5 R 0 R 0 LEGEND...

Page 1518: ...iphIDn registers are hard coded and the fields within the registers determine the reset values Figure 21 29 UART Peripheral Identification 0 UARTPeriphID0 Register 31 8 7 0 Reserved PID0 R 0 R 0x60 LE...

Page 1519: ...PeriphIDn registers are hard coded and the fields within the registers determine the reset values Figure 21 32 UART Peripheral Identification 3 UARTPeriphID3 Register 31 8 7 0 Reserved PID3 R 0 R 0x01...

Page 1520: ...llIDn registers are hard coded and the fields within the registers determine the reset values Figure 21 35 UART PrimeCell Identification 2 UARTPCellID2 Register 31 8 7 0 Reserved CID2 R 0 R 0x05 LEGEN...

Page 1521: ...2012 Revised November 2019 M3 Inter Integrated Circuit I2C Interface This chapter describes the features and operation of the M3 inter integrated circuit I2C module Topic Page 22 1 Introduction 1522 2...

Page 1522: ...The two I2C modules include the following features Devices on the I2C bus can be designated as either a master or a slave Supports both transmitting and receiving data as either a master or a slave Su...

Page 1523: ...bit determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition To generate a single transmit cycle the I2C Master Slave Address I2CMSA register is written...

Page 1524: ...ing the acknowledge cycle must comply with the data validity requirements described in Section 22 3 1 3 When a slave receiver does not acknowledge the slave address SDA must be left High by the slave...

Page 1525: ...e I2C clock rate is determined by the parameters CLK_PRD TIMER_PRD SCL_LP and SCL_HP where CLK_PRD is the system clock period SCL_LP is the low phase of SCL fixed at 6 SCL_HP is the high phase of SCL...

Page 1526: ...an interrupt condition is met software must check the ERROR and ARBLST bits in the I2C Master Control Status I2CMCS register to verify that an error didn t occur during the last transaction and to en...

Page 1527: ...er 22 3 4 Loopback Operation The I2C modules can be placed into an internal loopback mode for diagnostic or debug work by setting the LPBK bit in the I2C Master Configuration I2CMCR register In loopba...

Page 1528: ...USY bit 0 ERROR bit 0 YES Error Service Idle YES NO NO Write Slave Address and Transmit Bit to I2CMSA Functional Description www ti com 1528 SPRUHE8E October 2012 Revised November 2019 Submit Document...

Page 1529: ...YES Error Service Idle NO NO Read data from I2CMDR YES Write Slave Address and Receive Bit to I2CMSA www ti com Functional Description 1529 SPRUHE8E October 2012 Revised November 2019 Submit Document...

Page 1530: ...o I2CMCS YES Read I2CMCS BUSY bit 0 ERROR bit 0 YES NO Idle YES Error Service NO NO NO NO Sequence may be omitted in a Single Master system Write Slave Address and Transmit Bit to I2CMSA Functional De...

Page 1531: ...R Error Service ERROR bit 0 YES Write 1001 to I2CMCS Read I2CMCS BUSY bit 0 NO YES Sequence may be omitted in a Single Master system NO NO NO Write Slave Address and Receive Bit to I2CMSA www ti com F...

Page 1532: ...1 to I2CMCS Master operates in Master Receive mode Idle Repeated START condition is generated with changing data direction Write Slave Address and Receive Bit to I2CMSA Functional Description www ti c...

Page 1533: ...so valid www ti com Functional Description 1533 SPRUHE8E October 2012 Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated M3 Inter Integrated Circuit...

Page 1534: ...iod The TPR value is determined by the following equation TPR System Clock 2 SCL_LP SCL_HP SCL_CLK 1 TPR 20MHz 2 6 4 100000 1 TPR 9 8 Specify the slave address of the master and that the next operatio...

Page 1535: ...slave base address Table 22 2 Inter Integrated Circuit I2C Interface Register Map Offset Name Type Reset Description I2C Master 0x000 I2CMSA R W 0x0000 0000 I2C Master Slave Address 0x004 I2CMCS R W...

Page 1536: ...ight bits seven address bits A6 A0 and a receive send bit which determines if the next operation is a receive high or transmit low It is shown and described below Figure 22 14 I2C Master Slave Address...

Page 1537: ...0 Reserved BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 22 4 I2C Master Control Status I2CMCS Read Only Regi...

Page 1538: ...ing in Table 22 6 1 START Generate START 0 The controller does not generate the START condition 1 The controller generates the START or repeated START condition See field decoding in Table 22 6 0 RUN...

Page 1539: ...state X X 1 0 1 TRANSMIT followed by STOP condition master goes to Idle state 0 X 0 1 1 Repeated START condition followed by a TRANSMIT master remains in Master Transmit state 0 X 1 1 1 Repeated START...

Page 1540: ...aster Receive state X X 1 0 0 STOP condition master goes to Idle state 2 X 0 1 0 1 RECEIVE followed by STOP condition master goes to Idle state X 1 0 0 1 RECEIVE operation master remains in Master Rec...

Page 1541: ...ield Value Description 31 8 Reserved Reserved 7 0 DATA 00h Data Transferred Data transferred during transaction 22 6 4 I2C Master Timer Period I2CMTPR offset 0x00C Th I2C master timer period I2CMTPR r...

Page 1542: ...ription 31 1 Reserved Reserved 0 IM Interrupt Mask 0 The RIS interrupt is suppressed and not sent to the interrupt controller 1 The master interrupt is sent to the interrupt controller when the RIS bi...

Page 1543: ...ption 31 1 Reserved Reserved 0 MIS Masked Interrupt Status This bit is cleared by writing a 1 to the IC bit in the I2CMICR register 0 An interrupt has not occurred or is masked 1 An unmasked master in...

Page 1544: ...table below Figure 22 23 I2C Master Configuration I2CMCR Register 31 16 Reserved R 0 15 6 5 4 3 1 0 Reserved SFE MFE Reserved LPBK R 0 R W 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value a...

Page 1545: ...r when read The first register and description in this section is Read Only The second register and description in this section is Write Only This register is Read Only Figure 22 25 I2C Slave Control...

Page 1546: ...2 27 I2C Slave Data I2CSDR Register 31 8 7 0 Reserved DATA R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 17 I2C Slave Data I2CSDR Register Field Descriptions Bit Field Value...

Page 1547: ...ve Raw Interrupt Status I2CSRIS Register 31 3 2 1 0 Reserved STOPRIS STARTRIS DATARIS R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 22 19 I2C Slave Raw Interrupt Status I...

Page 1548: ...data received or data requested interrupt was signaled is pending 22 7 7 I2C Slave Interrupt Clear I2CSICR offset 0x818 The I2C Slave Interrupt Clear I2CSICR register clears the raw interrupt A read o...

Page 1549: ...e control with a high level of reliability The CAN module supports bit rates up to 1 Mbit s and is compliant with the CAN 2 0B protocol specification Topic Page 23 1 Overview 1550 23 2 Operating Modes...

Page 1550: ...pt lines Globsl power down and wakeup support 23 1 2 Functional Description The CAN module performs CAN protocol communication according to ISO 11898 1 identical to Bosch CAN protocol specification 2...

Page 1551: ...N Protocol Controller and the Rx Tx Shift register It handles all ISO 11898 1 protocol functions 23 1 3 2 Message Handler The message handler is a state machine which controls the data transfer betwee...

Page 1552: ...ge transfer is started It is possible to change the configuration of message objects during normal operation by the CPU After setup and subsequent transfer of the message object from interface registe...

Page 1553: ...uence can be delayed by a user defined number of clock cycles which can be defined in Section 23 15 8 NOTE If the CAN module goes Bus Off due to massive occurrence of CAN bus errors it stops all bus a...

Page 1554: ...Section 23 15 6 23 2 3 1 Silent Mode The silent mode may be used to analyze the traffic on the CAN bus without affecting it by sending dominant bits for example acknowledge bit overload flag active er...

Page 1555: ...onnection of signals CAN_TX and CAN_RX to the CAN core in loopback mode Loopback mode can be activated by setting the LBACK bit in the CAN_TEST register to one NOTE In loopback mode the signal path fr...

Page 1556: ...Mode It is also possible to combine loopback mode and silent mode by setting the LBack bit and Silent bit at the same time This mode can be used for a Hot Selftest that is the CAN hardware can be test...

Page 1557: ...access of the CPU will never generate or reset an interrupt Values between 1 and the number of the last message object indicates that the source of the interrupt is one of the message objects INT0ID...

Page 1558: ...application to wakeup the CAN For this the application needs to clear the Init bit in CAN Control register After the Init bit has been cleared the CAN module waits until it detects 11 consecutive rece...

Page 1559: ...to data area and no check will be done on read access If parity checking is enabled parity bits will be automatically generated and checked by the CAN A parity bit will be set if the modulo 2 sum of t...

Page 1560: ...ceived messages which pass the acceptance filtering are stored into the Message RAM messages with pending transmission request are loaded into the CAN Core s Shift register and are transmitted via the...

Page 1561: ...k 1 to allow groups of data frames with similar identifiers to be accepted The Dir bit should not be masked in typical applications If some bits of the Mask bits are set to don t care the correspondin...

Page 1562: ...d message objects The application has to update the data of the messages to be transmitted and to enable and request their transmission The transmission is requested automatically when a matching remo...

Page 1563: ...ge will be retransmitted as soon as the CAN bus is free again If meanwhile the transmission of a message with higher priority has been requested the messages will be transmitted in the order of their...

Page 1564: ...with the arbitration bits from the shift register This is repeated for all following message objects until a matching message object is found or until the end of the Message RAM is reached If a match...

Page 1565: ...the transmission of the matching data frame If the matching data frame is received before the remote frame could be transmitted the TxRqst bit is automatically reset Setting the TxRqst bit without cha...

Page 1566: ...Revised November 2019 Submit Documentation Feedback Copyright 2012 2019 Texas Instruments Incorporated M3 Controller Area Network CAN NOTE All message objects of a FIFO buffer needs to be read and cle...

Page 1567: ...AN nodes simultaneously try to transmit a frame a misplaced sample point may cause one of the transmitters to become error passive The analysis of such sporadic errors requires a detailed knowledge of...

Page 1568: ...or s tolerance range have to be considered 23 12 1 1 Synchronization Segment The Synchronization Segment Sync_Seg is the part of the bit time where edges of the CAN bus level are expected to occur If...

Page 1569: ...ation The phase buffer segments Phase_Seg1 and Phase_Seg2 and the synchronization jump width SJW are used to compensate for the oscillator tolerance The phase buffer segments surround the sample point...

Page 1570: ...t takes the lead in the transmission of the dominant acknowledge bit Synchronizations after the end of the arbitration will be caused by oscillator tolerance when the differences in the oscillator s c...

Page 1571: ...se spikes are filtered by synchronizations In both examples the spike starts at the end of Prop_Seg and has the length of Prop_Seg Phase_Seg1 In the first example the synchronization jump width is gre...

Page 1572: ...and Phase_Seg1 as TSEG1 is combined with Phase_Seg2 as TSEG2 in one byte SJW and BRP plus BRPE in third byte are combined in the other byte see Figure 23 15 Figure 23 15 Structure of the CAN Core s C...

Page 1573: ...aximum bus length as well as a maximum node delay has to be defined for expandible CAN bus systems The resulting time for Prop_Seg is converted into time quanta rounded up to the nearest integer multi...

Page 1574: ...1 1 3 8 1 4 1 1 2 1 1 6 so the Bit Timing register is programmed to 0x00000700 23 12 2 3 Example for Bit Timing at low Baudrate In this example the frequency of CAN_CLK is 2 MHz BRP is 1 the bit rate...

Page 1575: ...ansfer This transfer performed in parallel on all selected parts of the message object guarantees the data consistency of the CAN message That being said there is one condition that can cause a write...

Page 1576: ...ality can be programmed for each message object see IF3 Update Enable register Section 23 15 24 All valid message objects in Message RAM which are configured for automatic update will be checked for a...

Page 1577: ...ge Object Message Object UMask Msk 28 0 MXtd MDir EoB unused NewDat MsgLst RxIE TxIE IntPnd RmtEn TxRqst MsgVal ID 28 0 Xtd Dir DLC 3 0 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Table 23...

Page 1578: ...written into the data bytes of this message object by the message handler since the last time when this flag was cleared by the CPU 1 The message handler or the CPU has written new data into the data...

Page 1579: ...ay be overwritten by undefined values 23 14 2 Addressing Message Objects in RAM The starting location of a particular message object in RAM is Message RAM base address message object number 0x20 This...

Page 1580: ...Message RAM Representation in Debug Mode 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 MsgAddr 0x00 Reserved Reserved Parity 4 0 MsgAddr 0x04 MXtd MDir Rsvd Ms...

Page 1581: ...0x12C CAN IF2MCTL IF2 Message Control Register Section 23 15 17 0x130 CAN IF2DATA IF2 Data A Register Section 23 15 18 0x134 CAN IF2DATB IF2 Data B Register Section 23 15 18 0x140 CAN IF3OBS IF3 Obser...

Page 1582: ...nterrupts will assert line CANINT1 to 1 line remains active until pending interrupts are processed 16 InitDbg Internal init state while debug access 0 Not in debug mode or debug mode requested but not...

Page 1583: ...et the Init bit and stop all bus activities When the Init bit is cleared by the application again the module will then wait for 129 occurrences of Bus Idle 129 11 consecutive recessive bits before res...

Page 1584: ...LEC Last Error Code The LEC field indicates the type of the last error on the CAN bus This field will be cleared to 0 when a message has been transferred reception or transmission without error 0 No E...

Page 1585: ...tate of the Transmit Error Counter values from 0 to 255 23 15 4 Bit Timing Register CAN BTR The Bit Timing register CAN BTR is shown and described in the figure and table below Figure 23 22 Bit Timing...

Page 1586: ...e reset value of 0x00002301 configures the CAN for a bit rate of 500kBit s For details see Section 23 12 23 15 5 Interrupt Register CAN INT The Interrupt register CAN INT is shown and described in the...

Page 1587: ...aring the mailbox s IntPnd bit Among the message interrupts the mailbox s interrupt priority decreases with increasing message number 23 15 6 Test Register CAN TEST The Test register CAN TEST is shown...

Page 1588: ...erved R 0 15 11 10 8 7 0 Reserved Word Number Message Number R 0 R U R U LEGEND R Read n value after reset U Undefined Table 23 11 Parity Error Code Register Field Descriptions Bit Field Value Descrip...

Page 1589: ...ess to the CAN Control register while Auto Bus On timer is running the Auto Bus On procedure will be aborted NOTE During Debug mode running Auto Bus On timer will be paused 23 15 9 Transmission Reques...

Page 1590: ...o new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the CPU 1 The message handler or the CPU has written n...

Page 1591: ...by the message handler 23 15 13 Interrupt Multiplexer Registers CAN INTMUX The IntMux flag determine for each message object which of the two interrupt lines CAN0INT or CAN1INT will be asserted when...

Page 1592: ...wing points must be borne in mind while writing to this register 1 Do not write zeros to the whole register 2 Write to the register in a single 32 bit write or write the upper 16 bits before writing t...

Page 1593: ...IF1 or IF2 register set Direction Write The Message Control bits will be transferred from the IF1 or IF2 register set to the message object addressed by Message Number Bits 7 0 If the TxRqst NewDat bi...

Page 1594: ...been finished 14 DMAactive Activation of DMA feature for subsequent internal IF1 and IF2 update 0 DMA request line is independent of IF1 or IF2 activities 1 DMA is requested after completed transfer...

Page 1595: ...together with mask bits Msk 28 18 are considered 30 MDir Mask Message Direction 0 The message direction bit Dir has no effect on the acceptance filtering 1 The message direction bit Dir is used for ac...

Page 1596: ...nsmitted On reception of a data frame with matching identifier that message is stored in this message object 1 Direction transmit On TxRqst the respective message object is transmitted as a data frame...

Page 1597: ...the data portion of this message object 14 MsgLst Message Lost only valid for message objects with direction receive 0 No message lost since the last time when this bit was reset by the CPU 1 The mess...

Page 1598: ...f a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes When the message handler stores a data frame it will write the DLC to the value...

Page 1599: ...If IF3 Update Enable is used and no Observation flag is set the corresponding message objects will be copied to IF3 without activating the DMA request line and without waiting for DMA read accesses A...

Page 1600: ...fect on the acceptance filtering 1 The extended identifier bit IDE is used for acceptance filtering Note When 11 bit standard identifiers are used for a message object the identifiers of received data...

Page 1601: ...f RmtEn one 28 0 ID 28 0 Message Identifier ID 28 0 29 bit Identifier Extended Frame ID 28 1 8 11 bit Identifier Standard Frame 23 15 22 IF3 Message Control Register CAN IF3MCTL The IF3 Message Contro...

Page 1602: ...bject is not waiting for a transmission 1 The transmission of this message object is requested and is not yet done 7 EoB End of Block 0 The message object is part of a FIFO Buffer block and is not the...

Page 1603: ...g is set This means that an active NewDat flag of this message object e g due to reception of a CAN frame will trigger an automatic copy of the whole message object to IF3 register set NOTE IF3 Update...

Page 1604: ...rocessor including the programming model the memory model the exception model fault handling and power management For technical details on the instruction set see the Cortex M3 Instruction Set Technic...

Page 1605: ...this core to bring high performance 32 bit computing to cost sensitive embedded microcontroller applications such as factory automation and control industrial control power devices building and home...

Page 1606: ...emory protection unit MPU that provides fine grain memory control enabling applications to implement security privilege levels and separate code data and stack on a task by task basis 24 3 2 System Co...

Page 1607: ...urces In thread mode the CONTROL register controls whether software execution is privileged or unprivileged In handler mode software execution is always privileged Only privileged software can write t...

Page 1608: ...se Register 0 R1 R W Cortex General Purpose Register 1 R2 R W Cortex General Purpose Register 2 R3 R W Cortex General Purpose Register 3 R4 R W Cortex General Purpose Register 4 R5 R W Cortex General...

Page 1609: ...ose Registers 0 12 R0 R12 31 0 DATA R W LEGEND R W Read Write R Read only n value after reset Table 24 3 Cortex General Purpose Registers 0 12 R0 R12 Field Descriptions Bit Field Value Description 31...

Page 1610: ...ite R Read only n value after reset Table 24 6 Program Counter Register Field Descriptions Bit Field Value Description 31 0 PC Current program address 24 4 4 5 Program Status Register PSR The program...

Page 1611: ...d IPSR EAPSR R W APSR and EPSR Figure 24 7 Program Status Register PSR 31 30 29 28 27 26 25 24 N Z C V Q ICI IT THUMB R W 0 R W 0 R W 0 R W 0 R W 0 R 0 0x0 R 0 1 23 16 Reserved R 0 15 10 9 8 ICI IT Re...

Page 1612: ...set The following can clear the THUMB bit The BLX BX and POP PC instructions Restoration from the stacked xPSR value on an exception return Bit 0 of the vector value on an exception entry Attempting t...

Page 1613: ...sk Register PRIMASK The PRIMASK register prevents activation of all exceptions with programmable priority Reset non maskable interrupt NMI and hard fault are the only exceptions with fixed priority Ex...

Page 1614: ...t prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value Exceptions should be disabled when they might impact the timing of critical tasks This register i...

Page 1615: ...eserved ASP TMPL R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 24 12 Control Register CONTROL Field Descriptions Bit Field Value Description 31 2 Reserved Reserved 0 ASP...

Page 1616: ...in which the accesses complete matches the program order of the instructions providing the order does not affect the behavior of the instruction sequence Normally if correct program execution depends...

Page 1617: ...uctions execute The instruction synchronization barrier ISB instruction ensures that the effect of all completed memory transactions is recognizable by subsequent instructions Memory barrier instructi...

Page 1618: ...is also bit addressable through bit band alias 0x2200 0000 0x23FF FFFF SRAM bit band alias Data accesses to this region are remapped to bit band region A write operation is performed as read modify w...

Page 1619: ...d Mapping 24 6 4 1 Directly Accessing an Alias Region Writing to a word in the alias region updates a single bit in the bit band region Bit 0 of the value written to a word in the alias region determi...

Page 1620: ...ructions LDREXB and STREXB Software must use a load exclusive instruction with the corresponding store exclusive instruction To perform a guaranteed read modify write of a memory location software mus...

Page 1621: ...t source it may take several processor cycles for the NVIC to see the interrupt source de assert Thus if the interrupt clear is done as the last action in an interrupt handler it is possible for the i...

Page 1622: ...te on instruction execution An error on exception return An unaligned address on a word or halfword memory access or division by zero can cause a usage fault when the core is properly configured SVCal...

Page 1623: ...hronous Bus Fault 5 programmable 3 0x0000 0014 Synchronous when precise and asynchronous when imprecise On Concerto devices activated by memory access errors and RAM and flash uncorrectable data error...

Page 1624: ...000 00D0 Timer 3B 53 37 0x0000 00D4 I2C1 54 57 38 41 Reserved 58 42 0x0000 00E8 Ethernet Controller 60 44 0x0000 00F0 USB 61 45 Reserved 62 46 0x0000 00F8 DMA Software 63 47 0x0000 00FC DMA Error 64 6...

Page 1625: ...141 147 125 131 Reserved 148 132 0x0000 0250 GPIO Port R 149 133 0x0000 0254 GPIO Port S 24 7 3 Exception Handlers The processor handles exceptions using Interrupt Service Routines ISRs Interrupts IRQ...

Page 1626: ...ble priorities for all exceptions except Reset Hard fault and NMI If software does not configure any priorities then all exceptions with a configurable priority have a priority of 0 For information ab...

Page 1627: ...t handling a late arriving exception The processor pops the stack and restores the processor state to the state it had before the interrupt occurred See Section 24 7 7 2 for more information Tail Chai...

Page 1628: ...al the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception 24 7 7 2 Exception Return Exception return occurs when the pr...

Page 1629: ...Hard Fault Status HFAULTSTAT VECT Fault escalated to a hard fault Hard fault Hard Fault Status HFAULTSTAT FORCED MPU or default memory mismatch on instruction access Memory management fault Memory Man...

Page 1630: ...enabled If a bus fault occurs during a stack push when entering a bus fault handler the bus fault does not escalate to a hard fault Thus if a corrupted stack causes a fault the fault handler executes...

Page 1631: ...rs the register and continues executing instructions without entering sleep mode If the event register is 1 the processor must not enter sleep mode on execution of a WFE instruction Typically this sit...

Page 1632: ...ADD ADDS Rd Rn Op2 Add N Z C V ADD ADDW Rd Rn imm12 Add N Z C V ADR Rd label Load PC relative address AND ANDS Rd Rn Op2 Logical AND N Z C ASR ASRS Rd Rm Rs n Arithmetic shift right N Z C B label Bra...

Page 1633: ...result MLS Rd Rn Rm Ra Multiply and subtract 32 bit result MOV MOVS Rd Op2 Move N Z C MOV MOVW Rd imm16 Move 16 bit constant N Z C MOVT Rd imm16 Move top MRS Rd spec_reg Move from special register to...

Page 1634: ...Rd Rt Rn Store register exclusive halfword STRH STRHT Rt Rn offset Store register halfword STRSB STRSBT Rt Rn offset Store register signed byte STRSH STRSHT Rt Rn offset Store register signed halfwor...

Page 1635: ...mber 2019 Cortex M3 Peripherals This chapter provides information on the Cortex M3 processor peripherals Topic Page 25 1 Overview 1636 25 2 Functional Description 1636 25 3 Register Map 1643 25 4 Syst...

Page 1636: ...4EF 0xE000 EF00 0xE000 EF03 Nested Vectored Interrupt Controller 0xE000 E008 0xE000 E00F 0xE000 ED00 0xE000 ED3F System Control Block 0xE000 ED90 0xE000 EDB8 Memory Protection Unit 25 2 Functional Des...

Page 1637: ...n external Non maskable interrupt NMI The processor automatically stacks its state on exception entry and unstacks this state on exception exit with no instruction overhead providing low latency excep...

Page 1638: ...uration control and reporting of the system exceptions 25 2 4 Memory Protection Unit MPU NOTE This feature is disabled on these devices The MPU divides the memory map into a number of regions and defi...

Page 1639: ...TTR registers must be updated Each register can be programmed separately or with a multiple word write to program all of these registers You can use the MPUBASEx and MPUATTRx aliases to program up to...

Page 1640: ...ze and Enable An STM instruction can be used to optimize this R1 region number R2 address R3 size attributes in one LDR R0 MPUNUMBER 0xE000ED98 MPU region number register STM R0 R1 R3 Region number ad...

Page 1641: ...ermissions then the MPU generates a permission fault Table 25 3 shows the encodings for the TEX C B and S access permission bits All encodings are shown for completeness however the current implementa...

Page 1642: ...in the MPUATTR register that define the access permissions for privileged and unprivileged software Table 25 5 AP Bit Field Encoding AP Bit Field Privileged Permissions Unprivileged Permissions Descri...

Page 1643: ...ister spaces that are not used are reserved for future or internal use Software should not modify any reserved memory address Table 25 7 Peripherals Register Map Offset Name Type Reset Description 0x0...

Page 1644: ...Priority 0x42C PRI11 R W 0x0000 0000 Interrupt 44 47 Priority 0x430 PRI12 R W 0x0000 0000 Interrupt 48 51 Priority 0x434 PRI13 R W 0x0000 0000 Interrupt 52 55 Priority 0x438 PRI14 R W 0x0000 0000 Int...

Page 1645: ...tem Handler Control and State 0xD28 FAULTSTAT R W1C 0x0000 0000 Configurable Fault Status 0xD2C HFAULTSTAT R W1C 0x0000 0000 Hard Fault Status 0xD34 MMADDR R W Memory Management Fault Address 0xD38 FA...

Page 1646: ...Tick timer has counted to 0 since the last time this bit was read This bit is cleared by a read of the register or if the STCURRENT register is written with any value If read by the debugger using the...

Page 1647: ...Value Register STRELOAD 31 24 23 0 Reserved RELOAD R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 25 9 SysTick Reload Value Register STRELOAD Field Descriptions Bit Field Value...

Page 1648: ...ptions such as interrupts 25 5 1 Interrupt 0 31 Set Enable EN0 Register offset 0x100 The Interrupt 0 31 Set Enable EN0 register enables interrupts and shows which interrupts are enabled Bit 0 correspo...

Page 1649: ...g the corresponding INT n bit in the DIS1 register 25 5 3 Interrupt 64 95 Set Enable 2 EN2 offset 0x108 The Interrupt 64 95 Set Enable EN2 register enables interrupts and shows which interrupts are en...

Page 1650: ...T n bit in the DIS3 register 25 5 5 Interrupt 128 133 Set Enable 4 EN4 offset 0x110 The Interrupt 128 133 Set Enable EN4 register enables interrupts and shows which interrupts are enabled Bit 0 corres...

Page 1651: ...indicates the interrupt is disabled On a write no effect 1 On a read indicates the interrupt is enabled On a write clears the corresponding INT n bit in the EN0 register disabling interrupt n 25 5 7...

Page 1652: ...95 See the Cortex M3 Processor chapter for interrupt assignments Note This register can only be accessed from privileged mode Figure 25 12 Interrupt 64 95 Clear Enable DIS2 Register 31 0 INT R W 0 LE...

Page 1653: ...127 See the Cortex M3 Processor chapter for interrupt assignments Note This register can only be accessed from privileged mode Figure 25 13 Interrupt 96 127 Clear Enable DIS3 Register 31 0 INT R W 0...

Page 1654: ...rupt is enabled On a write clears the corresponding INT n bit in the EN2 register disabling interrupt n 25 5 11 Interrupt 0 31 Set Pending PEND0 Register offset 0x200 The Interrupt 0 31 Set Pending PE...

Page 1655: ...r 25 5 13 Interrupt 64 95 Set Pending PEND2 Register offset 0x208 The Interrupt 64 95 Set Pending PEND2 register forces interrupts into the pending state and shows which interrupts are pending Bit 0 c...

Page 1656: ...133 Set Pending PEND4 Register offset 0x210 The Interrupt 128 133 Set Pending PEND4 register forces interrupts into the pending state and shows which interrupts are pending Bit 0 corresponds to Interr...

Page 1657: ...is pending On a write clears the corresponding INT n bit in the PEND0 register so that interrupt n is no longer pending Setting a bit does not affect the active state of the corresponding interrupt 25...

Page 1658: ...sor chapter for interrupt assignments Note This register can only be accessed from privileged mode Figure 25 22 Interrupt 64 95 Clear Pending UNPEND2 Register 31 0 INT R W 0 LEGEND R W Read Write R Re...

Page 1659: ...ssor chapter for interrupt assignments Note This register can only be accessed from privileged mode Figure 25 23 Interrupt 96 127 Clear Pending UNPEND3 Register 31 0 INT R W 0 LEGEND R W Read Write R...

Page 1660: ...ar Pending 0 On a read indicates that the interrupt is not pending On a write no effect 1 On a read indicates that the interrupt is pending On a write clears the corresponding INT n bit in the PEND2 r...

Page 1661: ...nterrupt 64 95 Active Bit ACTIVE2 Register offset 0x308 The Interrupt 64 95 Active Bit ACTIVE2 register indicates which interrupts are active Bit 0 corresponds to Interrupt 64 bit 31 corresponds to In...

Page 1662: ...e Bit ACTIVE4 Register offset 0x310 The Interrupt 128 133 Active Bit ACTIVE4 register indicates which interrupts are active Bit 0 corresponds to Interrupt 128 bit 5 corresponds to Interrupt 133 See th...

Page 1663: ...Field Value Description 31 29 INTD Interrupt Priority for Interrupt 4n 3 This field holds a priority value 0 7 for the interrupt with the number 4n 3 where n is the number of the Interrupt Priority r...

Page 1664: ...he SWTRIG register Note Only privileged software can enable unprivileged access to the SWTRIG register Figure 25 31 Software Trigger Interrupt SWTRIG Register 31 6 5 0 Reserved INTID R 0 W0 LEGEND R W...

Page 1665: ...3 2 1 0 Reserved DISFOLD DISWBUF DISMCYC R 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 25 38 Auxiliary Control ACTLR Register Field Descriptions Bit Field Value Des...

Page 1666: ...d from privileged mode Figure 25 33 CPU ID Base CPUID Register 31 24 23 20 19 16 IMP VAR CON R 0 R 0 R 0 15 4 3 0 PARTNO REV R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 25 39 C...

Page 1667: ...rite R Read only n value after reset Table 25 40 Interrupt Control and State INTCTRL Register Field Descriptions Bit Field Value Description 31 NMISET NMI Set Pending 0 On a read indicates an NMI exce...

Page 1668: ...status for all interrupts excluding NMI and Faults 21 19 Reserved Reserved 18 12 VECPEND Interrupt Pending Vector Number This field contains the exception number of the highest priority pending enable...

Page 1669: ...Pending Vector Number This field contains the active exception number The exception numbers can be found in the description for the VECPEND field If this field is clear the processor is in Thread mod...

Page 1670: ...gure 25 35 Vector Table Offset VTABLE Register 31 30 29 28 16 Reserved BASE OFFSET R 0 R W 0 15 9 8 0 OFFSET Reserved R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 25 41 Vector...

Page 1671: ...ld bit Table 25 42 Interrupt Priority Levels PRIGROUP Bit Field Binary Point 1 Group Priority Field Subpriority Field Group Priorities Subpriorities 0x0 0x4 bxxx 7 5 None 8 1 0x5 bxx y 7 6 5 4 2 0x6 b...

Page 1672: ...opyright 2012 2019 Texas Instruments Incorporated Cortex M3 Peripherals Table 25 43 Application Interrupt and Reset Control APINT Register Field Descriptions continued Bit Field Value Description 0 VE...

Page 1673: ...Wake Up on Pending When an event or interrupt enters the pending state the event signal wakes up the processor from WFE If the processor is not waiting for an event the event is registered and affect...

Page 1674: ...t in NMI and Fault This bit enables handlers with priority 1 or 2 to ignore data bus faults caused by load and store instructions The setting of this bit applies to the hard fault NMI and FAULTMASK es...

Page 1675: ...EM Reserved R W 0 R 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 25 46 System Handler Priority 1 SYSPRI1 Register Field Descriptions Bit Field Value Description 31 24 Reserv...

Page 1676: ...0xD20 The System Handler Priority 3 SYSPRI3 register configures the priority level 0 to 7 of the SysTick exception and PendSV handlers This register is byte accessible Note This register can only be...

Page 1677: ...ed content can cause the processor to generate a fault exception Ensure software that writes to this register retains and subsequently restores the current active status If the value of a bit in this...

Page 1678: ...ding status of the usage fault exception 11 TICK SysTick Exception Active 0 A SysTick exception is not active 1 A SysTick exception is active This bit can be modified to change the active status of th...

Page 1679: ...Peripherals Table 25 49 System Handler Control and State SYSHNDCTRL Register Field Descriptions continued Bit Field Value Description 0 MEMA Memory Management Fault Active 0 Memory management fault i...

Page 1680: ...the BFARV bit in BFAULTSTAT to determine if the MMADDR or FAULTADDR contents are valid Software must follow this sequence because another higher priority exception might change the MMADDR or FAULTADD...

Page 1681: ...uction that makes illegal use of the EPSR register When this bit is set the PC value stacked for the exception return points to the instruction that attempted the illegal use of the Execution Program...

Page 1682: ...caused the fault When this bit is set the fault address is written to the FAULTADDR register This bit is cleared by writing a 1 to it 8 IBUS Instruction Bus Error 0 An instruction bus error has not o...

Page 1683: ...t is set the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is written to the MMADDR register This bit is cleared by writing a 1 t...

Page 1684: ...ns Bit Field Value Description 31 DBG Debug Event This bit is reserved for Debug use This bit must be written as a 0 otherwise behavior is unpredictable 30 FORCED Forced Hard Fault 0 No forced hard fa...

Page 1685: ...ite R Read only n value after reset Table 25 52 Memory Management Fault Address MMADDR Register Field Descriptions Bit Field Value Description 31 ADDR Fault Address When the MMARV bit of MFAULTSTAT is...

Page 1686: ...how many regions it supports Note This register can only be accessed from privileged mode Figure 25 47 MPU Type MPUTYPE Register 31 24 23 16 Reserved IREGION R 0 R 0 15 8 7 1 0 DREGION Reserved SEPARA...

Page 1687: ...sses from both privileged and unprivileged software When the MPU is enabled accesses to the System Control Space and vector table are always permitted Other areas are accessible based on regions and w...

Page 1688: ...ter Field Descriptions Bit Field Value Description 31 3 Reserved Reserved 2 0 NUMBER MPU Region to Access 0 This field indicates the MPU region referenced by the MPUBASE and MPUATTR registers The MPU...

Page 1689: ...nd Size MPUATTR Register offset 0xDA0 DB8 The MPU Region Attribute and Size MPUATTR register defines the region size and memory attributes of the MPU region specified by the MPU Region Number MPUNUMBE...

Page 1690: ...6 24 AP Access Privilege 0 For information on using this bit field see Table 25 5 23 22 Reserved Reserved 21 19 TEX Type Extension Mask 0 For information on using this bit field see Table 25 3 18 S Sh...

Page 1691: ...footnote 594 Section 6 5 15 9 Added this new section 613 Table 7 52 Changed the description of 00 values 789 Figure 8 10 Included the new figure 837 Section 9 4 1 3 Deleted second paragraph already s...

Page 1692: ...e resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reprod...

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