module clock frequency
+
I2C input clock frequency
( IPSC
)
1 )
28x device
divider
PLLCR
ICCH
IPSC
I C input clock
(SYSCLKOUT)
2
÷
Device input clock
Module clock
for I
2
C module operation
Master clock
on SCL pin
I
2
C module
ICCL,
To I
2
C-bus
÷
I2C Module Operational Details
1048
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
C28 Inter-Integrated Circuit Module
Figure 14-3. Clocking Diagram for the I2C Module
The module clock determines the frequency at which the I2C module operates. A programmable prescaler
in the I2C module divides down the I2C input clock to produce the module clock. To specify the divide-
down value, initialize the IPSC field of the prescaler register, I2CPSC. The resulting frequency is:
NOTE:
To meet all of the I2C protocol timing specifications, the module clock must be configured
between 7 - 12 MHz.
The prescaler must be initialized only while the I2C module is in the reset state (IRS = 0 in I2CMDR). The
prescaled frequency takes effect only when IRS is changed to 1. Changing the IPSC value while IRS = 1
has no effect.
The master clock appears on the SCL pin when the I2C module is configured to be a master on the I2C-
bus. This clock controls the timing of communication between the I2C module and a slave. As shown in
, a second clock divider in the I2C module divides down the module clock to produce the
master clock. The clock divider uses the ICCL value of I2CCLKL to divide down the low portion of the
module clock signal and uses the ICCH value of I2CCLKH to divide down the high portion of the module
clock signal. See section
for the master clock frequency equation.
14.2 I2C Module Operational Details
This section provides an overview of the I2C-bus protocol and how it is implemented.
14.2.1 Input and Output Voltage Levels
One clock pulse is generated by the master device for each data bit transferred. Due to a variety of
different technology devices that can be connected to the I2C-bus, the levels of logic 0 (low) and logic 1
(high) are not fixed and depend on the associated level of V
DD
. For details, see the data manual for your
particular device.
14.2.2 Data Validity
The data on SDA must be stable during the high period of the clock (see
). The high or low
state of the data line, SDA, should change only when the clock signal on SCL is low.
