SPI Registers and Waveforms
1007
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
C28 Serial Peripheral Interface (SPI)
12.3.1.9 SPI FIFO Transmit, Receive, and Control Registers
Figure 12-21. SPI FIFO Transmit (SPIFFTX) Register
−
Address 704Ah
15
14
13
12
11
10
9
8
SPIRST
SPIFFENA
TXFIFO
TXFFST4
TXFFST3
TXFFST2
TXFFST1
TXFFST0
R/W-1
R/W
−
0
R/W-1
R
−
0
R
−
0
R
−
0
R
−
0
R
−
0
7
6
5
4
3
2
1
0
TXFFINT Flag
TXFFINT CLR
TXFFIENA
TXFFIL4
TXFFIL3
TXFFIL2
TXFFIL1
TXFFIL0
R/W-0
W
−
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 12-17. SPI FIFO Transmit (SPIFFTX) Register Field Descriptions
Bit
Field
Value
Description
15
SPIRST
SPI reset
0
Write 0 to reset the SPI transmit and receive channels. The SPI FIFO register configuration bits will
be left as is.
1
SPI FIFO can resume transmit or receive. No effect to the SPI registers bits.
14
SPIFFENA
SPI FIFO enhancements enable
0
SPI FIFO enhancements are disabled
1
SPI FIFO enhancements are enabled
13
TXFIFO Reset
Transmit FIFO reset
0
Write 0 to reset the FIFO pointer to zero, and hold in reset.
1
Re-enable Transmit FIFO operation
12-8
TXFFST4
−
0
Transmit FIFO status
00000
Transmit FIFO is empty.
00001
Transmit FIFO has 1 word.
00010
Transmit FIFO has 2 words.
00011
Transmit FIFO has 3 words.
00100
Transmit FIFO has 4words, the maximum
7
TXFFINT
TXFIFO interrupt
0
TXFIFO interrupt has not occurred, This is a read-only bit.
1
TXFIFO interrupt has occurred, This is a read-only bit.
6
TXFFINT CLR
TXFIFO clear
0
Write 0 has no effect on TXFFINT flag bit, Bit reads back a zero.
1
Write 1 to clear TXFFINT flag in bit 7.
5
TXFFIENA
TX FIFO interrupt enable
0
TX FIFO interrupt based on TXFFIL match (less than or equal to) will be disabled .
1
TX FIFO interrupt based on TXFFIL match (less than or equal to) will be enabled.
4-0
TXFFIL4
−
0
TXFFIL4
−
0 transmit FIFO interrupt level bits. Transmit FIFO will generate interrupt when the FIFO
status bits (TXFFST4
−
0) and FIFO level bits (TXFFIL4
−
0 ) match (less than or equal to).
00000
Default value is 0x00000.
Figure 12-22. SPI FIFO Receive (SPIFFRX) Register
−
Address 704Bh
15
14
13
12
11
10
9
8
RXFFOVF Flag
RXFFOVF CLR
RXFIFO Reset
RXFFST4
RXFFST3
RXFFST2
RXFFST1
RXFFST0
R-0
W
−
0
R/W
−
1
R
−
0
R
−
0
R
−
0
R
−
0
R
−
0
7
6
5
4
3
2
1
0
RXFFINT Flag
RXFFINT CLR
RXFFIENA
RXFFIL4
RXFFIL3
RXFFIL2
RXFFIL1
RXFFIL0
R-0
W
−
0
R/W
−
0
R/W
−
1
R/W
−
1
R/W
−
1
R/W
−
1
R/W
−
1
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset