Texas Instruments Concerto F28M35 Series, Technical Reference Manual

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C-Boot ROM Description
593 SPRUH22I – April 2012 – Revised November 2019
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Copyright © 2012–2019, Texas Instruments Incorporated
ROM Code and Peripheral Booting
Table 6-24. CTOM IPC Messages (continued)
Value CTOMIPCCOM
(M3 - R, B.C28X R/W)
CTOMIPCADDR
(M3 - R, B.C28X R/W)
CTOMIPCDATAW
(M3 - R, B.C28X R/W)
CTOMIPCDATAR
(M3 – R/W, B.C28X-
R)
Description
0xFFFFFFFB C_BOOTROM_IPC_CTOM_CONTROL_SYSTE
M_IN_FLUNCERR DON’T CARE DON’T CARE DON’T CARE Tells the master
system that C-Boot
ROM detected a Flash
uncorrectable error.
C-Boot ROM is
waiting for a reset
from the master
subsystem, when this
even occurs
0xFFFFFFFA C_BOOTROM_IPC_CTOM_CONTROL_SYSTE
M_IN_RAMUNCERR DON’T CARE DON’T CARE DON’T CARE Tells the master
system that C-Boot
ROM detected a RAM
uncorrectable error
C-Boot ROM is
waiting for a reset
from the master
subsystem, when this
even occurs
NOTE: The master subsystem application software should clear CTOMIPCFLG[0] and CTOMIPCFLG[31]
bits as soon as it receives the respective messages in order to ‘not’ miss another IPC status message
from C-Boot ROM.
6.6.13 C-Boot ROM Handling of Exceptions and PIE Interrupts
Table 6-25 explains the actions taken by C-Boot ROM in response to various events that can occur during
boot.
Table 6-25. C-Boot ROM Exceptions Handling
Exception Event Source Description C-Boot ROM action C-Boot ROM state after
exception
CLOCKFAIL – from missing
clock detection logic CLKFAIL condition detected cbrom_handle_nmi :-> Clear
NMI Flags, Save error status in
CTOMBOOTSTS register bits
and returns from the interrupt
handler.
NMI is generated to the master
subsystem also, No IPC
message is sent. Continue to boot, because
missing clock circuit will switch
CPU to 10 MHz clock source
M3BISTERR M3 HW BIST Error NMI Flag Default NMI HANDLER:->
Clear NMI Flags, Save error
status in CTOMBOOTSTS
register bits and wait in
while(1) loop for master to
handle the error state. NMI is
generated to C28 also, so no
need to send an IPC message. Wait in While(1) loop, for reset
from master.
C28BISTERR C28 HW BIST Error NMI Flag Default NMI HANDLER:->
Clear NMI Flags, Save error
status in CTOMBOOTSTS
register bits and wait in
while(1) loop for master to
handle the error state. NMI is
generated to M3 also, so no
need to send an IPC message. Wait in While(1) loop, for reset
from master.
C28RAMUNCERR C28 RAM Uncorrectable Error
NMI Flag cbrom_handle_nmi :-> Clear
NMI Flags, Save error status in
CTOMBOOTSTS register,
send IPC message to master
and wait in while(1) loop for
master to handle the error
state.. Wait in While(1) loop, for reset
frommaster.