Texas Instruments Concerto F28M35 Series, Technical Reference Manual

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System Control Registers
231 SPRUH22I – April 2012 – Revised November 2019
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System Control and Interrupts
Table 1-119. Run Mode Clock Gating Control Register 1 (RCGC1) Field Descriptions (continued)
Bit Field Value Description
6 SSI2 SSI2 Clock Gating Control in Run Mode
This bit controls the clock gating for the SSI2 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
5 SSI1 SSI1 Clock Gating Control in Run Mode
This bit controls the clock gating for the SSI1 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
4 SSI0 SSI0 Clock Gating Control in Run Mode
This bit controls the clock gating for the SSI0 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
3 UART3 UART3 Clock Gating Control in Run Mode
This bit controls the clock gating for the UART3 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
2 UART2 UART2 Clock Gating Control in Run Mode
This bit controls the clock gating for the UART2 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
1 UART1 UART1 Clock Gating Control in Run Mode
This bit controls the clock gating for the UART1 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
0 UART0 UART0 Clock Gating Control in Run Mode
This bit controls the clock gating for the UART0 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
1.13.7.17 Sleep Mode Clock Gating Control Register 1 (SCGC1)
Figure 1-109. Sleep Mode Clock Gating Control Register 1 (SCGC1)
31 24
Reserved
R-0
23 20 19 18 17 16
Reserved TIMER3 TIMER2 TIMER1 TIMER0
R-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 8
Reserved I2C1 Reserved I2C0 Reserved
R-0 R/W-0 R-0 R/W-0 R-0
7 6 5 4 3 2 1 0
SSI3 SSI2 SSI1 SSI0 UART3 UART2 UART1 UART0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 1-120. Sleep Mode Clock Gating Control Register 1 (SCGC1) Field Descriptions
Bit Field Value Description
31 Reserved Reserved
30 EPI EPI Clock Gating Control in Sleep Mode
This bit controls the clock gating for the EPI module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
29-20 Reserved Reserved