Register Descriptions (I2C Slave)
1509
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
M3 Inter-Integrated Circuit (I2C) Interface
Figure 22-26. I2C Slave Control/Status (I2CSCSR) Register (Write-Only)
31
1
0
Reserved
DA
R-0
WO
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 22-16. I2C Slave Control/Status (I2CSCSR) Register Field Descriptions (Write-Only)
Bit
Field
Value
Description
31-1
Reserved
Reserved
0
DA
Device Active
0
Disables the I2C slave operation.
1
Enables the I2C slave operation.
22.7.3 I2C Slave Data (I2CSDR), offset 0x808
Important:
This register is read-sensitive. See the register description for details.
This register contains the data to be transmitted when in the Slave Transmit state, and the data received
when in the Slave Receive state. It is shown in the figure and table below.
Figure 22-27. I2C Slave Data (I2CSDR) Register
31
8
7
0
Reserved
DATA
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 22-17. I2C Slave Data (I2CSDR) Register Field Descriptions
Bit
Field
Value
Description
31-8
Reserved
Reserved
7-0
DATA
00h
Data for Transfer
This field contains the data for transfer during a slave receive or transmit operation.
22.7.4 I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C
The I2C Slave Interrupt Mask (I2CSIMR) register controls whether a raw interrupt is promoted to a
controller interrupt. It is shown in the figure and table below.
Figure 22-28. I2C Slave Interrupt Mask (I2CSIMR) Register
31
3
2
1
0
Reserved
STOPIM
STARTIM
DATAIM
R-0
R-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 22-18. I2C Slave Interrupt Mask (I2CSIMR) Register Field Descriptions
Bit
Field
Value
Description
31-3
Reserved
Reserved
2
STOPIM
Stop Condition Interrupt Mask
0
The STOPRIS interrupt is suppressed and not sent to the interrupt controller.
1
The STOP condition interrupt is sent to the interrupt controller when the STOPRIS bit in the
I2CSRIS register is set.