Functional Description
1283
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
M3 Universal Serial Bus (USB) Controller
If the size of the receive endpoint FIFO is at least twice the maximum packet size for the endpoint, two
data packets can be buffered and double-packet buffering can be used. When the first packet is received
and loaded into the receive FIFO, the RXRDY bit in the USBRXCSRL[
n
] register is set and the appropriate
receive endpoint interrupt is signaled to indicate that a packet can now be unloaded from the FIFO.
Note:
The FULL bit in USBRXCSRL[
n
] is not set when the first packet is received. It is only set if a second
packet is received and loaded into the receive FIFO.
After each packet has been unloaded, the RXRDY bit must be cleared to allow further packets to be
received. If the AUTOCL bit in the USBRXCSRH[
n
] register is set and a maximum-sized packet is
unloaded from the FIFO, the RXRDY bit is cleared automatically. For packet sizes less than the maximum,
RXRDY must be cleared manually. If the FULL bit is set when RXRDY is cleared, the USB controller first
clears the FULL bit, then sets RXRDY again to indicate that there is another packet waiting in the FIFO to
be unloaded.
Note:
Double-packet buffering is disabled if an endpoint’s corresponding EPn bit is set in the USB
Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS) register. This bit is set by default, so it
must be cleared to enable double-packet buffering.
18.2.1.1.3 Scheduling
The device has no control over the scheduling of transactions as scheduling is determined by the Host
controller. The USB controller can set up a transaction at any time. The USB controller waits for the
request from the Host controller and generates an interrupt when the transaction is complete or if it was
terminated due to some error. If the Host controller makes a request and the Device controller is not
ready, the USB controller sends a busy response (NAK) to all requests until it is ready.
18.2.1.1.4 Additional Actions
The USB controller responds automatically to certain conditions on the USB bus or actions by the Host
controller such as when the USB controller automatically stalls a control transfer or unexpected zero
length OUT data packets.
Stalled Control Transfer
The USB controller automatically issues a STALL handshake to a control transfer under the following
conditions:
1. The Host sends more data during an OUT data phase of a control transfer than was specified in the
Device request during the SETUP phase. This condition is detected by the USB controller when the
Host sends an OUT token (instead of an IN token) after the last OUT packet has been unloaded and
the DATAEND bit in the USB Control and Status Endpoint 0 Low (USBCSRL0) register has been set.
2. The Host requests more data during an IN data phase of a control transfer than was specified in the
Device request during the SETUP phase. This condition is detected by the USB controller when the
Host sends an IN token (instead of an OUT token) after the CPU has cleared TXRDY and set
DATAEND in response to the ACK issued by the Host to what should have been the last packet.
3. The Host sends more than USBRXMAXPn bytes of data with an OUT data token.
4. The Host sends more than a zero length data packet for the OUT STATUS phase.
Zero Length OUT Data Packets
A zero-length OUT data packet is used to indicate the end of a control transfer. In normal operation, such
packets should only be received after the entire length of the Device request has been transferred.
However, if the Host sends a zero-length OUT data packet before the entire length of Device request has
been transferred, it is signaling the premature end of the transfer. In this case, the USB controller
automatically flushes any IN token ready for the data phase from the FIFO and sets the DATAEND bit in
the USBCSRL0 register.
Setting the Device Address
