Register Descriptions
1262
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
External Peripheral Interface (EPI)
17.11.24 EPI Error Interrupt Status and Clear (EPIEISC) Register, offset 0x21C
This register is used to clear a pending error interrupt. Clearing any defined bit in the EPIEISC has no
effect; setting a bit clears the error source and the raw error returns to 0. it indicates that the ERRRIS bit
in the EPIRIS register is set and an EPI controller error is sent to the interrupt controller if the ERIM bit in
the EPIIM register is set. If any of bits [2:0] are written as 1, the register bit being written to, as well as the
ERRIS bit in the EPIRIS register and the ERIM bit in the EPIIM register are cleared. If the DMAWRIC or
DMARDIC bit in this register is set, then the corresponding bit in the EPIRIS and EPIMIS register is
cleared. Note that writing to this register and reading back immediately (pipelined by the processor)
returns the old register contents. One cycle is needed between write and read.his register is used to clear
a pending error interrupt. If any of these bits are set, the ERRRIS bit in the EPIRIS register is set, and an
EPI controller error is sent to the interrupt controller if the ERIM bit in the EPIIM register is set. Clearing
any defined bit has no effect; setting a bit clears the error source and the raw error returns to 0. Note that
writing to this register and reading back immediately (pipelined by the processor) returns the old register
contents. One cycle is needed between write and read.
Figure 17-51. EPI Error Interrupt Status and Clear (EPIEISC) Register [offset 0x21C]
31
16
Reserved
R-0x0000.000
15
5
4
3
2
1
0
Reserved
DMAW
RIC
DMAR
DIC
WTFU
LL
RSTA
LL
TOUT
R-0x0000.000
W1C-0 W1C-0
R/W1
C-0
R/W1
C-0
R/W1
C-0
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 17-37. EPI Error Interrupt Status and Clear (EPIEISC) Register Field Descriptions
Bit
Field
Value
Description
31-5
Reserved
Reserved
4
DMAWRIC
Write uDMA Interrupt Clear
0
1
Writing a 1 to this bit clears the DMAWRRIS bit in the EPIRIS register and the DMAWRMIS bit in
the EPIMIS register.
3
DMARDIC
Read uDMA Interrupt Clear
0
1
Writing a 1 to this bit clears the DMARDRIS bit in the EPIRIS register and the DMARDMIS bit in the
EPIMIS register.
2
WTFULL
Write FIFO Full Error
Writing a 1 to this bit clears it, as well as the ERRRIS and ERIM bits.
0
The WFERR bit is not enabled or no writes are stalled.
1
The WFERR bit is enabled and a write is stalled due to the WFIFO being full.
1
RSTALL
Read Stalled Error
Writing a 1 to this bit clears it, as well as as the ERRRIS and ERIM bits.
0
The RSERR bit is not enabled pr no pending reads are stalled.
1
The RSERR bit is enabled and a pending read is stalled due to writes in the WFIFO.
0
TOUT
Timeout Error
This bit is the timeout error source. The timeout error occurs when the iRDY or XFIFO not-ready
signals hold a transaction for more than the count in the MAXWAIT field (when not 0).
Writing a 1 to bit this clears it, as well as the ERRRIS and ERIM bits.
0
No timeout error has occurred.
1
A timeout error has occurred.
