Texas Instruments Concerto F28M35 Series, Technical Reference Manual

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I2C Module Registers
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1034 SPRUH22I – April 2012 – Revised November 2019
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C28 Inter-Integrated Circuit Module
Table 14-21. I2C Transmit FIFO Register (I2CFFTX) Field Descriptions (continued)
Bit Field Value Description
7 TXFFINT Transmit FIFO interrupt flag. This bit cleared by a CPU write of a 1 to the TXFFINTCLR bit. If the
TXFFIENA bit is set, this bit will generate an interrupt when it is set.
0 Transmit FIFO interrupt condition has not occurred.
1 Transmit FIFO interrupt condition has occurred.
6 TXFFINTCLR Transmit FIFO interrupt flag clear bit.
0 Writes of zeros have no effect. Reads return a 0.
1 Writing a 1 to this bit clears the TXFFINT flag.
5 TXFFIENA Transmit FIFO interrupt enable bit.
0 Disabled. TXFFINT flag does not generate an interrupt when set.
1 Enabled. TXFFINT flag does generate an interrupt when set.
4-0 TXFFIL4-0 Transmit FIFO interrupt level.
These bits set the status level that will set the transmit interrupt flag. When the TXFFST4-0 bits
reach a value equal to or less than these bits, the TXFFINT flag will be set. This will generate an
interrupt if the TXFFIENA bit is set.
14.5.14 I2C Receive FIFO Register (I2CFFRX)
The I2C receive FIFO register (I2CFFRX) is a 16-bit register that contains the control and status bits for
the receive FIFO mode of operation on the I2C peripheral. The bit fields are shown in
Figure 14-31 and
described in Table 14-22 .
Figure 14-31. I2C Receive FIFO Register (I2CFFRX)
15 14 13 12 11 10 9 8
Reserved RXFFRST RXFFST4 RXFFST3 RXFFST2 RXFFST1 RXFFST0
R-0 R/W-0 R-0 R-0 R-0 R-0 R-0
7 6 5 4 3 2 1 0
RXFFINT RXFFINTCLR RXFFIENA RXFFIL4 RXFFIL3 RXFFIL2 RXFFIL1 RXFFIL0
R-0 R/W1C-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 14-22. I2C Receive FIFO Register (I2CFFRX) Field Descriptions
Bit Field Value Description
15-14 Reserved Reserved. Reads will return a 0, writes have no effect.
13 RXFFRST I2C receive FIFO reset bit
0 Reset the receive FIFO pointer to 0000 and hold the receive FIFO in the reset state.
1 Enable the receive FIFO operation.
12-8 RXFFST4-0 Contains the status of the receive FIFO:
10000 Receive FIFO contains 16 bytes
0xxxx Receive FIFO contains xxxx bytes
00000 Receive FIFO is empty.
7 RXFFINT Receive FIFO interrupt flag. This bit cleared by a CPU write of a 1 to the RXFFINTCLR bit. If the
RXFFIENA bit is set, this bit will generate an interrupt when it is set.
0 Receive FIFO interrupt condition has not occurred.
1 Receive FIFO interrupt condition has occurred.
6 RXFFINTCLR Receive FIFO interrupt flag clear bit.
0 Writes of zeros have no effect. Reads return a zero.
1 Writing a 1 to this bit clears the RXFFINT flag.