Texas Instruments Concerto F28M35 Series, Technical Reference Manual

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SCI Registers
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1002 SPRUH22I – April 2012 – Revised November 2019
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C28 Serial Communications Interface (SCI)
Table 13-14. SCI Receive Data Buffer Register (SCIRXBUF) Field Descriptions
Bit Field Value Description
15 SCIFFFE SCIFFFE. SCI FIFO Framing error flag bit (applicable only if the FIFO is enabled)
0 No frame error occurred while receiving the character, in bits 7 − 0. This bit is associated with the
character on the top of the FIFO.
1 A frame error occurred while receiving the character in bits 7 − 0. This bit is associated with the
character on the top of the FIFO.
14 SCIFFPE SCIFFPE. SCI FIFO parity error flag bit (applicable only if the FIFO is enabled)
0 No parity error occurred while receiving the character, in bits 7 − 0. This bit is associated with the
character on the top of the FIFO.
1 A parity error occurred while receiving the character in bits 7 − 0. This bit is associated with the
character on the top of the FIFO.
13-8 Reserved
7-0 RXDT7 − 0 Receive Character bits
13.3.8 SCI Transmit Data Buffer Register (SCITXBUF)
Data bits to be transmitted are written to SCITXBUF. These bits must be rightjustified because the
leftmost bits are ignored for characters less than eight bits long. The transfer of data from this register to
the TXSHF transmitter shift register sets the TXRDY flag (SCICTL2.7), indicating that SCITXBUF is ready
to receive another set of data. If bit TX INT ENA (SCICTL2.0) is set, this data transfer also causes an
interrupt.
Figure 13-21. Transmit Data Buffer Register (SCITXBUF) — Address 7059h
7 6 5 4 3 2 1 0
TXDT7 TXDT6 TXDT5 TXDT4 TXDT3 TXDT2 TXDT1 TXDT0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
13.3.9 SCI FIFO Registers (SCIFFTX, SCIFFRX, SCIFFCT)
The SCI FIFO Registers (SCIFFTX, SCIFFRX, SCIFFCT) are shown and described here.
Figure 13-22. SCI FIFO Transmit (SCIFFTX) Register — Address 705Ah
15 14 13 12 11 10 9 8
SCIRST SCIFFENA TXFIFO Reset TXFFST4 TXFFST3 TXFFST2 TXFFST1 TXFFST0
R/W-1 R/W-0 R/W-1 R
−
0 R
−
0 R
−
0 R
−
0 R
−
0
7 6 5 4 3 2 1 0
TXFFINT Flag TXFFINT CLR TXFFIENA TXFFIL4 TXFFIL3 TXFFIL2 TXFFIL1 TXFFIL0
R − 0 W − 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 13-15. SCI FIFO Transmit (SCIFFTX) Register Field Descriptions
Bit Field Value Description
15 SCIRST SCI Reset
0 Write 0 to reset the SCI transmit and receive channels. SCI FIFO register configuration bits will be
left as is.
1 SCI FIFO can resume transmit or receive. SCIRST should be 1 even for Autobaud logic to work.
14 SCIFFENA SCI FIFO enable
0 SCI FIFO enhancements are disabled
1 SCI FIFO enhancements are enabled