Texas Instruments CDCM61001, User Manual

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Operating Mode Selection
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Table 2. Available Prescaler Divider and Feedback Divider Values with PFD
Frequency Range
Control Inputs PFD Frequency
(1)
Prescaler Feedback
PR1 PR0 Divider Divider Minimum Maximum
0 0 3 24 24.305 28.47
0 1 5. 15 23.33 27.33
1 0 3 25 23.33 27.33
1 1 4 20 21.875 25.62
(1)
PFD frequency = Reference Clock Frequency
The product of the prescaler divider and the feedback divider with reference clock frequency provides the
frequency at which the VCO operates:
VCO Frequency = Prescaler Divider × Feedback Divider × Reference Clock Frequency
6.2 Output Divider Selections
JP14 (OD0), JP13 (OD1), and JP12 (OD2) are the jumpers for the output dividers. Depending on whether
the device operates in logic '1' or logic '0', the divider offers up to six different frequencies. All outputs
have the same frequency because the outputs are generated from the same divider.
Table 3 lists the available output divider values.
Table 3. Programmable Output Divider Values
Control Inputs
OD2 OD1 OD0 Output Divider
0 0 0 1
0 0 1 2
0 1 0 3
0 1 1 4
1 0 1 6
1 1 1 8
Output Frequency = VCO Frequency / (Prescaler Divider × Output Divider)
6.3 Output Buffer Type Selection
JP16 (OS1) and JP15 (OS0) are the jumpers for output buffer selection (LVCMOS, LVDS, or LVPECL).
Each output pair provides two in-phase LVCMOS clocks.
Table 4 shows the output buffer options.
Table 4. Output Buffer Options
Control Inputs
OS1 OS0 Output Type
0 0 LVCMOS, OSC_OUT Off
0 1 LVDS, OSC_OUT Off
1 0 LVPECL, OSC_OUT Off
1 1 LVPECL, OSC_OUT On
4 Low Phase Noise Clock Evaluation Module SCAU027B – March 2009 – Revised March 2011
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