General Description
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2
General Description
The CDCM61001, CDCM61002, and CDCM61004 are high-performance, low phase noise clock
generators. Each device has one crystal/low-voltage CMOS (LVCMOS) input buffer and one, two, or four
universal outputs depending on the respective device.
This is a programmable clock generator with control pins only. No EEPROM or programming interface is
necessary to program these devices.
The CDCM6100x evaluation module (EVM) is designed to demonstrate the electrical performance of the
CDCM61004 and is representative of the performance of the CDCM61001 and CDCM61002. This
fully-assembled and factory-tested evaluation board allows complete validation of all device functions.
For optimum performance, the board is equipped with 50-
Ω
SMA connectors and well-controlled, 50-
Ω
impedance microstrip transmission lines.
Throughout this document, the abbreviation EVM and the phrases evaluation module and evaluation
board are synonymous with the CDCM6100xEVM. For clarity of reading, the abbreviation CDCM6100x
refers to the CDCM61001, CDCM61002, and CDCM61004, unless otherwise noted.
2.1
Reference Documents
The related documents listed in
are available through the Texas Instruments web site at
Table 1. EVM-Compatible Device Data Sheets
Device
Data Sheet
3
Signal Path and Control Circuitry
The CDCM6100x supports either a crystal input or a single-ended clock with a frequency range of 21.875
MHz to 28.47 MHz. The internal VCO operates from 1.75 GHz to 2.05 GHz. The output buffers provide
output frequencies from 43.75 MHz to 683.264 MHz for low-voltage differential signaling (LVDS) and
low-voltage positive emitter coupled logic (LVPECL), and from 43.75 MHz to 250 MHz for LVCMOS. An
optional, bypassed LVCMOS output is also available.
The output frequency depends on the input frequency, Prescaler, Feedback, and Output Divider settings.
See the respective product data sheet (listed in
) for complete descriptions of the various settings.
4
Getting Started
The EVM has self-explanatory labeling. Additionally, the naming conventions used for the EVM
correspond to that used in the respective product data sheets. Words shown in bold italics in this
document show the same name and label on the EVM board itself. The EVM can be used with either a
crystal input or external, single-ended clock input.
4.1
Power-Supply Connection
Connect the power-supply source to the banana plug labeled 3.3V (P4) and connect the ground of the
power-supply source to GND (P5). There are decoupling capacitors and ferrite bead to isolate the device
power pins dedicated for the PLL from the other power pins.
This EVM can operate from a 3.0-V to 3.6-V supply voltage.
5
Input Clock Selection
The CDCM6100xEVM offers the options to use either a crystal or a single-ended clock source as the clock
input.
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Low Phase Noise Clock Evaluation Module
SCAU027B – March 2009 – Revised March 2011
© 2009–2011, Texas Instruments Incorporated
