CC112X/CC1175
SWRU295C
Page 50 of 108
a) Interrupt Driven Solution
The GPIO pins can be used in both RX and TX to give an interrupt when a sync word has been
received/transmitted or when a complete packet has been received/transmitted by setting
IOCFGx.GPIOx_CFG = PKT_SYNC_RXTX
(6). In addition, there are four configurations for the
register that can be used as an interrupt source to provide information on how
many bytes are in the RX FIFO and TX FIFO respectively (see 7.6 for more details).
b) SPI Polling
register can be polled at a given rate to get information about the current GPIO
values. The
registers can be polled at a given rate to get
information about the number of bytes in the RX FIFO and TX FIFO respectively. It is also possible to
use
. These
register fields give the number of bytes available in the RX FIFO and free bytes in the TX FIFO, and
both register values saturates at 15.
7.6
TX FIFO and RX FIFO
The
CC112X
contains two 128 byte FIFOs, one for received data and one for transmit data. The SPI
interface is used to read from the RX FIFO and write to the TX FIFO. Section 3.2.4 contains details on
the SPI FIFO access. The FIFO controller will detect under/overflow in both the RX FIFO
and the TX FIFO.
A signal will assert when the number of bytes in the FIFO is equal to or higher than a programmable
threshold. This signal can be viewed on the GPIO pins and can be used for interrupt driven FIFO
routines to avoid polling the
(0) and the
IOCFGx.GPIOx_CFG = RXFIFO_THR_PKT
(1) configurations are
associated with the RX FIFO while the
(2) and the
IOCFGx.GPIOx_CFG = TXFIFO_THR_PKT
(3)
configurations are associated with the TX FIFO.
The 7-bit
setting is used to program threshold points. Table 25 lists the
settings and the corresponding thresholds for the RX and TX FIFO. The threshold value is
coded in opposite directions for the two FIFOs to give equal margin to the overflow and underflow
conditions when the threshold is reached.
FIFO_THR
Bytes in TX FIFO
Bytes in RX FIFO
0
127
1
1
126
2
2
125
3
...
...
...
126
1
127
127
0
128
Table 25:
FIFO_THR
Settings and the Corresponding FIFO Thresholds
To simplify debug and advanced FIFO features, the full FIFO buffer is memory mapped and can be
accessed directly(see Section 3.2.3). Both FIFO content and FIFO data pointers are accessible. This
can be used to significantly reduce the SPI traffic, see examples below
1.
In a hostile RF environment packets are lost and re-transmissions are often required.
Normally the packet data must then be written again over the SPI interface. By using the
direct FIFO access feature and changing the
register to point to the head of the
previous message, a re-transmission can be done without writing the packet over the SPI.
2.
In many protocols only parts of the message is changed between each transmission (e.g.
changing a read value from a sensor, incrementing a transmission counter). Direct FIFO
access can then be used to change only the new data (the FIFOs are reached through the
0x3E command, see Table 4), leaving the rest of the data unchanged. FIFO data pointers
(
) can then be manipulated to re-transmit the packet with changed
data.