Texas Instruments CC112 Series, User Manual, Page: 33 / 109

CC112X/CC1175
SWRU295C Page 33 of 108
5.5 Bit Synchronization
The bit synchronization algorithm extracts the clock from the incoming symbols. The algorithm
requires that the expected data rate is programmed as described in Section 4.2. Re-synchronization
is performed continuously to adjust for any offset between the incoming and programmed symbol
rate.
It is possible to select between two different bit synchronization algorithms.
TOC_CFG.TOC_LIMIT
sets the bit synchronization algorithm and Table 19 below shows the
properties of the bit synchronization algorithms.
TOC_LIMIT
Data Rate Offset Tolerance Required Preamble Length
0 < 2000 ppm 0.5 byte (only for gain adjustment)
1 < 2% 2- 4 bytes
2 Reserved
3 < 12% 2- 4 bytes
Table 19: Bit Synchronization Property
Using the low tolerance setting, the novel WaveMatch capture logic is enabled. The WaveMatch
algorithm does not need any preamble bits for bit synchronization or frequency offset compensation,
greatly reducing system settling times and system power consumption (4 bits preamble needed for
AGC settling).
5.6 Byte Synchronization, Sync Word Detection
Byte synchronization is achieved by a continuous sync word search using a correlation filter. The sync
word is configured through the
SYNC3/2/1/0
registers and can be programmed to be 11, 16, 18, 24
or 32 bits. This is done through the
SYNC_CFG0.SYNC_MODE
register field. In TX mode, these bits are
automatically inserted at the start of the packet by the modulator. The MSB in the sync word is sent
first. In RX mode, the demodulator uses the sync word to find the start of the incoming packet.
The
CC112X
will continuously calculate a sync word qualifier value to distinguish the sync word from
background noise. This value is available in the
PQT_SYNC_ERR.SYNC_ERROR
register field. If the
sync word qualifier value is less than the programmed sync threshold (
SYNC_CFG1.SYNC_THR)
divided by 2 the demodulator starts to demodulate the packet.
The
CC112X
supports DualSync search which makes it possible to concurrently search for 2 different
16 bit sync words. DualSync search is enabled by settings
SYNC_CFG0.SYNC_MODE = 111b
. As
soon as one of the sync words is found, the RX FIFO starts to fill up.
In addition to continuously calculating a sync word qualifier value the
CC112X
has several other
features that can be used to decrease the likelihood of detecting “false” packets.
Bit Check on Sync Word
This feature is enabled through
SYNC_CFG0.SUW_NUM_ERROR
and allows for bit check on
the last sync word byte. This feature is especially useful if the sync word used has weak
correlation properties
Carrier Sense Gating
When
MDMCFG1.CARRIER_SENSE_GATE = 1
, the demodulator will not start to look for a
sync word before
CS
is asserted. See Section 5.8.1 for more details on CS.
PQT Gating
When
SYNC_CFG1.DEM_CFG = 010b
or
110b
, the demodulator will not start to look for a
sync word before a preamble is detected. The preamble detector must be enabled for this
feature to work (
PREAMBLE_CFG0.PQT_EN = 1
). See Section 5.7 for more details on PQT.