Texas Instruments CC112 Series, User Manual, Page: 31 / 109

CC112X/CC1175
SWRU295C Page 31 of 108
5.2 DC Offset Removal
CC112X
supports Low-IF and Zero-IF receiver architecture, which is set by the
FREQ_IF_CFG.FREQ_IF
register field. For more information see section 8.11. For Zero-IF the DC
offset removal must be enabled by setting
DCFILT_CFG.DCFILT_FREEZE_COEFF = 0
. The
DCFILT_CFG
configures the DC filter bandwidth, both during settling period and during tracking.
There is a tradeoff between bandwidth and settle time. Narrower DC filter bandwidth requires longer
settling time, but improves performance.
For best performance, use Low-IF receiver architecture when possible.
5.3 Automatic Gain Control
CC112X
contains an Automatic Gain Control (AGC) for adjusting the input signal level to the
demodulator.
The AGC behavior depends on the following register fields:
AGC_CFG2.FE_PERFORMANCE_MODE
o
Sets the correct gain tables to be applied for a given operation mode (See Table 18).
See the complete register description for what the different modes are.
~39 dB Index 0 ~27 dB Index 0
~36 dB Index 1 ~24 dB Index 1
~32 dB Index 2 ~21 dB Index 2
~39 dB ~18 dB
~29 dB ~15 dB
~27 dB ~12 dB
~24 dB ~9 dB
~21 dB ~6 dB
~18 dB ~3 dB
~15 dB ~0 dB
~12 dB ~-6 dB
~9 dB ~-12 dB
~6 dB ~-18 dB
~3 dB ~-21 dB Index 13
~0 dB
~-6 dB FE_PERFORMANCE_MODE = 10b
~-12 dB
~-18 dB
~-21 dB Index 17
FE_PERFORMANCE_MODE = 00b or 01b
Table 18: AGC Gain Tables
o
The
AGC_CFG2.AGC_MAX_GAIN
and
AGC_CFG3.AGC_MIN_GAIN
register fields are
used to set the table indexes for maximum and minimum gain respectively. For
example, setting
AGC_MAX_GAIN = 2
and
AGC_MIN_GAIN = 15
limits the gain
table to 14 entries, where max gain is ~32 dB and min gain is -12 dB. A lower
maximum gain will reduce power consumption in the receiver front end, since the
highest gain settings are avoided. Limiting max gain also improves worst case
linearity in the front-end, something that is very useful when using external LNA.