Texas Instruments CC112 Series, User Manual, Page: 18 / 109

CC112X/CC1175
SWRU295C Page 18 of 108
If the radio tries to write to the RX FIFO after it is full or if the RX FIFO is tried read when it is empty,
the
RXFIFO_OVERFLOW
and
RXFIFO_UNDERFLOW
signals will be asserted and the radio will enter the
RX_FIFO_ERR state. Likewise, if the TX FIFO is tried written when it is full or if the TX FIFO runs
empty in the middle of a packet, the
TXFIFO_OVERFLOW
and
TXFIFO_UNDERFLOW
signals will be
asserted and the radio will enter the TX_FIFO_ERR state.
The TX FIFO may be flushed by issuing a
SFTX
command strobe. Similarly, a
SFRX
command strobe
will flush the RX FIFO. A
SFTX
or
SFRX
command strobe can only be issued in the IDLE,
TX_FIFO_ERR, or RX_FIFO_ERR states. Both FIFOs are flushed when going to the SLEEP state.
3.3 Optional PIN CTRL Radio Control Feature
The
CC112X
has an optional way of controlling the radio by reusing SI, SCLK, and CSn from the SPI
interface. This feature allows for a simple three-pin control of the major states of the radio: SLEEP,
IDLE, RX, and TX. This optional functionality is enabled with the
EXT_CTRL.PIN_CTRL_EN
configuration bit.
State changes are commanded as follows:
When CSn is high, the SI and SCLK are set to the desired state according to Table 8.
When CSn goes low, the state of SI and SCLK is latched and a command strobe is generated
internally according to the pin configuration.
If the device is in the TX state and the TX command is issued, it will be ignored. For RX state, an RX
command will restart RX. When CSn is low the SI and SCLK have normal SPI functionality.
All pin control command strobes are executed immediately, except the
SPWD
strobe. The
SPWD
strobe
is delayed until CSn goes high.
Pin control is useful to get precise timing on RX/TX strobes.
CSn SCLK SI Function
1 X X Chip unaffected by SCLK/SI
0 0
Generates
SPWD
strobe
0 1 Generates
STX
strobe
1 0 Generates
SIDLE
strobe
1 1
Generates
SRX
strobe
0 SPI
mode SPI
mode SPI mode (wakes up into
IDLE if in SLEEP/XOFF)
Table 8: Optional Pin Control Coding
3.4 General Purpose Input/Output Control Pins
The four digital I/O pins GPIO0, GPIO1, GPIO2 and GPIO3 are general control pins configured with
IOCFGx.GPIOx_CFG
(where x is 0, 1, 2, or 3). Table 10 shows the different signals that can be
monitored on the GPIO pins. The signal name field in the table should be interpreted as follows:
One signal name: The signal can be routed out to any of the four GPIO pins for full flexibility
Four signal names: The signal can only be routed out on the GPIO designated in the table.
GPIO1 is shared with the SO pin in the SPI interface. The default setting for GPIO1
/
SO is
HIGHZ
(tri-
state) output, which is useful when the SPI interface is shared with other devices. By selecting any
other of the programming options, the GPIO1
/
SO pin will become a generic pin when CSn is high
and function as SO when CSn is low.
When the
IOCFGx.GPIOx_CFG
setting is less than 0x30 and
IOCFGx.GPIOx_INV
is 0 (1) the
GPIO2 pin will be hardwired to 0 (1), and GPIO1 and GPIO3 will be hardwired to 1 (0) in the SLEEP
state. These signals will be hardwired until the
CHIP_RDYn
signal goes low. GPIO0 will be tri-stated in
SLEEP mode when
IOCFG0.GPIO0_CFG[5:4] ≠ 11b
. If the
IOCFGx.GPIOx_CFG
setting is 0x30
or higher, the GPIO pins will work as programmed also in SLEEP state.