Texas Instruments CC112 Series, User Manual, Page: 10 / 109

CC112X/CC1175
SWRU295C Page 10 of 108
3.2 SPI Access Types
Figure 4 shows the SPI memory map and the following sections are going to explain how the different
SPI access types (see Table 3) should be used. Table 4 shows the SPI address space.
Figure 4: SPI Memory Map
Access type Command/Address byte Description
Single Register Access
(register space) Address : R/W ¯ 0 A
5
A
4
A
3
A
2
A
1
A
0
(A
5 - 0
< 0x2F)
The R/W ¯ bit determines whether the operation is a read
(1) or a write (0) operation
The register accessed is determined by the address in
A
5 - 0
Exactly one data byte is expected after the address byte
The chip status byte is returned on the SO line both
when the address is sent on the SI line as well as when
data are written
Burst Register Access
(register space) Address : R/W ¯ 1 A
5
A
4
A
3
A
2
A
1
A
0
(A
5 - 0
< 0x2F)
The R/W ¯ bit determines whether the operation is a read
(1) or a write (0) operation
The address in A
5 - 0
determines the first register
accessed, after which an internal address counter is
incremented for each new data byte following the
address byte
Consecutive bytes are expected after the address byte
and the burst access is terminated by setting CSn high
The chip status byte is returned on the SO line both
when the address is sent on the SI line as well as when
data are written
If the internal address counter reaches address 0x2E
(last byte in register space) the counter will not
increment anymore and the same address will be
read/written until the burst access is being terminated
Single Register Access
(extended register space)
Command : R/W ¯ 0 1 0 1 1 1 1
Address : A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
(A
7 - 0
: See Table 5)
This access mode starts with a specific command
(0x2F)
The first byte following this command is interpreted as
the extended address
Exactly one data byte is expected after the extended
address byte
When the extended address is sent on the SI line, SO
will return all zeros. The chip status byte is returned on
the SO line when the command is transmitted as well as
when data are written to the extended address
0x00
Register space
0x2E
0x2F Extended address
0x00
Extended register space
0xFF
0x30
Command strobes
0x3D
0x3E FIFO direct access
0x00
Direct FIFO buffer access
(memory mapped
buffers)
0xFF
0x3F FIFO access