[
]
xoscx
IF
f
f
8
(ADC _ DIV 2 : 0
1)
=
´
+
SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015
In receive mode the frequency must be programmed to be the LO frequency. Low side LO injection is
used, hence
f
LO
= f
c
– f
IF
(11)
Where:
f
IF
is the IF frequency (ideally 307.2 kHz).
5.8.1
Dithering
Spurious signals will occur at certain frequencies depending on the division ratios in the PLL. To reduce
the strength of these spurs, a common technique is to use a dithering signal in the control of the frequency
dividers. Dithering is activated by setting the DITHER bit in the FREQ_0 registers. It is recommended to
use the dithering in order to achieve the best possible performance.
5.9
Receiver
5.9.1
IF Frequency
The IF frequency is derived from the crystal frequency as shown in
.
(12)
Where:
ADC_DIV[2:0] is set in the MODEM register.
The analog filter succeeding the mixer is used for wideband and anti-alias filtering, which is important for
the blocking performance at 1 MHz and larger offsets. This filter is fixed and centered on the nominal IF
frequency of 307.2 kHz. The bandwidth of the analog filter is about 160 kHz.
Using crystal frequencies which gives an IF frequency within 300 to 320 kHz means that the analog filter
can be used (assuming low frequency deviations and low data rates).
Large offsets, however, from the nominal IF frequency will give an un-symmetric filtering (variation in
group delay and different attenuation) of the signal, resulting in decreased sensitivity and selectivity. See
AN022 CC1020 Crystal Frequency Selection
(
) for more details.
For IF frequencies other than 300 to 320 kHz and for high frequency deviation and high data rates
(typically
≥
76.8 kBaud) the analog filter must be bypassed by setting FILTER_BYPASS = 1 in the FILTER
register. In this case the blocking performance at 1 MHz and larger offsets will be degraded.
The IF frequency is always the ADC clock frequency divided by 4. The ADC clock frequency should
therefore be as close to 1.2288 MHz as possible.
5.9.2
Receiver Channel Filter Bandwidth
In order to meet different channel spacing requirements, the receiver channel filter bandwidth is
programmable. It can be programmed from 9.6 to 307.2 kHz.
The minimum receiver channel filter bandwidth depends on baud rate, frequency separation and crystal
tolerance.
The signal bandwidth must be smaller than the available receiver channel filter bandwidth. The signal
bandwidth (SBW) can be approximated by (Carson’s rule) shown in
SBW = 2 × f
m
+ 2 × frequency deviation
(13)
Where:
f
m
is the modulating signal.
Copyright © 2006–2015, Texas Instruments Incorporated
Detailed Description
27
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