Texas Instruments C2000 Piccolo LaunchPad Workshop Manual And Lab Manual Download Page 224

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Direct Memory Access (DMA)

9 - 6

C2000 Microcontroller Workshop - Direct Memory Access Controller

DMA Examples

0x4444

0x0000

0x00004003

0x00004002

0x00004001

0x00004000

0x00000000

0x0000F003

0x0000F002

0x0000F001

0x0000F000

0x00000000

0x3333

0x0000

0x2222

0x0000

0x0000F000

0x1111

0x0000

Simple Example

Read/Write Data

Add Burst Step

to Address

Pointer

End Transfer

Add Transfer

Step to Address

Pointer

Moved

“Burst Size”

Words?

Moved

“Transfer Size”

Bursts?

Wait for event

to start/continue

transfer

SRC_ADDR_SHADOW

SRC_ADDR

SRC_BURST_STEP

SRC_TRANSFER_STEP

BURST_SIZE*

TRANSFER_SIZE*

Addr

Value

0x1111

0xF000

0x2222

0xF001

0x3333

0xF002

0x4444

0xF003

Source Registers

0x0001
0x0001

DST_ADDR_SHADOW

DST_ADDR

DST_BURST_STEP

DST_TRANSFER_STEP

Addr

Value

0x4000
0x4001
0x4002
0x4003

Destination Registers

0x00004000

0x0001
0x0001

2 words/burst
2 bursts/transfer

* Size registers are N-1

Objective: Move 4 words from memory location 0xF000 to
memory location 0x4000 and interrupt CPU at end of transfer

Start Transfer

Note: This example could also have been done using 1 word/burst and 4 bursts/transfer, or 4 words/burst

and 1 burst/transfer. This would affect Round-Robin progression, but not interrupts.

Interrupt to PIE

Data Binning Example

ADC Results

L7 SARAM

CH0

CH1

CH2

CH3

CH4

0x0B00

CH0

CH1

CH2

CH3

CH4

CH0

CH1

CH2

CH3

CH4

Conversion Sequence

0xF000

0xF003

0xF006

0xF009

0xF00C

0x0B01

0x0B02

0x0B03

0x0B04

0xF001

0xF004

0xF007

0xF00A

0xF00D

0xF002

0xF005

0xF008

0xF00B

0xF00E

Conversion Sequence

CH0

CH1

CH2

CH3

CH4

Objective: Bin 3 samples of 5 ADC channels, then interrupt the CPU

Summary of Contents for C2000 Piccolo LaunchPad

Page 1: ...C2000 Microcontroller Workshop Workshop Guide and Lab Manual F28xMcuMdw Revision 5 0 May 2014 Technical Training Organization ...

Page 2: ... requirements Customers are responsible for their applications using TI components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards TI assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license ...

Page 3: ...ective of this workshop is to gain a fully understand and a complete working knowledge of the C2000 microcontroller This will be accomplished through detailed presentations and hands on lab exercises The workshop will start with the basic topics and progress to more advanced topics in a logical flow such that each topic and lab exercise builds on the previous one presented At the end of the worksh...

Page 4: ...ess DMA Lab Use DMA to buffer ADC results 10 Control Law Accelerator CLA Lab Use CLA to filter PWM waveform 11 Viterbi Complex Math CRC Unit VCU 12 System Design Lab Run the code from flash memory 13 Communications 14 Support Resources Required Workshop Materials Required Workshop Materials http processors wiki ti com index php C2000_Piccolo_Multi Day_Workshop F28069 Experimenter s Kit TMDXDOCK280...

Page 5: ...er s Kit The kit consists of a controlCARD and USB Docking Station It is a self contained system that plugs into a free USB port on your computer The USB port provides power as well as communicates to the onboard JTAG emulation controller LED LD1 on the Docking Station and LED LD1 on the controlCARD illuminates when the board is powered LED LD2 on the controlCARD is connected to GPIO34 We will be ...

Page 6: ...nalog COMP w DAC FPU 6 Channel DMA CLA VCU ePWM HR ePWM eCAP HR eCAP eQEP SCI SPI I2C LIN McBSP USB External Interface When comparing the Delfino and Piccolo product lines you will notice that the Piccolo F2806x devices share many features with the Delfino product line The Delfino product line is shown in the table by the F2833x column therefore the F28069 being the most feature rich Piccolo devic...

Page 7: ...tion and operating system tasks Unless otherwise noted the terms C28x F28x and F2806x refer to TMS320F2806x devices throughout the remainder of these notes For specific details and differences please refer to the device data sheet and user s guide Module Objectives When this module is complete you should have a basic understanding of the F28x architecture and how all of its components work togethe...

Page 8: ...w 1 1 Module Topics 1 2 What is the TMS320C2000 1 3 TMS320C2000 Internal Bussing 1 4 F28x CPU FPU VCU and CLA 1 5 Special Instructions 1 6 Pipeline Advantage 1 7 F28x CPU FPU VCU Pipeline 1 8 Memory 1 9 Memory Map 1 9 Code Security Module CSM 1 10 Peripherals 1 10 Fast Interrupt Response 1 11 Summary 1 12 ...

Page 9: ... and data bus along with the link between the two buses This type of architecture greatly enhances the performance of the device In the upper left area of the block diagram you will find the memory section which consists of the boot ROM sectored flash and RAM Also you will notice that the six channel DMA has its own set of buses In the lower left area of the block diagram you will find the executi...

Page 10: ...cture Data write Address Bus 32 Program Address Bus 22 Execution R M W Atomic ALU Real Time JTAG Emulation Program Decoder PC XAR0 to XAR7 SP DP X ARAU MPY32x32 XT P ACC ALU Registers Debug Register Bus Result Bus Data Program write Data Bus 32 Data read Address Bus 32 Data read Data Bus 32 FPU R0H R7H Program Memory Data Memory Peripherals VCU VR0 VR8 CLA MR0 MR3 The 32 bit wide data busses provi...

Page 11: ... adds IEEE Single precision 32 bit floating point math operations CLA algorithm execution is independent of the main CPU Fast interrupt service time Single cycle read modify write instructions Unique real time debugging capabilities Data Bus 3 32 bit Timers CPU Register Bus Program Bus 32x32 bit Multiplier R M W Atomic ALU CLA CLA Bus FPU VCU PIE Watchdog The F28x design supports an efficient C en...

Page 12: ...er faster code Uninterruptible Atomic More efficient compiler AND XAR2 1234h 2 words 1 cycles Atomic Read Modify Write MOV AL XAR2 AND AL 1234h MOV XAR2 AL DINT EINT 6 words 6 cycles Standard Load Store Atomics are small common instructions that are non interuptable The atomic ALU capability supports instructions and code that manages tasks and processes These instructions usually execute several ...

Page 13: ...dress R1 R2 E W D2 R1 R2 E W F1 Instruction Address F2 Instruction Content D1 Decode Instruction D2 Resolve Operand Addr R1 Operand Address R2 Get Operand E CPU doing real work W store content to memory H The F28x uses a special 8 stage protected pipeline to maximize the throughput This protected pipeline prevents a write to and a read from the same location from occurring out of order This pipeli...

Page 14: ... negative etc Load Store 0 delay slot instruction 1 delay slot instruction D R E1 E2 W VCU Instruction D R E1 E2 W FPU Instruction Floating point and VCU operations are not pipeline protected Some instructions require delay slots for the operation to complete This can be accomplished by insert NOPs or other non conflicting instructions between operations In the user s guide instructions requiring ...

Page 15: ...AM 4Kw 0x000D00 0x002000 0x005000 0x006000 0x008000 0x008800 0x008C00 0x00A000 0x000E00 0x009000 reserved Data Program FLASH 128Kw PASSWORDS 8w 0x3D7CC0 0x3D7C80 0x3D8000 Boot ROM 32Kw 0x3F7FF8 0x3F8000 0x3FFFFF CSM Protected L0 L1 L2 L3 L4 OTP FLASH ADC CAL Flash Regs in PF0 0x3FFFC0 BROM Vectors 64w ADC OSC cal data DPSARAM L0 L1 L2 L3 accessible by CPU CLA PF 2 4Kw 0x007000 0x014000 0x3D7800 0x...

Page 16: ...d is stored in Flash 128 bits 2128 3 4 x 1038 possible passwords To try 1 password every 8 cycles at 80 MHz it would take at least 1 1 x 1024 years to try all possible combinations L0 DPSARAM 2Kw L1 DPSARAM 1Kw L2 DPSARAM 1Kw L3 DPSARAM 4Kw User OTP 1Kw ADC OSC cal data reserved reserved FLASH 128Kw PASSWORDS 8w reserved 0x008000 0x008800 0x008C00 0x00A000 0x009000 0x3D7800 0x3D7C00 0x3D7C80 0x3D7...

Page 17: ...ast Interrupt Response Manager 96 dedicated PIE vectors No software decision making required Direct access to RAM vectors Auto flags update Concurrent auto context save 28x CPU Interrupt logic 28x CPU INTM 96 Peripheral Interrupts 12x8 96 12 interrupts INT1 to INT12 PIE Register Map PIE module For 96 interrupts T ST0 AH AL PH PL AR1 L AR0 L DP ST1 DBSTAT IER PC msw PC lsw Auto Context Save IFR IER...

Page 18: ... precision floating point unit FPU Hardware Control Law Accelerator CLA Viterbi complex math CRC unit VCU Atomic read modify write instructions Fast interrupt response manager 128Kw on chip flash memory Code security module CSM Control peripherals 12 bit ADC module Comparators Direct memory access DMA Up to 54 shared GPIO pins Communications peripherals ...

Page 19: ...ent environment IDE tools to develop a program Creating projects and setting building options will be covered Use and the purpose of the linker command file will be described Module Objectives Module Objectives Use Code Composer Studio to Create a Project Set Build Options Create a user linker command file which Describes a system s available memory Indicates where sections will be placed in memor...

Page 20: ... Composer Studio 2 4 Edit and Debug Perspective CCSv6 2 5 Target Configuration 2 6 CCSv6 Project 2 7 Creating a New CCSv6 Project 2 8 CCSv6 Build Options Compiler Linker 2 9 CCSv6 Debug Environment 2 10 Creating a Linker Command File 2 12 Sections 2 12 Linker Command Files cmd 2 15 Memory Map Description 2 15 Section Placement 2 16 Summary Linker Command File 2 17 Lab File Directory Structure 2 18...

Page 21: ...bug Compile Graphs Profiling Code Simulator Development Tool External Emulator MCU Board Libraries lnk cmd Build Code Composer Studio includes a built in editor compiler assembler linker and an automatic build process Additionally tools to connect file input and output as well as built in graph displays for output are available Other features can be added using the plug ins capability Numerous mod...

Page 22: ...hardware allocation avoiding the possibility of memory resource conflicts Code Composer Studio Code Composer Studio IDE Integrates edit code generation and debug Single click access using buttons Powerful graphing profiling tools Automated tasks using Scripts Built in access to BIOS functions Based on the Eclipse open source software framework Code Composer Studio CCS is an integrated development ...

Page 23: ...indows toolbars and menus that are appropriate for a specific type of task such as code development or debugging This minimizes clutter to the user interface Edit and Debug Perspective CCSv6 Each perspective provides a set of functionality aimed at accomplishing a specific task Edit Perspective Displays views used during code development C C project editor etc Debug Perspective Displays views used...

Page 24: ...get Configuration tells CCS how to connect to the device It describes the device using GEL files and device configuration files The configuration files are XML files and have a ccxlm file extension Creating a Target Configuration File New Target Configuration File Select connection type Select device Save configuration ...

Page 25: ...r command files Project settings Build options compiler assembler linker and TI RTOS Build configurations Project files contain A project contains files such as C and assembly source files libraries BIOS configuration files and linker command files It also contains project settings such as build options which include the compiler assembler linker and BIOS as well as build configurations To create ...

Page 26: ...roject A graphical user interface GUI is used to assist in creating a new project The GUI is shown in the slide below Creating a New CCSv6 Project File New CCS Project 1 Project Name Location and Device 2 Advanced Settings 3 Project Templates and Examples After a project is created the build options are configured ...

Page 27: ...nk options PROJECT_ROOT specifies the current project directory There is a one to one relationship between the items in the text box on the main page and the GUI check and drop down box selections Once you have mastered the various options you can probably find yourself just typing in the options There are many linker options but these four handle all of the basic needs o filename specifies the ou...

Page 28: ...ow Start debugging Image Name Description Availability New Target Configuration Creates a new target configartion file File New Menu Target Menu Debug Opens a dialog to modify existing debug configura tions Its drop down can be used to access other launching options Debug Toolbar Target Menu Connect Target Connect to hardware targets TI Debug Toolbar Target Menu Debug View Context Menu Terminate A...

Page 29: ...er in the same method or if you are at the end of a method it will continue in the method from which the current method was called The cursor jumps to the decla ration of the method and selects this line Target Menu Debug View Toolbar Step Return Steps out of the current method Target Menu Debug View Toolbar Reset Resets the selected target The drop down menu has various advanced reset options dep...

Page 30: ...ocal variables are in a section stack and the code is placed in a section called txt Sections All code consists of different parts called sections All default section names begin with The compiler has default section names for initialized and uninitialized sections int x 2 int y 7 void main void long z z x y Global vars ebss Init values cinit Local vars stack Code text In the TI code generation to...

Page 31: ...Sections Note During development initialized sections could be linked to RAM since the emulator can be used to load the RAM Sections of a C program must be located in different memories in your target system This is the big advantage of creating the separate sections for code constants and variables In this way they can all be linked located into their proper memory locations in your target embedd...

Page 32: ...by the program Next we need to place the sections that were created by the compiler into the appropriate memory spaces The uninitialized sections ebss and stack need to be placed into RAM while the initialized sections cinit and txt need to be placed into flash Placing Sections in Memory ebss cinit text Memory M0SARAM 0x400 0x00 0000 0x3E 8000 0x00 0400 M1SARAM 0x400 FLASH 0x10000 Sections stack L...

Page 33: ...a out file This is the file that will be loaded into the microcontroller As an option we can generate a map file This map file will provide a summary of the link process such as the absolute address and size of each section Linking Linker Link cmd map obj out Memory description How to place s w into h w Memory Map Description The MEMORY section describes the memory configuration of the target syst...

Page 34: ... M1SARAM PAGE 1 MEMORY PAGE 0 Program Memory FLASH origin 0x3E8000 length 0x10000 PAGE 1 Data Memory M0SARAM origin 0x000000 length 0x400 M1SARAM origin 0x000400 length 0x400 A linker command file consists of two sections a memory section and a sections section In the memory section page 0 defines the program memory space and page 1 defines the data memory space Each memory block is given a unique...

Page 35: ...arly it will combine all like sections Beginning with the first section listed the linker will place it into the specified memory segment Summary Linker Command File The linker command file cmd contains the inputs commands for the linker This information is summarized below Linker Command File Summary Memory Map Description Name Location Size Sections Description Directs software sections into nam...

Page 36: ... always available for reuse if a file becomes corrupted Original Source Files Source Files are Added to the Project Folder Supporting Files and Libraries Note CCSv6 will automatically add ALL files contained in the folder where the project is created Easier to make projects portable PROJECT_ROOT provides an anchor point for paths to files that travel with the project Easier to maintain and update ...

Page 37: ...or slot Using the supplied USB cable plug the USB Standard Type A connector into the computer USB port and the USB Standard Type B connector into the Docking Station On the Docking Station move switch SW1 to the USB position This will power the Docking Station and controlCARD using the power supplied by the computer USB port Additionally this USB port will provide the JTAG communication link betwe...

Page 38: ...et configuration dialog box On the menu bar click File New Target Configuration File In the file name field type F28069_ExpKit ccxml This is just a descriptive name since multiple target configuration files can be created Leave the Use shared location box checked and select Finish 4 In the next window that appears select the emulator using the Connection pull down list and choose Texas Instruments...

Page 39: ...iles The next step is to add the source files to the project 11 To add the source files to the project right click on Lab2 in the Project Explorer window and select Add Files or click Project Add Files and make sure you re looking in C C28x Labs Lab2 Files With the files of type set to view all files select Lab2 c and Lab2 cmd then click OPEN A File Operation window will open choose Copy files and...

Page 40: ...eneration Hover your mouse over each button as you read the following descriptions Button Name Description_____________________________________ 1 Build Full build and link of all source files 2 Debug Automatically build link load and launch debug session 19 Click the Build button and watch the tools run in the Console window Check for errors in the Problems window we have deliberately put an error...

Page 41: ...cal variables actually live on the stack You can also view local variables in a memory browser by setting the address to SP after the code function has been entered 25 We can also add global variables to the Expressions window if desired Let s add the global variable z Click the Expressions tab at the top of the window In the empty box in the Expression column Add new expression type z and then en...

Page 42: ...er Command File 2 24 C2000 Microcontroller Workshop Programming Development Environment 28 Next close the project by right clicking on Lab2 in the Project Explorer window and select Close Project End of Exercise ...

Page 43: ... repetitive task the C code header files were created to make this a less complicated task The F2806x C code header files are part of a library consisting of C functions macros peripheral structures and variable definitions Together this set of files is known as the header files Registers and the bit fields are represented by structures C functions and macros are used to initialize or modify the s...

Page 44: ...rs Header Files 3 1 Module Topics 3 2 Traditional and Structure Approach to C Coding 3 3 Naming Conventions 3 7 F2806x C Code Header Files 3 9 Peripheral Structure h File 3 9 Global Variable Definitions File 3 11 Mapping Structures to Memory 3 12 Linker Command File 3 12 Peripheral Specific Routines 3 13 Summary 3 14 ...

Page 45: ...e in many cases Advantages Simple fast and easy to type Variable names exactly match register names easy to remember In the traditional approach to C coding we used a define to assign the address of the register and referenced it with a pointer The first line of code on this slide we are writing to the entire register with a 16 bit value The second line we are ORing a bit field Advantages Simple f...

Page 46: ...t slide Generates most efficient code on C28x The structure approach to C coding uses the peripheral register header files First a peripheral is specified followed by a control register Then you can modify the complete register or selected bits This is almost self commented code The first line of code on this slide we are writing to the entire register The second line of code we are modifying a bi...

Page 47: ...ch to coding using define we can only view the complete register values As an example notice the control register ADCCTL1 has a value of 0x40E4 We would need to refer to the reference guide to know the settings of the individual bit fields Expressions Window using Structures With the structure approach we can add the peripheral to an expressions window allowing us to ...

Page 48: ...0 OR 4 0x0010 MOVL XAR4 0x010000 MOVL 2 XAR4 AND 4 0xFFEF 5 words 5 cycles Easy to read the code w o comments Bit mask built in to structure C28x Compiler v5 0 1 with g and either o1 o2 or o3 optimization level Compare with the define Approach The define approach relies heavily on less efficient pointers for random memory access and often does not take advantage of C28x atomic operations C Source ...

Page 49: ...its of 32 bit register PeripheralName RegisterName bit FieldName Access specified bit fields of register Notes 1 PeripheralName are assigned by TI and found in the F2806x header files They are a combination of capital and small letters i e CpuTimer0Regs 2 RegisterName are the same names as used in the data sheet They are always in capital letters i e TCR TIM TPR 3 FieldName are the same names as u...

Page 50: ...u type AdcRegs Then when you type a a window opens up allowing you to select a control register In this example ADCCTL1 is selected Then when you type the a window opens up allowing you to select all or bit In this example bit is selected Then when you type the a window opens up allowing you to select a bit field In this example RESET is selected And now the structure is completed ...

Page 51: ... Package located at C TI controlSUITE device_support A peripheral is programmed by writing values to a set of registers Sometimes individual fields are written to as bits or as bytes or as entire words Unions are used to overlap memory register so the contents can be accessed in different ways The header files group all the registers belonging to a specific peripheral Peripheral data structures ca...

Page 52: ...aster reset Allow access to the bit fields or entire register union ADCCTL1_REG Uint16 all struct ADCCTL1_BITS bit ADC External References Function Declarations extern volatile struct ADC_REGS AdcRegs Next we will discuss the steps needed to use the header files with your project The h files contain the bit field structure definitions for each peripheral register Peripheral Structure h files 2 of ...

Page 53: ...f the structure for each peripheral Each structure is placed in its own section using a DATA_SECTION pragma to allow linking to the correct memory see next slide Add this file to your CCS project F2806x_GlobalVariableDefs c include F2806x_Device h pragma DATA_SECTION AdcRegs AdcRegsFile volatile struct ADC_REGS AdcRegs F2806x_GlobalVariableDefs c The global variable definition file declares a glob...

Page 54: ... ADC origin 0x007100 length 0x000080 SECTIONS AdcRegsFile ADC PAGE 1 F2806x_Headers_nonBIOS cmd include F2806x_Device h pragma DATA_SECTION AdcRegs AdcRegsFile volatile struct ADC_REGS AdcRegs F2806x_GlobalVariableDefs c The header file package has two linker command file versions one for non BIOS projects and one for BIOS projects This linker command file is used to link each structure to the add...

Page 55: ...c C functions are used to initialize the peripherals They are used by adding the appropriate c file to the project Peripheral Specific Examples Example projects for each peripheral Helpful to get you started The peripheral register header file package includes example projects for each peripheral This can be very helpful to getting you started ...

Page 56: ... the correct header file package for your device Go to http www ti com and enter controlSUITE in the keyword search box F2806x F2803x F2802x F2833x and F2823x F280x and F2801x F2804x F281x In summary the peripheral register header files allow for easier code development they are easy to use generates the most efficient code works great with Code Composer Studio and TI has already done the work for...

Page 57: ...upts Introduction This module describes the interrupt process and explains how the Peripheral Interrupt Expansion PIE works Module Objectives Module Objectives Describe the F28x reset process List the event sequence during an interrupt Describe the F28x interrupt structure ...

Page 58: ...t Mode 4 6 Reset Code Flow Summary 4 6 Emulation Boot Mode using Code Composer Studio GEL 4 7 Getting to main 4 8 Interrupts 4 9 Interrupt Processing 4 10 Interrupt Flag Register IFR 4 11 Interrupt Enable Register IER 4 11 Interrupt Global Mask Bit INTM 4 12 Peripheral Interrupt Expansion PIE 4 12 PIE Block Initialization 4 14 Interrupt Signal Flow Summary 4 16 Interrupt Response and Latency 4 17 ...

Page 59: ...active To XRS pin F28x core XRS Power on Reset Brown out Reset Missing Clock Detect Logic shown is functional representation not actual implementation There are various reset sources available for this device an external reset pin watchdog timer reset power on reset which generates a device reset during power up conditions brownout reset which generates a device reset if the power supply drops bel...

Page 60: ... 0 Reset ENPIE 0 INTM 1 YES NO Emulator Connected After reset the PIE block is disabled and the global interrupt line is disabled The reset vector is fetched from the boot ROM and the bootloader process begins Then the bootloader determines if the emulator is connected by checking the JTAG test reset line If the emulator is connected we are in emulation boot mode The boot is then determined by two...

Page 61: ...ASH Boot Mode SCI SPI I2C OTP CAN FLASH OTP_BMODE 0x0001 0x0004 0x0005 0x0006 0x0007 other NO NO YES YES OTP_KEY 0x005A In emulation boot mode first the EMU_KEY register is checked to see if it has a value of 0x55AA If either EMU_KEY or EMU_BMODE are invalid the wait boot mode is used These values can then be modified using the debugger and a reset issued to restart the boot process This can be co...

Page 62: ...GPIO pins 37 and 34 determine if the boot mode is parallel I O SCI or wait The default unconnected pins would set the boot mode to GetMode In GetMode first the OTP_KEY register is checked to see if it has a value of 0x005A An unprogrammed OTP is set to the FLASH boot mode as expected If the OTP_KEY register has a value of 0x005A then the hex value in the OTP_BMODE register determines the boot mode...

Page 63: ...on is called each time the device is reset This function can be modified to include a call to set the device to Boot to SARAM emulation mode automatically if desired OnReset int nErrorCode C28x_Mode Unlock_CSM Device_Cal CLA_Clock_Enable Enable CLA clock EMU_BOOT_SARAM Set EMU Boot Variables Boot to SARAM EMU_BOOT_FLASH Set EMU Boot Variables Boot to flash The GEL file also provides a function to ...

Page 64: ...N_M0 origin 0x000000 length 0x000002 SECTIONS codestart BEGIN_M0 PAGE 0 Linker cmd Note the above example is for boot mode set to M0 SARAM to run out of Flash the codestart section would be linked to the entry point of the Flash memory block After reset how do we get to main When the bootloader process is completed a branch to the compiler runtime support library is located at the code entry point...

Page 65: ...ces include the general purpose timers 0 1 and 2 and all of the peripherals on the device External interrupt sources include the three external interrupt lines the trip zones and the external reset pin The core has 14 interrupt lines As you can see the number of interrupt sources exceeds the number of interrupt lines on the core The PIE or Peripheral Interrupt Expansion block is connected to the c...

Page 66: ...rupt switch This switch must be closed for any interrupts to propagate into the core The next layer out is the interrupt enable register The appropriate interrupt line switch must be closed to allow an interrupt through The interrupt flag register gets set when an interrupt occurs Once the core starts processing an interrupt the INTM switch opens to avoid nested interrupts and the flag is cleared ...

Page 67: ...terrupt is acknowledged by CPU Register cleared on reset Manual setting clearing IFR extern cregister volatile unsigned int IFR IFR 0x0008 set INT4 in IFR IFR 0xFFF7 clear INT4 in IFR Interrupt Enable Register IER Interrupt Enable Register IER RTOSINT DLOGINT INT14 INT13 INT12 INT11 INT10 INT9 8 9 10 11 12 13 14 15 INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1 0 1 2 3 4 5 6 7 Enable Set IER Bit 1 Disabl...

Page 68: ...terrupt Expansion PIE IFR IER INTM 28x Core Core Interrupt logic PIE module for 96 Interrupts INT1 y interrupt group INT2 y interrupt group INT3 y interrupt group INT4 y interrupt group INT5 y interrupt group INT6 y interrupt group INT7 y interrupt group INT8 y interrupt group INT9 y interrupt group INT10 y interrupt group INT11 y interrupt group INT12 y interrupt group INT1 INT12 12 Interrupts 96...

Page 69: ...EPWM4 _INT EPWM3 _INT EPWM2 _INT EPWM1 _INT INT4 HRCAP2 _INT HRCAP1 _INT ECAP3 _INT ECAP2 _INT ECAP1 _INT INT5 HRCAP4 _INT HRCAP3 _INT EQEP2 _INT EQEP1 _INT INT6 MXINTA MRINTA SPITX INTB SPIRX INTB SPITX INTA SPIRX INTA INT7 DINTCH6 DINTCH5 DINTCH4 DINTCH3 DINTCH2 DINTCH1 INT8 I2CINT2A I2CINT1A INT9 SCITX INTB SCIRX INTB SCITX INTA SCIRX INTA INT10 ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 A...

Page 70: ...t IFR for XINT1 in PIE group 1 PieCtrlRegs PIEIER3 bit INTx2 1 enable EPWM2_INT in PIE group 3 PieCtrlRegs PIEACK all 0x0004 acknowledge the PIE group 3 PieCtrlRegs PIECTRL bit ENPIE 1 enable the PIE PIE Block Initialization PIE Block Initialization CPU Initialization InitPieCtrl Main c Initialize PIE_RAM memcpy PieCtrl c Enable PIE Block PieCtrlRegs PIECTRL bit ENPIE 1 Base Vectors PieVect c PIE_...

Page 71: ...ch asm rts2800_fpu32 lib Boot option determines code execution entry point interrupt void name void DefaultIsr c Interrupt sect codestart In summary the PIE initialization code flow is as follows After the device is reset and executes the boot code the selected boot option determines the code entry point This figure shows two different entry points The one on the left is for memory block M0 and th...

Page 72: ...Vector Table INTx y name interrupt void name void DefaultIsr c Core INTx For peripheral interrupts where x 1 to 12 and y 1 to 8 In summary the following steps occur during an interrupt process First a peripheral interrupt is generated and the PIE interrupt flag register is set If the PIE interrupt enable register is enabled then the core interrupt flag register will be set Next if the core interru...

Page 73: ...PC Loads PC with int vector address Clear other status bits Clear LOOP EALLOW IDLESTAT Interrupt Latency Latency Depends on wait states INTM etc Maximum latency Recognition delay 3 SP alignment 1 interrupt placed in pipeline 4 Minimum latency to when real work occurs in the ISR Internal interrupts 14 cycles External interrupts 16 cycles Get vector and place in PC 3 reg pairs saved 3 F1 F2 D1 of IS...

Page 74: ...Interrupts 4 18 C2000 Microcontroller Workshop Reset and Interrupts ...

Page 75: ...SC PLL based clock module and watchdog timer Also the general purpose digital I O ports external interrups various low power modes and the EALLOW protected registers will be covered Module Objectives Module Objectives OSC PLL Clock Module Watchdog Timer General Purpose Digital I O External Interrupts Low Power Modes Register Protection ...

Page 76: ...nitialization Module Topics System Initialization 5 1 Module Topics 5 2 Oscillator PLL Clock Module 5 3 Watchdog Timer 5 7 General Purpose Digital I O 5 12 External Interrupts 5 16 Low Power Modes 5 17 Register Protection 5 19 Lab 5 System Initialization 5 21 ...

Page 77: ... MUX 1 n DIVSEL OSC1CLK OSC2CLK EXTCLK Watchdog Module WDCLK CPUTMR2CLK default The oscillator PLL clock module has two internal 10 MHz oscillators and the availability of an external oscillator or crystal This provides redundancy in case an oscillator fails as well as the ability to use multiple oscillators The asterisks in the multiplexers show the default settings This module has the capability...

Page 78: ...OUT 12 1 1 1 SYSCLKOUT 14 LSBs in reg others reserved A clock source can be fed directly into the core or multiplied using the PLL The PLL gives us the capability to use the internal 10 MHz oscillator multiplied by 18 2 and run the device at the full 90 MHz clock frequency If the input clock is removed after the PLL is locked the input clock failed detect circuitry will issue a limp mode clock of ...

Page 79: ... 1 ignores HALT Mode Watchdog HALT Mode Ignore 0 automatic turn on off 1 ignores HALT Mode XCLKIN Off 0 on 1 off Crystal Oscillator Off 0 on 1 off NMI Reset 0 no delay 1 delay 0 default Clock Control Register SysCtrlRegs CLKCTL lab file SysCtrl c 7 5 4 3 2 1 0 TMR2CLKSRCSEL WDCLK SRCSEL OSCCLK SRC2SEL OSCCLK SRCSEL TMR2CLKPRESCALE Oscillator Clock Source 0 internal OSC1 1 external or internal OSC2...

Page 80: ...CtrlRegs PCLKCR1 reserved reserved reserved reserved reserved 15 14 13 11 10 9 8 12 7 6 5 4 3 2 1 0 SysCtrlRegs PCLKCR2 SCIB ENCLK MCBSPA ENCLK reserved ECAP2 ENCLK ECAP3 ENCLK EQEP2 ENCLK EPWM8 ENCLK reserved reserved reserved reserved HRCAP1 ENCLK HRCAP2 ENCLK HRCAP3 ENCLK HRCAP4 ENCLK reserved reserved reserved 15 14 13 11 10 9 8 12 CPUTIMER2 ENCLK CPUTIMER1 ENCLK CPUTIMER0 ENCLK reserved 7 6 5...

Page 81: ...h a 10 MHz WDCLK The watchdog timer provides a safeguard against CPU crashes by automatically initiating a reset if it is not serviced by the CPU at regular intervals In motor control applications this helps protect the motor and drive electronics when control is lost due to a CPU lockup Any CPU reset will revert the PWM outputs to a high impedance state which should turn off the power converters ...

Page 82: ...ded by 512 and prescaled if desired The watchdog disable switch allows the watchdog to be enabled and disabled The watchdog override switch is a safety mechanism and once closed it can only be open by resetting the device During initialization 101 is written into the watchdog check bit fields Any other values will cause a reset or interrupt During run time the correct keys must be written into the...

Page 83: ...Hz 512 256 13 11 ms reset default Watchdog Timer Control Register SysCtrlRegs WDCR lab file Watchdog c WDFLAG WDDIS 7 6 5 3 2 0 WDPS WDCHK Logic Check Bits Write as 101 or reset immediately triggered WD Prescale Selection Bits Watchdog Disable Bit Write 1 to disable Functions only if WD OVERRIDE bit in SCSR is equal to 1 reserved 15 8 WD Flag Bit Gets set when the WD causes a reset Writing a 1 cle...

Page 84: ... this catches main code crashes and also ISR crashes reserved 7 0 15 8 WDKEY WDKEY Write Results Sequential Step 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Value Written to WDKEY AAh AAh 55h 55h 55h AAh AAh 55h AAh 55h 23h AAh 55h AAh Result No action No action WD counter enabled for reset on next AAh write WD counter enabled for reset on next AAh write WD counter enabled for reset on next AAh write WD coun...

Page 85: ... from being disabled 0 WDDIS bit in WDCR has no effect WD cannot be disabled 1 WDDIS bit in WDCR can disable the watchdog This bit is a clear only bit write 1 to clear The reset default of this bit is a 1 0 1 2 15 3 WDOVERRIDE WDENINT WDINTS reserved WD Enable Interrupt WD Interrupt Status read only 0 active 1 not active 0 WD generates a MCU reset 1 WD generates a WDINT interrupt ...

Page 86: ... GPIO 48 to 63 Each general purpose I O pin has a maximum of four options either general purpose I O or up to three possible peripheral pin assignments This is selected using the GPIO port multiplexer If the pin is set to GPIO the direction register sets it as an input or an output The input qualification will be explained shortly F2806x GPIO Pin Block Diagram lab file Gpio c 01 00 MUX Control Bit...

Page 87: ...multiplexer can be set to select up to three other possible peripheral pin assignments Also the pin has an option for an internal pull up F2806x GPIO Input Qualification Qualification available on ports A B only Individually selectable per pin no qualification peripherals only sync to SYSCLKOUT only qualify 3 samples qualify 6 samples AIO pins are fixed as sync to SYSCLKOUT Input Qualification pin...

Page 88: ...06x GPIO Control Registers GpioCtrlRegs register lab file Gpio c Register Description GPACTRL GPIO A Control Register GPIO 0 31 GPAQSEL1 GPIO A Qualifier Select 1 Register GPIO 0 15 GPAQSEL2 GPIO A Qualifier Select 2 Register GPIO 16 31 GPAMUX1 GPIO A Mux1 Register GPIO 0 15 GPAMUX2 GPIO A Mux2 Register GPIO 16 31 GPADIR GPIO A Direction Register GPIO 0 31 GPAPUD GPIO A Pull Up Disable Register GP...

Page 89: ...r GPIO 0 31 GPACLEAR GPIO A Data Clear Register GPIO 0 31 GPATOGGLE GPIO A Data Toggle GPIO 0 31 GPBDAT GPIO B Data Register GPIO 32 63 GPBSET GPIO B Data Set Register GPIO 32 63 GPBCLEAR GPIO B Data Clear Register GPIO 32 63 GPBTOGGLE GPIO B Data Toggle GPIO 32 63 AIODAT ANALOG I O Data Register AIO 0 15 AIOSET ANALOG I O Data Set Register AIO 0 15 AIOCLEAR ANALOG I O Data Clear Register AIO 0 15...

Page 90: ...er resets to zero each time the interrupt occurs External Interrupt Registers Pin Selection Register chooses which pin the signal comes out on Only one pin can be assigned to each interrupt signal Configuration Register controls the enable disable and polarity Counter Register holds the interrupt counter Interrupt Pin Selection Register Configuration Register Counter Register GpioIntRegs register ...

Page 91: ...0 WDINTE QUALSTDBY reserved Low Power Mode Selection 00 Idle default 01 Standby 1x Halt Wake from STANDBY GPIO signal qualification 000000 2 OSCCLKs 000001 3 OSCCLKs 111111 65 OSCCLKS default 15 Watchdog Interrupt wake device from STANDBY 0 disable default 1 enable Low Power Mode Entering 1 Set LPM bits 2 Enable desired exit interrupt s 3 Execute IDLE instruction 4 The power down sequence of the h...

Page 92: ... yes yes yes GPIO Low Power Wakeup Select SysCtrlRegs GPIOLPMSEL Wake device from HALT and STANDBY mode GPIO Port A 0 disable default 1 enable 0 GPIO2 GPIO14 GPIO8 GPIO11 GPIO5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GPIO0 GPIO1 GPIO4 GPIO3 GPIO9 GPIO6 GPIO10 GPIO7 GPIO12 GPIO13 GPIO15 16 GPIO18 GPIO30 GPIO24 GPIO27 GPIO21 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 GPIO16 GPIO17 GPIO20 GPIO19 GPIO25...

Page 93: ... a peripheral register and then read a different register for the same peripheral e g write to control read from status register Peripheral Frame Registers PF0 eCAN COMP ePWM eCAP eQEP LIN GPIO PF1 System Control SPI SCI Watchdog XINT ADC I2C Protected address 0x4000 0x7FFF EALLOW Protection 1 of 2 EALLOW stands for Emulation Allow Code access to protected registers allowed only when EALLOW 1 in t...

Page 94: ...DIS disable protected register access EALLOW register access C code example Device Emulation Flash Code Security Module PIE Vector Table LIN some registers eCANA B control registers only mailbox RAM not protected ePWM1 7 and COMP1 3 some registers GPIO control registers only System Control See device datasheet and peripheral users guides for detailed listings The following registers are protected ...

Page 95: ...hdog operation by having the watchdog cause a reset In the second part of the lab exercise the PIE vectors will be added and tested by using the watchdog to generate an interrupt This lab will make use of the F2806x C code header files to simplify the programming of the device as well as take care of the register definitions and addresses Please review these files and make use of them in the futur...

Page 96: ...ject The bootloader must branch to the codestart section at the end of the boot process Recall that the emulation boot mode M0 SARAM branches to address 0x000000 upon bootloader completion Modify the linker command file Lab_5_6_7 cmd to create a new memory block named BEGIN_M0 origin 0x000000 length 0x0002 in program memory You will also need to modify the existing memory block M0SARAM in data mem...

Page 97: ... and set a breakpoint by double clicking in the line number field to the left of the code line Notice that line is highlighted with a blue dot indicating that the breakpoint has been set Alternately you can set a breakpoint on the line by right clicking the mouse and selecting Breakpoint Code Composer Studio Breakpoint The breakpoint is set to prove that the watchdog is disabled If the watchdog ca...

Page 98: ... C C28x Labs Lab5 Files DefaultIsr_5 c PieCtrl c PieVect c Check your files list to make sure the files are there 19 In Main_5 c add code to call the InitPieCtrl function There are no passed parameters or return values so the call code is simply InitPieCtrl 20 Using the PIE Interrupt Assignment Table shown in the previous module find the location for the watchdog interrupt WAKEINT This will be use...

Page 99: ...ect Run To Line 27 Run your code Where did your code stop Are the results as expected If things went as expected your code should stop at the ESTOP0 instruction in the WAKEINT ISR Terminate Debug Session and Close Project 28 Terminate the active debug session using the Terminate button This will close the debugger and return CCS to the CCS Edit Perspective view 29 Next close the project by right c...

Page 100: ...Lab 5 System Initialization 5 26 C2000 Microcontroller Workshop System Initialization ...

Page 101: ...tiplexer has its own dedicated sample and hold circuit Therefore sequential as well as simultaneous sampling is supported The ADC system is start of conversion SOC based where each independent SOCx where x 0 to 15 register configures the trigger source that starts the conversion the channel to convert and the acquisition sample window size Up to 16 results registers are used to store the conversio...

Page 102: ...ics 6 2 Analog to Digital Converter 6 3 ADC Block and Functional Diagrams 6 3 ADC Triggering 6 4 ADC Conversion Priority 6 6 ADC Clock and Timing 6 8 ADC Converter Registers 6 9 Signed Input Voltages 6 14 ADC Calibration and Reference 6 15 Comparator 6 17 Comparator Block Diagram 6 17 Comparator Registers 6 18 Lab 6 Analog to Digital Converter 6 19 ...

Page 103: ...CB x 1 to 8 CPU Timer 0 1 2 SOCx Signal ADCINT1 ADCINT2 SOCx Configuration Registers The ADC module is based around a 12 bit converter There are 16 input channels and 16 result registers The SOC configuration registers select the trigger source channel to convert and the acquisition prescale window size The triggers include software by selecting a bit CPU timers 0 1 and 2 EPWMA and EPWMB 1 through...

Page 104: ...EL2 INTSELxNy ADCRESULTx ADC Triggering Example ADC Triggering sequential sampling Sample A2 B3 A7 when ePWM1 SOCB is generated and then generate ADCINT1 Channel A2 Sample 7 cycles Result0 Channel B3 Sample 10 cycles Result1 Channel A7 Sample 8 cycles Result2 SOC0 SOC1 SOC2 no interrupt no interrupt ADCINT1 SOCB ETPWM1 Then after above sample A0 B0 A5 continuously and generate ADCINT2 Channel A0 S...

Page 105: ...terrupt Result2 Result3 Channel A2 B2 Sample 7 cycles SOC4 no interrupt Result4 Result5 Channel A3 B3 Sample 7 cycles SOC6 Result6 Result7 Channel A4 B4 Sample 7 cycles SOC8 no interrupt Result8 Result9 Channel A5 B5 Sample 7 cycles SOC10 no interrupt Result10 Result11 Channel A6 B6 Sample 7 cycles SOC12 no interrupt Result12 Result13 Channel A7 B7 Sample 7 cycles SOC14 Result14 Result15 ADCINT1 A...

Page 106: ...gh priority SOC will interrupt the round robin wheel after current conversion completes and insert itself as the next conversion After its conversion completes the round robin wheel will continue where it was interrupted Conversion Priority Functional Diagram Round Robin Pointer Points to the last converted round robin SOCx and determines order of conversions SOC Priority Determines cutoff point f...

Page 107: ...OC2 is converted RRPOINTER points to SOC2 SOC3 is now highest RR priority SOCPRIORITY configured as 0 RRPOINTER configured as 15 SOC0 is highest RR priority High Priority Example SOC 4 SOC 5 SOC 0 SOC 6 SOC 7 SOC 8 SOC 9 SOC 10 SOC 11 SOC 12 SOC 13 SOC 14 SOC 15 RRPOINTER SOC 1 SOC 2 SOC 3 High Priority SOC7 trigger received SOC7 is converted RRPOINTER points to SOC7 SOC8 is now highest RR priorit...

Page 108: ... PLLSTS DIVSEL bits 10b 2 To CPU sampling window ACQ_PS 1 1 ADCCLK PCLKCR0 ADCENCLK 1 PLLCR DIV bits 10010b x18 ADCCTL2 CLKDIV bits 001b 2 ADC Timing Sequential Sampling 7 Clocks Sample 6 Clocks 7 Clocks Convert 2 Clocks Write 2 Clocks Latch Generate Early Interrupt Generate Late Interrupt Start Sampling Next Channel Max Continuous Sampling 45 MHz 13 cycles 1 sample 3 46 MSPS Note Sampling window ...

Page 109: ...le Adc c ADCCTL1 Control 1 Register ADCCTL2 Control 2 Register ADCSOCxCTL SOC0 to SOC15 Control Registers ADCINTSOCSELx Interrupt SOC Selection 1 and 2 Registers ADCSAMPLEMODE Sampling Mode Register ADCSOCFLG1 SOC Flag 1 Register ADCSOCFRC1 SOC Force 1 Register ADCSOCOVF1 SOC Overflow 1 Register ADCSOCOVFCLR1 SOC Overflow Clear 1 Register INTSELxNy Interrupt x and y Selection Registers ADCINTFLG I...

Page 110: ...DCINB4 05h ADCINA5 0Dh ADCINB5 06h ADCINA6 0Eh ADCINB6 07h ADCINA7 0Fh ADCINB7 ADC Control Register 1 AdcRegs ADCCTL1 ADC Power Down 0 analog circuitry powered down 1 analog circuitry powered up ADC Reference Select 0 internal 1 external VREFHI VREFLO ADCBGPWN ADCREFPWD ADCPWN reserved 7 Lower Register VREFLO CONV INTPULSE POS 6 5 4 3 2 0 ADC Bandgap Power Down 0 bandgap circuitry powered down 1 b...

Page 111: ...DCINA0 B0 1h ADCINA1 1h ADCINA1 B1 2h ADCINA2 2h ADCINA2 B2 3h ADCINA3 3h ADCINA3 B3 4h ADCINA4 4h ADCINA4 B4 5h ADCINA5 5h ADCINA5 B5 6h ADCINA6 6h ADCINA6 B6 7h ADCINA7 7h ADCINA7 B7 8h ADCINB0 8h Fh invalid 9h ADCINB1 Ah ADCINB2 Bh ADCINB3 Ch ADCINB4 Dh ADCINB5 Eh ADCINB6 Fh ADCINB7 Sequential S M SIMULENx 0 Simultaneous S M SIMULENx 1 00h software 01h CPU Timer 0 02h CPU Timer 1 03h CPU Timer ...

Page 112: ...upt Select Selects which if any ADCINT triggers SOCx 00 no ADCINT will trigger SOCx TRIGSEL field determines SOCx trigger 01 ADCINT1 will trigger SOCx TRIGSEL field ignored 10 ADCINT2 will trigger SOCx TRIGSEL field ignored 11 invalid selection ADC Sample Mode Register AdcRegs ADCSAMPLEMODE reserved 15 8 7 SIMULEN14 SIMULEN12 SIMULEN10 SIMULEN8 SIMULEN6 SIMULEN4 SIMULEN2 SIMULEN0 6 5 4 3 2 1 0 Sim...

Page 113: ...ed SOC5 highest priority 05h SOC5 last converted SOC6 highest priority 06h SOC6 last converted SOC7 highest priority 07h SOC7 last converted SOC8 highest priority 08h SOC8 last converted SOC9 highest priority 09h SOC9 last converted SOC10 highest priority 0Ah SOC10 last converted SOC11 highest priority 0Bh SOC11 last converted SOC12 highest priority 0Ch SOC12 last converted SOC13 highest priority ...

Page 114: ...esponding ADCRESULTx and ADCRESULTx 1 registers Input Digital AdcResult Voltage Result ADCRESULTx 3 3 FFFh 0000 1111 1111 1111 1 65 7FFh 0000 0111 1111 1111 0 00081 1h 0000 0000 0000 0001 0 0h 0000 0000 0000 0000 LSB MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AdcResult ADCRESULTx x 0 15 Signed Input Voltages How Can We Handle Signed Input Voltages Example 1 65 V Vin 1 65 V 1 Add 1 65 volts to the a...

Page 115: ... main void Device_cal call Device_cal Manual ADC Calibration If the offset and gain errors in the datasheet are unacceptable for your application or you want to also compensate for board level errors e g sensor or amplifier offset you can manually calibrate Offset error Compensated in analog with the ADCOFFTRIM register No reduction in full scale range Configure input B5 to VREFLO set ADCOFFTRIM t...

Page 116: ...not sufficient for your application there is the option to use an external reference External reference will scale an input voltage range from VREFLO to VREFHI ratiometric The reference value changes the 0 3 3 V full scale range of the ADC The ADCREFSEL in ADCCTL1 controls the reference choice See device datasheet for exact specifications and ADC reference hardware connections 2 0 15 5 ADCREFSEL A...

Page 117: ... B5 B6 B7 This device has three analog comparators that share the input pins with the analog to digital converter module If neither the ADC or comparator input pins are needed the input pins can be used as analog I O pins As you can see one of the inputs to the comparator comes directly from the input pin and the other input can be taken from the input pin or the 10 bit digital to analog converter...

Page 118: ...erved 15 10 DACVAL 9 0 Scales output of DAC from 0 1023 Value 0 3FFh AdcRegs DACVAL DAC Value Register reserved 15 1 COMPSTS 0 AdcRegs COMPSTS Compare Output Status Register Logical latched value of the comparator reserved 15 9 7 3 SYNCSEL QUALSEL CMPINV COMPSOURCE COMPDACE 8 2 1 0 AdcRegs COMPCTL Compare Control Register Synchronization Select Output before being feed to ETPWM GPIO blocks 0 Async...

Page 119: ...it where x 0 to 15 in the ADC SOC Force 1 Register ADCSOCFRC1 causes a software initiated conversion 2 Automatically triggered on user selectable conditions a CPU Timer 0 1 2 interrupt b ePWMxSOCA ePWMxSOCB where x 1 to 7 ePWM underflow CTR 0 ePWM period match CTR PRD ePWM underflow or period match CTR 0 or PRD ePWM compare match CTRU D CMPA B c ADC interrupt ADCINT1 or ADCINT2 triggers SOCx where...

Page 120: ...lide Lab 6 Code Flow Diagram Start General Initialization PLL and clocks watchdog configure GPIO setup PIE initialization ADC Initialization convert channel A0 on ePWM2 period match send interrupt on EOC to trigger ADC ISR setup a results buffer in memory ePWM2 Initialization clear counter set period register set to trigger ADC on period match set the clock prescaler enable the timer Main Loop whi...

Page 121: ...ns The InitEPwm function is used to configure ePWM2 to trigger the ADC at a 50 kHz rate Details about the ePWM and control peripherals will be discussed in the next module 3 Edit Adc c to configure SOC0 in the ADC as follows SOC0 converts input ADCINA0 in single sample mode SOC0 has a 7 cycle acquisition window SOC0 is triggered by the ePWM2 SOCA SOC0 triggers ADCINT1 on end of conversion All SOCs...

Page 122: ...and halt it after a few seconds Verify that the ADC results buffer contains the expected value of 0x0000 Note that you may not get exactly 0x0000 if the device you are using has positive offset error 12 Adjust the connector wire to connect the ADCINA0 pin ADC A0 to 3 3V pin GPIO 20 on the Docking Station Note pin GPIO 20 has been set to 1 in Gpio c Then run the code again and halt it after a few s...

Page 123: ...d select Remove All Measurement Marks or Ctrl Alt M Using Real time Emulation Real time emulation is a special emulation feature that offers two valuable capabilities A Windows within Code Composer Studio can be updated at up to a 10 Hz rate while the MCU is running This not only allows graphs and watch windows to update but also allows the user to change values in watch or memory windows and have...

Page 124: ...ith_Reset reset CPU enter real time mode run CPU Run_Realtime_with_Restart restart CPU enter real time mode run CPU Full_Halt exit real time mode halt CPU Full_Halt_with_Reset exit real time mode halt CPU reset CPU These Script functions are executed by clicking Scripts Realtime Emulation Control Function In the remaining lab exercises we will be using the first and third above Script functions to...

Page 125: ...erminate button This will close the debugger and return CCS to the CCS Edit Perspective view 26 Next close the project by right clicking on Lab6 in the Project Explorer window and select Close Project Optional Exercise If you finish early you might want to experiment with the code by observing the effects of changing the OFFTRIM value Open a watch window to the AdcRegs ADCOFFTRIM register and chan...

Page 126: ...Lab 6 Analog to Digital Converter 6 26 C2000 Microcontroller Workshop Analog to Digital Converter ...

Page 127: ...discussed Module Objectives Module Objectives Pulse Width Modulation PWM review Generate a PWM waveform with the Pulse Width Modulator Module ePWM Use the Capture Module eCAP to measure the width of a waveform Explain the function of Quadrature Encoder Pulse Module eQEP Note Different numbers of ePWM eCAP and eQEP modules are available on F2806x devices See the device datasheet for more informatio...

Page 128: ...M Compare Sub Module 7 11 ePWM Action Qualifier Sub Module 7 13 Asymmetric and Symmetric Waveform Generation using the ePWM 7 19 PWM Computation Example 7 20 ePWM Dead Band Sub Module 7 21 ePWM Chopper Sub Module 7 24 ePWM Digital Compare and Trip Zone Sub Modules 7 27 ePWM Event Trigger Sub Module 7 33 Hi Resolution PWM HRPWM 7 36 eCAP 7 37 eQEP 7 43 Lab 7 Control Peripherals 7 45 ...

Page 129: ...hod for representing an analog signal with a digital approximation The PWM signal consists of a sequence of variable width constant amplitude pulses which contain the same total energy as the original analog signal This property is valuable in digital motor control as sinusoidal current energy can be delivered to the motor using PWM signals applied to the power converter Although energy is input t...

Page 130: ...ol in saturated region PWM is a digital signal easy for MCU to output PWM approx of desired signal DC Supply Desired signal to system DC Supply Unknown Gate Signal Gate Signal Known with PWM PWM Power switching devices are difficult to control in the proportional region but are easy to control in the saturation and cutoff region Since PWM is a digital signal and easy for microcontrollers to genera...

Page 131: ...UX TZ1 TZ3 GPIO MUX An ePWM module can be synchronized with adjacent ePWM modules The generated PWM waveforms are available as outputs on the GPIO pins Additionally the EPWM module can generate ADC starter conversion signals and generate interrupts to the PIE block External trip zone signals can trip the output and generate interrupts too The outputs of the comparators are used as inputs to the di...

Page 132: ...opper Trip Zone Shadowed Compare Register Shadowed Period Register Clock Prescaler Shadowed Compare Register EPWMxA EPWMxB SYSCLKOUT TZy EPWMxSYNCI EPWMxSYNCO TBCLK Digital Compare TZ1 TZ3 COMPxOUT The ePWM or enhanced PWM block diagram consists of a series of sub modules In this section we will learn about the operation and details of each sub module ...

Page 133: ...YNCI EPWMxSYNCO TBCLK Digital Compare TZ1 TZ3 COMPxOUT In the time base sub module the clock prescaler divides down the device core system clock and clocks the 16 bit time base counter The time base counter is used to generate asymmetrical and symmetrical waveforms using three different count modes count up mode countdown mode and count up and down mode A period register is used to control the max...

Page 134: ...unt Up and Down Mode Asymmetrical Waveform Asymmetrical Waveform Symmetrical Waveform The upper two figures show the time base counter in the count up mode and countdown mode These modes are used to generate asymmetrical waveforms The lower figure shows the time base counter in the count up and down mode This mode is used to generate symmetrical waveforms ...

Page 135: ...ncIn To eCAP1 SyncIn If needed an ePWM module can be synchronized with adjacent ePWM modules Synchronization is based on a synch in signal time base counter equals zero or time base counter equals compare B register Additionally the waveform can be phase shifted ePWM Time Base Sub Module Registers lab file EPwm c Name Description Structure TBCTL Time Base Control EPwmxRegs TBCTL all TBSTS Time Bas...

Page 136: ...Up Mode CTR PRD Down Mode CTR 0 Up Down Mode CTR 0 1x free run do not stop Phase Direction 0 count down after sync 1 count up after sync HSPCLKDIV is for legacy compatibility ePWM Time Base Control Register EPwmxRegs TBCTL Lower Register CTRMODE SWFSYNC SYNCOSEL PRDLD PHSEN 6 5 4 3 1 0 2 Software Force Sync Pulse 0 no action 1 force one time sync Sync Output Select source of EPWMxSYNC0 signal 00 E...

Page 137: ...CLK Digital Compare TZ1 TZ3 COMPxOUT The compare sub module uses two compare registers to detect time base count matches These compare match events are fed into the action qualifier sub module Notice that the output of this block feeds two signals into the action qualifier ePWM Compare Event Waveforms TBCTR TBCTR TBCTR TBPRD TBPRD TBPRD Count Up Mode Count Down Mode Count Up and Down Mode Asymmetr...

Page 138: ...wmxRegs CMPCTL all CMPA Compare A EPwmxRegs CMPA CMPB Compare B EPwmxRegs CMPB ePWM Compare Control Register EPwmxRegs CMPCTL 6 5 4 1 0 LOADBMODE LOADAMODE reserved 3 2 SHDWBMODE SHDWAMODE CMPA and CMPB Operating Mode 0 shadow mode double buffer w shadow register 1 immediate mode shadow register not used CMPA and CMPB Shadow Load Mode 00 load on CTR 0 01 load on CTR PRD 10 load on CTR 0 or PRD 11 ...

Page 139: ...OUT TZy EPWMxSYNCI EPWMxSYNCO TBCLK Digital Compare TZ1 TZ3 COMPxOUT The action qualifier sub module uses the inputs from the compare logic and time base counter to generate various actions on the output pins These first few modules are the main components used to generate a basic PWM waveform ePWM Action Qualifier Actions for EPWMA and EPWMB Z Z Z X Z T CA CA CA X CA T CB CB CB X CB T P P P X P T...

Page 140: ... action using software ePWM Count Up Asymmetric Waveform with Independent Modulation on EPWMA B Z P X CB X CA Z P X CB X CA Z P X Z P X CB CA X Z P X CB CA X Z P X TBCTR TBPRD EPWMA EPWMB CMPA CMPB The next few figures show how the action qualifier uses the compare matches to modulate the output pins Notice that the output pins for EPWMA and EPWMB are completely independent Here on the EPWMA outpu...

Page 141: ... on compare A match and clear low on compare B match while the EPWMB output is configured to toggle on zero match ePWM Count Up Down Symmetric Waveform with Independent Modulation on EPWMA B CA CA CA CA CB CB CB CB EPWMA EPWMB TBCTR TBPRD CMPB CMPA Here you can see that we can have different output actions on the up count and down count using a single compare register So for the EPWMA and EPWMB ou...

Page 142: ...metric Waveform with Independent Modulation on EPWMA CA CB CA CB Z P Z P EPWMA EPWMB TBCTR TBPRD CMPB CMPA And finally again using different output actions on the up count and down count we have the EPWMA output set high on the compare A up count match and clear low on the compare B down count match The EPWMB output will clear low on zero match and set high on period match ...

Page 143: ...orce EPwmxRegs AQSFRC all AQCSFRC AQ Cont S W Force EPwmxRegs AQCSFRC all ePWM Action Qualifier Control Register EPwmxRegs AQCTLy y A or B ZRO CBU CAD CAU PRD 1 0 CBD 15 12 reserved 3 2 5 4 7 6 9 8 11 10 00 do nothing action disabled 01 clear low 10 set high 11 toggle low high high low Action when CTR CMPB on DOWN Count Action when CTR CMPB on UP Count Action when CTR CMPA on DOWN Count Action whe...

Page 144: ... 0 or CTR PRD 11 load immediately from active reg One Time S W Force on Output B A 0 no action 1 single s w force event Action on One Time S W Force B A 00 do nothing action disabled 01 clear low 10 set high 11 toggle low high high low ePWM Action Qualifier Continuous S W Force Register EPwmxRegs AQCSFRC CSFA CSFB 1 0 15 4 reserved 3 2 Continuous S W Force on Output B A 00 forcing disabled 01 forc...

Page 145: ...olution The PWM compare function resolution can be computed once the period register value is determined The largest power of 2 is determined that is less than or close to the period value As an example if asymmetric was 1000 and symmetric was 500 then Asymmetric PWM approx 10 bit resolution since 210 1024 1000 Symmetric PWM approx 9 bit resolution since 29 512 500 PWM duty cycle Duty cycle calcul...

Page 146: ...0 375 TBPRD fTBCLK fPWM 2 2 1 1 90 kHz 90 MHz 500 Counter Compare Period PWM Pin fTBCLK 90 MHz CA CA fPWM 90 kHz TPWM 11 1 µs TTBCLK 11 1 ns Asymmetric PWM Computation Example Determine TBPRD and CMPA for 90 kHz 25 duty asymmetric PWM from a 90 MHz time base clock CMPA 100 duty cycle TBPRD 1 1 0 75 999 1 1 749 TBPRD fTBCLK fPWM 90 kHz 90 MHz 1 999 1 Counter Compare Period PWM Pin P CA fTBCLK 90 MH...

Page 147: ... Shadowed Compare Register EPWMxA EPWMxB SYSCLKOUT TZy EPWMxSYNCI EPWMxSYNCO TBCLK Digital Compare TZ1 TZ3 COMPxOUT The dead band sub module provides a means to delay the switching of a gate signal thereby allowing time for gates to turn off and preventing a short circuit Motivation for Dead Band to power switching device supply rail gate signals are complementary PWM Transistor gates turn on fast...

Page 148: ...g gate will eventually shut even brief periods of a short circuit condition can produce excessive heating and over stress in the power converter and power supply ePWM Dead Band Block Diagram Rising Edge Delay In Out 10 bit counter Falling Edge Delay In Out 10 bit counter 0 1 0 1 0 1 1 0 PWMxA PWMxB PWMxB PWMxA S1 S0 S2 S3 FED RED OUT MODE POLSEL 0 1 0 1 S4 S5 IN MODE HALFCYCLE Two basic approaches...

Page 149: ... is called dead band While it is possible to perform software implementation of dead band the C28x offers on chip hardware for this purpose that requires no additional CPU overhead Compared to the passive approach dead band offers more precise control of gate timing requirements In addition the dead time is typically specified with a single program variable that is easily changed for different pow...

Page 150: ...WMxA is source for FED PWMxB is source for RED 10 PWMxA is source for RED PWMxB is source for FED 11 PWMxB is source for RED and FED OUT_MODE POLSEL 1 0 14 6 reserved 3 2 IN_MODE 5 4 HALFCYCLE 15 Half Cycle Clocking 0 full cycle clocking TBCLK rate 1 half cycle clocking TBCLK 2 rate ePWM Chopper Sub Module ePWM Chopper Sub Module 16 Bit Time Base Counter Compare Logic Action Qualifier Dead Band PW...

Page 151: ...e the PWM waveform generated by the Action Qualifier and Dead Band modules Used with pulse transformer based gate drivers to control power switching elements As you can see in this figure a high frequency carrier signal is ANDed with the ePWM outputs Also this circuit provides an option to include a larger one shot pulse width before the sustaining pulses ePWM Chopper Waveform EPWMxA EPWMxB CHPFRE...

Page 152: ...T 8 0001 2 x SYSCLKOUT 8 1001 10 x SYSCLKOUT 8 0010 3 x SYSCLKOUT 8 1010 11 x SYSCLKOUT 8 0011 4 x SYSCLKOUT 8 1011 12 x SYSCLKOUT 8 0100 5 x SYSCLKOUT 8 1100 13 x SYSCLKOUT 8 0101 6 x SYSCLKOUT 8 1101 14 x SYSCLKOUT 8 0110 7 x SYSCLKOUT 8 1110 15 x SYSCLKOUT 8 0111 8 x SYSCLKOUT 8 1111 16 x SYSCLKOUT 8 Chopper Clk Freq 000 SYSCLKOUT 8 1 001 SYSCLKOUT 8 2 010 SYSCLKOUT 8 3 011 SYSCLKOUT 8 4 100 SY...

Page 153: ...provide a protection mechanism to protect the output pins from abnormalities such as over voltage over current and excessive temperature rise Purpose of the Digital Compare Sub Module Generates compare events that can Trip the ePWM Generate a Trip interrupt Sync the ePWM Generate an ADC start of conversion The inputs to the digital compare module are Analog comparator outputs COMP1 COMP2 COMP3 Tri...

Page 154: ...DCAEVT2 DCBEVT1 DCBEVT2 blanking blanking The inputs to the digital compare sub module are the trip zone pins and the analog comparator outputs This module generates compare events that can generate a PWM sync generate an ADC start of conversion trip a PWM output and generate a trip interrupt Optional blinking can be used to temporarily disable the compare action in alignment with PWM switching to...

Page 155: ...ne shot trip for major short circuits or over current conditions 2 cycle by cycle trip for current limiting operation CPU core P W M O U T P U T S EPWMxTZINT TZ6 TZ5 TZ4 TZ3 TZ2 TZ1 Over Current Sensors Cycle by Cycle Mode One Shot Mode EPWMxA EPWMxB COMPxOUT Digital Compare CPU SYSCTRL eQEP1 EMUSTOP CLOCKFAIL EQEP1ERR The power drive protection is a safety feature that is provided for the safe op...

Page 156: ... EPwmxRegs DCFWINDOWCNT TZDCSEL Digital Compare EPwmxRegs TZDCSEL all TZCTL Trip Zone Control EPwmxRegs TZCTL all TZSEL Trip Zone Select EPwmxRegs TZSEL all TZEINT Enable Interrupt EPwmxRegs TZEINT all TZFLG Trip Zone Flag EPwmxRegs TZFLG all TZCLR Trip Zone Clear EPwmxRegs TZCLR all TZFRC Trip Zone Force EPwmxRegs TZFRC all ePWM Digital Compare Trip Select Register EPwmxRegs DCTRIPSEL DCBLCOMPSEL...

Page 157: ... Event 2 1 Select Digital Compare Output B Event 2 1 Select ePWM Digital Compare Control Register EPwmxRegs DCyCTL y A or B 9 8 2 0 reserved 1 7 4 15 10 EVT1FRC SYNCSEL EVT2FRC SYNCSEL EVT2SRC SEL EVT1SRC SEL EVT1 SYNCE EVT1 SOCE reserved 3 DCyEVT1 Source Signal Select 0 DCyEVT1 signal 1 DCEVTFILT signal DCyEVT2 Source Signal Select 0 DCyEVT2 signal 1 DCEVTFILT signal DCyEVT1 Source Force Sync Sig...

Page 158: ...tput Event 2 1 Action on EPWMxA Digital Compare Output Event 2 1 Action on EPWMxB ePWM Trip Zone Select Register EPwmxRegs TZSEL OSHT1 OSHT5 OSHT4 OSHT3 OSHT2 8 OSHT6 15 9 10 11 12 13 CBC1 CBC5 CBC4 CBC3 CBC2 0 CBC6 7 1 2 3 4 5 Cycle by Cycle Trip Zone event cleared when CTR 0 i e cleared every PWM cycle 0 disable as trip source 1 enable as trip source One Shot Trip Zone event only cleared under S...

Page 159: ...ble 1 enable 3 4 5 6 Digital Compare Output A Event 2 1 Interrupt Enable 0 disable 1 enable ePWM Event Trigger Sub Module ePWM Event Trigger Sub Module 16 Bit Time Base Counter Compare Logic Action Qualifier Dead Band PWM Chopper Trip Zone Shadowed Compare Register Shadowed Period Register Clock Prescaler Shadowed Compare Register EPWMxA EPWMxB SYSCLKOUT TZy EPWMxSYNCI EPWMxSYNCO TBCLK Digital Com...

Page 160: ...ounter equal zero or period counter up equal compare A counter down equal compare A counter up equal compare B counter down equal compare B Notice counter up and down are independent and separate ePWM Event Trigger Sub Module Registers lab file EPwm c Name Description Structure ETSEL Event Trigger Selection EPwmxRegs ETSEL all ETPS Event Trigger Pre Scale EPwmxRegs ETPS all ETFLG Event Trigger Fla...

Page 161: ...CTR 0 or PRD 100 CTRU CMPA 101 CTRD CMPA 110 CTRU CMPB 111 CTRD CMPB ePWM Event Trigger Prescale Register EPwmxRegs ETPS 15 14 11 10 7 4 1 0 INTCNT INTPRD reserved 2 3 SOCBPRD SOCAPRD SOCACNT SOCBCNT 9 8 13 12 EPWMxSOCB A Counter number of events have occurred 00 no events 01 1 event 10 2 events 11 3 events EPWMxSOCB A Period number of events before SOC 00 disabled 01 SOC on first event 10 SOC on ...

Page 162: ...Period Device Clock i e 90 MHz Regular PWM Step i e 11 1 ns HRPWM Micro Step 150 ps HRPWM divides a clock cycle into smaller steps called Micro Steps Step Size 150 ps ms ms ms ms ms ms Calibration Logic Calibration Logic tracks the number of Micro Steps per clock to account for variations caused by Temp Volt Process The high resolution PWM feature significantly increases the resolution of conventi...

Page 163: ...s or falling edges Second if the ADCSOC pin is held high longer than one conversion period a second conversion will be immediately initiated upon completion of the first This unwanted second conversion could still be in progress when a desired conversion is needed In addition if the end of conversion ADC interrupt is enabled this second conversion will trigger an unwanted interrupt upon its comple...

Page 164: ...om incr encoder Measure the time width of a pulse vk x tk tk 1 vk t xk xk 1 x Auxiliary PWM generation eCAP Module Block Diagram Capture Mode 32 Bit Time Stamp Counter Capture 1 Register Event Prescale Polarity Select 1 Polarity Select 2 Polarity Select 3 Polarity Select 4 Capture 2 Register Capture 3 Register Capture 4 Register Event Logic ECAPx pin SYSCLKOUT CAP1POL CAP2POL CAP3POL CAP4POL PRESC...

Page 165: ...mode immediate mode If the capture module is not used it can be configured as an asynchronous PWM module eCAP Module Registers lab file ECap c Name Description Structure ECCTL1 Capture Control 1 ECapxRegs ECCTL1 all ECCTL2 Capture Control 2 ECapxRegs ECCTL2 all TSCTR Time Stamp Counter ECapxRegs TSCTR CTRPHS Counter Phase Offset ECapxRegs CTRPHS CAP1 Capture 1 ECapxRegs CAP1 CAP2 Capture 2 ECapxRe...

Page 166: ... divide by 1 bypass 00001 divide by 2 00010 divide by 4 00011 divide by 6 00100 divide by 8 11110 divide by 60 11111 divide by 62 CAP1 4 Load on Capture Event 0 disable 1 enable eCAP Control Register 1 ECapxRegs ECCTL1 Lower Register CTRRST4 CAP4POL 7 3 0 2 CTRRST3 CAP3POL CTRRST2 CAP2POL CTRRST1 CAP1POL 1 4 5 6 Counter Reset on Capture Event 0 no reset absolute time stamp mode 1 reset after captu...

Page 167: ...ontrol Register 2 ECapxRegs ECCTL2 Lower Register SYNCO_SEL SYNCI_EN 7 6 3 0 2 1 TSCTRSTOP REARM STOP_WRAP CONT_ONESHT 4 5 Sync Out Select 00 sync in to sync out 01 CTR PRD event generates sync out 1X disable Counter Sync In 0 disable 1 enable Time Stamp Counter Stop 0 stop 1 run Re arm capture mode only 0 no effect 1 arm sequence Stop Value for One Shot Mode Wrap Value for Continuous Mode capture...

Page 168: ...ed and some alternate action would be taken for updating the velocity estimate As a second example consider the case where two successive captures are needed before a computation proceeds e g measuring the width of a pulse If the width of the pulse is needed as soon as the pulse ends then the capture interrupt is the best option However the capture interrupt will occur after each of the two captur...

Page 169: ... 4 Incremental Optical Encoder The eQEP circuit when enabled decodes and counts the quadrature encoded input pulses The QEP circuit can be used to interface with an optical encoder to get position and speed information from a rotating machine How is Position Determined from Quadrature Signals Ch A Ch B 00 11 10 01 A B 00 01 11 10 Quadrature Decoder State Machine increment counter decrement counter...

Page 170: ...ompare match Measure the elapsed time between the unit position events used for low speed measurement Generate periodic interrupts for velocity calculations Monitors the quadrature clock to indicate proper operation of the motion control system Quadrature clock mode Direction count mode The QEP module features a direct interface to encoders In addition to channels A and B being used for rotational...

Page 171: ... this step will be viewed numerically in a memory window Lab 7 Control Peripherals ADC RESULT0 data memory CPU copies result to buffer during ADC ISR ePWM2 connector wire Capture 1 Register ADC INA0 TB Counter Compare Action Qualifier ePWM1 eCAP1 Capture 2 Register Capture 3 Register Capture 4 Register View ADC buffer PWM Samples Code Composer Studio ePWM2 triggering ADC on period match using SOCA...

Page 172: ...values for TBPRD and CMPA as a challenge or make use of the global variable names and values that have been set using define in the beginning of Lab h file Notice that ePWM2 has been initialized earlier in the code for the ADC lab Save your work and close the modified files Build and Load 4 Click the Build button and watch the tools run in the Console window Check for errors in the Problems window...

Page 173: ...n the ruler icon with the red arrow Note when you hover your mouse over the icon it will show Toggle Measurement Marker Mode Move the mouse to the first measurement position and left click Again left click on the Toggle Measurement Marker Mode icon Move the mouse to the second measurement position and left click The graph will automatically calculate the difference between the two values taken ove...

Page 174: ...form The results of this step will be viewed numerically in a memory window and can be compared to the results obtained using the graphing features of Code Composer Studio 14 Switch to the CCS Edit Perspective view by clicking the CCS Edit icon in the upper right hand corner Add the following file to the project from C C28x Labs Lab7 Files ECap_7_8_9_10_12 c Check your files list to make sure the ...

Page 175: ... address label PwmPeriod Type PwmPeriod in the address box The address label PwmDuty address PwmDuty should appear in the same memory browser window 23 Set the memory browser properties format to 32 Bit Unsigned Integer We will be running our code in real time mode and we will need to have the memory browser continuously refresh 24 Using the connector wire provided connect the PWM1A pin GPIO 00 to...

Page 176: ...register in EPwm c highlight the EPwm1Regs structure and right click then select Add Watch Expression and then OK In the Expressions window open EPwm1Regs then open CMPA and open half Under half change the CMPA value The Expressions window must be enabled for continuous refresh Notice the effect on the PWM waveform in the graph You have just modulated the PWM waveform by manually changing the CMPA...

Page 177: ...of highly optimized and high precision mathematical functions used to seamlessly port floating point algorithms into fixed point code These C C routines are typically used in computationally intensive real time applications where optimal execution speed and high accuracy is needed By using these routines a user can achieve execution speeds considerable faster than equivalent code written in standa...

Page 178: ...tiplication 8 6 Binary Fractions 8 8 Representing Fractions in Binary 8 8 Fraction Basics 8 8 Multiplying Binary Fractions 8 9 Fraction Coding 8 11 Fractional vs Integer Representation 8 12 Floating Point 8 13 IQmath 8 16 IQ Fractional Representation 8 16 Traditional Q Math Approach 8 17 IQmath Approach 8 19 IQmath Library 8 24 Converting ADC Results into IQ Format 8 26 AC Induction Motor Example ...

Page 179: ... number may be represented Examples 01102 0 8 1 4 1 2 0 1 610 111102 1 16 1 8 1 4 1 2 0 1 3010 Two s Complement Numbers Notice that binary numbers can only represent positive numbers Often it is desirable to be able to represent both positive and negative numbers The two s complement numbering system modifies the binary system to include negative numbers by making the most significant bit MSB nega...

Page 180: ...n bit the MSB of the original number to all unfilled bits to the left in the register sign extension Consider our two previous values copied into an 8 bit register Examples Original No 0 1 1 02 610 1 1 1 1 02 210 1 Load low 0 1 1 0 1 1 1 1 0 2 Sign Extend 0 0 0 0 0 1 1 0 4 2 6 1 1 1 1 1 1 1 0 128 64 2 2 Integer Basics Integer Basics Unsigned Binary Integers 0100b 0 23 1 22 0 21 0 20 4 1101b 1 23 1...

Page 181: ...ctice to always select the desired SXM at the beginning of a module to assure the proper mode What is Sign Extension When moving a value from a narrowed width location to a wider width location the sign bit is extended to fill the width of the destination Sign extension applies to signed numbers only It keeps negative numbers negative Sign extension controlled by SXM bit in ST0 register When SXM 1...

Page 182: ...es and an 8 bit accumulation Integer Multiplication signed 0100 x 1101 00000100 0000000 000100 11100 11110100 Accumulator Data Memory 11110100 4 x 3 12 In this example consider the following What are the two input values and the expected result Why are the partial products shifted left as the calculation continues Why is the final partial product different than the others What is the result obtain...

Page 183: ...loss of precision and a problem in how to interpret the results later Store both the upper and lower accumulator to memory This solves the above problems but creates some new ones Extra code space memory space and cycle time are used How can the result be used as the input to a subsequent calculation Is such a condition likely consider any feedback system From this analysis it is clear that intege...

Page 184: ...ive values the two s complement process will again be used However in the case of fractions we will not set the LSB to 1 as was the case for integers When one considers that the range of fractions is from 1 to 1 and that the only bit which conveys negative information is the MSB it seems that the MSB must be the negative ones position Since binary representation is based on powers of two it follow...

Page 185: ...his result be loaded into the accumulator How shall we fill the remaining bit Is this value still the expected one How can the result be stored back to memory What problems arise To read the results of the fractional multiply it is necessary to locate the binary point the base 2 equivalent of the base 10 decimal point Start by identifying the location of the binary point in the input values The MS...

Page 186: ...y This offers maximum detail but has the same problems as with integer multiply Store only the high or low accumulator back to memory This creates a potential for a memory littered with varying Q types Store the upper accumulator shifted to the left by 1 This would store values back to memory in the same Q format as the input values and with equal precision to the inputs How shall the left shift b...

Page 187: ...ction by 32K 32768 a normalized fraction is created which can be passed through the COFF tools as an integer Once in the C28x the normalized fraction looks and behaves exactly as a fraction Thus when using fractional constants in a C28x program the coder first multiplies the fraction by 32768 and uses the resulting integer rounded to the nearest whole value to represent the fraction The following ...

Page 188: ...range to integer calculations but this becomes a problem in storing the results back to 16 bit memory Conversely when using fractions the extra accumulator bits increase precision which helps minimize accumulative errors Since any number is accurate at best to one half of a LSB summing two of these values together would yield a worst case result of 1 LSB error Four summations produce two LSBs of e...

Page 189: ...a fraction 8 bit exponent 1 bit sign Case 1 if e 255 and f 0 then v NaN Case 2 if e 255 and f 0 then v 1 s infinity Case 3 if 0 e 255 then v 1 s 2 e 127 1 f Case 4 if e 0 and f 0 then v 1 s 2 126 0 f Case 5 if e 0 and f 0 then v 1 s 0 Advantage Exponent gives large dynamic range Disadvantage Precision of a number depends on its exponent Normalized values Number Line Insight Floating Point 0 0 Non ...

Page 190: ... variant that has the FPU will automatically select this option so normally no user action is required define AdcFsVoltage float 3 3 ADC full scale voltage float Result ADC result void main void Convert unsigned 16 bit result to 32 bit float Gives value of 0 to 4095 Scale result by 1 4096 Gives value of 0 to 1 Scale result by AdcFsVoltage Gives value of 0 to 3 3 Result AdcFsVoltage 4096 0 float Ad...

Page 191: ...ros and Cons Advantages Easy to write code No scaling required Disadvantages Somewhat higher device cost May offer insufficient precision for some calculations due to 23 bit mantissa and the influence of the exponent What if you don t have the luxury of using a floating point C28x device ...

Page 192: ...target systems The effort and skill involved in converting a floating point algorithm to function using a 16 bit or 32 bit fixed point device is quite significant A great deal of time many days or weeks would be needed for reformatting scaling and coding the problem Additionally the final implementation typically has little resemblance to the original algorithm Debugging is not an easy task and th...

Page 193: ...er Line Insight Distributions Both floating point and IQ formats have 232 possible values on the number line It s how each distributes these values that differs Floating Point non uniform distribution variable precision 0 Traditional Q Math Approach Traditional 32 bit Q Math Approach y mx b Y int64 M int64 X int64 B Q Q in C Note Requires support for 64 bit integer data type in compiler 24 Align B...

Page 194: ...e slide shows the implementation of the equation on a processor containing hardware that can perform a 32x32 bit multiplication 64 bit addition and 64 bit shifts logical and arithmetic effi ciently The basic approach in traditional fixed point Q math is to align the binary point of the operands that get added to or subtracted from the multiplication result As shown in the slide the multipli cation...

Page 195: ... this is given by linear equation below int32 Y M X B Y int64 M int64 X 24 B The slide shows the implementation of the equation on a processor containing hardware that can perform a 32x32 bit multiply 32 bit addition subtraction and 64 bit logical and arithmetic shifts efficiently The key advantage of this approach is shown by what can then be done with the C and C com piler to simplify the coding...

Page 196: ...iq X return int64 M int64 X 24 Then the linear equation in C becomes Y M X B This final equation looks identical to the floating point representation It looks natural The four approaches are summarized in the table below Math Implementations Linear Equation Code 32 bit floating point math in C Y M X B 32 bit fixed point Q math in C Y int64 M int64 X int64 B 24 24 32 bit IQmath in C Y _IQ24mpy M X ...

Page 197: ... 32 bits of M X QMPYL ACC XT X ACC high 32 bits of M X LSL64 ACC P 32 Q ACC ACC P 32 Q same as P ACC P Q ADDL ACC B Add B MOVL Y ACC Result Y _IQmpy M X B 7 Cycles C28x compiler supports _IQmpy intrinsic assembly code generated IQmath Approach It looks like floating point float Y M X B Y M X B Floating Point long Y M X B Y i64 M i64 X i64 B Q Q Traditional Fix Point Q _iq Y M X B Y _IQmpy M X B IQ...

Page 198: ...2 bit multiply 64 bit shifts logical and arithmetic and 32 bit add subtract operations which are ideally suited for 32 bit IQmath Some enhancements were made to the basic IQmath approach to improve flexibility They are Setting of GLOBAL_Q Parameter Value Depending on the application the amount of numerical resolution or dynamic range required may vary In the linear equation example we used a Q val...

Page 199: ...ny floating point compiler e g PC Matlab fixed point w RTS lib etc Selecting FLOAT_MATH or IQ_MATH Mode As was highlighted in the introduction we would ideally like to be able to have a single source code that can execute on a floating point or fixed point target device simply by recompiling the code The IQmath library supports this by setting a mode which selects either IQ_MATH or FLOAT_MATH This...

Page 200: ... multiply A IQ 1 2345 A _IQ 1 2345 A 1 2345 constant iq A B _iq A B float A B type IQmath in C IQmath in C Floating Point Operation Additionally the IQmath library contains DSP library modules for filters FIR IIR and Fast Fourier Transforms FFT IFFT IQmath Library Conversion Functions IQmath lib contains library of math functions IQmathLib h C header file IQmathCPP h C header file atoIQ char _atoI...

Page 201: ... numbers when you can simply use 32 bit numbers pick one value of Q that will accommodate all cases and not worry about spending too much time optimizing Of course there is a concern on data RAM usage if numbers that could be represented in 16 bits all use 32 bits This is becoming less of an issue in today s processors because of the finer tech nology used and the amount of RAM that can be cheaply...

Page 202: ...Before these values are filtered using the IQmath library they need to to be put into the IQ format as a 32 bit long For uni polar ADC inputs i e 0 to 3 3 V inputs a conversion to global IQ format can be achieved with IQresult_unipolar _IQmpy _IQ 3 3 _IQ12toIQ _iq AdcResult ADCRESULT0 How can we modify the above to recover bi polar inputs for example 1 65 volts One could do the following to offset...

Page 203: ...Q 3 3 ADC full scale voltage else MATH_TYPE is FLOAT_MATH define AdcFsVoltage _IQ 3 3 4096 0 ADC full scale voltage endif _iq Result ADC result void main void Result _IQmpy AdcFsVoltage _IQ12toIQ _iq AdcResult ADCRESULT0 Can a Single ADC Interface Code Line be Written for IQmath and Floating Point does nothing FLOAT_MATH behavior float ...

Page 204: ...k diagram representation of the key control blocks and their interconnec tions Essentially this system implements a Forward Control block for controlling the d q axis motor current using PID controllers and a Feedback Control block using back emf s integration with compensated voltage from current model for estimating rotor flux based on current and volt age measurements The motor speed is simply ...

Page 205: ...lc PARK v float cos_ang sin_ang sin_ang sin TWO_PI v ang cos_ang cos TWO_PI v ang v de v ds cos_ang v qs sin_ang v qe v qs cos_ang v ds sin_ang include IQmathLib h _IQ 6 28318530717959 _iq _IQsin _IQmpy TWO_PI v ang _IQcos _IQmpy TWO_PI v ang _IQmpy v ds cos_ang _IQmpy v qs sin_ang _IQmpy v qs cos_ang _IQmpy v ds sin_ang The complete system was coded using IQmath Based on analysis of coefficients ...

Page 206: ...eventually settles to the desired reference value and the stator current exhibits a clean and stable oscillation The block diagram slide shows at which points in the control system the plots are taken from I8Q24 Fractions 0 What s Happening Here Equal Precision in the Computation Region In the region where these particular computations occur the precision of single precision floating point just ha...

Page 207: ...ple C2000 Microcontroller Workshop Numerical Concepts 8 31 AC Induction Motor Example GLOBAL_Q 27 system unstable IQmath speed IQmath current AC Induction Motor Example GLOBAL_Q 16 system unstable IQmath speed IQmath current ...

Page 208: ...or setting the initial GLOBAL_Q value Then through simulation or experimentation the user can reduce the GLOBAL_Q until the system resolution starts to cause instability or performance deg radation The user then has a maximum and minimum limit and a safe approach is to pick a mid point What the above analysis also confirms is that this particular problem does require some calcula tions to be perfo...

Page 209: ...403 B3 Feedback control cycles 2336 792 1011 Total control cycles B2 B3 2757 1163 1414 of available MHz used 36 8 15 5 18 9 20 kHz control loop Notes C28x compiled on codegen tools v5 0 0 g debug enabled o3 max optimization fast RTS lib v1 0beta1 IQmath lib v1 4d Using the profiling capabilities of the respective DSP tools the table above summarizes the num ber of cycles and code size of the forwa...

Page 210: ...ut sacrificing time and cycles Rapid conversion porting and implementation of algorithms IQmath library is freeware available from controlSUITE and TI website http www ti com c2000 IQmath fixed point processor with 32 bit capabilities The IQmath approach matched to a fixed point processor with 32x32 bit capabilities enables the following Seamless portability of code between fixed and floating poin...

Page 211: ...n the IQmathLib h file Lab 8 IQmath FIR Filter CPU copies result to buffer during ADC ISR ADC RESULT0 ePWM2 connector wire ADCINA0 data memory Display using CCS TB Counter Compare Action Qualifier ePWM1 ePWM2 triggering ADC on period match using SOCA trigger every 20 µs 50 kHz FIR Filter Procedure Open the Project 1 A project named Lab8 has been created for this lab Open the project by clicking on...

Page 212: ...ary Under C2000 Linker select File Search Path In the top box Include library file or command file as input click the Add icon Then in the Add file path window type IQmath lib Click OK to include the library file In the bottom box Add dir to library search path click the Add icon In the Add directory path window type PROJECT_ROOT IQmath lib Click OK to include the library search path Finally selec...

Page 213: ...will provide 8 integer bits and 24 fractional bits Dynamic range is therefore 128 x 128 which is sufficient for our purposes in the workshop Notice that the math type is defined as IQmath by define MATH_TYPE IQ_MATH Close the file IQmath Single Sample FIR Filter 7 Open and inspect DefaultIsr_8 c Notice that the ADCINT1_ISR calls the IQmath single sample FIR filter function IQssfir The filter coeff...

Page 214: ...the jumper wire connecting PWM1A pin GPIO 00 to ADCINA0 pin ADC A0 is in place on the Docking Station 13 Run the code in real time mode using the Script function Scripts Realtime Emulation Control Run_Realtime_with_Reset and watch the memory browser update Verify that the ADC result buffer contains updated values 14 Open and setup a dual time graph to plot a 50 point window of the filtered and unf...

Page 215: ...t the higher frequency components are reduced using the Low Pass FIR filter in the filtered graph as compared to the unfiltered graph 18 Fully halt the CPU real time mode by using the Script function Scripts Realtime Emulation Control Full_Halt Changing Math Type to Floating Point 19 Switch to the CCS Edit Perspective view by clicking the CCS Edit icon in the upper right hand corner In the Project...

Page 216: ...enerated FIR filtered 2 kHz 25 duty cycle symmetric PWM waveform in the Dual Time A display and the unfiltered waveform in the Dual Time B display The FFT Magnitude graphical displays should show the frequency components of the filtered and unfiltered 2 kHz 25 duty cycle symmetric PWM waveforms 24 Fully halt the CPU real time mode by using the Script function Scripts Realtime Emulation Control Ful...

Page 217: ... 8 IQmath FIR Filter C2000 Microcontroller Workshop Numerical Concepts 8 41 Lab 8 Reference Low Pass FIR Filter Bode Plot of Digital Low Pass Filter Coefficients 1 16 4 16 6 16 4 16 1 16 Sample Rate 50 kHz ...

Page 218: ...Lab 8 IQmath FIR Filter 8 42 C2000 Microcontroller Workshop Numerical Concepts ...

Page 219: ...ndent PIE interrupts Module Objectives Module Objectives Understand the operation of the Direct Memory Access DMA controller Show how to use the DMA to transfer data between peripherals and or memory without intervention from the CPU The DMA allows data to be transferred between peripherals and or memory without intervention from the CPU The DMA can read data from the ADC result registers transfer...

Page 220: ...Memory Access Controller Module Topics Direct Memory Access Controller 9 1 Module Topics 9 2 Direct Memory Access DMA 9 3 Basic Operation 9 4 DMA Examples 9 6 DMA Priority Modes 9 8 DMA Throughput 9 9 DMA Registers 9 10 Lab 9 Servicing the ADC with DMA 9 14 ...

Page 221: ...NTCH1 6 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 SysCtrlRegs EPWMCNF bit CONCNF maps ePWM to DMA bus or CLA bus DMA Definitions Word 16 or 32 bits Word size is configurable per DMA channel Burst Consists of multiple words Smallest amount of data transferred at one time Burst Size Number of words per burst Specified by BURST_SIZE register 5 bit N 1 value maximum of 32 words burst Transfer Consists of multiple...

Page 222: ...fer Move Word Start Transfer DMA can be configured to re initialize at the end of the transfer continuous mode Basic Address Control Registers SRC_ADDR SRC_ADDR_SHADOW DST_ADDR DST_ADDR_SHADOW SRC_BURST_STEP SRC_TRANSFER_STEP DST_BURST_STEP DST_TRANSFER_STEP Active pointers Pointer shadow registers copied to active pointers at start of transfer Signed value added to active pointer after each word ...

Page 223: ...tart continue transfer Start Transfer End Transfer DMA Interrupts Each DMA channel has its own PIE interrupt The mode for each interrupt can be configured individually The CHINTMODE bit in the MODE register selects the interrupt mode Read Write Data Add Burst Step to Address Pointer End Transfer Add Transfer Step to Address Pointer Moved Burst Size Words Moved Transfer Size Bursts Y Y N N Wait for...

Page 224: ...ST_ADDR DST_BURST_STEP DST_TRANSFER_STEP Addr Value 0x4000 0x4001 0x4002 0x4003 Destination Registers 0x00004000 0x0001 0x0001 2 words burst 2 bursts transfer Size registers are N 1 Objective Move 4 words from memory location 0xF000 to memory location 0x4000 and interrupt CPU at end of transfer Start Transfer Note This example could also have been done using 1 word burst and 4 bursts transfer or 4...

Page 225: ...CH1 CH1 CH2 CH2 CH2 CH3 CH3 CH3 CH4 CH4 CH4 0xF001 0xF004 0xF007 0xF00A 0xF00D 0xF002 0xF005 0xF008 0xF00B 0xF00E 0x0B03 0x0B04 Objective Bin 3 samples of 5 ADC channels then interrupt the CPU SOC0 SOC4 configured to CH0 CH4 respectively ADC configured to re trigger continuous conversion ADC Registers DMA Registers 0x0000F000 starting address Typically use a relocatable symbol in your code not a h...

Page 226: ...rt continuetransfer Start Transfer Convert ADC Channel ADCINA0 1 conversion per trigger i e ePWM2SOCA DMA Registers ADC Registers Other DST_ADDR_SHADOW must be changed between ping and pong buffer address in the DMA ISR Typically use a relocatable symbol in your code not a hard value DMA Priority Modes Channel Priority Modes Round Robin Mode All channels have equal priority After each enabled chan...

Page 227: ...o start continue transfer Point where CH1 can interrupt other channels in CH1 Priority Mode Start Transfer End Transfer DMA Throughput DMA Throughput 4 cycles word 5 for McBSP reads 1 cycle delay to start each burst 1 cycle delay returning from CH1 high priority interrupt 32 bit transfer doubles throughput except McBSP which supports 16 bit transfers only Example 128 16 bit words from ADC to RAM 8...

Page 228: ...CTRL DMA Control Register PRIORITYCTRL1 Priority Control Register 1 MODE Mode Register CONTROL Control Register BURST_SIZE Burst Size Register BURST_COUNT Burst Count Register SRC_BURST_STEP Source Burst Step Size Register DST_BURST_STEP Destination Burst Step Size Register TRANSFER_SIZE Transfer Size Register TRANSFER_COUNT Transfer Count Register SRC_TRANSFER_STEP Source Transfer Step Size Regis...

Page 229: ...0 15 2 reserved 1 Priority Reset 0 writes ignored always reads back 0 1 reset state machine after any pending burst transfer complete Hard Reset 0 writes ignored always reads back 0 1 reset DMA module Priority Control Register 1 DmaRegs PRIORITYCTRL1 CH1PRIORITY 0 15 1 reserved DMA CH1 Priority 0 same priority as other channels 1 highest priority channel ...

Page 230: ...ter 9 4 0 6 5 7 8 Channel Interrupt Generation 0 at beginning of transfer 1 at end of transfer Peripheral Interrupt Trigger 0 disable 1 enable CHINTMODE PERINTE OVRINTE PERINTSEL reserved Overflow Interrupt Enable 0 disable 1 enable Peripheral Interrupt Source Select Peripheral INT 0 none 1 ADCINT1 2 ADCINT2 3 XINT1 4 XINT2 5 XINT3 6 reserved 7 USB0EP1RX Peripheral INT 16 reserved 17 Reserved 18 e...

Page 231: ...Transfer Status 0 no activity 1 transferring Peripheral Interrupt Trigger Flag 0 no interrupt event trigger 1 interrupt event trigger read only PERINTFLG reserved Control Register DmaRegs CHx CONTROL Lower Register 7 3 0 2 PERINTCLR PERINTFRC SOFTRESET HALT RUN 1 4 6 5 Error Clear 0 no effect 1 clear SYNCERR Peripheral Interrupt Clear 0 no effect 1 clears event and PERINTFLG Peripheral Interrupt F...

Page 232: ...e of Code Composer Studio Lab 9 Servicing the ADC with DMA ADC RESULT0 ePWM2 connector wire ADCINA0 data memory Display using CCS TB Counter Compare Action Qualifier ePWM1 ePWM2 triggering ADC on period match using SOCA trigger every 20 µs 50 kHz Objective Configure the DMA to buffer ADC Channel A0 ping pong style with 50 samples per buffer ping CPU runs data through filter during DMA ISR FIR Filt...

Page 233: ...the peripheral interrupt trigger and set the channel for interrupt generation at the start of transfer Configure for 16 bit data transfers with one burst per trigger and auto re initialization at the end of the transfer In the DMA Channel 1 Control Register CONTROL clear the error and peripheral interrupt bits Enable the channel to run 4 Open Main_9 c and add a line of code in main to call the Ini...

Page 234: ...M using the Scripts menu Run the Code Test the DMA Operation Note For the next step check to be sure that the jumper wire connecting PWM1A pin GPIO 00 to ADCINA0 pin ADC A0 is in place on the Docking Station 11 Run the code in real time mode using the Script function Scripts Realtime Emulation Control Run_Realtime_with_Reset and watch the memory browser update Verify that the ADC result buffer con...

Page 235: ...rminate Debug Session and Close Project 15 Terminate the active debug session using the Terminate button This will close the debugger and return CCS to the CCS Edit Perspective view 16 Next close the project by right clicking on Lab9 in the Project Explorer window and select Close Project End of Exercise ...

Page 236: ...Lab 9 Servicing the ADC with DMA 9 18 C2000 Microcontroller Workshop Direct Memory Access Controller ...

Page 237: ...t delay enabling faster system response and higher frequency operation Utilizing the CLA for time critical tasks frees up the CPU to perform other system and communication functions concurrently Module Objectives Module Objectives Explain the purpose and operation of the Control Law Accelerator CLA Describe the CLA initialization procedure Review the CLA registers instruction set and programming f...

Page 238: ...ck Diagram 10 3 CLA Memory and Register Access 10 4 CLA Tasks 10 4 Control and Execution Registers 10 5 CLA Registers 10 6 CLA Initialization 10 9 CLA Task Programming 10 10 CLA C Language Implementation and Restrictions 10 10 CLA Assembly Language Implementation 10 13 CLA Code Debugging 10 16 controlSUITE CLA Software Support 10 16 Lab 10 CLA Floating Point FIR Filter 10 17 ...

Page 239: ...o peripheral interrupts independent of the CPU Frees up the CPU for other tasks communications and diagnostics C28x CPU CLA PWM ADC CMP CLA Block Diagram CLA Block Diagram MPERINT1 8 CLA_INT1 8 LVF LUF PIE C28x CPU INT11 INT12 CLA Control Execution Registers CLA Program Bus CLA Data Bus MSG RAMs CPU to CLA CLA to CPU Program RAM Data RAM0 Data RAM1 Data RAM2 Task Triggers Peripheral Interrupts ADC...

Page 240: ...RAM2 L0 DPSARAM Periph Regs ADC Results ePWM HRPWM Comparator eCAP eQEP ADC Results Regs ePWM all regs HRPWM all regs Peripheral Reg Access Comparator all regs eCAP all regs eQEP all regs 4Kw 1Kw 1Kw 2Kw 128w 128w CLA Tasks CLA Tasks A Task is similar to an interrupt service routine CLA supports 8 Tasks Task1 8 A task is started by a peripheral interrupt trigger Triggers are enabled in the MPISRCS...

Page 241: ...W Note Use of IACK requires Cla1Regs MCTL bit IACKE 1 Control and Execution Registers CLA Control and Execution Registers MPISRCSEL1 Peripheral Interrupt Source Select Task 1 8 MVECT1 8 Task Interrupt Vector MVECT1 2 3 4 5 6 7 8 MMEMCFG Memory Map Configuration RAM2E RAM1E RAM0E PROGE MPC 12 bit Program Counter initialized by appropriate MVECTx register MR0 3 CLA Floating Point Result Registers 32...

Page 242: ...pt Overflow Flag Register MICLROVF Interrupt Overflow Flag Clear Register MIRUN Interrupt Run Status Register MVECTx Task x Interrupt Vector x 1 8 MPC CLA 12 bit Program Counter MARx CLA Auxiliary Register x x 0 1 MRx CLA Floating Point 32 bit Result Register x 0 3 MSTF CLA Floating Point Status Register Register Description CLA Control Register Cla1Regs MCTL HARDRESET IACKE SOFTRESET reserved 15 ...

Page 243: ...a space CLA Peripheral Interrupt Source Select 1 Register Cla1Regs MPISRCSEL1 PERINT8SEL 31 28 19 16 PERINT7SEL PERINT6SEL PERINT5SEL 27 24 23 20 0000 Default Note select no source if task is generated by software Upper Register Task 8 Peripheral Interrupt Input 0000 ADCINT8 0010 CPU Timer 0 0100 eQEP1 0101 eQEP2 1000 eCAP1 1001 eCAP2 1010 eCAP3 other no source Task 7 Peripheral Interrupt Input 00...

Page 244: ...01 eQEP2 1000 eCAP1 1001 eCAP2 1010 eCAP3 other no source Task 3 Peripheral Interrupt Input 0000 ADCINT3 0010 ePWM3 xxx1 no source Task 2 Peripheral Interrupt Input 0000 ADCINT2 0010 ePWM2 xxx1 no source Task 1 Peripheral Interrupt Input 0000 ADCINT1 0010 ePWM1 xxx1 no source CLA Interrupt Enable Register Cla1Regs MIER INT2 INT3 INT4 INT5 INT6 INT7 INT8 INT1 0 1 2 3 4 5 6 7 15 8 reserved include F...

Page 245: ... IACK to start task using software avoids EALLOW Map CLA program RAM and data RAMs to CLA space 4 Configure desired CLA task completion interrupts in the PIE 5 Enable CLA tasks triggers in the MIER register 6 Initialize the desired peripherals to trigger the CLA tasks CLA initialization is performed by the CPU using C code typically done with the Peripheral Register Header Files Data is passed bet...

Page 246: ...nd C for non critical tasks CLA C Language Implementation and Restrictions CLA C Language Implementation Supports C only no C or GCC extension support Different data type sizes than C28x CPU No support for 64 bit integer or 64 bit floating point CLA architecture is designed for 32 bit data types 16 bit computations incur overhead for sign extension Primarily used for reading and writing to 16 bit ...

Page 247: ...level of function nesting Task can call a function but a function cannot call another function Function with more than two arguments Recursive function calls Function pointers CLA C Language Restrictions 2 of 2 CLA C compiler does not support Certain fundamental math operations integer division z x y modulus remainder z x y unsigned 32 bit integer compares Uint32 i if i 10 not valid int32 i if i 1...

Page 248: ...hpad area accessed directly using symbols All CLA C code will be placed in the section Cla1Prog Symbol used to define the start of CLA program memory Must allocate to memory section that CLA has write access CLA Task C Code Example include Lab h interrupt void Cla1Task1 void __mdebugstop xDelay 0 float32 AdcResult ADCRESULT0 Y coeffs 4 xDelay 4 xDelay 4 xDelay 3 xDelay 1 xDelay 0 Y Y coeffs 0 xDel...

Page 249: ...Load MSTF MMOV32 MSTF mem32 1 Compare Min Max MCMPF32 MRa MRb 1 Absolute Negative Value MABSF32 MRa MRb 1 Unsigned Integer to Float MUI16TOF32 MRa mem16 1 Integer to Float MI32TOF32 MRa mem32 1 Float to Integer Round MF32TOI16R MRa MRb 1 Float to Integer MF32TOI32 MRa MRb 1 Multiply Add Subtract MMPYF32 MRa MRb MRc 1 1 X 16 bit Accurate MEINVF32 MRa MRb 1 1 Sqrt x 16 bit Accurate MEISQRTF32 MRa MR...

Page 250: ...ADDF32 MRa MRb MRc MMOV32 mem32 MRe 1 Multiply Add Subtract MAC Parallel Load MADDF32 MRa MRb MRc MMOV32 MRe mem32 1 Both operations complete in a single cycle CLA Assembly Addressing Modes Two addressing modes Direct and Indirect Both modes can access the low 64Kw of memory only All of the CLA data space Both message RAMs Shared peripheral registers Direct Populates opcode field with 16 bit addre...

Page 251: ...de MSTOP instruction used at the end of the task CLA Initialization Code Example include F2806x_Cla_typedefs h include F2806x_Device h extern Uint16 Cla1Prog_Start extern interrupt void Cla1Task1 extern interrupt void Cla1Task2 extern interrupt void Cla1Task8 Lab h include Lab h Symbols used to calculate vector address Cla1Regs MVECT1 Uint16 Uint32 Cla1Task1 Uint32 Cla1Prog_Start Cla1Regs MVECT2 U...

Page 252: ...ngle step the CLA code Can also run to the next MDEBUGSTOP or to the end of task If another task is pending it will start at end of previous task 5 Disable CLA breakpoints if desired The CLA can halt single step and run independently from the CPU Both the CLA and CPU are debugged from the same JTAG port CLA single step CLA pipeline is clocked only one cycle and then frozen CPU single step CPU pipe...

Page 253: ...triggering ADC on period match using SOCA trigger every 20 µs 50 kHz CLA Cla1Task1 Cla1Task2 Cla1Task8 Recall that a task is similar to an interrupt service routine Once a task is triggered it runs to completion In this lab two tasks will be used Task 1 contains the low pass filter Task 8 contains a one time initialization routine that is used to clear set to zero the filter delay chain This must ...

Page 254: ...ocessor Options Notice the Specify CLA support is set to cla0 This is needed to compile and assemble CLA code Click OK to close the Properties window Inspect Lab_10 cmd 3 Open and inspect Lab_10 cmd Notice that a section called Cla1Prog is being linked to L3DPSARAM This section links the CLA program tasks to the CPU memory space This memory space will be remapped to the CLA memory space during ini...

Page 255: ...ce the line that includes the F2806x_Cla_typedefs h header file This file is needed to make the CLA C compiler work correctly with the peripheral register header files when unsupported data types are used 6 Edit Cla_10 c to implement the CLA operation as described in the objective for this lab exercise Configure the L3DPSARAM memory block to be mapped to CLA program memory space Configure the L2DP...

Page 256: ...ains the CLA interrupt service routine Save and close all modified files Build and Load 13 Click the Build button and watch the tools run in the Console window Check for errors in the Problems window 14 Click the Debug button green bug The CCS Debug Perspective view should open the program will load automatically and you should now be at the start of main If the device has been power cycled since ...

Page 257: ... cla will not need to change 19 Switch to the CCS Edit Perspective view by clicking the CCS Edit icon in the upper right hand corner Open ClaTasks_C cla and at the beginning of Task 1 change the if preprocessor directive from 1 to 0 The sections of code between the if and endif will not be compiled This has the same effect as commenting out this code We need to do this to avoid a conflict with the...

Page 258: ...er scratchpad area allocated by the linker command file will not be needed 25 Switch to the CCS Edit Perspective view by clicking the CCS Edit icon in the upper right hand corner Open ClaTasks asm and at the beginning of Task 2 change the assembly preprocessor if directive to 1 Recall that the assembly preprocessor endif directive is located at the end of Task 8 Now Task 2 through Task 8 will be a...

Page 259: ...same as before 30 Fully halt the CPU real time mode by using the Script function Scripts Realtime Emulation Control Full_Halt Terminate Debug Session and Close Project 31 Terminate the active debug session using the Terminate button This will close the debugger and return CCS to the CCS Edit Perspective view 32 Next close the project by right clicking on Lab10 in the Project Explorer window and se...

Page 260: ...Lab 10 CLA Floating Point FIR Filter 10 24 C2000 Microcontroller Workshop Control Law Accelerator ...

Page 261: ...o manage the communication link Module Objectives Module Objectives Understand the purpose and operation of the Viterbi Complex Math and CRC Unit VCU VCU Overview CRC Unit Viterbi Unit Complex Math Unit The Viterbi complex math CRC unit extends the C2000 instruction set to support Viterbi operations used in communications complex math which includes complex FFTs and complex filters and is used in ...

Page 262: ...ller Workshop Viterbi Complex Math CRC Unit Module Topics Viterbi Complex Math CRC Unit 11 1 Module Topics 11 2 Viterbi Complex Math CRC Unit 11 3 VCU Overview 11 3 CRC Unit 11 5 Viterbi Unit 11 6 Complex Math Unit 11 8 VCU Summary 11 10 ...

Page 263: ...spectrum communications and many signal processing algorithms Complex filters used to improve data reliability transmission distance and power efficiency Power Line Communications PLC and radar applications Cyclic Redundancy Check CRC Communications and memory robustness checks VCU Registers Viterbi and Complex Math general purpose registers Viterbi transition registers Status register Accumulated...

Page 264: ... on the left Same mnemonics as C28x and FPU but with a leading V CPU MPY ACC T loc16 FPU MPYF32 R0H R1H R2H VCU VCMPY VR3 VR2 VR1 VR0 Destination Source Operands Enabling VCU Support in CCS Set the Specify VCU support project option to vcu0 When creating a new CCS project choosing a device variant that has the VCU will automatically select this option so normally no user action is required ...

Page 265: ...gen Tools v6 x linker can generate a CRC of an output section and automatically embed it into the out file CRC Unit CRC Unit Cyclic Redundancy Check CRC is an error detecting code used to ensure data integrity Communication networks Data storage memory content check Supports 4 different CRC polynomials CRC Operation Polynomial Standard CRC8 0x07 PRIME CRC16 Poly 1 0x8005 CRC16 Poly 2 0x1021 G3 PLC...

Page 266: ...8005 VCRC16P1L_1 mem16 VCRC16P1L_1 mem16 1 1 CRC16 Poly 2 0x1021 VCRC16P2L_1 mem16 VCRC16P2L_1 mem16 1 1 CRC32 Poly 0x04C11DB7 VCRC32L_1 mem16 VCRC32H_1 mem16 1 1 CRC register VCRC contains current CRC value updated as CRC instructions read memory Viterbi Unit Viterbi Unit Viterbi an error correcting decoder Encoder adds redundant data to a message Viterbi decoder used to detect and correct errors...

Page 267: ...erbi F28x Decoder VCU Viterbi Implementation Decoder has 3 main parts Branch metrics calculation Calculates local distance between every possible state and the received symbol Code Rate 1 2 1 cycle Code Rate 1 3 2p cycles Butterfly add compare select operation Calculates path metrics to choose an optimal path 4 calculations done in a single cycle VITDLADDSUB VCU 2 cycles F28x 15 cycles Trace back ...

Page 268: ... Trace Back VTRACE mem32 VR0 VT0 VT1 VTRACE VR1 VR0 VT0 VT1 1 1 Double Add and Subtract or Subtract and Add with Parallel Store VITDLADDSUB VR4 VR3 VR2 VRa VMOV32 mem32 VRb 1 1 Branch Matric CR 1 2 or 1 3 with Parallel Load VBITM3 VR0 VR1 VR2 VMOV32 VR2 mem32 2p 1 Viterbi Select with Parallel Load VITLSEL VRa VRb VR4 VR3 VMOV32 VR2 mem32 1 1 VBITM2 VMOV32 For CR 1 2 cycles are 1 1 Complex Math Uni...

Page 269: ... bit real VR2 32 bit imaginary Input 2 VR5 32 bit real VR4 32 bit imaginary a c SHR b d SHR j VR5 VR4 Result VR5 32 bit real VR4 32 bit imaginary Complex Multiply VCMPY VR3 VR2 VR1 VR0 a bj c dj ac bcj adj bd j 2 ac bd bc ad j a bj VR0 Input 1 VR0H 16 bit real VR0L 16 bit imaginary Input 2 VR1H 16 bit real VR1L 16 bit imaginary c dj VR1 ac bd bc ad j VR3 VR2 Result VR3 32 bit real VR2 32 bit imagi...

Page 270: ...VR1 VR0 2p Complex MAC VCMAC VR5 VR4 VR3 VR2 VR1 VR0 2p RPT MAC VCMAC VR7 VR6 VR5 VR4 mem32 XAR7 2p N Add Sub Multiply with Parallel Load VCADD VR5 VR4 VR3 VR2 VMOV32 VR2 mem32 1 1 ADD16 SUB16 with Parallel Load VCSUB16 VR6 VR4 VR3 VR2 VMOV32 VR2 mem32 1 1 Multiply with Parallel Store VCMPY VR3 VR2 VR1 VR0 VMOV32 mem32 VR2 2p 1 MAC with Parallel Load VMAC VR5 VR4 VR3 VR2 VR1 VR0 VMOV32 VRa mem32 2...

Page 271: ...of system design Details of the emulation and analysis block along with JTAG will be explored Flash memory programming and the Code Security Module will be described Module Objectives Module Objectives Emulation and Analysis Block Flash Configuration and Memory Performance Flash Programming Code Security Module CSM ...

Page 272: ...orkshop System Design Module Topics System Design 12 1 Module Topics 12 2 Emulation and Analysis Block 12 3 Flash Configuration and Memory Performance 12 6 Flash Programming 12 9 Code Security Module CSM 12 11 Lab 12 Programming the Flash 12 14 ...

Page 273: ...t all TI MCU DSP platforms although those can certainly be used These emulators are much slower than the ones listed above but are also available at a lower cost than XDS510 class and are NOT C2000 specific H E A D E R System Under Test SCAN IN SCAN OUT Emulator Pod TMS320C2000 XDS200 CLASS offers a balance of low cost with good performance fitting between XDS100 and XDS510 Emulator Connections to...

Page 274: ...chpoint with Data Halt on a specified instruction only after some other specific routine has executed 1 Pair Chained Breakpoints Halt on a specified instruction for debugging in Flash 2 Hardware Breakpoints A memory location is getting corrupted halt the processor when any value is written to this location 2 Address Watchpoints Debug Activity Analysis Configuration On Chip Emulation Analysis Block...

Page 275: ...e to code as well Configure a watchpoint to monitor for writes near the end of the stack Watchpoint triggers maskable RTOSINT interrupt Works with DSP BIOS and non DSP BIOS See TI application report SPRA820 for implementation details Data Memory Monitor for data writes in region near the end of the stack Region of memory occupied by the stack Stack grows towards higher memory addresses ...

Page 276: ...defaults are maximum value 15 Flash configuration code should not be run from the Flash memory FlashRegs FBANKWAIT RANDWAIT reserved 15 0 4 3 8 7 PAGEWAIT reserved 12 11 FlashRegs FOTPWAIT OTPWAIT reserved 15 0 5 4 Refer to the F2806x datasheet for detailed numbers For 90 MHz PAGEWAIT 3 RANDWAIT 3 OTPWAIT 5 16 or 32 dispatched 16 64 Aligned 64 bit fetch 2 level deep fetch buffer 64 C28x Core decod...

Page 277: ...s to execute them 4 instructions 4 cycles 90 MHz 90 MIPS RPT will increase this PC discontinuity will degrade this Benchmarking in control applications has shown actual performance of about 81 MIPS Data Access Performance Assume 90 MHz SYSCLKOUT Internal RAM has best data performance put time critical data here Flash performance usually sufficient for most constants and tables Note that the flash ...

Page 278: ...IT Flash read access wait state register 0x00 0A87 FOTPWAIT OTP read access wait state register FPWR Save power by putting Flash OTP to Sleep or Standby mode Flash will automatically enter active mode if a Flash OTP access is made FSTATUS Various status bits e g PWR mode FSTDBYWAIT FACTIVEWAIT Specify of delay cycles during wake up from sleep to standby and from standby to active respectively The ...

Page 279: ...G Emulator SPI Flash Utility Code Flash Data I2C ROM Bootloader CAN SCI RS232 GPIO Flash Programming Basics Sequence of steps for Flash programming Minimum Erase size is a sector 8Kw or 16Kw Minimum Program size is a bit Important not to lose power during erase step If CSM passwords happen to be all zeros the CSM will be permanently locked Chance of this happening is quite small Erase step is perf...

Page 280: ... requires Signum emulator SCI Serial Port Bootloader Based Code Skin http www code skin com Elprotronic FlashPro2000 Production Test Programming Equipment Based BP Micro programmer Data I O programmer Build your own custom utility Can use any of the ROM bootloader methods Can embed flash programming into your application Flash API algorithms provided by TI TI web has links to all utilities http ww...

Page 281: ...ip memory is restricted Flash Registers 0x000A80 L0 DPSARAM 2Kw L1 DPSARAM 1Kw L2 DPSARAM 1Kw L3 DPSARAM 4Kw User OTP 1Kw ADC OSC cal data reserved reserved FLASH 128Kw PASSWORDS 8w reserved 0x008000 0x008800 0x008C00 0x00A000 0x009000 0x3D7800 0x3D7C00 0x3D7C80 0x3D7CC0 0x3D8000 0x3F7FF8 0x3F8000 L4 DPSARAM 8Kw 0x00C000 CSM Password 128 bit user defined password is stored in Flash 128 bit KEY reg...

Page 282: ...iption 0x3F 7FF8 PWL0 Low word of 128 bit password 0x3F 7FF9 PWL1 2nd word of 128 bit password 0x3F 7FFA PWL2 3rd word of 128 bit password 0x3F 7FFB PWL3 4th word of 128 bit password 0x3F 7FFC PWL4 5th word of 128 bit password 0x3F 7FFD PWL5 6th word of 128 bit password 0x3F 7FFE PWL6 7th word of 128 bit password 0x3F 7FFF PWL7 High word of 128 bit password PWL in memory reserved for passwords onl...

Page 283: ...ry Don t link the stack to secured RAM if you have any code that runs from unsecured RAM Do not embed the passwords in your code Generally the CSM is unlocked only for debug Code Composer Studio can do the unlocking CSM Password Match Flow Flash device secure after reset or runtime Do dummy reads of PWL 0x3F 7FF8 0x3F 7FFF Start Device permanently locked Device unlocked User can access on chip sec...

Page 284: ...ystem into Flash Memory Learn use of CCS Flash Programmer DO NOT PROGRAM PASSWORDS ADC RESULT0 ePWM2 connector wire TB Counter Compare Action Qualifier ePWM1 ADCINA0 ePWM2 triggering ADC on period match using SOCA trigger every 20 µs 50 kHz CPU copies result to buffer during CLA ISR data memory Display using CCS CLA _Cla1Task1 _Cla1Task2 _Cla1Task8 Procedure Open the Project 1 A project named Lab1...

Page 285: ...hich is the address from which the section is accessed at runtime The linker assigns both addresses to the section Most initialized sections can have the same LOAD and RUN address in the flash However some initialized sections need to be loaded to flash but then run from RAM This is required for example if the contents of the section needs to be modified at runtime by the code 2 Open and inspect t...

Page 286: ...a is used to place the InitFlash function into a linkable section named secureRamFuncs 8 The secureRamFuncs section will be linked using the user linker command file Lab_12 cmd Open and inspect Lab_12 cmd The secureRamFuncs will load to flash load address but will run from L4SARAM run address Also notice that the linker has been asked to generate symbols for the load start load size and run start ...

Page 287: ...o be placed at this address Note that the CSM passwords begin at address 0x3F7FF8 There are exactly two words available to hold this branch instruction and not coincidentally a long branch instruction LB in assembly code occupies exactly two words Generally the branch instruction will branch to the start of the C environment initialization routine located in the C compiler runtime support library ...

Page 288: ...ory space Close the inspected files Build Lab out 18 Click the Build button to generate the Lab out file to be used with the CCS Flash Programmer Check for errors in the Problems window Programming the On Chip Flash Memory In CCS the on chip flash programmer is integrated into the debugger When the program is loaded CCS will automatically determine which sections reside in flash memory based on th...

Page 289: ...lCARD blinking Try resetting the CPU select the EMU_BOOT_FLASH boot mode and then hitting run without doing all the stepping and the Go Main procedure The LED should be blinking again 26 Halt the CPU Terminate Debug Session and Close Project 27 Terminate the active debug session using the Terminate button This will close the debugger and return CCS to the CCS Edit Perspective view 28 Next close th...

Page 290: ...page 0 FLASH length 0x1FF80 page 0 0x3D 8000 0x3F 7F80 0x3F 7FF6 0x3F 7FF8 origin SECTIONS codestart BEGIN_FLASH PAGE 0 passwords PASSWORDS PAGE 0 csm_rsvd CSM_RSVD PAGE 0 Lab_12 cmd Startup Sequence from Flash Memory 0x3F 7FF6 0x3D 8000 0x3F 8000 0x3F FFC0 Boot ROM 32Kw BROM vector 32w 0x3F F75C Boot Code RESET 0x3F F75C SCAN GPIO FLASH 128Kw Passwords 8w _c_int00 LB rts2800_ml lib user code sect...

Page 291: ...pabilities Once these features and capabilities are understood additional information can be obtained from various resources such as documentation as needed This module will cover the basic operation of the communication peripherals as well as some basic terms and how they work Module Objectives Module Objectives Serial Peripheral Interface SPI Serial Communication Interface SCI Multichannel Buffe...

Page 292: ...Summary 13 15 Multichannel Buffered Serial Port McBSP 13 16 Definition Bit Word and Frame 13 16 Multi Channel Selection 13 17 McBSP Summary 13 18 Inter Integrated Circuit I2C 13 19 I2C Operating Modes and Data Formats 13 20 I2C Summary 13 21 Universal Serial Bus USB 13 22 USB Communication 13 23 Enumeration 13 23 F2806x USB Hardware 13 24 USB Controller Summary 13 24 Enhanced Controller Area Netwo...

Page 293: ...of high level communication between devices Like the GPIO pins they may be used in stand alone or multiprocessing systems In a multiprocessing system they are an excellent choice when both devices have an available serial port and the data rate requirement is relatively low Serial interface is even more desirable when the devices are physically distant from each other because the inherently low nu...

Page 294: ...e SPIDAT register Data to be transmitted is written directly to the SPIDAT register and received data is latched into the SPIBUF register for reading by the CPU This allows for double buffered receive operation in that the CPU need not read the current received data from SPIBUF before a new receive operation can be started However the CPU must read SPIBUF before the new operation is complete of a ...

Page 295: ... data to be sent to its shift register SPIDAT or SPITXBUF 3 Completing Step 2 automatically starts SPICLK signal of the Master 4 MSB of the Master s shift register SPIDAT is shifted out and LSB of the Slave s shift register SPIDAT is loaded 5 Step 4 is repeated until specified number of bits are transmitted 6 SPIDAT register is copied to SPIRXBUF register 7 SPI INT Flag bit is set to 1 8 An interr...

Page 296: ...n is complete such that received characters of less than 16 bits will be right justified in SPIBUF The non utilized higher significance bits must be masked off by the CPU software when it interprets the character For example a 9 bit character transmission would require masking off the 7 MSB s SPI Data Character Justification Programmable data length of 1 to 16 bits Transmitted data of less than 16...

Page 297: ...ts baud rate register SPIBRR 6 0 For SPIBRR 3 to 127 SPI Baud Rate 1 SPIBRR LSPCLK bits sec For SPIBRR 0 1 or 2 SPI Baud Rate 4 LSPCLK bits sec From the above equations one can compute Maximum data rate 20 Mbps 80 MHz Character Length Determination The Master and Slave must be configured for the same transmission character length This is done with bits 0 1 2 and 3 of the configuration control regi...

Page 298: ...PIFFTX FIFO Receive SpixRegs SPIFFRX FIFO Enable FIFO Reset FIFO Over flow flag Over flow Clear Number of Words in FIFO FIFO Status FIFO Interrupt Enable Interrupt Status Interrupt Clear FIFO Interrupt Level Number of Words in FIFO Note refer to the reference guide for a complete listing of registers SPI Summary SPI Summary Synchronous serial communications Two wire transmit or receive half duplex...

Page 299: ...l duplex interface which provides for simultaneous data transmit and receive Parity checking and data formatting is also designed to be done by the port hardware further reducing software overhead SCI Pin Connections Transmitter data buffer register SCI Device 1 SCIRXD SCITXD SCITXD SCIRXD SCI Device 2 8 Receiver data buffer register 8 Transmitter data buffer register Receiver shift register Trans...

Page 300: ...ame Frames are organized into groups called blocks If more than two serial ports exist on the SCI bus a block of data will usually begin with an address frame which specifies the destination port of the data as determined by the user s protocol The start bit is a low bit at the beginning of each frame which marks the beginning of a frame The SCI uses a NRZ Non Return to Zero format which means tha...

Page 301: ... SCICLK periods per data bit Multiprocessor Wake Up Modes Multiprocessor Wake Up Modes Allows numerous processors to be hooked up to the bus but transmission occurs between only two of them Idle line or Address bit modes Sequence of Operation 1 Potential receivers set SLEEP 1 which disables RXINT except when an address frame is received 2 All transmissions begin with an address frame 3 Incoming ad...

Page 302: ...eriod 10 bits or greater Idle Period 10 bits or greater Address frame follows 10 bit or greater idle 1st data frame SP ST Addr Idle periods of less than 10 bits Address Bit Wake Up Mode All frames contain an extra address bit Receiver wakes up when address bit detected Automatic setting of Addr Data bit in frame by setting TXWAKE 1 prior to writing address to SCITXBUF Last Data ST ST Data SCIRXD S...

Page 303: ...racter has been received and shifted into SCIRXBUF the RXRDY flag is set In addition the BRKDT flag is set if a break condition occurs A break condition is where the SCIRXD line remains continuously low for at least ten bits beginning after a missing stop bit Each of the above flags can be polled by the CPU to control SCI operations or interrupts associated with the flags can be enabled by setting...

Page 304: ...ILBAUD 7 6 5 4 3 2 1 0 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1 BAUD7 BAUD0 LSB SCI baud rate LSPCLK BRR 1 x 8 LSPCLK 16 BRR 1 to 65535 BRR 0 Baud Rate Determination The values in the baud select registers SCIHBAUD and SCILBAUD concatenate to form a 16 bit number that specifies the baud rate for the SCI For BRR 1 to 65535 SCI Baud Rate 8 1 BRR LSPCLK bits sec For BRR 0 SCI Baud Rate 16 LSPCLK bits sec Max da...

Page 305: ...ScixRegs SCIFFRX FIFO Enable FIFO Reset FIFO Over flow flag Over flow Clear Number of Words in FIFO FIFO Status FIFO Interrupt Enable Interrupt Status Interrupt Clear FIFO Interrupt Level Number of Words in FIFO Note refer to the reference guide for a complete listing of registers SCI Summary SCI Summary Asynchronous communications format 65 000 different programmable baud rates Two wake up multip...

Page 306: ...TX Buffer XSR1 16 DRR2 RX Buffer RBR2 Register 16 DRR1 RX Buffer RBR1 Register 16 RSR2 16 RSR1 MDXx MDRx MFSXx MFSRx MCLKXx MCLKRx Peripheral DMA Bus Peripheral DMA Bus 16 16 16 16 CPU Definition Bit Word and Frame Definition Bit and Word CLK b7 b6 b5 b4 b3 b2 b1 b0 Word FS a1 a0 Bit D Word or channel contains number of bits 8 12 16 20 24 32 Bit one data bit per serial clock period ...

Page 307: ... registers MCR Multi channel Control Reg enables Mc mode R XCER A H Rec Xmt Channel Enable Regs enable disable channels Up to 128 channels can be enabled disabled C O D E C M c B S P Frame TDM Bit Stream Ch0 Ch1 Ch31 0 Ch0 Ch1 Ch31 1 Transmit Receive only selected Channels Multi channel Allows multiple channels words to be independently selected for transmit and receive e g only enable Ch0 5 27 fo...

Page 308: ...ry McBSP Summary Independent clocking and framing for transmit and receive Internal or external clock and frame sync Data size of 8 12 16 20 24 or 32 bits TDM mode up to 128 channels Used for T1 E1 interfacing µ law and A law companding SPI mode Direct Interface to many codecs Can be serviced by the DMA ...

Page 309: ...or Slave Master initiates data transfer and generates clock signal Device addressed by Master is considered a Slave Multi Master mode supported Standard Mode send exactly n data values specified in register Repeat Mode keep sending data values use software to initiate a stop or new start condition 28xx I2C I2C Controller I2C EPROM 28xx I2C Pull up Resistors VDD Serial Data SDA Serial Clock SCL I2C...

Page 310: ...ves data from a slave can only be entered from master transmit mode Master transmitter mode Module is a master and transmits to a slave all masters begin in this mode I2C Serial Data Formats S Slave Address R W ACK Data Data ACK ACK P 1 7 1 1 n 1 n 1 1 7 Bit Addressing Format S 11110AA R W ACK AAAAAAAA Data ACK ACK P 1 7 1 1 8 1 n 1 1 10 Bit Addressing Format S Data ACK Data Data ACK ACK P 1 n 1 n...

Page 311: ...h is overruled by another master transmitter that drives SDA low Procedure gives priority to the data stream with the lowest binary value 1 0 1 0 0 1 0 1 1 0 0 1 0 1 SCL SDA Data from device 1 Data from device 2 Device 1 lost arbitration and switches to slave receiver mode Device 2 drives SDA I2C Summary I2C Summary Compliance with Philips I2C bus specification version 2 1 7 bit and 10 bit address...

Page 312: ... access controller DMA All six endpoints can trigger separate DMA events Channel requests asserted when FIFO contains required amount of data USB Formed by the USB Implementers Forum USB IF http www usb org USB IF has defined standardized interfaces for common USB application known as Device Classes Human Interface Device HID Mass Storage Class MSC Communication Device Class CDC Device Firmware Up...

Page 313: ...e bus Only the master keeps track of other devices on bus Only the master can initiate transactions Slave simply responds to host commands This makes USB simpler and cheaper to implement Enumeration Enumeration USB is universal because of Enumeration Process in which a Host attempts to identify a Device If no device attached to a downstream port then the port sees Hi Z When full speed device is at...

Page 314: ...sing 100k and internal device ESD diode clamps Note 1 VBus sensing is only required in self powered applications 2 Device pins D and D have special buffers to support the high speed requirements of USB therefore their position on the device is not user selectable USB Controller Summary USB Controller Summary Complies with USB 2 0 specifications Full speed 12 Mbps Device controller Full Low speed 1...

Page 315: ...e and more reliable Redundant error checking high reliability No node addressing message identifiers Broadcast based signaling C E D A B CAN does not use physical addresses to address stations Each message is sent with an identifier that is recognized by the different nodes The identifier has two functions it is used for message filtering and for message priority The identifier determines if a tra...

Page 316: ... Mbps CAN NODE B CAN NODE A CAN NODE C CAN_H CAN_L 120Ω 120Ω The MCU communicates to the CAN Bus using a transceiver The CAN bus is a twisted pair wire and the transmission rate depends on the bus length If the bus is less than 40 meters the transmission rate is capable up to 1 Mbit second CAN Node Wired AND Bus Connection RX TX CAN Controller e g TMS320F28035 CAN_L CAN_H 120Ω 120Ω CAN Transceiver...

Page 317: ...nt it is processed received otherwise it is ignored Unique identifier also determines the priority of the message lower the numerical value of the identifier the higher the priority When two or more nodes attempt to transmit at the same time a non destructive arbitration technique guarantees messages are sent in order of priority and no messages are lost Non Destructive Bitwise Arbitration Bus arb...

Page 318: ...er CAN v2 0B 11 bit Identifier R T R S O F I D E r0 DLC 0 8 Bytes Data CRC ACK E O F Arbitration Field Control Field Data Field Control Field 11 bit Identifier R T R S O F I D E r0 DLC 0 8 Bytes Data CRC ACK r1 18 bit Identifier S R R E O F Arbitration Field Data Field The MCU CAN module is a full CAN Controller It contains a message handler for transmission and reception management and frame stor...

Page 319: ...ntroller module contains 32 mailboxes for objects of 0 to 8 byte data lengths configurable transmit receive mailboxes configurable with standard or extended indentifier The CAN module mailboxes are divided into several parts MID contains the identifier of the mailbox MCF Message Control Field contains the length of the message to transmit or receive and the RTR bit Remote Transmission Request used...

Page 320: ...AN standard v2 0B Supports data rates up to 1 Mbps Thirty two mailboxes Configurable as receive or transmit Configurable with standard or extended identifier Programmable receive mask Uses 32 bit time stamp on messages Programmable interrupt scheme two levels Programmable alarm time out Programmable wake up on bus activity Self test mode ...

Page 321: ...opment Support Introduction This module contains various references to support the development process Module Objectives Module Objectives TI Workshops Download Site controlSUITE TI Development Tools Additional Resources Product Information Center On line support ...

Page 322: ...dule Topics 14 2 TI Support Resources 14 3 C2000 Workshop Download Wiki 14 3 controlSUITE 14 4 C2000 Experimenter s Kits 14 5 F28335 Peripheral Explorer Kit 14 6 C2000 controlSTICK Evaluation Tool 14 7 C2000 LaunchPad Evaluation Kit 14 8 C2000 controlCARD Application Kits 14 9 Product Information Resources 14 10 ...

Page 323: ...op Download Wiki C2000 Workshop Download Wiki http www ti com hands on training At the C2000 Workshop Download Wiki you will find all of the materials for the C2000 One day and Multi day Workshops as well as the C2000 archived workshops which include support for the F2407 F2812 F2808 and F28335 device families ...

Page 324: ...ware and has been designed to minimize software development time Included in controlSUITE are device specific drivers and support software as well as complete system design examples used in sophisticated applications controlSUITE is a one stop single centralized location to find all of your C2000 software needs Download controlSUITE from the TI website ...

Page 325: ...d the TI eStore Part Number TMDSDOCK28069 TMDSDOCK28035 TMDSDOCK28027 TMDSDOCK28335 TMDSDOCK2808 TMDSDOCKH52C1 TMDSDOCK28377D JTAG emulator required for TMDSDOCK28343 TMDSDOCK28346 168 The C2000 development kits are designed to be modular and robust These kits are complete open source evaluation and development tools where the user can modify both the hardware and software to best fit their needs ...

Page 326: ...ull hardware details Code Composer Studio Peripheral Explorer features ADC input variable resistors GPIO hex encoder push buttons eCAP infrared sensor GPIO LEDs I2C CAN connection Analog I O AIC McBSP Onboard USB JTAG Emulation JTAG emulator not required Available through TI authorized distributors and the TI eStore TMDSPREX28335 The Peripheral Explorer Kit provides a simple way to learn and inter...

Page 327: ...ion JTAG emulator not required Access to controlSTICK signals C2000 Applications Software CD with example code and full hardware details Code Composer Studio Available through TI authorized distributors and the TI eStore Part Number TMDX28069USB TMDS28027USB The controlSTICK is an entry level evaluation kit It is a simple stand alone tool that allows users to learn the device and software quickly ...

Page 328: ...G emulator not required Access to LaunchPad signals C2000 Applications Software with example code and full hardware details in available in controlSUITE Code Composer Studio Available through TI authorized distributors and the TI eStore Part Number LAUNCHXL F28027 LAUNCHXL F28027F The LaunchPad is a low cost evaluation kit Like the controlSTICK it is a simple stand alone tool that allows users to ...

Page 329: ...ftware download includes Complete schematics BOM gerber files and source code for board and all software Quickstart demonstration GUI for quick and easy access to all board features Fully documented software specific to each kit and application See www ti com c2000 for other kits and more details Available through TI authorized distributors and the TI eStore The controlCARD based Application Kits ...

Page 330: ...E mail support ti com TI E2E Community videos forums blogs http e2e ti com Embedded Processor Wiki http processors wiki ti com TI Training http www ti com training TI eStore http estore ti com TI website http www ti com For more information and support you can contact the product information center visit the TI E2E community embedded processor Wiki TI training web page TI eStore and the TI website...

Page 331: ...C2000 Microcontroller Workshop Appendix A Experimenter s Kit A 1 Appendix A Experimenter s Kit ...

Page 332: ...p View A 3 LD1 LD2 LD3 A 3 SW1 A 3 SW2 A 4 F28035 controlCARD A 5 F28035 PCB Outline Top View A 5 LD1 LD2 LD3 A 5 SW1 A 5 SW2 A 6 SW3 A 6 F28335 controlCARD A 7 F28335 PCB Outline Top View A 7 LD1 LD2 LD3 A 8 SW1 A 8 SW2 A 9 Docking Station A 10 SW1 LD1 A 10 JP1 JP2 A 10 J1 J2 J3 J8 J9 A 10 F2833x Boot Mode Selection A 11 F280xx Boot Mode Selection A 11 J3 DB 9 to 4 Pin Header Cable A 12 ...

Page 333: ...F28069 controlCARD C2000 Microcontroller Workshop Appendix A Experimenter s Kit A 3 F28069 controlCARD F28069 PCB Outline Top View LD1 LD2 LD3 SW1 ...

Page 334: ...F28069 controlCARD A 4 C2000 Microcontroller Workshop Appendix A Experimenter s Kit SW2 ...

Page 335: ...F28035 controlCARD C2000 Microcontroller Workshop Appendix A Experimenter s Kit A 5 F28035 controlCARD F28035 PCB Outline Top View LD1 LD2 LD3 SW1 ...

Page 336: ...F28035 controlCARD A 6 C2000 Microcontroller Workshop Appendix A Experimenter s Kit SW2 SW3 ...

Page 337: ...F28335 controlCARD C2000 Microcontroller Workshop Appendix A Experimenter s Kit A 7 F28335 controlCARD F28335 PCB Outline Top View ...

Page 338: ...F28335 controlCARD A 8 C2000 Microcontroller Workshop Appendix A Experimenter s Kit LD1 LD2 LD3 SW1 ...

Page 339: ...boot options used in this workshop are shown below Position 1 GPIO 84 Position 2 GPIO 85 Position 3 GPIO 86 Position 4 GPIO 87 Boot Mode 0 0 1 0 SARAM 1 1 1 1 FLASH For a complete list of boot mode options see the F2833x Boot Mode Selection table in the Docking Station section in this appendix ...

Page 340: ...5 0 V power supply input JP2 USB JTAG emulation port J1 J2 J3 J8 J9 J1 ControlCARD 100 pin DIMM socket J2 JTAG header connector J3 UART communications header connector J8 Internal emulation enable disable jumper NO jumper for internal emulation J9 User virtual COM port to C2000 device Note ControlCARD would need to be modified to disconnect the C2000 UART connection from header J3 ...

Page 341: ...Station routes through the FT2232 USB device By default this device enables the USB connection to perform JTAG communication and in parallel create a virtual serial port SCI UART As shipped the C2000 device is not connected to the virtual COM port and is instead connected to J3 F2833x Boot Mode Selection F280xx Boot Mode Selection ...

Page 342: ...ocking Station A 12 C2000 Microcontroller Workshop Appendix A Experimenter s Kit J3 DB 9 to 4 Pin Header Cable Note This cable is NOT included with the Experimenter s Kit and is only shown for reference ...

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