Hardware
Table 7. P1 - GPIO Header Pin
Assignments (continued)
Pin Number
Pin Function
11
GPIO5
12
Ground (DGND)
13
VIO
14
Ground (DGND)
NOTE:
The P1 - GPIO header is a 7x2 dual row unshrouded header. Pin 1 has a square pad on the
underside of the PCB, and the silk screen for the header indicates pin 1 with a small white
dot. All even numbered pins are on one, and all odd numbered pins are on the other, row of
the header.
5.3
Test Points
contains a list of test points provided on the evaluation module.
Table 8. bq76PL455EVM Test Points
Name
Description
BAT16
Positive terminal of cell 16
BAT0
Negative terminal of cell 1
S0-S16
Connected to Vsense0-16 on bq76PL455A-Q1
TOP
Connected to TOP pin of bq76PL455A-Q1 – primary power supply to bq76PL455A-Q1
VP1
Regulated 5.3-V supply
VDIG
Digital 5.3-V supply (connected to VP1)
V5VAO
5.3-V output from bq76PL455A-Q1
AGND1
Local analog ground
AGND2
Quiet analog ground
OUT
AFE analog output from bq76PL455A-Q1
VREF
2.500 V precision reference output from bq76PL455A-Q1
VIO
I/O supply (connected to VIO pin on the bq76PL455A-Q1)
DGND
Local digital ground
VM
–5-V charge pump output from bq76PL455A-Q1
CHP
Charge pump flying capacitor connection
V1.8
1.8-V output from bq76PL455A-Q1 (provided for compatibility with early devices only)
WAKEUP
The single-ended, active high wake pin to the bq76PL455A-Q1
FLT-N
The single-ended, active low fault pin from the bq76PL455A-Q1 (to the PC)
RX
The single-ended serial data receive pin on the bq76PL455A-Q1 (data from PC)
TX
The single-ended serial data transmit pin on the bq76PL455A-Q1 (data to the PC)
COMMH+
Half of the differential pair communicating data to and from the lower of two neighboring bq76PL455EVMs to
the next higher bq76PL455EVM
COMMH–
Half of the differential pair communicating data to and from the lower of two neighboring bq76PL455EVMs to
the next higher bq76PL455EVM
COMML+
Half of the differential pair communicating data to and from the higher of two neighboring bq76PL455EVMs
to the next lower bq76PL455EVM
COMML–
Half of the differential pair communicating data to and from the higher of two neighboring bq76PL455EVMs
to the next lower bq76PL455EVM
Half of the differential pair receiving fault information from the next higher bq76PL455EVM
FAULTH–
Half of the differential pair receiving fault information from the next higher bq76PL455EVM
Half of the differential pair transmitting fault information to the next lower bq76PL455EVM
FAULTL–
Half of the differential pair transmitting fault information to the next lower bq76PL455EVM
16
bq76PL455EVM and GUI User Guide
SLUUBA7A – April 2015 – Revised July 2015
Copyright © 2015, Texas Instruments Incorporated