Texas Instruments BQ76942, Manual

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7.19 Analog-to-Digital Converter (continued)
Typical values stated where T
A
= 25°C and V
BAT
= 55.0 V, min/max values stated where T
A
= -40°C to 85°C and V
BAT
= 4.7 V
to 55 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
B
(ADC_INL)
Integral nonlinearity
(when using V
REF1
and differential cell
voltage measurement
mode at VC10 - VC9)
(3)
16-bit, best fit over -0.1 V to 5.5 V –6.6 6.6 LSB
(4)
16-bit, best fit over -0.2 V to 0.2 V –4 4 LSB
(4)
B
(ADC_DNL)
Differential
nonlinearity 16-bit, no missing codes, using differential
cell voltage measurement at VC10-VC9
±0.12 LSB
(4)
B
(ADC_OFF_CELL)
Differential cell offset
error
16-bit, uncalibrated, using VC10 - VC9 –2.75 3.5 LSB
(4)
B
(ADC_OFF)
ADCIN offset error
16-bit, uncalibrated, using ADCIN mode on
TS1 pin
0.53 LSB
(5)
B
(ADC_OFF_DIV)
Divider offset error
16-bit, uncalibrated, using divider mode on
PACK pin
0.17 LSB
(7)
B
(ADC_OFF_DRIFT_CELL)
Differential cell offset
error drift
(3)
Offset error measured 16-bit, post calibration,
using VC10 - VC9. Drift measured as
change in offset over operating temperature
range as compared to offset at 30°C.
0.004 0.07 LSB/°C
(4)
B
(ADC_GAIN)
Gain
Gain measured 16-bit, over ideal input
voltage range, differential cell input mode on
VC10 - VC9, uncalibrated.
5385 5406 5427 LSB/V
(4)
B
(ADC_GAIN_DRIFT)
Gain drift
(3)
Gain measured 16-bit, over ideal input
voltage range, differential cell input mode
on VC10 - VC9, uncalibrated. Drift value
measured as change in gain over operating
temperature range, compared to gain at
30°C.
–0.25 0.025 0.25
LSB/V/
°C
(4)
R
(ADC_IN_CELL)
Effective input
resistance
(2)
Differential cell input mode on VC10 - VC9
(8)
3.0 MΩ
R
(ADC_IN_LD)
Effective input
resistance Divider measurement on LD pin (only active
while the LD pin is being measured)
2 MΩ
R
(ADC_IN_DIV)
Effective input
resistance
Divider measurement on VC10 and PACK
pins (only active while the pin is being
measured)
600 kΩ
B
(ADC_RES)
Code stability
(1) (3)
Single conversion, in NORMAL
mode,
Settings:Configuration:Power
Config[FASTADC] = 0
13.5 15 bits
B
(ADC_RES_FAST)
Code stability in fast
mode
(1)
Single conversion, in NORMAL
mode,
Settings:Configuration:Power
Config[FASTADC] = 1
14 bits
t
(ADC_CONV)
Conversion-time
Single conversion, in NORMAL
mode,
Settings:Configuration:Power
Config[FASTADC] = 0
2.93 ms
t
(ADC_CONV_FAST)
Conversion-time in
fast mode
Single conversion, in NORMAL
mode,
Settings:Configuration:Power
Config[FASTADC] = 1
1.46 ms
(1) Code stability is defined as the resolution such that the data exhibits 3-sigma variation within ±1-LSB.
(2) Specified by design
(3) Specified by characterization
(4) The 16-bit LSB size of the differential cell voltage measurement is given by 1 LSB = 5 x V
REF1
/ 2
N-1
≈ 5 x 1.212 V / 2
15
= 185 µV
(5) The 16-bit LSB size of the ADCIN voltage measurement is given by 1 LSB = 5 / 3 x V
REF1
/ 2
N-1
≈ 5 / 3 x 1.212 V / 2
15
= 62 µV
(6) The LSB size of the external thermistor voltage measurement when reported in 32-bit format is given by 1 LSB = 5 / 3 x V
REG18
/ 2
N-1
≈
5 / 3 x 1.8 V / 2
23
= 358 nV
(7) The 16-bit LSB size of the divider voltage measurement is given by 1 LSB = 425 / 3 x V
REF1
/ 2
N-1
≈ 425 / 3 x 1.212 / 2
15
= 5.24 mV
BQ76942
SLUSE14B – DECEMBER 2020 – REVISED DECEMBER 2021
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