Test Procedure
6
Test Procedure
This procedure describes the test configuration of the bq51025EVM-649 evaluation board (PWR649) for
bench evaluation.
6.1
Definition
The following naming conventions are used:
VXXX :
External voltage supply name (VBAT, VTS, V
OUT
)
LOADW:
External load name (LOADR, LOADI)
V(TPyy):
Voltage at internal test point TPyy. For example, V(TP02) means the voltage at TP02.
V(Jxx):
Voltage at header Jxx
V(TP(XXX)):
Voltage at test point XXX. For example, V(TP(ACDET)) means the voltage at the test
point which is marked as ACDET.
V(XXX, YYY):
Voltage across point XXX and YYY
I(JXX(YYY)):
Current going out from the YYY terminal of header XX
Jxx(BBB):
Terminal or pin BBB of header xx
JPx ON :
Internal jumper Jxx terminals are shorted
JPx OFF:
Internal jumper Jxx terminals are open
JPx (-YY-) ON:
Internal jumper Jxx adjacent terminals marked as YY are shorted
UUT:
Unit Under Test (PWR649 EVM)
Assembly drawings have locations for jumpers, test points, and individual components.
6.2
Procedure
The following operating procedures are provided at a variety of operating loads. Initial testing is done with
the 10-W transmitter (PWR648).
shows the proper alignment between the transmitter (PWR648) and receiver (PWR649).
10
bq51025 Evaluation Module (PWR649)
SLUUB55 – September 2014
Copyright © 2014, Texas Instruments Incorporated
