9.5.1.25 ADCCTRL0 Register (Address = 0x40) [reset = 0x2]
ADCCTRL0 is shown in
and described in
Return to
.
Figure 9-40. ADCCTRL0 Register
7
6
5
4
3
2
1
0
ADC_READ_RATE_1:0
ADC_CONV_S
TART
ADC_CONV_SPEED_1:0
ADC_COMP1_2:0
R/W-2b00
R/W-1b0
R/W-2b00
R/W-3b010
Table 9-34. ADCCTRL0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
ADC_READ_RATE_1:0
R/W
2b00
Read rate for ADC measurements in BAT Only operation
2b00 = Manual Read (Measurement done when
ADC_CONV_START is set)
2b01 = Continuous
2b10 = Every 1 second
2b11 = Every 1 minute
5
ADC_CONV_START
R/W
1b0
ADC Conversion Start Trigger
Bit goes back to 0 when conversion is complete
1b0 = No ADC conversion
1b1 = Initiates ADC measurement in Manual Read operation
4-3
ADC_CONV_SPEED_1:0 R/W
2b00
ADC Conversion Speed
2b00 = 24 ms (highest accuracy)
2b01 = 12 ms
2b10 = 6 ms
2b11 = 3 ms
2-0
ADC_COMP1_2:0
R/W
3b010
ADC Channel for Comparator 1
3b000 = Disabled
3b001 = ADCIN
3b010 = TS
3b011 = VBAT
3b100 = ICHARGE
3b101 = VIN
3b110 = PMID
3b111 = IIN
SLUSEC5 – DECEMBER 2020
Copyright © 2020 Texas Instruments Incorporated
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