9.5.1.23 ICCTRL1 Register (Address = 0x36) [reset = 0x0]
.
Return to
.
Figure 9-38. ICCTRL1 Register
7
6
5
4
3
2
1
0
MR_LPRESS_ACTION_1:0
ADCIN_MODE
RESERVED
PG_MODE_1:0
PMID_MODE_1:0
R/W-2b00
R/W-1b0
R/W-1b0
R/W-2b00
R/W-2b00
Table 9-32. ICCTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
MR_LPRESS_ACTION_1:
0
R/W
2b00
MR Long Press Action
2b00 = HW Reset (Power Cycle)
2b01 = Do nothing
2b10 = Enter Ship Mode
2b11 = Enter Ship Mode
5
ADCIN_MODE
R/W
1b0
ADCIN Pin Mode of Operation
1b0 = General Purpose ADC input (no Internal biasing)
1b1 = 10K NTC ADC input (80 µA biasing)
4
RESERVED
R/W
1b0
Reserved
3-2
PG_MODE_1:0
R/W
2b00
PG Pin Mode of Operation
2b00 = VIN Power Good
2b01 = Deglitched Level Shifted /MR
2b10 = General Purpose Open Drain Output
2b11 = General Purpose Open Drain Output
1-0
PMID_MODE_1:0
R/W
2b00
PMID Control
Sets how PMID is powered in any state, except Ship Mode.
2b00 = PMID powered from BAT or VIN if present
2b01 = PMID powered from BAT only, even if VIN is present
2b10 = PMID disconnected and left floating
2b11 = PMID disconnected and pulled down.
SLUSEC5 – DECEMBER 2020
Copyright © 2020 Texas Instruments Incorporated
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