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Bill of Materials, Board Layouts and Schematics

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1. Place input capacitor as close as possible to switching MOSFET

s supply and ground connections, and

use shortest copper trace connection. These parts must be placed on the same layer of the PCB
instead of on different layers and vias used to make this connection.

2. The integrated circuit (IC) must be placed close to the switching MOSFET

s gate terminals and the

gate drive signal traces kept short for a clean MOSFET drive. The IC can be placed on the other side
of the PCB of switching MOSFETs.

3. Place inductor input terminal to switching MOSFET's output terminal as close as possible. Minimize the

copper area of this trace to lower electrical and magnetic field radiation but make the trace wide
enough to carry the charging current. Do not use multiple layers in parallel for this connection.
Minimize parasitic capacitance from this area to any other trace or plane.

4. The charging current sensing resistor mut be placed right next to the inductor output. Route the sense

leads connected across the sensing resistor back to the IC in the same layer, close to each other
(minimize loop area), and do not route the sense leads through a high-current path. Place decoupling
capacitor on these traces next to the IC.

5. Place output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections need to be tied to the same copper that connects to the input

capacitor ground before connecting to system ground.

7. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the

IC, use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise
coupling.

8. Route analog ground separately from power ground. Connect analog ground and power ground

separately. Connect analog ground and power ground together using power pad as the single ground
connection point. Or use a 0-

Ω

resistor to tie analog ground to power ground (power pad must tie to

analog ground in this case if possible).

9. Decoupling capacitors must be placed next to the IC pins, and make trace connection as short as

possible.

10. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB

ground. Ensure that sufficient thermal vias are directly under the IC, connecting to the ground plane on
the other layers.

4

Bill of Materials, Board Layouts and Schematics

4.1

Bill of Materials

Table 2. Bill of Materials

Count

RefDes

Value

Description

Size

Part Number

MFR

1

C1

2.2

µ

F

Capacitor, Ceramic, 25V, X7R, 10%

1210

Std

Std

6

C2, C3, C4,

10

µ

F

Capacitor, Ceramic, 25V, X7R, 10%

1206

Std

Std

C5, C6, C7

6

C8, C14, C15, 0.1

µ

F

Capacitor, Ceramic, 25V, X7R, 10%

603

Std

Std

C16, C17,
C19

4

C9, C10, C20, 1

µ

F

Capacitor, Ceramic, 25V, X7R, 10%

603

Std

Std

C25

2

C11, C12

0.01

µ

F

Capacitor, Ceramic, 25V, X7R, 10%

603

Std

Std

0

C13, C18,

OPEN

Capacitor, Ceramic, 25V, X7R, 10%

603

Std

Std

C24, C26

1

C21

0.047

µ

F

Capacitor, Ceramic, 25V, X7R, 10%

603

Std

Std

1

C22

100 pF

Capacitor, Ceramic, 25V, X7R, 10%

603

Std

Std

1

C23

2200 pF

Capacitor, Ceramic, 25V, X7R, 10%

603

Std

Std

1

D1

BAT54-V-G

Diode, Schottky, 200-mA, 30-V

SOT23

BAT54-V-G

Vishay-Liteon

1

D2

BAT54C-V-G

Diode, Dual Schottky, 200-mA, 30-V

SOT23

BAT54C-V-G

Vishay-Liteon

1

J1

ED120/2DS

Terminal Block, 2-pin, 15-A, 5.1mm

0.40 x 0.35 inch

ED120/2DS

OST

1

J2

ED120/3DS

Terminal Block, 3-pin, 15-A, 5.1mm

0.60 x 0.35 inch

ED120/3DS

OST

2

J3, J4

ED555/3DS

Terminal Block, 3-pin, 6-A, 3.5mm

0.41 x 0.25 inch

ED555/3DS

OST

1

JP1

PEC02SAAN

Header, Male 2-pin, 100mil spacing,

0.100 inch x 2

PEC02SAAN

Sullins

8

bq24725EVM Evaluation Module

SLUU439A

August 2010

Revised May 2011

Submit Documentation Feedback

Copyright

©

2010

2011, Texas Instruments Incorporated

Summary of Contents for bq24725EVM

Page 1: ...2 10 Bottom Mask 12 11 Top Silkscreen 13 12 Bottom Silkscreen 13 13 Top Assembly 14 14 Bottom Assembly 14 List of Tables 1 bq24275EVM and EV2300 Connections 4 2 Bill of Materials 8 1 Introduction 1 1 EVM Features Evaluation module for bq24725 High efficiency NMOS NMOS synchronous buck charger with 750 kHz frequency High efficiency and low cost NMOS power path selector and integrated gate driver Us...

Page 2: ...r overload High accuracy current sense amplifiers enable accurate measurement of the ac adapter current allowing monitoring of overall system power For details see bq24725 data sheet SLUS702 1 3 I O Description Jack Description J1 DCIN AC adapter positive output J1 GND AC adapter negative output J2 SYS Connected to system J2 BAT Connected to battery pack J2 GND Ground J3 ACOK ACOK pin J3 IOUT IOUT...

Page 3: ...erve A B Observe if A B occur If they do not occur the unit under test has failed Assembly drawings have location for jumpers test points and individual components 2 2 Equipment 2 2 1 Power Supplies Power Supply 1 PS 1 a power supply capable of supplying 20 V at 5 A is required Power Supply 2 PS 2 a power supply capable of supplying 5 V at 1 A is required Power Supply 3 PS 3 a power supply capable...

Page 4: ...nd is newer do not overwrite the newer file 8 Click Finish 2 3 Equipment Setup 1 Set the power supply 1 for 0 V 100 mVdc with the current limit set to 5 A and then turn off supply 2 Connect the output of power supply 1 in series with a current meter multimeter to J1 DCIN GND 3 Connect a voltage meter across J1 DCIN GND 4 Set the power supply 2 for 3 3 V 100 mVdc 0 2 A 0 1 A current limit and then ...

Page 5: ...puter Open the bq24725 evaluation software The main window of the software is shown in Figure 3 Figure 3 Main Window of the bq24725 Evaluation Software 5 SLUU439A August 2010 Revised May 2011 bq24725EVM Evaluation Module Submit Documentation Feedback Copyright 2010 2011 Texas Instruments Incorporated ...

Page 6: ...inal EVM2300 installation USB port Open the bq24725 evaluation software The main window of the software is shown in Figure 3 3 Type in 512 mA in the Charge Current DAC and click the Write button This sets the battery charge current regulation threshold 4 Type in 12592 mV in the Charge Voltage DAC and click the Write button This sets the battery voltage regulation threshold Measure V J2 BAT 12 6 V ...

Page 7: ...nt meter with PS 3 Make sure a voltage meter is connected across J2 BAT GND Enable the output of the PS 3 Ensure that the output voltage is 10 V 500 mV Measure Measure V J2 SYS 19 5 V 1 V adapter connected to system 3 Turn off PS 1 Measure V J2 SYS 10 V 1 V battery connected to system Measure V J2 BAT 10 V 1 V battery connected to system 3 PCB Layout Guideline The switching node rise and fall time...

Page 8: ...om power ground Connect analog ground and power ground separately Connect analog ground and power ground together using power pad as the single ground connection point Or use a 0 Ω resistor to tie analog ground to power ground power pad must tie to analog ground in this case if possible 9 Decoupling capacitors must be placed next to the IC pins and make trace connection as short as possible 10 It ...

Page 9: ...1 603 Std Std 1 R15 430k Resistor Chip 1 16W 1 603 Std Std 1 R16 10 Resistor Chip 1 4W 1 1206 Std Std 3 R17 R18 10 0k Resistor Chip 1 16W 1 603 Std Std R19 1 R20 100k Resistor Chip 1 16W 1 603 Std Std 1 R21 12 1k Resistor Chip 1 16W 1 603 Std Std 1 R22 316k Resistor Chip 1 16W 1 603 Std Std 1 R23 3 01M Resistor Chip 1 16W 1 603 Std Std 1 R24 10 Resistor Chip 1 16W 1 603 Std Std 1 TP1 131 4244 00 A...

Page 10: ...nd Schematics www ti com 4 2 Board Layouts Figure 5 Top Layer Figure 6 Second Layer 10 bq24725EVM Evaluation Module SLUU439A August 2010 Revised May 2011 Submit Documentation Feedback Copyright 2010 2011 Texas Instruments Incorporated ...

Page 11: ...als Board Layouts and Schematics Figure 7 Third Layer Figure 8 Bottom Layer 11 SLUU439A August 2010 Revised May 2011 bq24725EVM Evaluation Module Submit Documentation Feedback Copyright 2010 2011 Texas Instruments Incorporated ...

Page 12: ... Layouts and Schematics www ti com Figure 9 Top Mask Figure 10 Bottom Mask 12 bq24725EVM Evaluation Module SLUU439A August 2010 Revised May 2011 Submit Documentation Feedback Copyright 2010 2011 Texas Instruments Incorporated ...

Page 13: ...oard Layouts and Schematics Figure 11 Top Silkscreen Figure 12 Bottom Silkscreen 13 SLUU439A August 2010 Revised May 2011 bq24725EVM Evaluation Module Submit Documentation Feedback Copyright 2010 2011 Texas Instruments Incorporated ...

Page 14: ...Figure 13 Top Assembly Figure 14 Bottom Assembly 4 3 Schematics The schematic is shown on the following page 14 bq24725EVM Evaluation Module SLUU439A August 2010 Revised May 2011 Submit Documentation Feedback Copyright 2010 2011 Texas Instruments Incorporated ...

Page 15: ...www ti com Bill of Materials Board Layouts and Schematics 15 SLUU439A August 2010 Revised May 2011 bq24725EVM Evaluation Module Submit Documentation Feedback Copyright 2010 2011 Texas Instruments Incorporated ...

Page 16: ...roduct This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engineer or visit www ti com esh No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine process or combination in which such TI products...

Page 17: ...horized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge ...

Page 18: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments BQ24725EVM 542 ...

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