•
Measure
➡
V
VBUS-PGND
(TP23 and TP44) = 12.0 V ±0.2 V
•
Measure
➡
V
BAT-PGND
(TP29 and TP46) = 8.0 V ±0.1 V
•
Measure
➡
I
BAT_SENSE
(voltage across 0.01-Ω resistor between TP19 and TP20) = 500 mA ±50 mA
•
Measure
➡
I
VAC1_SENSE
(voltage across 0.01-Ω resistor between TP1 and TP2) = 900 mA ±60 mA
•
Click READ ALL REGISTERS and Verify
➡
Charge Status reports fast charge
5. Increase Load #1 regulation voltage to 8.4 V and take measurements as follows:
•
Measure
➡
V
BAT-PGND
(TP29 and TP46) = 8.4 V ±0.04 V
•
Measure
➡
I
BAT_SENSE
(voltage across 0.01-Ω resistor between TP19 and TP20) = 0 mA ±10 mA
•
Click READ ALL REGISTERS and Verify
➡
Charge Status reports termination
6. Helpful hints when changing voltages and register settings from those above during charge mode:
• If increasing charge current or adding a load at SYS J3 terminal, you will likely need to disable the
EN_ILIM bit using the Charger Configuration page and increase the IINDPM register setting in the
Charger Configuration page.
• If increasing the input voltage above 8 V for the charger to enter buck mode, you will need to increase the
VAC_OVP from 7 V default using Charger Configuration page.
• The battery configuration is set at startup using the PROG pin (Jumpers JP24 to JP31). The battery
configuration can also be changed using the Quick Start page. Note that the SYSMIN and charge current
charge with cell configuration.
• The status, fault and interrupt bits report are helpful debug tools.
2.4.4 OTG Mode Verification
Use the following steps for OTG mode verification for boost operation:
1. Power up then turn off Load#2 output. Set to CR = 12 V/0.5 A = 24 Ω. Disconnect PS1 from J1 and attach
Load#2 to J1 (VIN1 and GND).
2. Increase Load #1 regulation voltage to 8.0 V and take measurements as follows:
•
Measure
➡
V
BAT-PGND
(TP29 and TP46) = 8.0 V ±0.1 V
3. Prepare the OTG mode charger register settings in the following way:
• In the
Chip Configuration
page below the
Chip Configuration
section
– Uncheck "EN Charge" to disable charge mode
– Check "EN OTG Mode" to enable OTG mode
– Check "EN ADRV1" to enable ACDR1 FETs
• In the
OTG Configuration
page below the
OTG Configuration
section
– Set the OTG Reg Voltage to 12.000 mV.
– Set the IOTG Limit to 1.000 A
4. Take measurements as follows:
•
Measure
➡
V
VBUS-PGND
(TP23 and TP44) = 12.0 V ±0.2 V
•
Measure
➡
V
AC1-PGND
(TP24 and TP44) = 12.0 V ±0.2 V. Note that the PCB silk screen for VAC1 and
VAC2 are reversed.
•
Click READ ALL REGISTERS
–
Verify
➡
REG1Bb[6] reports VINDPM or OTG
–
Verify
➡
REG1Cb[4:1] reports VBUS Status as Normal OTG
5. Turn on Load#2 output set to constant resistance (CR) of 24 Ω.
6. Take measurements as follows:
•
Measure
➡
V
AC1-PGND
(TP23 and TP44) = 12.0 V ±0.2 V
•
Measure
➡
I
AC1-SENSE
(TP1 and TP2) = 500 mA ±0.10 A
7. Lower the Load#2 to constant resistance (CR) to 10 Ω.
8. Take measurements as follows to confirm OTG current limit function:
•
Measure
➡
V
AC1-PGND
(TP23 and TP44) < 12.0 V ±0.2 V
•
Measure
➡
I
AC1-SENSE
(TP1 and TP2) = 1000 mA ±0.10 A
•
Click READ ALL REGISTERS and Verify
➡
REG1Bb[7] reports IINDPM
9. Hints for further OTG testing:
• Enabling OTG mode is a two-step process, first enable OTG and then turn on the appropriate AC drive
FETs.
Test Setup and Results
10
BQ25672 Evaluation Module
SLUUCF3A – DECEMBER 2020 – REVISED OCTOBER 2021
Copyright © 2021 Texas Instruments Incorporated
