PCB Layout Guidelines
9
SLUUC51A – June 2020 – Revised July 2020
Copyright © 2020, Texas Instruments Incorporated
BQ25790EVM (BMS027) Evaluation Module User's Guide
9. Hints for further OTG testing:
•
Enabling OTG mode is a two-step process, first enable OTG and then turn on the appropriate AC
drive FETs.
3
PCB Layout Guidelines
Careful placement of components is critical in order for the charger to meet specifications. The items
below are listed in order of placement priority.
1. Place high frequency decoupling capacitors for PMID and SYS (C24 and C26 on the EVM) as close
possible to their respective pins and ground pin on the same layer as the charger IC (in other words,
no vias) in order to have the smallest current loop.
2. Place bulk capacitors for PMID and SYS as close possible to their respective pins and the charger's
ground pin on the same layer as the charger IC on the same layer as the charger IC (in other words,
no vias).
3. Place the REGN capacitor (C34) to ground and BTST capacitors (C3 and C13) to SW as close as
possible to their respective pins only using vias for 1 side of each component if necessary.
4. Place high frequency decoupling capacitors for VBUS and BAT pins as close as possible to their
respective pins. Use at least 2 vias per capacitor terminal if required.
5. Place bulk capacitors for VBUS and BAT pins as close as possible to their respective pins. Use at
least 2 vias per capacitor terminal if required.
6. Place the inductor close to SW1 and SW2 pins. It is acceptable to use multiple vias to make these
connections as the vias are only adding small amounts of inductance and resistance to an inductor.
7. While this EVM has analog ground (AGND) and power ground (PGND) planes that connect close to
the charge GND pin, two grounds not required. Resistors and capacitors used for setting sensitive
nodes (for example, ILIM, TS) can use one common ground plane but with their ground terminals
connected away from high current ground return paths containing switching noise.
Note that this EVM has test points and jumpers requiring traces out to the PCB edges. Routing these
traces required some PCB layout compromises for less critical components than those listed in the first six
items above.
