Configuration 3: 802.3af Fully Compliant PD Interface with Rear Aux Power Support
www.ti.com
Note:
1.The sum of C1 and C2 comprises the valid signature capacitance. In practice, this configuration can delete C2 and
change C1 to 0.1µF.
2. R6 may need to be installed for classification other than the default Class 0. Refer to LM5073 datasheet for R6
selection.
3. The installed R7 (15.8k) is intended for high power PD applications, which sets the dc current limit to 800 mA. For
fully compliant applications, R7 may need to be removed or replaced in order to limit the dc current per IEEE 802.3af.
Refer to LM5073 datasheet for R7 selection.
Figure 3. IEEE 802.3af Fully Compliant PD Interface with Front Aux Power Support
11
Configuration 3: 802.3af Fully Compliant PD Interface with Rear Aux Power Support
shows the evaluation board configuration for an IEEE 802.3af fully compliant PD interface with rear Aux
power support. This configuration is recommended for low voltage Aux power sources such as 12V or 24
ac adapters. The minimum RAUX input voltage can be as low as 10V. Note that R12 (24.9k) is used to
overcome any leakage current of D2 in order to avoid faulty RAUX pin potential during PoE operation.
Also note that R1 and R2 are used to provide simple RAUX input filtering as well as inrush limit.
The following table shows the jumper positions for this configuration.
Table 4. Jumper Positions of Configuration 3
Jumper
Function
JMP1
Jumper pins short for Aux dominant.
Jumper pins open for non-Aux dominant feature.
JMP2
All three pins open.
JMP3
Pins 2 and 3 short, Pin 1 open.
JMP4, JMP5
Pins 2 and 3 short, Pin 1 open.
JMP6
Pins 2 and 3 short, Pin 1 open.
JMP7
Pins open.
JMP8
All three pins open.
6
AN-1574 LM5073 Evaluation Board
SNVA214A – April 2007 – Revised April 2013
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated