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SPRUI64E – May 2017 – Revised September 2019

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Copyright © 2017–2019, Texas Instruments Incorporated

Known Deficiencies in AM572x IDK EVM

Appendix A

SPRUI64E – May 2017 – Revised September 2019

Known Deficiencies in AM572x IDK EVM

A.1

Power solution not sufficient for full PCIe plug-in card compliance

The AM572x IDK EVM supports compatibility to PCIe x1 plug-in cards. It is not compliant with the PCIe
Card Electro-Mechanical (CEM) specification. Specifically, the board does not provide the recommended
power per the CEM. It provides up to 0.5A of current on the 3.3V/3.3V_AUX input pins and up to 0.5A on
the 12V input pins. Also, the root complex design implemented does not support hot plug-in of cards.

A.2

Early versions of the AM572x IDK EVM not installed with SOC devices rated for the

full industrial temperature range

A.3

AM572x IDK EVM does not support eMMC HS200 mode

The interface voltage for the eMMC is fixed at 3.3V in all modes of operation. This prevents support of
HS200 which requires a transition to 1.8V. The AM572x IDK EVM does support this voltage shift for the
SDCARD attached to the MMC1 port. The MMC1 port is on VDDSHV8 supply that is attached to the
LDO1 PMIC output that supports this voltage shift for higher speed modes. The eMMC is attached to the
VDDSHV11 supply fixed at 3.3V. Board designs that require HS200 support for eMMC would need a
solution to transition from 3.3V to 1.8V under software control.

A.4

PCIe PERSTn line not in proper state at start-up

The board does not contain pull-up or pull-down resistors to allow this line to be pulled-high at start-up.
This can cause PCIe link training to fail. Future software releases need to properly control the GPIO
output pins to enable this correctly at start-up.

A.5

EDIO connectors J4 and J7 should support real-time debugging for both PRU1 and

PRU2

The pins chosen provide visibility to the PRU2 MII0 and MII1 ports and PRU1 EDIO ports.

A.6

HDQ implementation not correct

HDQ was intended to be attached to the Expansion Connector. Since this pin is multiplexed with
XREF_CLK3/CLKOUT3 used with the Camera connector, the clock options implemented for the camera
connector prevent use of HDQ without addition of a wire. This can be enabled by adding a wire between
the open pads of R905 and R300.

A.7

Removing the power plug and inserting it again while the power supply is energized

may cause damage

Removing the power plug and inserting it again while the power supply is energized may damage the
AM572x IDK EVM and/or other devices attached to the board such as emulators that provide an alternate
path to ground. Removal of AC power from the external power supply is a safer method, if required. It is
also recommended that the external power supply have the common return bonded to earth ground. If this
is not possible, a separate connection from the board ground to earth ground may need to be provided.
Test fixtures that repeatedly cycle main power on and off should have the board ground bonded to earth
ground at all times during this testing.

Summary of Contents for AM5728

Page 1: ...AM572x Industrial Development Kit IDK Evaluation Module EVM Hardware User s Guide Literature Number SPRUI64E May 2017 Revised September 2019 ...

Page 2: ...nfiguration Setup 16 4 1 Boot Configuration 16 4 2 I2C Address Assignments 16 4 3 SEEPROM Header 17 4 4 JTAG Emulation 17 5 Memories Supported 18 5 1 DDR3L SDRAM 18 5 2 SPI NOR Flash 18 5 3 Board Identity Memory 18 5 4 SD MMC 18 5 5 eMMC NAND Flash 18 6 Ethernet Ports 19 6 1 100Mb Ethernet Ports on PRU ICSS 19 6 2 Gigabit 1000Mb Ethernet Ports 19 7 USB Ports 20 7 1 Processor USB Port 1 20 7 2 Proc...

Page 3: ...tion not correct 38 A 7 Removing the power plug and inserting it again while the power supply is energized may cause damage 38 A 8 Software shutdown of PMIC not operational 39 A 9 PMIC implementation does not support required SOC shut down sequence 39 A 10 USB port providing UART console and XDS100 emulation not isolated from EVM board supplies 39 A 11 Need 47 µf capacitor at camera header 39 A 12...

Page 4: ...ader Connector J37 26 8 MicroSD Connector J15 27 9 Power Jack Connector J1 27 10 Power Terminal Block Connector J2 27 11 PRU1ETH0 RJ45 Connector J3 28 12 PRU1ETH1 RJ45 Connector J5 28 13 PRU2ETH0 RJ45 Connector J6 29 14 PRU2ETH1 RJ45 Connector J8 29 15 PRU2ETH0 Test Header Connector J7 30 16 PRU2ETH1 Test Header Connector J4 30 17 Camera Connector J9 30 18 GigE RJ45 Connector J10 31 19 GigE RJ45 C...

Page 5: ...sion 2 0 Data Manual SPRZ429 AM572x Sitara Processors Silicon Errata Describes the known exceptions to the functional specifications for the device SPRUHZ6 AM572x Sitara Processors Technical Reference Manual Details the integration the environment the functional description and the programming models for each peripheral and subsystem in the device Support Resources TI E2E support forums are an eng...

Page 6: ...es the AM572x IDK may interface to other processors or systems and act as a communication gateway or controller In addition it can directly operate as a standard remote I O system or a sensor connected to an industrial communication network The AM572x IDK contains embedded emulation circuitry to quickly enable developers to begin using this IDK The embedded emulation logic allows emulation and deb...

Page 7: ...he AM572x IDK EVM consists of the main board and the camera board There is also an optional LCD panel and touch screen assembly that can be attached to the AM572x IDK EVM The top and the bottom views of the AM572x IDK EVM are provided in Figure 1 and Figure 2 respectively The top and the bottom views of the AM572x IDK EVM with the optional LCD display assembly attached are provided in Figure 3 and...

Page 8: ... SPRUI64E May 2017 Revised September 2019 Submit Documentation Feedback Copyright 2017 2019 Texas Instruments Incorporated AM572x Industrial Development Kit IDK Evaluation Module EVM Hardware Figure 2 AM572x IDK EVM Bottom View ...

Page 9: ...17 Revised September 2019 Submit Documentation Feedback Copyright 2017 2019 Texas Instruments Incorporated AM572x Industrial Development Kit IDK Evaluation Module EVM Hardware Figure 3 AM572x IDK EVM with LCD Display Assembly Attached Top View ...

Page 10: ...7 Revised September 2019 Submit Documentation Feedback Copyright 2017 2019 Texas Instruments Incorporated AM572x Industrial Development Kit IDK Evaluation Module EVM Hardware Figure 4 AM572x IDK EVM with LCD Display Assembly Attached Bottom View ...

Page 11: ...2 TPD2EUSB30 TPD4E05U06 DCAN Header PR1_MII0 muxed with RGMII0 TPD12S016 www ti com Functional Description 11 SPRUI64E May 2017 Revised September 2019 Submit Documentation Feedback Copyright 2017 2019 Texas Instruments Incorporated AM572x Industrial Development Kit IDK Evaluation Module EVM Hardware 2 Functional Description The AM572x IDK EVM is implemented on a single board with interface circuit...

Page 12: ... and RTC_PORz can only be directly connected as long as VDDSHV3 and VDDSHV5 are driven at the same voltage RSTOUTn Output signal from SOC indicating that the device has entered reset This is used to reset other circuits that must be reset at the same time as the processor More details about the behavior of these reset pins within the AM572x processor can be found in the AM572x Sitara Processors Si...

Page 13: ...d that the external power supply have the common return bonded to earth ground If this is not possible a separate connection from the board ground to earth ground may need to be provided 3 2 TPS6590377 PMIC The power requirements of the processor are met by the TPS6590377 Power Management IC PMIC The power sequencing requirements of the AM572x processor are also handled by the TPS6590377 PMIC Figu...

Page 14: ...12 0V from the main supply input It supplies voltage to the industrial interface circuits and the PCIe card connector TPS51200 DDR Termination Voltage LDO 2 each This LDO provides the push pull termination current required for the DDR3 memory interfaces There is one implemented for each DDR3 EMIF LP38693ADJ Low Dropout Regulator This LDO generates the 3 7V LCD bias voltage TPS61081DRC LCD Backligh...

Page 15: ... 06 V 1 06 V 1 35 V or 1 5 V 1 35 V or 1 5 V 1 8 V 1 8 V 1 35 V or 1 5 V 1 8 V 3 3 V 3 3 V 1 8 V 0 675 V or 0 75 V 1 8 V Peripherals DDR_REF SMPS9 1 A max LDO2 300 mA max VDDSHV5 RTC I O 3 3 V 3 3 V VREF 0 675 V or 0 75 V VDD_1V8 VDDA_1V8 PLLs 1V8_PHY USB SATA VDDA_RTC 1 8 V Domains 1V8_PHY HDMI PCIe LDO4 200 mA max OSC16MIN OSC16MOUT 1 8 V 3 3V Input Power TPS22965 Power Switch REGEN1 www ti com ...

Page 16: ... QSPI1 4 2 I2C Address Assignments The AM572x IDK EVM contains multiple I2C buses connected to a master port on the processor Each bus contains one or more I2C slave devices that must have unique addresses to prevent contention Table 1 and Table 2 list the addresses of the I2C slave devices attached to buses I2C1 and I2C2 respectively Table 1 I2C1 IND_I2C I2C Slave Device Address es TPS590377 PMIC...

Page 17: ...Kit EVM Version 4 Hardware version code for board in ASCII 1 3A revision 01 3A Serial Number 12 Serial number of the board This is a 12 character string that is WWYY4P47nnnn where WW 2 digit week of the year of production YY 2 digit year of production nnnn incrementing board number Configuration Option 32 Codes to show the configuration setup on this board Reserved Ethernet MAC Address 0 6 Etherne...

Page 18: ...y Each of the AM572x IDK EVM boards contains a 256Kb 32KB Serial EEPROM that contains board specific data This data allows the application software to automatically detect the type of board that it is running on and also to determine its version and potentially optional features Other hardware specific data can be stored on this memory device as well The part number of the memory device is CAT24C2...

Page 19: ... that provides rapid link status on the COL pin Therefore this pin is connected to the RXLINK input to the PRU ICSS ports for this purpose Test headers J4 and J7 are available to support real time code development The signals contained are available for simplified probing The reset for the transceivers is driven low coincident with the PORz reset to the AM5728 processor The reset for each transcei...

Page 20: ...add 150µF of additional capacitance to the VBUS pin The shunt for this header is shown on the schematic as M2 It is not installed on units when shipped as we expect this port to primarily be used in device mode 7 3 FTDI USB Port The FTDI bridge device provides both XDS100V2 JTAG emulation and UART Console over the USB Its USB connector is J19 and it is also a USB Micro AB connector but it only ope...

Page 21: ...pacitive touch overlay The video output driven for the LCD panel from the AM5728 processor is on VOUT1 A MIPI bridge device from Toshiba TC358778 is implemented to convert from the 24 bit RGB presented on the VOUT1 pins to serial MIPI RGB streams The LCD panel is shipped with FPC cables that plug into J16 for the MIPI video and into J17 for the touchscreen controller Both the MIPI bridge device an...

Page 22: ...15 2 I O Expansion Header J37 The input values are clocked into the SPI3 port of the AM5728 processor 11 3 Industrial Outputs LEDs I2C to 8 bit LED driver TPIC2810 is used to drive the eight Industrial output LEDs D5 to D12 The I2C interface is connected to the I2C1 port of the AM5728 processor along with the other devices on the IND_I2C bus The eight LED driver outputs are also driven to the I O ...

Page 23: ...E0 GPIO3_29 G2 PRU1ETH1_INTn Input INT PU VIN2A_FLD0 GPIO3_30 H7 PRU2ETH0_INTn Input INT PU VIN2A_HSYNC0 GPIO3_31 G1 PRU2ETH1_INTn Input INT PU VIN1A_D5 GPIO3_9 AH5 AM57XX_INDETHER_LED0_GRN Output EXT PD VIN2A_VSYNC0 GPIO4_0 G6 AM57XX_STATUSLED0_RED Output EXT PD VOUT1_FLD GPIO4_21 B11 eMMC_RSTn Output EXT PU MCASP1_ACLKR GPIO5_0 B14 GB_ETH0_INTn Input EXT PU MCASP1_FSR GPIO5_1 J14 GB_ETH1_INTn In...

Page 24: ...LE 9 No Connect AM57XX_PRU1ETH1_TXCLK 10 GPMC_OEN_REN 11 No Connect AM57XX_PRU1ETH1_TXD3 12 GPMC_WEN 13 PR2_EDC_LATCH0 AM57XX_PRU1ETH_MDCLK 14 GPMC_BEN0 15 PR2_EDC_LATCH1 PRU1ETH1_TXD1 16 GPMC_BEN1 17 PR2_EDC_SYNC0 PRU1ETH1_RXCLK 18 No Connect 19 PR2_EDC_SYNC1 PRU1ETH1_RXD3 20 No Connect 21 No Connect PRU1ETH1_RXD1 22 DGND 23 No Connect PRU1ETH1_RXERR 24 SPI2_SCLK 25 SYS_RESETn 26 SPI2_DIN 27 IND_...

Page 25: ... IDK Evaluation Module EVM Hardware Table 6 Expansion Connector J21 continued Pin Signal Name Secondary Signal Name 45 AM57XX_PR1_UART0_TXD 46 AM57XX_GPMC_AD14 47 AM57XX_PR1_UART0_RXD 48 AM57XX_GPMC_AD15 49 AM57XX_PR2_PROFI_TXEN 50 HDQ 51 AM57XX_GPMC_AD4 52 GPMC_WAIT0 53 AM57XX_GPMC_AD5 54 PR2_UART0_RXD 55 AM57XX_GPMC_AD6 56 PR2_UART0_TXD 57 AM57XX_GPMC_AD7 58 GPMC_CLK 59 DGND 60 DGND ...

Page 26: ...e EVM Hardware Table 7 I O Expansion Header Connector J37 Pin Signal Name 1 INDUS_INPUT0 2 V12_0D 3 INDUS_INPUT1 4 V12_0D 5 INDUS_INPUT2 6 V12_0D 7 INDUS_INPUT3 8 V12_0D 9 INDUS_INPUT4 10 V12_0D 11 INDUS_INPUT5 12 V12_0D 13 INDUS_INPUT6 14 V12_0D 15 INDUS_INPUT7 16 V12_0D 17 DGND 18 No Connect 19 DRAIN0 20 DRAIN1 21 DRAIN2 22 DRAIN3 23 DRAIN4 24 DRAIN5 25 DRAIN6 26 DRAIN7 27 V5_0D 28 V5_0D 29 DGND...

Page 27: ... Table 8 MicroSD Connector J15 Pin Pin Name Signal Name 1 DAT2 MMC_D2 2 DAT3 MMC_D3 3 CMD MMC_CMD 4 VDD V3_3D 5 CLOCK MMC_CLK 6 DGND VSS 7 DAT0 MMC_D0 8 DAT1 MMC_D1 9 GND DGND 10 CD MMC1_SDCD 11 GND3 DGND 12 GND4 DGND 13 GND5 DGND 14 GND6 DGND 15 GND7 DGND 16 GND8 DGND Table 9 Power Jack Connector J1 Pin Signal Name 1 VPWRIN_JCK 2 DGND 3 DGND Table 10 Power Terminal Block Connector J2 Pin Signal N...

Page 28: ...THER0_TDN 7 N C No connect 8 AC GND DGND 9 YEL LED Anode V3_3D 10 YEL LED Cathode RXLINK 11 GRN LED Anode V3_3D 12 GRN LED Cathode PRU1ETH0_LINKLED SHLD1 Shield AGNDFRAME_PRU1ETH0 SHLD2 Shield AGNDFRAME_PRU1ETH0 Table 12 PRU1ETH1 RJ45 Connector J5 Pin Pin Name Signal Name 1 RD PRU1ETHER1_RDP 2 RD PRU1ETHER1_RDN 3 RCT V3_3D 4 TCT V3_3D 5 TD PRU1ETHER1_TDP 6 TD PRU1ETHER1_TDN 7 N C No connect 8 AC G...

Page 29: ...THER0_TDN 7 N C No connect 8 AC GND DGND 9 YEL LED Anode V3_3D 10 YEL LED Cathode RXLINK 11 GRN LED Anode V3_3D 12 GRN LED Cathode PRU2ETH0_LINKLED SHLD1 Shield AGNDFRAME_PRU2ETH0 SHLD2 Shield AGNDFRAME_PRU2ETH0 Table 14 PRU2ETH1 RJ45 Connector J8 Pin Pin Name Signal Name 1 RD PRU2ETHER1_RDP 2 RD PRU2ETHER1_RDN 3 RCT V3_3D 4 TCT V3_3D 5 TD PRU2ETHER1_TDP 6 TD PRU2ETHER1_TDN 7 N C No connect 8 AC G...

Page 30: ...I1_RXDV PRU2ETH1_RXDV 3 RT2_MII1_EDIO_DATA0 AM57XX_VIN2A_HSYNC0 4 RT2_MII1_EDIO_DATA1 AM57XX_VIN2A_DE0 5 DGND DGND Table 17 Camera Connector J9 Pin Pin Name Signal Name 1 Power VMAIN 2 CAM1_VSYNC DGND 3 CAM1_DATA0 AM572X_VIN4B_DATA0 4 CAM1_HSYNC AM572X_VIN4B_HSYNC 5 CAM1_DATA1 AM572X_VIN4B_DATA1 6 CAM1_DATA6 AM572X_VIN4B_DATA6 7 CAM1_DATA2 AM572X_VIN4B_DATA2 8 CAM1_DATA7 AM572X_VIN4B_DATA7 9 CAM1_...

Page 31: ...ER0_D1N 9 MX0 ETHER0_D0P 10 MX0 ETHER0_D0N 11 RT GRN Anode PU to PHY0_LED_ACTn 12 RT YEL Anode DGND 13 LEFT GRN Anode DGND 14 LEFT YEL Anode PU to PHY0_LED_LINKn SHLD1 Shield AGND_GBETH0 SHLD2 Shield AGND_GBETH0 Table 19 GigE RJ45 Connector J12 Pin Pin Name Signal Name 1 CH GND DGND 2 VCC No connect 3 MX3 ETHER1_D3P 4 MX3 ETHER1_D3N 5 MX2 ETHER1_D2P 6 MX2 ETHER1_D2N 7 MX1 ETHER1_D1P 8 MX1 ETHER1_D...

Page 32: ...D DGND 11 MIPI_LN2_N LCD_MIPI2N 12 MIPI_LN2_P LCD_MIPI2P 13 GND DGND 14 MIPI_LN1_N LCD_MIPI1N 15 MIPI_LN1_P LCD_MIPI1P 16 GND DGND 17 MIPI_LN0_N LCD_MIPI0N 18 MIPI_LN0_P LCD_MIPI0P 19 GND DGND 20 MIPI_CLK_N LCD_CLKN 21 MIPI_CLK_P LCD_CLKP 22 GND DGND 23 LED_CATHODE VLED 24 LED_CATHODE VLED 25 LED_CATHODE VLED 26 LED_CATHODE VLED 27 LED_CATHODE VLED 28 LED_CATHODE VLED 29 LED Anode Supply VLED 30 L...

Page 33: ... HDMI_CLK 11 CLK_S DGND 12 CLK HDMI_CLK 13 CEC HDMICONN_CEC 14 NC No Connect 15 SCL HDMICONN_I2CSCL 16 SDA HDMICONN_I2CSDA 17 DDC CEC GND DGND 18 5V V5_0HDMICONN 19 HPLG HDMICONN_HPLG MTG1 Sheild DGND MTG2 Sheild DGND MTG3 Sheild DGND MTG4 Sheild DGND Table 23 MIPI 60 JTAG Connector J18 Pin Pin Name Signal Name 1 VREF_DBG PU to V3_3D 2 TMS JTAG_TMS 3 TCK JTAG_TCK 4 TDO JTAG_TDO 5 TDI JTAG_TDI 6 RE...

Page 34: ...MU6 28 TRD1 5 No Connect 29 TRD0 6 EMU7 30 TRD1 6 No Connect 31 TRD0 7 EMU8 32 TRD1 7 No Connect 33 TRD0 8 EMU9 34 TRD1 8 No Connect 35 TRD0 9 EMU10 36 TRD1 9 No Connect 37 TRD3 0 EMU11 38 TRD2 0 No Connect 39 TRD3 1 EMU12 40 TRD2 1 No Connect 41 TRD3 2 EMU13 42 TRD2 2 No Connect 43 TRD3 3 EMU14 44 TRD2 3 No Connect 45 TRD3 4 EMU15 46 TRD2 4 No Connect 47 TRD3 5 EMU16 48 TRD2 5 No Connect 49 TRD3 ...

Page 35: ...NDUSBJ S2 S2 GNDUSBJ S3 S3 GNDUSBJ S4 S4 GNDUSBJ Table 25 USB Port 1 USB3 0 Standard A type Connector J23 Pin Pin Name Signal Name 1 VBUS VUSB_VBUS1 2 DM USB1_CONN_DM 3 DP USB1_CONN_DP 4 GND DGND 5 STDA_SSRX USB1_3_0_STDA_SSRX 6 STDA_SSRX USB1_3_0_STDA_SSRX 7 GND_DRAIN DGND 8 STDA_SSTX USB1_3_0_STDA_SSTX 9 STDA_SSTX USB1_3_0_STDA_SSTX S1 S1 GNDUSB1 S2 S2 GNDUSB1 Table 26 USB Port 2 USB2 1 Micro AB...

Page 36: ... Kit IDK Evaluation Module EVM Hardware Table 27 CAN Header Connector J38 Pin Signal Name 1 VCAN1 2 CAN1_H 3 CAN1_L 4 GND_CAN1 5 No Connect Table 28 Profibus DB9F Connector J14 Pin Signal Name 1 No Connect 2 No Connect 3 PROFIBUS_A 4 No Connect 5 GND_PROFI 6 VPROFI 7 No Connect 8 PROFIBUS_B 9 No Connect Table 29 RS 485 Header Connector J39 Pin Signal Name 1 RS485_A 2 RS485_B 3 DGND ...

Page 37: ...PCIE_TRSTn B10 3 3V AUX V3_3AUX_PCIE B11 WAKE PCIE_WAKEn B12 CLKREQ No Connect B13 Ground DGND B14 HSOp 0 PCIECONN_PETp0 B15 HSOn 0 PCIECONN_PETn0 B16 Ground DGND B17 PRSNT2 DGND B18 Ground DGND A1 PRSNT1 PCIE_CRDPRESENT A2 12 V V12_0D A3 12 V V12_0D A4 Ground DGND A5 TCK PD to DGND A6 TDI PU to V3_3D A7 TDO TP20 A8 TMS PU to V3_3D A9 3 3V V3_3D A10 3 3V V3_3D A11 PERST PCIE_PERSTn A12 Ground DGND...

Page 38: ...o 1 8V under software control A 4 PCIe PERSTn line not in proper state at start up The board does not contain pull up or pull down resistors to allow this line to be pulled high at start up This can cause PCIe link training to fail Future software releases need to properly control the GPIO output pins to enable this correctly at start up A 5 EDIO connectors J4 and J7 should support real time debug...

Page 39: ... supplies Whenever the EVM power supplies are cycled the USB connection supporting the UART console and XDS100 emulation also drops Since this port takes time to enumerate after power is restored initial console output can be lost Also this results in power leakage from the USB VBUS back into the EVM when it is not powered Please refer to the AM571 IDK EVM design v1 3 or later for an example of th...

Page 40: ... 0pf load capacitance to allow crystals to operate at their target frequency Crystal load capacitors can be added to the oscillator circuit to allow the generated clock to output at the required nominal frequency so that this programming is not required The default capacitance within the CDCE913 is 10pF so the capacitors C172 C173 C193 and C194 should be 8pF Please refer to the CDCE L 913 Flexible...

Page 41: ...oduction IDK EVMs contain the TPS6590377 PMIC which powers off the DDR supply at the wrong time The default programming has been corrected in the TPS6590379 PMIC This part will be used for future builds A 21 PMIC OSC16MCAP pin mistakenly grounded The OSC16MCAP pin on the TPS659037x PMIC should be connected to a 2 2 μF capacitor to ground Unfortunately all versions of this IDK EVM have this pin con...

Page 42: ...64E May 2017 Revised September 2019 Submit Documentation Feedback Copyright 2017 2019 Texas Instruments Incorporated Revision History Revision History Changes from D Revision July 2019 to E Revision Page Update was made in Section 3 1 13 ...

Page 43: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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