GPIO Registers
25.4.1.20 GPIO_LEVELDETECT1 Register (offset = 144h) [reset = 0h]
GPIO_LEVELDETECT1 is shown in
and described in
The GPIO_LEVELDETECT1 register is used to enable/disable for each input lines the high-level (1)
detection to be used for the interrupt request generation. Enabling at the same time high-level detection
and low-level detection for one given pin makes a constant interrupt generator.
Figure 25-26. GPIO_LEVELDETECT1 Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LEVELDETECT1[n]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 25-25. GPIO_LEVELDETECT1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
LEVELDETECT1[n]
R/W
0h
High Level Interrupt Enable
0x0 = Disable the IRQ assertion on high-level detect.
0x1 = Enable the IRQ assertion on high-level detect.
4088
General-Purpose Input/Output
SPRUH73H – October 2011 – Revised April 2013
Copyright © 2011–2013, Texas Instruments Incorporated