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Functional Description

22.3.10.3.2 Receive Bit Stream Data Alignment

The McASP receiver supports serial formats of:

•

Slot or time slot size = 8, 12, 16, 20, 24, 28, 32 bits.

•

Word size

≤

Slot size.

•

Alignment when more bits/slot than bits/words, then:

–

Left aligned = word shifted first, remaining bits are pad.

–

Right aligned = pad bits are shifted first, word occupies the last bits in slot.

•

Order of bits shifted out:

–

MSB: most-significant bit of word is shifted out first, last bit is LSB.

–

LSB: least-significant bit of word is shifted out last, last bit is MSB.

Hardware support for these serial formats comes from the programmable options in the receive bitstream
format register (RFMT):

•

RRVRS: bit reverse (1) or no bit reverse (0).

•

RROT: rotate right by 0, 4, 8, 12, 16, 20, 24, or 28 bits.

•

RSSZ: receive slot size of 8, 12, 16, 20, 24, 28, or 32 bits.

RSSZ should always be programmed to match the slot size of the serial stream. The word size is not
directly programmed into the McASP, but rather is used to determine the rotation needed in the RROT
field.

and

show the RRVRS and RROT fields for each serial format and for both

integer and Q31 fractional internal representations.

This discussion assumes that all slot size and word size options are multiples of 4; since the receive rotate
right unit only supports rotation by multiples of 4. However, the bit mask/pad unit does allow for any
number of significant digits. For example, a Q31 number may have 19 significant digits (word) and be
transmitted in a 24-bit slot; this would be formatted as a word size of 20 bits and a slot size of 24 bits.
However, it is possible to set the bit mask unit to only pass the 19 most-significant digits (program the
mask value to FFFF E000h). The digits that are not significant can be set to a selected pad value, which
can be any one of the significant digits, a fixed value of 0, or a fixed value of 1.

The receive bit mask/pad unit operates on data as the final step of the receive format unit (see

), and the data is aligned in the same representation as it is read from the receiver by the processor

(typically Q31 or integer).

Table 22-9. Receive Bitstream Data Alignment

RFMT Bit

Bit Stream

Internal Numeric

Figure 22-30

Bit Stream Order

Alignment

Representation

RROT

(1)

RRVRS

(a)

(2)

MSB first

Left aligned

Q31 fraction

SLOT

1

(b)

MSB first

Right aligned

Q31 fraction

WORD

1

(c)

LSB first

Left aligned

Q31 fraction

(32 - (SLOT - WORD)) % 32

0

(d)

LSB first

Right aligned

Q31 fraction

0

0

(e)

(2)

MSB first

Left aligned

Integer

SLOT - WORD

1

(f)

MSB first

Right aligned

Integer

0

1

(g)

LSB first

Left aligned

Integer

32 - SLOT

0

(h)

LSB first

Right aligned

Integer

32 - WORD

0

(1)

WORD = Word size rounded up to the nearest multiple of 4; SLOT = slot size; % = modulo operator

(2)

To transmit in I2S format, select MSB first, left aligned, and also select RDATDLY = 01 (1 bit delay)

3807

SPRUH73H – October 2011 – Revised April 2013

Multichannel Audio Serial Port (McASP)

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Copyright © 2011–2013, Texas Instruments Incorporated

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Summary of Contents for AM335 Series

Page 1: ...AM335x ARM Cortex A8 Microprocessors MPUs Technical Reference Manual Literature Number SPRUH73H October 2011 Revised April 2013 ...

Page 2: ...n During EMAC Boot 154 1 2 12 Added EFUSE_SMA Register for Help Identifying Different Device Variants 154 2 Memory Map 155 2 1 ARM Cortex A8 Memory Map 155 3 ARM MPU Subsystem 164 3 1 ARM Cortex A8 MPU Subsystem 165 3 1 1 Features 166 3 1 2 MPU Subsystem Integration 166 3 1 3 MPU Subsystem Clock and Reset Distribution 167 3 1 4 ARM Subchip 170 3 1 5 Interrupt Controller 171 3 1 6 Power Management ...

Page 3: ...366 7 2 OCMC RAM 398 7 2 1 Introduction 398 7 2 2 Integration 399 7 3 EMIF 400 7 3 1 Introduction 400 7 3 2 Integration 402 7 3 3 Functional Description 404 7 3 4 Use Cases 422 7 3 5 EMIF4D Registers 422 7 3 6 DDR2 3 mDDR PHY Registers 467 7 4 ELM 476 7 4 1 Introduction 476 7 4 2 Integration 477 7 4 3 Functional Description 478 7 4 4 Basic Programming Model 481 7 4 5 ELM Registers 487 8 Power Rese...

Page 4: ...set 0h 778 9 3 17 init_priority_0 Register offset 608h reset 0h 779 9 3 18 init_priority_1 Register offset 60Ch reset 0h 780 9 3 19 mmu_cfg Register offset 610h reset 0h 781 9 3 20 tptc_cfg Register offset 614h reset 0h 782 9 3 21 usb_ctrl0 Register offset 620h reset 0h 783 9 3 22 usb_sts0 Register offset 624h reset 0h 785 9 3 23 usb_ctrl1 Register offset 628h reset 0h 786 9 3 24 usb_sts1 Register...

Page 5: ... 9 3 67 tpcc_evt_mux_44_47 Register offset FBCh reset 0h 831 9 3 68 tpcc_evt_mux_48_51 Register offset FC0h reset 0h 832 9 3 69 tpcc_evt_mux_52_55 Register offset FC4h reset 0h 833 9 3 70 tpcc_evt_mux_56_59 Register offset FC8h reset 0h 834 9 3 71 tpcc_evt_mux_60_63 Register offset FCCh reset 0h 835 9 3 72 timer_evt_capt Register offset FD0h reset 0h 836 9 3 73 ecap_evt_capt Register offset FD4h r...

Page 6: ...17 11 3 14 EDMA3 Prioritization 917 11 3 15 EDMA3 Operating Frequency Clock Control 918 11 3 16 Reset Considerations 918 11 3 17 Power Management 918 11 3 18 Emulation Considerations 918 11 3 19 EDMA Transfer Examples 920 11 3 20 EDMA Events 936 11 4 EDMA3 Registers 939 11 4 1 EDMA3 Channel Controller Registers 939 11 4 2 EDMA3 Transfer Controller Registers 993 11 5 Appendix A 1018 11 5 1 Debug Ch...

Page 7: ...ister offset 0h reset 0h 1130 13 5 2 CTRL Register offset 4h reset 0h 1131 13 5 3 LIDD_CTRL Register offset Ch reset 0h 1132 13 5 4 LIDD_CS0_CONF Register offset 10h reset 0h 1133 13 5 5 LIDD_CS0_ADDR Register offset 14h reset 0h 1134 13 5 6 LIDD_CS0_DATA Register offset 18h reset 0h 1135 13 5 7 LIDD_CS1_CONF Register offset 1Ch reset 0h 1136 13 5 8 LIDD_CS1_ADDR Register offset 20h reset 0h 1137 ...

Page 8: ...1225 14 3 5 RMII Interface 1225 14 3 6 RGMII Interface 1226 14 3 7 Common Platform Time Sync CPTS 1228 14 3 8 MDIO 1233 14 4 Software Operation 1235 14 4 1 Transmit Operation 1235 14 4 2 Receive Operation 1237 14 4 3 Initializing the MDIO Module 1238 14 4 4 Writing Data to a PHY Register 1238 14 4 5 Reading Data from a PHY Register 1239 14 4 6 Initialization and Configuration of CPSW 1239 14 5 Eth...

Page 9: ...Method 1698 16 3 4 Clock PLL and PHY Initialization 1698 16 3 5 Indexed and Non Indexed Register Spaces 1698 16 3 6 Dynamic FIFO Sizing 1698 16 3 7 USB Controller Host and Peripheral Modes Operation 1699 16 3 8 Protocol Description s 1701 16 3 9 Communications Port Programming Interface CPPI 4 1 DMA 1734 16 3 10 USB 2 0 Test Modes 1758 16 4 Supported Use Cases 1759 16 5 USB Registers 1760 16 5 1 U...

Page 10: ...ation 3384 18 4 2 MMC SD SDIO Controller Initialization Flow 3384 18 4 3 Operational Modes Configuration 3387 18 5 Multimedia Card Registers 3389 18 5 1 MULTIMEDIA_CARD Registers 3389 19 Universal Asynchronous Receiver Transmitter UART 3446 19 1 Introduction 3447 19 1 1 UART Mode Features 3447 19 1 2 IrDA Mode Features 3447 19 1 3 CIR Mode Features 3447 19 1 4 Unsupported UART Features 3447 19 2 I...

Page 11: ...gration 3700 21 2 1 I2C Connectivity Attributes 3700 21 2 2 I2C Clock and Reset Management 3701 21 2 3 I2C Pin List 3701 21 3 Functional Description 3702 21 3 1 Functional Block Diagram 3702 21 3 2 I2C Master Slave Contoller Signals 3702 21 3 3 I2C Reset 3703 21 3 4 Data Validity 3703 21 3 5 START STOP Conditions 3705 21 3 6 I2C Operation 3705 21 3 7 Arbitration 3707 21 3 8 I2C Clock Generation an...

Page 12: ...CFG Registers 3826 22 4 2 McASP Data Port Registers 3880 23 Controller Area Network CAN 3881 23 1 Introduction 3882 23 1 1 DCAN Features 3882 23 1 2 Unsupported DCAN Features 3882 23 2 Integration 3883 23 2 1 DCAN Connectivity Attributes 3883 23 2 2 DCAN Clock and Reset Management 3884 23 2 3 DCAN Pin List 3884 23 3 Functional Description 3885 23 3 1 CAN Core 3885 23 3 2 Message Handler 3886 23 3 ...

Page 13: ...5 MSGVAL12 Register offset C4h reset 0h 3951 23 4 26 MSGVAL34 Register offset C8h reset 0h 3952 23 4 27 MSGVAL56 Register offset CCh reset 0h 3953 23 4 28 MSGVAL78 Register offset D0h reset 0h 3954 23 4 29 INTMUX12 Register offset D8h reset 0h 3955 23 4 30 INTMUX34 Register offset DCh reset 0h 3956 23 4 31 INTMUX56 Register offset E0h reset 0h 3957 23 4 32 INTMUX78 Register offset E4h reset 0h 395...

Page 14: ...0 24 3 10 Access to Data Registers 4031 24 3 11 Programming Aid 4031 24 3 12 Interrupt and DMA Events 4032 24 4 McSPI Registers 4032 24 4 1 SPI Registers 4032 25 General Purpose Input Output 4056 25 1 Introduction 4057 25 1 1 Purpose of the Peripheral 4057 25 1 2 GPIO Features 4057 25 1 3 Unsupported GPIO Features 4057 25 2 Integration 4058 25 2 1 GPIO Connectivity Attributes 4058 25 2 2 GPIO Cloc...

Page 15: ...ion 4150 26 1 11 Wakeup 4152 26 1 12 Tracing 4153 27 Debug Subsystem 4156 27 1 Functional Description 4157 27 1 1 Debug Suspend Support for Peripherals 4157 A Revision History 4159 15 SPRUH73H October 2011 Revised April 2013 Contents Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 16: ...6 6 15 INTC_ITR0 Register 217 6 16 INTC_MIR0 Register 218 6 17 INTC_MIR_CLEAR0 Register 219 6 18 INTC_MIR_SET0 Register 220 6 19 INTC_ISR_SET0 Register 221 6 20 INTC_ISR_CLEAR0 Register 222 6 21 INTC_PENDING_IRQ0 Register 223 6 22 INTC_PENDING_FIQ0 Register 224 6 23 INTC_ITR1 Register 225 6 24 INTC_MIR1 Register 226 6 25 INTC_MIR_CLEAR1 Register 227 6 26 INTC_MIR_SET1 Register 228 6 27 INTC_ISR_SE...

Page 17: ...6 Asynchronous Single Write on an AAD Multiplexed Device 286 7 17 Synchronous Single Read GPMCFCLKDIVIDER 0 288 7 18 Synchronous Single Read GPMCFCLKDIVIDER 1 289 7 19 Synchronous Multiple Burst Read GPMCFCLKDIVIDER 0 291 7 20 Synchronous Multiple Burst Read GPMCFCLKDIVIDER 1 292 7 21 Synchronous Single Write on an Address Data Multiplexed Device 293 7 22 Synchronous Multiple Write Burst Write in ...

Page 18: ...E 372 7 59 GPMC_CONFIG 373 7 60 GPMC_STATUS 374 7 61 GPMC_CONFIG1_i 375 7 62 GPMC_CONFIG2_i 377 7 63 GPMC_CONFIG3_i 378 7 64 GPMC_CONFIG4_i 380 7 65 GPMC_CONFIG5_i 382 7 66 GPMC_CONFIG6_i 383 7 67 GPMC_CONFIG7_i 384 7 68 GPMC_NAND_COMMAND_i 385 7 69 GPMC_NAND_ADDRESS_i 385 7 70 GPMC_NAND_DATA_i 385 7 71 GPMC_PREFETCH_CONFIG1 386 7 72 GPMC_PREFETCH_CONFIG2 388 7 73 GPMC_PREFETCH_CONTROL 388 7 74 GP...

Page 19: ...YS Register 453 7 119 ZQ_CONFIG Register 454 7 120 Read Write Leveling Ramp Window Register 455 7 121 Read Write Leveling Ramp Control Register 456 7 122 Read Write Leveling Control Register 457 7 123 DDR_PHY_CTRL_1 Register 458 7 124 DDR_PHY_CTRL_1_SHDW Register 460 7 125 Priority to Class of Service Mapping Register 462 7 126 Connection ID to Class of Service 1 Mapping Register 463 7 127 Connect...

Page 20: ...SYNDROME_FRAGMENT_2_i Register 495 7 151 ELM_SYNDROME_FRAGMENT_3_i Register 496 7 152 ELM_SYNDROME_FRAGMENT_4_i Register 496 7 153 ELM_SYNDROME_FRAGMENT_5_i Register 496 7 154 ELM_SYNDROME_FRAGMENT_6_i Register 497 7 155 ELM_LOCATION_STATUS_i Register 497 7 156 ELM_ERROR_LOCATION_0 15_i Registers 498 8 1 Functional and Interface Clocks 500 8 2 Generic Clock Domain 505 8 3 Clock Domain State Transi...

Page 21: ... 575 8 48 CM_PER_UART4_CLKCTRL Register 576 8 49 CM_PER_TIMER7_CLKCTRL Register 577 8 50 CM_PER_TIMER2_CLKCTRL Register 578 8 51 CM_PER_TIMER3_CLKCTRL Register 579 8 52 CM_PER_TIMER4_CLKCTRL Register 580 8 53 CM_PER_GPIO1_CLKCTRL Register 581 8 54 CM_PER_GPIO2_CLKCTRL Register 582 8 55 CM_PER_GPIO3_CLKCTRL Register 583 8 56 CM_PER_TPCC_CLKCTRL Register 584 8 57 CM_PER_DCAN0_CLKCTRL Register 585 8 ...

Page 22: ...er 628 8 97 CM_IDLEST_DPLL_DDR Register 629 8 98 CM_SSC_DELTAMSTEP_DPLL_DDR Register 630 8 99 CM_SSC_MODFREQDIV_DPLL_DDR Register 631 8 100 CM_CLKSEL_DPLL_DDR Register 632 8 101 CM_AUTOIDLE_DPLL_DISP Register 633 8 102 CM_IDLEST_DPLL_DISP Register 634 8 103 CM_SSC_DELTAMSTEP_DPLL_DISP Register 635 8 104 CM_SSC_MODFREQDIV_DPLL_DISP Register 636 8 105 CM_CLKSEL_DPLL_DISP Register 637 8 106 CM_AUTOID...

Page 23: ...1 8 145 CM_CPTS_RFT_CLKSEL Register 682 8 146 CLKSEL_TIMER1MS_CLK Register 683 8 147 CLKSEL_GFX_FCLK Register 684 8 148 CLKSEL_PRU_ICSS_OCP_CLK Register 685 8 149 CLKSEL_LCDC_PIXEL_CLK Register 686 8 150 CLKSEL_WDT1_CLK Register 687 8 151 CLKSEL_GPIO0_DBCLK Register 688 8 152 CM_MPU_CLKSTCTRL Register 689 8 153 CM_MPU_MPU_CLKCTRL Register 690 8 154 CM_CLKOUT_CTRL Register 692 8 155 CM_RTC_RTC_CLKC...

Page 24: ... PM_CEFUSE_PWRSTCTRL Register 744 8 194 PM_CEFUSE_PWRSTST Register 745 9 1 Event Crossbar 749 9 2 USB Charger Detection 751 9 3 Timer Events 755 9 4 control_revision Register 762 9 5 control_hwinfo Register 763 9 6 control_sysconfig Register 764 9 7 control_status Register 765 9 8 control_emif_sdram_config Register 766 9 9 core_sldo_ctrl Register 768 9 10 mpu_sldo_ctrl Register 769 9 11 clk32kdivr...

Page 25: ...e_opp_100 Register 811 9 51 bb_scale Register 812 9 52 usb_vid_pid Register 813 9 53 efuse_sma Register 814 9 54 conf_ module _ pin Register 815 9 55 cqdetect_status Register 816 9 56 ddr_io_ctrl Register 817 9 57 vtp_ctrl Register 818 9 58 vref_ctrl Register 819 9 59 tpcc_evt_mux_0_3 Register 820 9 60 tpcc_evt_mux_4_7 Register 821 9 61 tpcc_evt_mux_8_11 Register 822 9 62 tpcc_evt_mux_12_15 Regist...

Page 26: ...am 877 11 5 EDMA3 Transfer Controller EDMA3TC Block Diagram 878 11 6 Definition of ACNT BCNT and CCNT 879 11 7 A Synchronized Transfers ACNT n BCNT 4 CCNT 3 880 11 8 AB Synchronized Transfers ACNT n BCNT 4 CCNT 3 881 11 9 PaRAM Set 883 11 10 Channel Options Parameter OPT 885 11 11 Linked Transfer 892 11 12 Link to Self Transfer 893 11 13 DMA Channel and QDMA Channel to PaRAM Mapping 898 11 14 QDMA...

Page 27: ...e Number Register QDMAQNUM 949 11 49 Queue Priority Register QUEPRI 950 11 50 Event Missed Register EMR 951 11 51 Event Missed Register High EMRH 951 11 52 Event Missed Clear Register EMCR 952 11 53 Event Missed Clear Register High EMCRH 952 11 54 QDMA Event Missed Register QEMR 953 11 55 QDMA Event Missed Clear Register QEMCR 954 11 56 EDMA3CC Error Register CCERR 954 11 57 EDMA3CC Error Clear Re...

Page 28: ... QEECR 989 11 102 QDMA Event Enable Set Register QEESR 990 11 103 QDMA Secondary Event Register QSER 991 11 104 QDMA Secondary Event Clear Register QSECR 992 11 105 Peripheral ID Register PID 994 11 106 EDMA3TC Configuration Register TCCFG 995 11 107 EDMA3TC System Configuration Register SYSCONFIG 996 11 108 EDMA3TC Channel Status Register TCSTAT 997 11 109 Error Register ERRSTAT 999 11 110 Error ...

Page 29: ... 12 DMAENABLE_SET Register 1046 12 13 DMAENABLE_CLR Register 1047 12 14 CTRL Register 1048 12 15 ADCSTAT Register 1049 12 16 ADCRANGE Register 1050 12 17 ADC_CLKDIV Register 1051 12 18 ADC_MISC Register 1052 12 19 STEPENABLE Register 1053 12 20 IDLECONFIG Register 1054 12 21 TS_CHARGE_STEPCONFIG Register 1055 12 22 TS_CHARGE_DELAY Register 1056 12 23 STEPCONFIG1 Register 1057 12 24 STEPDELAY1 Regi...

Page 30: ... Structure 1110 13 6 16 Entry Palette Buffer Format 1 2 4 12 16 BPP 1111 13 7 256 Entry Palette Buffer Format 8 BPP 1112 13 8 16 BPP Data Memory Organization TFT Mode Only Little Endian 1112 13 9 12 BPP Data Memory Organization Little Endian 1113 13 10 8 BPP Data Memory Organization 1113 13 11 4 BPP Data Memory Organization 1113 13 12 2 BPP Data Memory Organization 1114 13 13 1 BPP Data Memory Org...

Page 31: ...s 1174 14 6 CPSW_3G Block Diagram 1182 14 7 Tx Buffer Descriptor Format 1187 14 8 Rx Buffer Descriptor Format 1190 14 9 VLAN Header Encapsulation Word 1194 14 10 CPTS Block Diagram 1228 14 11 Event FIFO Misalignment Condition 1230 14 12 HW1 4_TSP_PUSH Connection 1231 14 13 Port TX State RAM Entry 1236 14 14 Port RX DMA State 1237 14 15 IDVER Register 1241 14 16 CONTROL Register 1242 14 17 PRESCALE...

Page 32: ...1287 14 57 RX_INTMASK_CLEAR Register 1288 14 58 DMA_INTSTAT_RAW Register 1289 14 59 DMA_INTSTAT_MASKED Register 1290 14 60 DMA_INTMASK_SET Register 1291 14 61 DMA_INTMASK_CLEAR Register 1292 14 62 RX0_PENDTHRESH Register 1293 14 63 RX1_PENDTHRESH Register 1294 14 64 RX2_PENDTHRESH Register 1295 14 65 RX3_PENDTHRESH Register 1296 14 66 RX4_PENDTHRESH Register 1297 14 67 RX5_PENDTHRESH Register 1298...

Page 33: ...egister 1340 14 106 TX1_CP Register 1341 14 107 TX2_CP Register 1342 14 108 TX3_CP Register 1343 14 109 TX4_CP Register 1344 14 110 TX5_CP Register 1345 14 111 TX6_CP Register 1346 14 112 TX7_CP Register 1347 14 113 RX0_CP Register 1348 14 114 RX1_CP Register 1349 14 115 RX2_CP Register 1350 14 116 RX3_CP Register 1351 14 117 RX4_CP Register 1352 14 118 RX5_CP Register 1353 14 119 RX6_CP Register ...

Page 34: ...gister 1390 14 154 P1_RX_DSCP_PRI_MAP7 Register 1391 14 155 P2_CONTROL Register 1392 14 156 P2_MAX_BLKS Register 1394 14 157 P2_BLK_CNT Register 1395 14 158 P2_TX_IN_CTL Register 1396 14 159 P2_PORT_VLAN Register 1397 14 160 P2_TX_PRI_MAP Register 1398 14 161 P2_TS_SEQ_MTYPE Register 1399 14 162 P2_SA_LO Register 1400 14 163 P2_SA_HI Register 1401 14 164 P2_SEND_PERCENT Register 1402 14 165 P2_RX_...

Page 35: ... C0_MISC_EN Register 1446 14 205 C1_RX_THRESH_EN Register 1447 14 206 C1_RX_EN Register 1448 14 207 C1_TX_EN Register 1449 14 208 C1_MISC_EN Register 1450 14 209 C2_RX_THRESH_EN Register 1451 14 210 C2_RX_EN Register 1452 14 211 C2_TX_EN Register 1453 14 212 C2_MISC_EN Register 1454 14 213 C0_RX_THRESH_STAT Register 1455 14 214 C0_RX_STAT Register 1456 14 215 C0_TX_STAT Register 1457 14 216 C0_MIS...

Page 36: ...Submodule Block Diagram 1501 15 10 Time Base Submodule Signals and Registers 1503 15 11 Time Base Frequency and Period 1505 15 12 Time Base Counter Synchronization Scheme 1 1506 15 13 Time Base Up Count Mode Waveforms 1508 15 14 Time Base Down Count Mode Waveforms 1509 15 15 Time Base Up Down Count Waveforms TBCTL PHSDIR 0 Count Down on Synchronization Event 1509 15 16 Time Base Up Down Count Wave...

Page 37: ...52 15 51 Required PWM Waveform for a Requested Duty 40 5 1554 15 52 Low Duty Cycle Range Limitation Example When PWM Frequency 1 MHz 1556 15 53 High Duty Cycle Range Limitation Example when PWM Frequency 1 MHz 1556 15 54 Simplified ePWM Module 1557 15 55 EPWM1 Configured as a Typical Master EPWM2 Configured as a Slave 1558 15 56 Control of Four Buck Stages Here FPWM1 FPWM2 FPWM3 FPWM4 1559 15 57 B...

Page 38: ...re A High Resolution Register CMPAHR 1605 15 99 HRPWM Control Register HRCTL 1606 15 100 Multiple eCAP Modules 1608 15 101 Capture and APWM Modes of Operation 1609 15 102 Capture Function Diagram 1610 15 103 Event Prescale Control 1611 15 104 Prescale Function Waveforms 1611 15 105 Continuous One shot Block Diagram 1612 15 106 Counter and Synchronization Block Diagram 1613 15 107 Interrupts in eCA...

Page 39: ...nter Register QPOSCNT 1673 15 150 eQEP Position Counter Initialization Register QPOSINIT 1673 15 151 eQEP Maximum Position Count Register QPOSMAX 1673 15 152 eQEP Position Compare Register QPOSCMP 1674 15 153 eQEP Index Position Latch Register QPOSILAT 1674 15 154 eQEP Strobe Position Latch Register QPOSSLAT 1674 15 155 eQEP Position Counter Latch Register QPOSLAT 1675 15 156 eQEP Unit Timer Regis...

Page 40: ...nfiguration 1753 16 19 Transmit USB Data Flow Example Initialization 1754 16 20 Receive Buffer Descriptors and Queue Status Configuration 1756 16 21 Receive USB Data Flow Example Initialization 1757 16 22 REVREG Register 1762 16 23 SYSCONFIG Register 1763 16 24 IRQSTATRAW Register 1764 16 25 IRQSTAT Register 1765 16 26 IRQENABLER Register 1766 16 27 IRQCLEARR Register 1767 16 28 IRQDMATHOLDTX00 Re...

Page 41: ...B0IRQENABLESET1 Register 1820 16 74 USB0IRQENABLECLR0 Register 1822 16 75 USB0IRQENABLECLR1 Register 1824 16 76 USB0TXMODE Register 1826 16 77 USB0RXMODE Register 1828 16 78 USB0GENRNDISEP1 Register 1832 16 79 USB0GENRNDISEP2 Register 1833 16 80 USB0GENRNDISEP3 Register 1834 16 81 USB0GENRNDISEP4 Register 1835 16 82 USB0GENRNDISEP5 Register 1836 16 83 USB0GENRNDISEP6 Register 1837 16 84 USB0GENRND...

Page 42: ...r 1888 16 122 USB1GENRNDISEP10 Register 1889 16 123 USB1GENRNDISEP11 Register 1890 16 124 USB1GENRNDISEP12 Register 1891 16 125 USB1GENRNDISEP13 Register 1892 16 126 USB1GENRNDISEP14 Register 1893 16 127 USB1GENRNDISEP15 Register 1894 16 128 USB1AUTOREQ Register 1895 16 129 USB1SRPFIXTIME Register 1897 16 130 USB1TDOWN Register 1898 16 131 USB1UTMI Register 1899 16 132 USB1UTMILB Register 1900 16 ...

Page 43: ...ter 1951 16 171 TXGCR4 Register 1952 16 172 RXGCR4 Register 1953 16 173 RXHPCRA4 Register 1955 16 174 RXHPCRB4 Register 1956 16 175 TXGCR5 Register 1957 16 176 RXGCR5 Register 1958 16 177 RXHPCRA5 Register 1960 16 178 RXHPCRB5 Register 1961 16 179 TXGCR6 Register 1962 16 180 RXGCR6 Register 1963 16 181 RXHPCRA6 Register 1965 16 182 RXHPCRB6 Register 1966 16 183 TXGCR7 Register 1967 16 184 RXGCR7 R...

Page 44: ...XGCR16 Register 2013 16 221 RXHPCRA16 Register 2015 16 222 RXHPCRB16 Register 2016 16 223 TXGCR17 Register 2017 16 224 RXGCR17 Register 2018 16 225 RXHPCRA17 Register 2020 16 226 RXHPCRB17 Register 2021 16 227 TXGCR18 Register 2022 16 228 RXGCR18 Register 2023 16 229 RXHPCRA18 Register 2025 16 230 RXHPCRB18 Register 2026 16 231 TXGCR19 Register 2027 16 232 RXGCR19 Register 2028 16 233 RXHPCRA19 Re...

Page 45: ...269 RXHPCRA28 Register 2075 16 270 RXHPCRB28 Register 2076 16 271 TXGCR29 Register 2077 16 272 RXGCR29 Register 2078 16 273 RXHPCRA29 Register 2080 16 274 RXHPCRB29 Register 2081 16 275 DMA_SCHED_CTRL Register 2082 16 276 WORD0 to WORD63 Register 2083 16 277 QMGRREVID Register 2109 16 278 QMGRRST Register 2110 16 279 FDBSC0 Register 2111 16 280 FDBSC1 Register 2112 16 281 FDBSC2 Register 2113 16 2...

Page 46: ... QUEUE_1_D Register 2150 16 319 QUEUE_2_A Register 2151 16 320 QUEUE_2_B Register 2152 16 321 QUEUE_2_C Register 2153 16 322 QUEUE_2_D Register 2154 16 323 QUEUE_3_A Register 2155 16 324 QUEUE_3_B Register 2156 16 325 QUEUE_3_C Register 2157 16 326 QUEUE_3_D Register 2158 16 327 QUEUE_4_A Register 2159 16 328 QUEUE_4_B Register 2160 16 329 QUEUE_4_C Register 2161 16 330 QUEUE_4_D Register 2162 16 ...

Page 47: ..._A Register 2199 16 368 QUEUE_14_B Register 2200 16 369 QUEUE_14_C Register 2201 16 370 QUEUE_14_D Register 2202 16 371 QUEUE_15_A Register 2203 16 372 QUEUE_15_B Register 2204 16 373 QUEUE_15_C Register 2205 16 374 QUEUE_15_D Register 2206 16 375 QUEUE_16_A Register 2207 16 376 QUEUE_16_B Register 2208 16 377 QUEUE_16_C Register 2209 16 378 QUEUE_16_D Register 2210 16 379 QUEUE_17_A Register 2211...

Page 48: ..._26_B Register 2248 16 417 QUEUE_26_C Register 2249 16 418 QUEUE_26_D Register 2250 16 419 QUEUE_27_A Register 2251 16 420 QUEUE_27_B Register 2252 16 421 QUEUE_27_C Register 2253 16 422 QUEUE_27_D Register 2254 16 423 QUEUE_28_A Register 2255 16 424 QUEUE_28_B Register 2256 16 425 QUEUE_28_C Register 2257 16 426 QUEUE_28_D Register 2258 16 427 QUEUE_29_A Register 2259 16 428 QUEUE_29_B Register 2...

Page 49: ..._38_C Register 2297 16 466 QUEUE_38_D Register 2298 16 467 QUEUE_39_A Register 2299 16 468 QUEUE_39_B Register 2300 16 469 QUEUE_39_C Register 2301 16 470 QUEUE_39_D Register 2302 16 471 QUEUE_40_A Register 2303 16 472 QUEUE_40_B Register 2304 16 473 QUEUE_40_C Register 2305 16 474 QUEUE_40_D Register 2306 16 475 QUEUE_41_A Register 2307 16 476 QUEUE_41_B Register 2308 16 477 QUEUE_41_C Register 2...

Page 50: ..._50_D Register 2346 16 515 QUEUE_51_A Register 2347 16 516 QUEUE_51_B Register 2348 16 517 QUEUE_51_C Register 2349 16 518 QUEUE_51_D Register 2350 16 519 QUEUE_52_A Register 2351 16 520 QUEUE_52_B Register 2352 16 521 QUEUE_52_C Register 2353 16 522 QUEUE_52_D Register 2354 16 523 QUEUE_53_A Register 2355 16 524 QUEUE_53_B Register 2356 16 525 QUEUE_53_C Register 2357 16 526 QUEUE_53_D Register 2...

Page 51: ..._63_A Register 2395 16 564 QUEUE_63_B Register 2396 16 565 QUEUE_63_C Register 2397 16 566 QUEUE_63_D Register 2398 16 567 QUEUE_64_A Register 2399 16 568 QUEUE_64_B Register 2400 16 569 QUEUE_64_C Register 2401 16 570 QUEUE_64_D Register 2402 16 571 QUEUE_65_A Register 2403 16 572 QUEUE_65_B Register 2404 16 573 QUEUE_65_C Register 2405 16 574 QUEUE_65_D Register 2406 16 575 QUEUE_66_A Register 2...

Page 52: ..._75_B Register 2444 16 613 QUEUE_75_C Register 2445 16 614 QUEUE_75_D Register 2446 16 615 QUEUE_76_A Register 2447 16 616 QUEUE_76_B Register 2448 16 617 QUEUE_76_C Register 2449 16 618 QUEUE_76_D Register 2450 16 619 QUEUE_77_A Register 2451 16 620 QUEUE_77_B Register 2452 16 621 QUEUE_77_C Register 2453 16 622 QUEUE_77_D Register 2454 16 623 QUEUE_78_A Register 2455 16 624 QUEUE_78_B Register 2...

Page 53: ..._87_C Register 2493 16 662 QUEUE_87_D Register 2494 16 663 QUEUE_88_A Register 2495 16 664 QUEUE_88_B Register 2496 16 665 QUEUE_88_C Register 2497 16 666 QUEUE_88_D Register 2498 16 667 QUEUE_89_A Register 2499 16 668 QUEUE_89_B Register 2500 16 669 QUEUE_89_C Register 2501 16 670 QUEUE_89_D Register 2502 16 671 QUEUE_90_A Register 2503 16 672 QUEUE_90_B Register 2504 16 673 QUEUE_90_C Register 2...

Page 54: ...er 2542 16 711 QUEUE_100_A Register 2543 16 712 QUEUE_100_B Register 2544 16 713 QUEUE_100_C Register 2545 16 714 QUEUE_100_D Register 2546 16 715 QUEUE_101_A Register 2547 16 716 QUEUE_101_B Register 2548 16 717 QUEUE_101_C Register 2549 16 718 QUEUE_101_D Register 2550 16 719 QUEUE_102_A Register 2551 16 720 QUEUE_102_B Register 2552 16 721 QUEUE_102_C Register 2553 16 722 QUEUE_102_D Register 2...

Page 55: ...112_A Register 2591 16 760 QUEUE_112_B Register 2592 16 761 QUEUE_112_C Register 2593 16 762 QUEUE_112_D Register 2594 16 763 QUEUE_113_A Register 2595 16 764 QUEUE_113_B Register 2596 16 765 QUEUE_113_C Register 2597 16 766 QUEUE_113_D Register 2598 16 767 QUEUE_114_A Register 2599 16 768 QUEUE_114_B Register 2600 16 769 QUEUE_114_C Register 2601 16 770 QUEUE_114_D Register 2602 16 771 QUEUE_115_...

Page 56: ...124_B Register 2640 16 809 QUEUE_124_C Register 2641 16 810 QUEUE_124_D Register 2642 16 811 QUEUE_125_A Register 2643 16 812 QUEUE_125_B Register 2644 16 813 QUEUE_125_C Register 2645 16 814 QUEUE_125_D Register 2646 16 815 QUEUE_126_A Register 2647 16 816 QUEUE_126_B Register 2648 16 817 QUEUE_126_C Register 2649 16 818 QUEUE_126_D Register 2650 16 819 QUEUE_127_A Register 2651 16 820 QUEUE_127_...

Page 57: ...136_C Register 2689 16 858 QUEUE_136_D Register 2690 16 859 QUEUE_137_A Register 2691 16 860 QUEUE_137_B Register 2692 16 861 QUEUE_137_C Register 2693 16 862 QUEUE_137_D Register 2694 16 863 QUEUE_138_A Register 2695 16 864 QUEUE_138_B Register 2696 16 865 QUEUE_138_C Register 2697 16 866 QUEUE_138_D Register 2698 16 867 QUEUE_139_A Register 2699 16 868 QUEUE_139_B Register 2700 16 869 QUEUE_139_...

Page 58: ...148_D Register 2738 16 907 QUEUE_149_A Register 2739 16 908 QUEUE_149_B Register 2740 16 909 QUEUE_149_C Register 2741 16 910 QUEUE_149_D Register 2742 16 911 QUEUE_150_A Register 2743 16 912 QUEUE_150_B Register 2744 16 913 QUEUE_150_C Register 2745 16 914 QUEUE_150_D Register 2746 16 915 QUEUE_151_A Register 2747 16 916 QUEUE_151_B Register 2748 16 917 QUEUE_151_C Register 2749 16 918 QUEUE_151_...

Page 59: ...7 16 956 QUEUE_7_STATUS_A Register 2788 16 957 QUEUE_7_STATUS_B Register 2789 16 958 QUEUE_7_STATUS_C Register 2790 16 959 QUEUE_8_STATUS_A Register 2791 16 960 QUEUE_8_STATUS_B Register 2792 16 961 QUEUE_8_STATUS_C Register 2793 16 962 QUEUE_9_STATUS_A Register 2794 16 963 QUEUE_9_STATUS_B Register 2795 16 964 QUEUE_9_STATUS_C Register 2796 16 965 QUEUE_10_STATUS_A Register 2797 16 966 QUEUE_10_S...

Page 60: ...r 2836 16 1005 QUEUE_23_STATUS_B Register 2837 16 1006 QUEUE_23_STATUS_C Register 2838 16 1007 QUEUE_24_STATUS_A Register 2839 16 1008 QUEUE_24_STATUS_B Register 2840 16 1009 QUEUE_24_STATUS_C Register 2841 16 1010 QUEUE_25_STATUS_A Register 2842 16 1011 QUEUE_25_STATUS_B Register 2843 16 1012 QUEUE_25_STATUS_C Register 2844 16 1013 QUEUE_26_STATUS_A Register 2845 16 1014 QUEUE_26_STATUS_B Registe...

Page 61: ...B Register 2885 16 1054 QUEUE_39_STATUS_C Register 2886 16 1055 QUEUE_40_STATUS_A Register 2887 16 1056 QUEUE_40_STATUS_B Register 2888 16 1057 QUEUE_40_STATUS_C Register 2889 16 1058 QUEUE_41_STATUS_A Register 2890 16 1059 QUEUE_41_STATUS_B Register 2891 16 1060 QUEUE_41_STATUS_C Register 2892 16 1061 QUEUE_42_STATUS_A Register 2893 16 1062 QUEUE_42_STATUS_B Register 2894 16 1063 QUEUE_42_STATUS_...

Page 62: ...C Register 2934 16 1103 QUEUE_56_STATUS_A Register 2935 16 1104 QUEUE_56_STATUS_B Register 2936 16 1105 QUEUE_56_STATUS_C Register 2937 16 1106 QUEUE_57_STATUS_A Register 2938 16 1107 QUEUE_57_STATUS_B Register 2939 16 1108 QUEUE_57_STATUS_C Register 2940 16 1109 QUEUE_58_STATUS_A Register 2941 16 1110 QUEUE_58_STATUS_B Register 2942 16 1111 QUEUE_58_STATUS_C Register 2943 16 1112 QUEUE_59_STATUS_...

Page 63: ...A Register 2983 16 1152 QUEUE_72_STATUS_B Register 2984 16 1153 QUEUE_72_STATUS_C Register 2985 16 1154 QUEUE_73_STATUS_A Register 2986 16 1155 QUEUE_73_STATUS_B Register 2987 16 1156 QUEUE_73_STATUS_C Register 2988 16 1157 QUEUE_74_STATUS_A Register 2989 16 1158 QUEUE_74_STATUS_B Register 2990 16 1159 QUEUE_74_STATUS_C Register 2991 16 1160 QUEUE_75_STATUS_A Register 2992 16 1161 QUEUE_75_STATUS_...

Page 64: ...B Register 3032 16 1201 QUEUE_88_STATUS_C Register 3033 16 1202 QUEUE_89_STATUS_A Register 3034 16 1203 QUEUE_89_STATUS_B Register 3035 16 1204 QUEUE_89_STATUS_C Register 3036 16 1205 QUEUE_90_STATUS_A Register 3037 16 1206 QUEUE_90_STATUS_B Register 3038 16 1207 QUEUE_90_STATUS_C Register 3039 16 1208 QUEUE_91_STATUS_A Register 3040 16 1209 QUEUE_91_STATUS_B Register 3041 16 1210 QUEUE_91_STATUS_...

Page 65: ...ister 3081 16 1250 QUEUE_105_STATUS_A Register 3082 16 1251 QUEUE_105_STATUS_B Register 3083 16 1252 QUEUE_105_STATUS_C Register 3084 16 1253 QUEUE_106_STATUS_A Register 3085 16 1254 QUEUE_106_STATUS_B Register 3086 16 1255 QUEUE_106_STATUS_C Register 3087 16 1256 QUEUE_107_STATUS_A Register 3088 16 1257 QUEUE_107_STATUS_B Register 3089 16 1258 QUEUE_107_STATUS_C Register 3090 16 1259 QUEUE_108_ST...

Page 66: ...A Register 3130 16 1299 QUEUE_121_STATUS_B Register 3131 16 1300 QUEUE_121_STATUS_C Register 3132 16 1301 QUEUE_122_STATUS_A Register 3133 16 1302 QUEUE_122_STATUS_B Register 3134 16 1303 QUEUE_122_STATUS_C Register 3135 16 1304 QUEUE_123_STATUS_A Register 3136 16 1305 QUEUE_123_STATUS_B Register 3137 16 1306 QUEUE_123_STATUS_C Register 3138 16 1307 QUEUE_124_STATUS_A Register 3139 16 1308 QUEUE_1...

Page 67: ...B Register 3179 16 1348 QUEUE_137_STATUS_C Register 3180 16 1349 QUEUE_138_STATUS_A Register 3181 16 1350 QUEUE_138_STATUS_B Register 3182 16 1351 QUEUE_138_STATUS_C Register 3183 16 1352 QUEUE_139_STATUS_A Register 3184 16 1353 QUEUE_139_STATUS_B Register 3185 16 1354 QUEUE_139_STATUS_C Register 3186 16 1355 QUEUE_140_STATUS_A Register 3187 16 1356 QUEUE_140_STATUS_B Register 3188 16 1357 QUEUE_1...

Page 68: ...EUE_153_STATUS_A Register 3226 16 1395 QUEUE_153_STATUS_B Register 3227 16 1396 QUEUE_153_STATUS_C Register 3228 16 1397 QUEUE_154_STATUS_A Register 3229 16 1398 QUEUE_154_STATUS_B Register 3230 16 1399 QUEUE_154_STATUS_C Register 3231 16 1400 QUEUE_155_STATUS_A Register 3232 16 1401 QUEUE_155_STATUS_B Register 3233 16 1402 QUEUE_155_STATUS_C Register 3234 17 1 Mailbox Integration 3237 17 2 Mailbo...

Page 69: ...TUS_CLR_3 Register 3300 17 43 IRQENABLE_SET_3 Register 3302 17 44 IRQENABLE_CLR_3 Register 3304 17 45 REV Register 3309 17 46 SYSCONFIG Register 3310 17 47 SYSTATUS Register 3311 17 48 LOCK_REG_0 Register 3312 17 49 LOCK_REG_1 Register 3313 17 50 LOCK_REG_2 Register 3314 17 51 LOCK_REG_3 Register 3315 17 52 LOCK_REG_4 Register 3316 17 53 LOCK_REG_5 Register 3317 17 54 LOCK_REG_6 Register 3318 17 5...

Page 70: ... Data Packet for Block Transfer 4 Bit 3356 18 16 Data Packet for Block Transfer 8 Bit 3357 18 17 DMA Receive Mode 3364 18 18 DMA Transmit Mode 3365 18 19 Buffer Management for a Write 3367 18 20 Buffer Management for a Read 3368 18 21 Busy Timeout for R1b R5b Responses 3371 18 22 Busy Timeout After Write CRC Status 3371 18 23 Write CRC Status Timeout 3372 18 24 Read Data Timeout 3372 18 25 Boot Ac...

Page 71: ...DA Module IrDA CIR Application 3449 19 3 UART IrDA CIR Functional Specification Block Diagram 3454 19 4 FIFO Management Registers 3459 19 5 RX FIFO Interrupt Request Generation 3461 19 6 TX FIFO Interrupt Request Generation 3462 19 7 Receive FIFO DMA Request Generation 32 Characters 3463 19 8 Transmit FIFO DMA Request Generation 56 Spaces 3464 19 9 Transmit FIFO DMA Request Generation 8 Spaces 346...

Page 72: ...ine Status Register LSR 3518 19 47 CIR Line Status Register LSR 3519 19 48 Modem Status Register MSR 3520 19 49 Transmission Control Register TCR 3521 19 50 Scratchpad Register SPR 3521 19 51 Trigger Level Register TLR 3522 19 52 Mode Definition Register 1 MDR1 3523 19 53 Mode Definition Register 2 MDR2 3524 19 54 Status FIFO Line Status Register SFLSR 3525 19 55 RESUME Register 3525 19 56 Status ...

Page 73: ...dth Modulation with SCPWM 0 3560 20 8 Timing Diagram of Pulse Width Modulation with SCPWM 1 3561 20 9 TIDR Register 3567 20 10 TIOCP_CFG Register 3568 20 11 IRQ_EOI Register 3569 20 12 IRQSTATUS_RAW Register 3570 20 13 IRQSTATUS Register 3571 20 14 IRQENABLE_SET Register 3572 20 15 IRQENABLE_CLR Register 3573 20 16 IRQWAKEEN Register 3574 20 17 TCLR Register 3575 20 18 TCRR Register 3577 20 19 TLD...

Page 74: ...ters 3629 20 60 Compensation Illustration 3630 20 61 SECONDS_REG Register 3634 20 62 MINUTES_REG Register 3635 20 63 HOURS_REG Register 3636 20 64 DAYS_REG Register 3637 20 65 MONTHS_REG Register 3638 20 66 YEARS_REG Register 3639 20 67 WEEKS_REG Register 3640 20 68 ALARM_SECONDS_REG Register 3641 20 69 ALARM_MINUTES_REG Register 3642 20 70 ALARM_HOURS_REG Register 3643 20 71 ALARM_DAYS_REG Regist...

Page 75: ...Register 3692 20 110 WDT_WSPR Register 3693 20 111 WDT_WIRQSTATRAW Register 3694 20 112 WDT_WIRQSTAT Register 3695 20 113 WDT_WIRQENSET Register 3696 20 114 WDT_WIRQENCLR Register 3697 21 1 I2C0 Integration and Bus Application 3700 21 2 I2C 1 2 Integration and Bus Application 3700 21 3 I2C Functional Block Diagram 3702 21 4 Multiple I2C Modules Connected 3703 21 5 Bit Transfer on the I2C Bus 3704 ...

Page 76: ...Register 3764 21 45 I2C_ACTOA Register 3765 21 46 I2C_SBLOCK Register 3766 22 1 McASP0 1 Integration 3771 22 2 McASP Block Diagram 3774 22 3 McASP to Parallel 2 Channel DACs 3775 22 4 McASP to 6 Channel DAC and 2 Channel DAC 3775 22 5 McASP to Digital Amplifier 3776 22 6 McASP as Digital Audio Encoder 3776 22 7 McASP as 16 Channel Digital Processor 3776 22 8 TDM Format 6 Channel TDM Example 3777 2...

Page 77: ...45 Pin Data Set Register PDSET 3838 22 46 Pin Data Clear Register PDCLR 3840 22 47 Global Control Register GBLCTL 3842 22 48 Audio Mute Control Register AMUTE 3844 22 49 Digital Loopback Control Register DLBCTL 3846 22 50 Digital Mode Control Register DITCTL 3847 22 51 Receiver Global Control Register RGBLCTL 3848 22 52 Receive Format Unit Bit Mask Register RMASK 3849 22 53 Receive Bit Stream Form...

Page 78: ...ming Configuration 3888 23 5 CAN Core in Silent Mode 3890 23 6 CAN Core in Loopback Mode 3891 23 7 CAN Core in External Loopback Mode 3892 23 8 CAN Core in Loop Back Combined With Silent Mode 3893 23 9 CAN Interrupt Topology 1 3895 23 10 CAN Interrupt Topology 2 3895 23 11 Local Power Down Mode Flow Diagram 3897 23 12 CPU Handling of a FIFO Buffer Interrupt Driven 3906 23 13 Bit Timing 3907 23 14 ...

Page 79: ...ter 3972 23 60 IF2MCTL Register 3973 23 61 IF2DATA Register 3975 23 62 IF2DATB Register 3976 23 63 IF3OBS Register 3977 23 64 IF3MSK Register 3979 23 65 IF3ARB Register 3980 23 66 IF3MCTL Register 3981 23 67 IF3DATA Register 3983 23 68 IF3DATB Register 3984 23 69 IF3UPD12 Register 3985 23 70 IF3UPD34 Register 3986 23 71 IF3UPD56 Register 3987 23 72 IF3UPD78 Register 3988 23 73 TIOC Register 3989 2...

Page 80: ... MCSPI_IRQENABLE 4040 24 31 McSPI System Register MCSPI_SYST 4042 24 32 McSPI Module Control Register MCSPI_MODULCTRL 4044 24 33 McSPI Channel i Configuration Register MCSPI_CH i CONF 4046 24 34 McSPI Channel i Status Register MCSPI_CH i STAT 4050 24 35 McSPI Channel i Control Register MCSPI_CH I CTRL 4051 24 36 McSPI Channel i Transmit Register MCSPI_TX i 4052 24 37 McSPI Channel i Receive Regist...

Page 81: ...6 7 Fast External Boot 4113 26 8 Memory Booting 4114 26 9 GPMC XIP Timings 4116 26 10 Image Shadowing on GP Device 4118 26 11 GPMC NAND Timings 4119 26 12 NAND Device Detection 4124 26 13 NAND Invalid Blocks Detection 4125 26 14 NAND Read Sector Procedure 4126 26 15 ECC Data Mapping for 2 KB Page and 8b BCH Encoding 4127 26 16 ECC Data Mapping for 4 KB Page and 16b BCH Encoding 4128 26 17 MMC SD B...

Page 82: ...TC_IDLE Register Field Descriptions 213 6 12 INTC_IRQ_PRIORITY Register Field Descriptions 214 6 13 INTC_FIQ_PRIORITY Register Field Descriptions 215 6 14 INTC_THRESHOLD Register Field Descriptions 216 6 15 INTC_ITR0 Register Field Descriptions 217 6 16 INTC_MIR0 Register Field Descriptions 218 6 17 INTC_MIR_CLEAR0 Register Field Descriptions 219 6 18 INTC_MIR_SET0 Register Field Descriptions 220 ...

Page 83: ...62 7 10 Idle Cycle Insertion Configuration 273 7 11 Chip Select Configuration for NAND Interfacing 302 7 12 ECC Enable Settings 311 7 13 Flattened BCH Codeword Mapping 512 Bytes 104 Bits 316 7 14 Aligned Message Byte Mapping in 8 bit NAND 316 7 15 Aligned Message Byte Mapping in 16 bit NAND 317 7 16 Aligned Nibble Mapping of Message in 8 bit NAND 317 7 17 Misaligned Nibble Mapping of Message in 8 ...

Page 84: ...PMC_IRQENABLE Field Descriptions 370 7 60 GPMC_TIMEOUT_CONTROL Field Descriptions 371 7 61 GPMC_ERR_ADDRESS Field Descriptions 371 7 62 GPMC_ERR_TYPE Field Descriptions 372 7 63 GPMC_CONFIG Field Descriptions 373 7 64 GPMC_STATUS Field Descriptions 374 7 65 GPMC_CONFIG1_i Field Descriptions 375 7 66 GPMC_CONFIG2_i Field Descriptions 377 7 67 GPMC_CONFIG3_i Field Descriptions 378 7 68 GPMC_CONFIG4_...

Page 85: ...DR2 3 mDDR Address Mapping for REG_IBANK_POS 1 and REG_EBANK_POS 1 412 7 106 OCP Address to DDR2 3 mDDR Address Mapping for REG_IBANK_POS 2 and REG_EBANK_POS 1 413 7 107 OCP Address to DDR2 3 mDDR Address Mapping for REG_IBANK_POS 3 and REG_EBANK_POS 1 413 7 108 Refresh Modes 416 7 109 Filter Configurations for Performance Counters 417 7 110 EMIF4D REGISTERS 422 7 111 EMIF_MOD_ID_REV Register Fiel...

Page 86: ...criptions 469 7 151 DDR PHY Command 0 1 2 Address Command DLL Lock Difference Register CMD0 1 2_REG_PHY_DLL_LOCK_DIFF_0 Field Descriptions 469 7 152 DDR PHY Command 0 1 2 Invert Clockout Selection Register CMD0 1 2_REG_PHY_INVERT_CLKOUT_0 Field Descriptions 470 7 153 DDR PHY Data Macro 0 1 Read DQS Slave Ratio Register DATA0 1_REG_PHY_RD_DQS_SLAVE_RATIO_0 Field Descriptions 470 7 154 DDR PHY Data ...

Page 87: ...ons 496 7 187 ELM_SYNDROME_FRAGMENT_5_i Register Field Descriptions 496 7 188 ELM_SYNDROME_FRAGMENT_6_i Register Field Descriptions 497 7 189 ELM_LOCATION_STATUS_i Register Field Descriptions 497 7 190 ELM_ERROR_LOCATION_0 15_i Registers Field Descriptions 498 8 1 Master Module Standby Mode Settings 501 8 2 Master Module Standby Status 502 8 3 Module Idle Mode Settings 502 8 4 Idle States for a Sl...

Page 88: ...M_PER_L4FW_CLKCTRL Register Field Descriptions 571 8 51 CM_PER_MCASP1_CLKCTRL Register Field Descriptions 572 8 52 CM_PER_UART1_CLKCTRL Register Field Descriptions 573 8 53 CM_PER_UART2_CLKCTRL Register Field Descriptions 574 8 54 CM_PER_UART3_CLKCTRL Register Field Descriptions 575 8 55 CM_PER_UART4_CLKCTRL Register Field Descriptions 576 8 56 CM_PER_TIMER7_CLKCTRL Register Field Descriptions 577...

Page 89: ...gister Field Descriptions 622 8 99 CM_AUTOIDLE_DPLL_MPU Register Field Descriptions 623 8 100 CM_IDLEST_DPLL_MPU Register Field Descriptions 624 8 101 CM_SSC_DELTAMSTEP_DPLL_MPU Register Field Descriptions 625 8 102 CM_SSC_MODFREQDIV_DPLL_MPU Register Field Descriptions 626 8 103 CM_CLKSEL_DPLL_MPU Register Field Descriptions 627 8 104 CM_AUTOIDLE_DPLL_DDR Register Field Descriptions 628 8 105 CM_...

Page 90: ...s 672 8 145 CM_DIV_M6_DPLL_CORE Register Field Descriptions 673 8 146 CM_DPLL REGISTERS 674 8 147 CLKSEL_TIMER7_CLK Register Field Descriptions 675 8 148 CLKSEL_TIMER2_CLK Register Field Descriptions 676 8 149 CLKSEL_TIMER3_CLK Register Field Descriptions 677 8 150 CLKSEL_TIMER4_CLK Register Field Descriptions 678 8 151 CM_MAC_CLKSEL Register Field Descriptions 679 8 152 CLKSEL_TIMER5_CLK Register...

Page 91: ...195 PM_MPU_PWRSTST Register Field Descriptions 723 8 196 RM_MPU_RSTST Register Field Descriptions 724 8 197 PRM_DEVICE REGISTERS 724 8 198 PRM_RSTCTRL Register Field Descriptions 726 8 199 PRM_RSTTIME Register Field Descriptions 727 8 200 PRM_RSTST Register Field Descriptions 728 8 201 PRM_SRAM_COUNT Register Field Descriptions 729 8 202 PRM_LDO_SRAM_CORE_SETUP Register Field Descriptions 730 8 20...

Page 92: ...ns 780 9 29 mmu_cfg Register Field Descriptions 781 9 30 tptc_cfg Register Field Descriptions 782 9 31 usb_ctrl0 Register Field Descriptions 783 9 32 usb_sts0 Register Field Descriptions 785 9 33 usb_ctrl1 Register Field Descriptions 786 9 34 usb_sts1 Register Field Descriptions 788 9 35 mac_id0_lo Register Field Descriptions 789 9 36 mac_id0_hi Register Field Descriptions 790 9 37 mac_id1_lo Regi...

Page 93: ...gister Field Descriptions 831 9 78 tpcc_evt_mux_48_51 Register Field Descriptions 832 9 79 tpcc_evt_mux_52_55 Register Field Descriptions 833 9 80 tpcc_evt_mux_56_59 Register Field Descriptions 834 9 81 tpcc_evt_mux_60_63 Register Field Descriptions 835 9 82 timer_evt_capt Register Field Descriptions 836 9 83 ecap_evt_capt Register Field Descriptions 837 9 84 adc_evt_capt Register Field Descriptio...

Page 94: ... System Configuration Register SYSCONFIG Field Descriptions 945 11 29 DMA Channel Map n Registers DCHMAPn Field Descriptions 946 11 30 QDMA Channel Map n Registers QCHMAPn Field Descriptions 947 11 31 DMA Channel Queue n Number Registers DMAQNUMn Field Descriptions 948 11 32 Bits in DMAQNUMn 948 11 33 QDMA Channel Queue Number Register QDMAQNUM Field Descriptions 949 11 34 Queue Priority Register ...

Page 95: ...ld Descriptions 980 11 72 Interrupt Enable Register IER Field Descriptions 981 11 73 Interrupt Enable Register High IERH Field Descriptions 981 11 74 Interrupt Enable Clear Register IECR Field Descriptions 982 11 75 Interrupt Enable Clear Register High IECRH Field Descriptions 982 11 76 Interrupt Enable Set Register IESR Field Descriptions 983 11 77 Interrupt Enable Set Register High IESRH Field D...

Page 96: ...ptions 1017 11 116 Destination FIFO Source Address B Reference Register DFSRCBREFn Field Descriptions 1017 11 117 Destination FIFO Destination Address B Reference Register DFDSTBREFn Field Descriptions 1018 11 118 Debug List 1018 12 1 TSC_ADC Connectivity Attributes 1024 12 2 TSC_ADC Clock Signals 1025 12 3 TSC_ADC Pin List 1025 12 4 TSC_ADC_SS REGISTERS 1033 12 5 REVISION Register Field Descripti...

Page 97: ...ONFIG15 Register Field Descriptions 1085 12 52 STEPDELAY15 Register Field Descriptions 1086 12 53 STEPCONFIG16 Register Field Descriptions 1087 12 54 STEPDELAY16 Register Field Descriptions 1088 12 55 FIFO0COUNT Register Field Descriptions 1089 12 56 FIFO0THRESHOLD Register Field Descriptions 1090 12 57 DMA0REQ Register Field Descriptions 1091 12 58 FIFO1COUNT Register Field Descriptions 1092 12 5...

Page 98: ...gister Field Descriptions 1157 13 38 IRQENABLE_CLEAR Register Field Descriptions 1159 13 39 CLKC_ENABLE Register Field Descriptions 1161 13 40 CLKC_RESET Register Field Descriptions 1162 14 1 Unsupported CPGMAC Features 1165 14 2 Ethernet Switch Connectivity Attributes 1167 14 3 Ethernet Switch Clock Signals 1168 14 4 Ethernet Switch Pin List 1169 14 5 GMII Interface Signal Descriptions in GIG 100...

Page 99: ...gister Field Descriptions 1269 14 50 EMCONTROL Register Field Descriptions 1270 14 51 TX_PRI0_RATE Register Field Descriptions 1271 14 52 TX_PRI1_RATE Register Field Descriptions 1272 14 53 TX_PRI2_RATE Register Field Descriptions 1273 14 54 TX_PRI3_RATE Register Field Descriptions 1274 14 55 TX_PRI4_RATE Register Field Descriptions 1275 14 56 TX_PRI5_RATE Register Field Descriptions 1276 14 57 TX...

Page 100: ...scriptions 1315 14 96 CPTS_INTSTAT_MASKED Register Field Descriptions 1316 14 97 CPTS_INT_ENABLE Register Field Descriptions 1317 14 98 CPTS_EVENT_POP Register Field Descriptions 1318 14 99 CPTS_EVENT_LOW Register Field Descriptions 1319 14 100 CPTS_EVENT_HIGH Register Field Descriptions 1320 14 101 CPSW_STATS REGISTERS 1321 14 102 CPDMA_STATERAM REGISTERS 1321 14 103 TX0_HDP Register Field Descri...

Page 101: ...DSCP_PRI_MAP3 Register Field Descriptions 1368 14 148 P0_RX_DSCP_PRI_MAP4 Register Field Descriptions 1369 14 149 P0_RX_DSCP_PRI_MAP5 Register Field Descriptions 1370 14 150 P0_RX_DSCP_PRI_MAP6 Register Field Descriptions 1371 14 151 P0_RX_DSCP_PRI_MAP7 Register Field Descriptions 1372 14 152 P1_CONTROL Register Field Descriptions 1373 14 153 P1_MAX_BLKS Register Field Descriptions 1375 14 154 P1_...

Page 102: ...eld Descriptions 1418 14 194 BOFFTEST Register Field Descriptions 1419 14 195 RX_PAUSE Register Field Descriptions 1420 14 196 TX_PAUSE Register Field Descriptions 1421 14 197 EMCONTROL Register Field Descriptions 1422 14 198 RX_PRI_MAP Register Field Descriptions 1423 14 199 TX_GAP Register Field Descriptions 1424 14 200 CPSW_SS REGISTERS 1424 14 201 ID_VER Register Field Descriptions 1425 14 202...

Page 103: ..._IMAX Register Field Descriptions 1470 14 247 C2_RX_IMAX Register Field Descriptions 1471 14 248 C2_TX_IMAX Register Field Descriptions 1472 14 249 RGMII_CTL Register Field Descriptions 1473 14 250 Management Data Input Output MDIO Registers 1474 14 251 MDIO Version Register MDIOVER Field Descriptions 1474 14 252 MDIO Control Register MDIOCONTROL Field Descriptions 1475 14 253 PHY Acknowledge Stat...

Page 104: ...zation for 1525 15 24 EPWMx Run Time Changes for 1525 15 25 EPWMx Initialization for 1527 15 26 EPWMx Run Time Changes for 1527 15 27 EPWMx Initialization for 1529 15 28 EPWMx Run Time Changes for 1529 15 29 EPWMx Initialization for 1531 15 30 EPWMx Run Time Changes for 1531 15 31 EPWMx Initialization for 1533 15 32 EPWMx Run Time Changes for 1533 15 33 Dead Band Generator Submodule Registers 1534...

Page 105: ...Band Generator Rising Edge Delay Register DBRED Field Descriptions 1595 15 77 Dead Band Generator Falling Edge Delay Register DBFED Field Descriptions 1595 15 78 Trip Zone Submodule Registers 1596 15 79 Trip Zone Submodule Select Register TZSEL Field Descriptions 1596 15 80 Trip Zone Control Register TZCTL Field Descriptions 1597 15 81 Trip Zone Enable Interrupt Register TZEINT Field Descriptions ...

Page 106: ...ition Counter Initialization Register QPOSINIT Field Descriptions 1673 15 126 eQEP Maximum Position Count Register QPOSMAX Field Descriptions 1673 15 127 eQEP Position Compare Register QPOSCMP Field Descriptions 1674 15 128 eQEP Index Position Latch Register QPOSILAT Field Descriptions 1674 15 129 eQEP Strobe Position Latch Register QPOSSLAT Field Descriptions 1674 15 130 eQEP Position Counter Lat...

Page 107: ...er Descriptor Word 5 BD5 Bit Field Descriptions 1740 16 23 Buffer Descriptor Word 6 BD6 Bit Field Descriptions 1740 16 24 Buffer Descriptor Word 7 BD7 Bit Field Descriptions 1740 16 25 Teardown Descriptor Word 0 Bit Field Descriptions 1741 16 26 Teardown Descriptor Words 1 to 7 Bit Field Descriptions 1741 16 27 Queue Endpoint Assignments 1742 16 28 53 Bytes Test Packet Content 1758 16 29 USBSS REG...

Page 108: ... USB0_CTRL REGISTERS 1803 16 73 USB0REV Register Field Descriptions 1805 16 74 USB0CTRL Register Field Descriptions 1806 16 75 USB0STAT Register Field Descriptions 1808 16 76 USB0IRQMSTAT Register Field Descriptions 1809 16 77 USB0IRQSTATRAW0 Register Field Descriptions 1810 16 78 USB0IRQSTATRAW1 Register Field Descriptions 1812 16 79 USB0IRQSTAT0 Register Field Descriptions 1814 16 80 USB0IRQSTAT...

Page 109: ...6 122 USB1RXMODE Register Field Descriptions 1878 16 123 USB1GENRNDISEP1 Register Field Descriptions 1880 16 124 USB1GENRNDISEP2 Register Field Descriptions 1881 16 125 USB1GENRNDISEP3 Register Field Descriptions 1882 16 126 USB1GENRNDISEP4 Register Field Descriptions 1883 16 127 USB1GENRNDISEP5 Register Field Descriptions 1884 16 128 USB1GENRNDISEP6 Register Field Descriptions 1885 16 129 USB1GEN...

Page 110: ...CRB0 Register Field Descriptions 1936 16 171 TXGCR1 Register Field Descriptions 1937 16 172 RXGCR1 Register Field Descriptions 1938 16 173 RXHPCRA1 Register Field Descriptions 1940 16 174 RXHPCRB1 Register Field Descriptions 1941 16 175 TXGCR2 Register Field Descriptions 1942 16 176 RXGCR2 Register Field Descriptions 1943 16 177 RXHPCRA2 Register Field Descriptions 1945 16 178 RXHPCRB2 Register Fi...

Page 111: ...s 1997 16 220 RXGCR13 Register Field Descriptions 1998 16 221 RXHPCRA13 Register Field Descriptions 2000 16 222 RXHPCRB13 Register Field Descriptions 2001 16 223 TXGCR14 Register Field Descriptions 2002 16 224 RXGCR14 Register Field Descriptions 2003 16 225 RXHPCRA14 Register Field Descriptions 2005 16 226 RXHPCRB14 Register Field Descriptions 2006 16 227 TXGCR15 Register Field Descriptions 2007 1...

Page 112: ...Descriptions 2058 16 269 RXHPCRA25 Register Field Descriptions 2060 16 270 RXHPCRB25 Register Field Descriptions 2061 16 271 TXGCR26 Register Field Descriptions 2062 16 272 RXGCR26 Register Field Descriptions 2063 16 273 RXHPCRA26 Register Field Descriptions 2065 16 274 RXHPCRB26 Register Field Descriptions 2066 16 275 TXGCR27 Register Field Descriptions 2067 16 276 RXGCR27 Register Field Descript...

Page 113: ...MEMCTRL4 Register Field Descriptions 2136 16 319 QMEMRBASE5 Register Field Descriptions 2137 16 320 QMEMCTRL5 Register Field Descriptions 2138 16 321 QMEMRBASE6 Register Field Descriptions 2139 16 322 QMEMCTRL6 Register Field Descriptions 2140 16 323 QMEMRBASE7 Register Field Descriptions 2141 16 324 QMEMCTRL7 Register Field Descriptions 2142 16 325 QUEUE_0_A Register Field Descriptions 2143 16 32...

Page 114: ...16 367 QUEUE_10_C Register Field Descriptions 2185 16 368 QUEUE_10_D Register Field Descriptions 2186 16 369 QUEUE_11_A Register Field Descriptions 2187 16 370 QUEUE_11_B Register Field Descriptions 2188 16 371 QUEUE_11_C Register Field Descriptions 2189 16 372 QUEUE_11_D Register Field Descriptions 2190 16 373 QUEUE_12_A Register Field Descriptions 2191 16 374 QUEUE_12_B Register Field Descriptio...

Page 115: ...tions 2233 16 416 QUEUE_22_D Register Field Descriptions 2234 16 417 QUEUE_23_A Register Field Descriptions 2235 16 418 QUEUE_23_B Register Field Descriptions 2236 16 419 QUEUE_23_C Register Field Descriptions 2237 16 420 QUEUE_23_D Register Field Descriptions 2238 16 421 QUEUE_24_A Register Field Descriptions 2239 16 422 QUEUE_24_B Register Field Descriptions 2240 16 423 QUEUE_24_C Register Field...

Page 116: ...tions 2282 16 465 QUEUE_35_A Register Field Descriptions 2283 16 466 QUEUE_35_B Register Field Descriptions 2284 16 467 QUEUE_35_C Register Field Descriptions 2285 16 468 QUEUE_35_D Register Field Descriptions 2286 16 469 QUEUE_36_A Register Field Descriptions 2287 16 470 QUEUE_36_B Register Field Descriptions 2288 16 471 QUEUE_36_C Register Field Descriptions 2289 16 472 QUEUE_36_D Register Field...

Page 117: ...tions 2331 16 514 QUEUE_47_B Register Field Descriptions 2332 16 515 QUEUE_47_C Register Field Descriptions 2333 16 516 QUEUE_47_D Register Field Descriptions 2334 16 517 QUEUE_48_A Register Field Descriptions 2335 16 518 QUEUE_48_B Register Field Descriptions 2336 16 519 QUEUE_48_C Register Field Descriptions 2337 16 520 QUEUE_48_D Register Field Descriptions 2338 16 521 QUEUE_49_A Register Field...

Page 118: ...tions 2380 16 563 QUEUE_59_C Register Field Descriptions 2381 16 564 QUEUE_59_D Register Field Descriptions 2382 16 565 QUEUE_60_A Register Field Descriptions 2383 16 566 QUEUE_60_B Register Field Descriptions 2384 16 567 QUEUE_60_C Register Field Descriptions 2385 16 568 QUEUE_60_D Register Field Descriptions 2386 16 569 QUEUE_61_A Register Field Descriptions 2387 16 570 QUEUE_61_B Register Field...

Page 119: ...tions 2429 16 612 QUEUE_71_D Register Field Descriptions 2430 16 613 QUEUE_72_A Register Field Descriptions 2431 16 614 QUEUE_72_B Register Field Descriptions 2432 16 615 QUEUE_72_C Register Field Descriptions 2433 16 616 QUEUE_72_D Register Field Descriptions 2434 16 617 QUEUE_73_A Register Field Descriptions 2435 16 618 QUEUE_73_B Register Field Descriptions 2436 16 619 QUEUE_73_C Register Field...

Page 120: ...tions 2478 16 661 QUEUE_84_A Register Field Descriptions 2479 16 662 QUEUE_84_B Register Field Descriptions 2480 16 663 QUEUE_84_C Register Field Descriptions 2481 16 664 QUEUE_84_D Register Field Descriptions 2482 16 665 QUEUE_85_A Register Field Descriptions 2483 16 666 QUEUE_85_B Register Field Descriptions 2484 16 667 QUEUE_85_C Register Field Descriptions 2485 16 668 QUEUE_85_D Register Field...

Page 121: ... 2527 16 710 QUEUE_96_B Register Field Descriptions 2528 16 711 QUEUE_96_C Register Field Descriptions 2529 16 712 QUEUE_96_D Register Field Descriptions 2530 16 713 QUEUE_97_A Register Field Descriptions 2531 16 714 QUEUE_97_B Register Field Descriptions 2532 16 715 QUEUE_97_C Register Field Descriptions 2533 16 716 QUEUE_97_D Register Field Descriptions 2534 16 717 QUEUE_98_A Register Field Desc...

Page 122: ...ions 2576 16 759 QUEUE_108_C Register Field Descriptions 2577 16 760 QUEUE_108_D Register Field Descriptions 2578 16 761 QUEUE_109_A Register Field Descriptions 2579 16 762 QUEUE_109_B Register Field Descriptions 2580 16 763 QUEUE_109_C Register Field Descriptions 2581 16 764 QUEUE_109_D Register Field Descriptions 2582 16 765 QUEUE_110_A Register Field Descriptions 2583 16 766 QUEUE_110_B Registe...

Page 123: ...ions 2625 16 808 QUEUE_120_D Register Field Descriptions 2626 16 809 QUEUE_121_A Register Field Descriptions 2627 16 810 QUEUE_121_B Register Field Descriptions 2628 16 811 QUEUE_121_C Register Field Descriptions 2629 16 812 QUEUE_121_D Register Field Descriptions 2630 16 813 QUEUE_122_A Register Field Descriptions 2631 16 814 QUEUE_122_B Register Field Descriptions 2632 16 815 QUEUE_122_C Registe...

Page 124: ...ions 2674 16 857 QUEUE_133_A Register Field Descriptions 2675 16 858 QUEUE_133_B Register Field Descriptions 2676 16 859 QUEUE_133_C Register Field Descriptions 2677 16 860 QUEUE_133_D Register Field Descriptions 2678 16 861 QUEUE_134_A Register Field Descriptions 2679 16 862 QUEUE_134_B Register Field Descriptions 2680 16 863 QUEUE_134_C Register Field Descriptions 2681 16 864 QUEUE_134_D Registe...

Page 125: ...ions 2723 16 906 QUEUE_145_B Register Field Descriptions 2724 16 907 QUEUE_145_C Register Field Descriptions 2725 16 908 QUEUE_145_D Register Field Descriptions 2726 16 909 QUEUE_146_A Register Field Descriptions 2727 16 910 QUEUE_146_B Register Field Descriptions 2728 16 911 QUEUE_146_C Register Field Descriptions 2729 16 912 QUEUE_146_D Register Field Descriptions 2730 16 913 QUEUE_147_A Registe...

Page 126: ... Descriptions 2773 16 956 QUEUE_2_STATUS_B Register Field Descriptions 2774 16 957 QUEUE_2_STATUS_C Register Field Descriptions 2775 16 958 QUEUE_3_STATUS_A Register Field Descriptions 2776 16 959 QUEUE_3_STATUS_B Register Field Descriptions 2777 16 960 QUEUE_3_STATUS_C Register Field Descriptions 2778 16 961 QUEUE_4_STATUS_A Register Field Descriptions 2779 16 962 QUEUE_4_STATUS_B Register Field ...

Page 127: ...1004 QUEUE_18_STATUS_B Register Field Descriptions 2822 16 1005 QUEUE_18_STATUS_C Register Field Descriptions 2823 16 1006 QUEUE_19_STATUS_A Register Field Descriptions 2824 16 1007 QUEUE_19_STATUS_B Register Field Descriptions 2825 16 1008 QUEUE_19_STATUS_C Register Field Descriptions 2826 16 1009 QUEUE_20_STATUS_A Register Field Descriptions 2827 16 1010 QUEUE_20_STATUS_B Register Field Descript...

Page 128: ...s 2870 16 1053 QUEUE_34_STATUS_C Register Field Descriptions 2871 16 1054 QUEUE_35_STATUS_A Register Field Descriptions 2872 16 1055 QUEUE_35_STATUS_B Register Field Descriptions 2873 16 1056 QUEUE_35_STATUS_C Register Field Descriptions 2874 16 1057 QUEUE_36_STATUS_A Register Field Descriptions 2875 16 1058 QUEUE_36_STATUS_B Register Field Descriptions 2876 16 1059 QUEUE_36_STATUS_C Register Fiel...

Page 129: ...s 2919 16 1102 QUEUE_51_STATUS_A Register Field Descriptions 2920 16 1103 QUEUE_51_STATUS_B Register Field Descriptions 2921 16 1104 QUEUE_51_STATUS_C Register Field Descriptions 2922 16 1105 QUEUE_52_STATUS_A Register Field Descriptions 2923 16 1106 QUEUE_52_STATUS_B Register Field Descriptions 2924 16 1107 QUEUE_52_STATUS_C Register Field Descriptions 2925 16 1108 QUEUE_53_STATUS_A Register Fiel...

Page 130: ...s 2968 16 1151 QUEUE_67_STATUS_B Register Field Descriptions 2969 16 1152 QUEUE_67_STATUS_C Register Field Descriptions 2970 16 1153 QUEUE_68_STATUS_A Register Field Descriptions 2971 16 1154 QUEUE_68_STATUS_B Register Field Descriptions 2972 16 1155 QUEUE_68_STATUS_C Register Field Descriptions 2973 16 1156 QUEUE_69_STATUS_A Register Field Descriptions 2974 16 1157 QUEUE_69_STATUS_B Register Fiel...

Page 131: ...s 3017 16 1200 QUEUE_83_STATUS_C Register Field Descriptions 3018 16 1201 QUEUE_84_STATUS_A Register Field Descriptions 3019 16 1202 QUEUE_84_STATUS_B Register Field Descriptions 3020 16 1203 QUEUE_84_STATUS_C Register Field Descriptions 3021 16 1204 QUEUE_85_STATUS_A Register Field Descriptions 3022 16 1205 QUEUE_85_STATUS_B Register Field Descriptions 3023 16 1206 QUEUE_85_STATUS_C Register Fiel...

Page 132: ...9 QUEUE_100_STATUS_A Register Field Descriptions 3067 16 1250 QUEUE_100_STATUS_B Register Field Descriptions 3068 16 1251 QUEUE_100_STATUS_C Register Field Descriptions 3069 16 1252 QUEUE_101_STATUS_A Register Field Descriptions 3070 16 1253 QUEUE_101_STATUS_B Register Field Descriptions 3071 16 1254 QUEUE_101_STATUS_C Register Field Descriptions 3072 16 1255 QUEUE_102_STATUS_A Register Field Desc...

Page 133: ... 3115 16 1298 QUEUE_116_STATUS_B Register Field Descriptions 3116 16 1299 QUEUE_116_STATUS_C Register Field Descriptions 3117 16 1300 QUEUE_117_STATUS_A Register Field Descriptions 3118 16 1301 QUEUE_117_STATUS_B Register Field Descriptions 3119 16 1302 QUEUE_117_STATUS_C Register Field Descriptions 3120 16 1303 QUEUE_118_STATUS_A Register Field Descriptions 3121 16 1304 QUEUE_118_STATUS_B Registe...

Page 134: ... 3164 16 1347 QUEUE_132_STATUS_C Register Field Descriptions 3165 16 1348 QUEUE_133_STATUS_A Register Field Descriptions 3166 16 1349 QUEUE_133_STATUS_B Register Field Descriptions 3167 16 1350 QUEUE_133_STATUS_C Register Field Descriptions 3168 16 1351 QUEUE_134_STATUS_A Register Field Descriptions 3169 16 1352 QUEUE_134_STATUS_B Register Field Descriptions 3170 16 1353 QUEUE_134_STATUS_C Registe...

Page 135: ...QUEUE_148_STATUS_C Register Field Descriptions 3213 16 1396 QUEUE_149_STATUS_A Register Field Descriptions 3214 16 1397 QUEUE_149_STATUS_B Register Field Descriptions 3215 16 1398 QUEUE_149_STATUS_C Register Field Descriptions 3216 16 1399 QUEUE_150_STATUS_A Register Field Descriptions 3217 16 1400 QUEUE_150_STATUS_B Register Field Descriptions 3218 16 1401 QUEUE_150_STATUS_C Register Field Descri...

Page 136: ...FOSTATUS_5 Register Field Descriptions 3263 17 31 FIFOSTATUS_6 Register Field Descriptions 3264 17 32 FIFOSTATUS_7 Register Field Descriptions 3265 17 33 MSGSTATUS_0 Register Field Descriptions 3266 17 34 MSGSTATUS_1 Register Field Descriptions 3267 17 35 MSGSTATUS_2 Register Field Descriptions 3268 17 36 MSGSTATUS_3 Register Field Descriptions 3269 17 37 MSGSTATUS_4 Register Field Descriptions 32...

Page 137: ... 77 LOCK_REG_16 Register Field Descriptions 3328 17 78 LOCK_REG_17 Register Field Descriptions 3329 17 79 LOCK_REG_18 Register Field Descriptions 3330 17 80 LOCK_REG_19 Register Field Descriptions 3331 17 81 LOCK_REG_20 Register Field Descriptions 3332 17 82 LOCK_REG_21 Register Field Descriptions 3333 17 83 LOCK_REG_22 Register Field Descriptions 3334 17 84 LOCK_REG_23 Register Field Descriptions...

Page 138: ...6 Register Field Descriptions 3414 18 34 SD_DATA Register Field Descriptions 3415 18 35 SD_PSTATE Register Field Descriptions 3416 18 36 SD_HCTL Register Field Descriptions 3419 18 37 SD_SYSCTL Register Field Descriptions 3422 18 38 SD_STAT Register Field Descriptions 3424 18 39 SD_IE Register Field Descriptions 3429 18 40 SD_ISE Register Field Descriptions 3432 18 41 SD_AC12 Register Field Descri...

Page 139: ...tions 3513 19 38 FIFO Control Register FCR Field Descriptions 3514 19 39 Line Control Register LCR Field Descriptions 3515 19 40 Modem Control Register MCR Field Descriptions 3516 19 41 UART Line Status Register LSR Field Descriptions 3517 19 42 IrDA Line Status Register LSR Field Descriptions 3518 19 43 CIR Line Status Register LSR Field Descriptions 3519 19 44 Modem Status Register MSR Field Des...

Page 140: ...ister Field Descriptions 3545 19 82 ISR2 Register Field Descriptions 3546 19 83 FREQ_SEL Register Field Descriptions 3547 19 84 Mode Definition Register 3 MDR3 Register Field Descriptions 3548 19 85 TX_DMA_THRESHOLD Register Field Descriptions 3549 20 1 Timer Resolution and Maximum Range 3552 20 2 Timer 0 Connectivity Attributes 3554 20 3 Timer 2 7 Connectivity Attributes 3555 20 4 Timer Clock Sig...

Page 141: ...egister Field Descriptions 3613 20 49 TSICR Register Field Descriptions 3614 20 50 TCAR2 Register Field Descriptions 3615 20 51 TPIR Register Field Descriptions 3616 20 52 TNIR Register Field Descriptions 3617 20 53 TCVR Register Field Descriptions 3618 20 54 TOCR Register Field Descriptions 3619 20 55 TOWR Register Field Descriptions 3620 20 56 RTC Module Connectivity Attributes 3622 20 57 RTC Cl...

Page 142: ...LARM2_YEARS_REG Register Field Descriptions 3667 20 97 RTC_PMIC Register Field Descriptions 3668 20 98 RTC_DEBOUNCE Register Field Descriptions 3669 20 99 Public WD Timer Module Connectivity Attributes 3671 20 100 Public WD Timer Clock Signals 3672 20 101 Watchdog Timer Events 3673 20 102 Count and Prescaler Default Reset Values 3674 20 103 Prescaler Clock Ratio Values 3675 20 104 Reset Period Exa...

Page 143: ... Field Descriptions 3738 21 20 I2C_DMATXENABLE_CLR Register Field Descriptions 3739 21 21 I2C_DMARXWAKE_EN Register Field Descriptions 3740 21 22 I2C_DMATXWAKE_EN Register Field Descriptions 3742 21 23 I2C_SYSS Register Field Descriptions 3744 21 24 I2C_BUF Register Field Descriptions 3745 21 25 I2C_CNT Register Field Descriptions 3747 21 26 I2C_DATA Register Field Descriptions 3748 21 27 I2C_CON ...

Page 144: ...1 Receiver Interrupt Control Register RINTCTL Field Descriptions 3856 22 32 Receiver Status Register RSTAT Field Descriptions 3857 22 33 Current Receive TDM Time Slot Registers RSLOT Field Descriptions 3858 22 34 Receive Clock Check Control Register RCLKCHK Field Descriptions 3859 22 35 Receiver DMA Event Control Register REVTCTL Field Descriptions 3860 22 36 Transmitter Global Control Register XG...

Page 145: ...78 Register Field Descriptions 3939 23 27 NWDAT_X Register Field Descriptions 3940 23 28 NWDAT12 Register Field Descriptions 3941 23 29 NWDAT34 Register Field Descriptions 3942 23 30 NWDAT56 Register Field Descriptions 3943 23 31 NWDAT78 Register Field Descriptions 3944 23 32 INTPND_X Register Field Descriptions 3945 23 33 INTPND12 Register Field Descriptions 3946 23 34 INTPND34 Register Field Des...

Page 146: ...2 24 11 McSPI Revision Register MCSPI_REVISION Field Descriptions 4034 24 12 McSPI System Configuration Register MCSPI_SYSCONFIG Field Descriptions 4035 24 13 McSPI System Status Register MCSPI_SYSSTATUS Field Descriptions 4036 24 14 McSPI Interrupt Status Register MCSPI_IRQSTATUS Field Descriptions 4037 24 15 McSPI Interrupt Enable Register MCSPI_IRQENABLE Field Descriptions 4040 24 16 McSPI Syst...

Page 147: ...88 25 26 GPIO_RISINGDETECT Register Field Descriptions 4089 25 27 GPIO_FALLINGDETECT Register Field Descriptions 4090 25 28 GPIO_DEBOUNCENABLE Register Field Descriptions 4091 25 29 GPIO_DEBOUNCINGTIME Register Field Descriptions 4092 25 30 GPIO_CLEARDATAOUT Register Field Descriptions 4093 25 31 GPIO_SETDATAOUT Register Field Descriptions 4094 26 1 ROM Exception Vectors 4099 26 2 Dead Loops 4099 ...

Page 148: ... Boot in RGMII Mode 4146 26 34 Pins Used for EMAC Boot in RMII Mode 4146 26 35 Ethernet PHY Mode Selection 4147 26 36 Pins Used for UART Boot 4147 26 37 Customized Descriptor Parameters 4148 26 38 Pins Used for USB Boot 4149 26 39 GP Device Image Format 4150 26 40 Booting Parameters Structure 4151 26 41 Tracing Vectors 4153 27 1 Debug Subsystem Registers 4157 27 2 Suspend Control Registers Field D...

Page 149: ...ted documentation and development support tools visit www ti com Cortex is a trademark of ARM Limited ARM is a registered trademark of ARM Limited EtherCAT is a registered trademark of EtherCAT Technology Group USSE is a trademark of Imagination Technologies Ltd POWERVR is a registered trademark of Imagination Technologies Ltd EtherNet IP is a trademark of Open DeviceNet Vendor Association Inc 149...

Page 150: ... EtherCAT EtherCAT PRU ICSS Graphics Accelerator N Y N N Y Y SGX Memory Map Y Y Y Y Y Y Interrupts Y Y Y Y Y Y Memory Subsystem Y Y Y Y Y Y Power and Clock Y Y Y Y Y Y Management PRCM Control Module Y Y Y Y Y Y Interconnects Y Y Y Y Y Y Enhanced Direct Memory Y Y Y Y Y Y Access EDMA Touchscreen Controller Y Y Y Y Y Y LCD Controller Y Y Y Y Y Y Ethernet Subsystem ZCE 1 port ZCE 1 port No ZCE No ZCE...

Page 151: ...ns Bit Field Value Description 31 28 DEVREV Device revision 0000b Silicon Revision 1 0 0001b Silicon Revision 2 0 0010b Silicon Revision 2 1 See device errata for detailed information on functionality in each device revision Reset value is revision dependent 27 12 PARTNUM Device part number 0xB944 11 1 MFGR Manufacturer s ID 0x017 0 Reserved Read always as 0 0x0 1 1 3 Feature Identification The AM...

Page 152: ...0 0 0 0 1 0 0x00FC0382 AM3354 0 0 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0x20FC0382 AM3356 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0x00FD0383 AM3357 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0x00FF0383 AM3358 0 0 1 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0x20FD0383 AM3359 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 ...

Page 153: ...26 1 8 6 1 2 Enumeration Descriptors PG1 0 Product string in USB descriptor is Subarctic PG2 x Product string in USB descriptor is AM335x USB 1 2 4 Added DPLL Power Switch Control and Status Registers See Section 9 3 14 dpll_pwr_sw_status Register and Section 9 3 76 dpll_pwr_sw_ctrl Register PG1 0 DPLL Power Switch Control and Status registers do not exist PG2 x Added DPLL Power Switch Control and...

Page 154: ...et value is 1 1 2 11 Changed the Method of Determining Speed of Operation During EMAC Boot See Section 26 1 8 4 EMAC Boot Procedure and Errata Advisory 1 0 7 PG1 0 Link speed is determined by CONTROL register bit 6 in the external ethernet PHY Note that some PHYs may not update this bit as it is not necessary as described in the 802 3 specification PG2 x Link speed is determined by reading the Aut...

Page 155: ...erved 0x4060_0000 0x407F_FFFF 2MB Reserved Reserved 0x4080_0000 0x4083_FFFF 256KB Reserved Reserved 0x4084_0000 0x40DF_FFFF 5888KB Reserved Reserved 0x40E0_0000 0x40E0_7FFF 32KB Reserved Reserved 0x40E0_8000 0x40EF_FFFF 992KB Reserved Reserved 0x40F0_0000 0x40F0_7FFF 32KB Reserved Reserved 0x40F0_8000 0x40FF_FFFF 992KB Reserved Reserved 0x4100_0000 0x41FF_FFFF 16MB Reserved Reserved 0x4200_0000 0x...

Page 156: ... 1MB EDMA3 Transfer Controller 0 Registers TPTC1 EDMA3TC1 0x4990_0000 0x499F_FFFF 1MB EDMA3 Transfer Controller 1 Registers TPTC2 EDMA3TC2 0x49A0_0000 0x49AF_FFFF 1MB EDMA3 Transfer Controller 2 Registers Reserved 0x49B0_0000 0x49BF_FFFF 1MB Reserved Reserved 0x49C0_0000 0x49FF_FFFF 4MB Reserved L4_FAST 0x4A00_0000 0x4AFF_FFFF 16MB L4_FAST DebugSS 0x4B00_0000 0x4BFF_FFFF 16MB Debug Subsystem regio...

Page 157: ...e Peripheral Registers CM_WKUP 0x44E0_0400 0x44E0_04FF 256 Bytes Clock Module Wakeup Registers CM_DPLL 0x44E0_0500 0x44E0_05FF 256 Bytes Clock Module PLL Registers CM_MPU 0x44E0_0600 0x44E0_06FF 256 Bytes Clock Module MPU Registers CM_DEVICE 0x44E0_0700 0x44E0_07FF 256 Bytes Clock Module Device Registers CM_RTC 0x44E0_0800 0x44E0_08FF 256 Bytes Clock Module RTC Registers CM_GFX 0x44E0_0900 0x44E0_...

Page 158: ... SmartReflex0 0x44E3_7000 0x44E3_7FFF 4KB L3 Registers 0x44E3_8000 0x44E3_8FFF 4KB Reserved SmartReflex1 0x44E3_9000 0x44E3_9FFF 4KB L3 Registers 0x44E3_A000 0x44E3_AFFF 4KB Reserved Reserved 0x44E3_B000 0x44E3_DFFF 12KB Reserved RTCSS 0x44E3_E000 0x44E3_EFFF 4KB RTC Registers 0x44E3_F000 0x44E3_FFFF 4KB Reserved DebugSS 0x44E4_0000 0x44E7_FFFF 256KB Debug Registers Instrumentation HWMaster1 Port ...

Page 159: ... Reserved 0x4803_4000 0x4803_4FFF 4KB Reserved 0x4803_5000 0x4803_5FFF 4KB Reserved Reserved 0x4803_6000 0x4803_6FFF 4KB Reserved 0x4803_7000 0x4803_7FFF 4KB Reserved McASP0 CFG 0x4803_8000 0x4803_9FFF 8KB McASP0 CFG Registers 0x4803_A000 0x4803_AFFF 4KB Reserved Reserved 0x4803_B000 0x4803_BFFF 4KB Reserved McASP1 CFG 0x4803_C000 0x4803_DFFF 8KB McASP1 CFG Registers 0x4803_E000 0x4803_EFFF 4KB Re...

Page 160: ...8KB Reserved 0x4812_0000 0x4812_0FFF 4KB Reserved Reserved 0x4812_1000 0x4812_1FFF 4KB Reserved Reserved 0x4812_2000 0x4812_2FFF 4KB Reserved 0x4812_3000 0x4812_3FFF 4KB Reserved Reserved 0x4812_4000 0x4813_FFFF 112KB Reserved Reserved 0x4814_0000 0x4815_FFFF 128KB Reserved 0x4816_0000 0x4816_0FFF 4K Reserved Reserved 0x4816_1000 0x4817_FFFF 124KB Reserved Reserved 0x4818_0000 0x4818_2FFF 12KB Res...

Page 161: ..._B000 0x481C_BFFF 4KB Reserved DCAN0 0x481C_C000 0x481C_DFFF 8KB DCAN0 Registers 0x481C_E000 0x481C_FFFF 8KB Reserved DCAN1 0x481D_0000 0x481D_1FFF 8KB DCAN1 Registers 0x481D_2000 0x481D_3FFF 8KB Reserved Reserved 0x481D_4000 0x481D_4FFF 4KB Reserved 0x481D_5000 0x481D_5FFF 4KB Reserved Reserved 0x481D_6000 0x481D_6FFF 4KB Reserved 0x481D_7000 0x481D_7FFF 4KB Reserved MMC1 0x481D_8000 0x481D_8FFF ...

Page 162: ...F 16KB Reserved Reserved 0x4832_6000 0x48FF_FFFF 13MB 152KB Reserved Table 2 4 L4 Fast Peripheral Memory Map Device Name Start_address hex End_address hex Size Description L4_Fast configuration 0x4A00_0000 0x4A00_07FF 2KB Address Protection AP 0x4A00_0800 0x4A00_0FFF 2KB Link Agent LA 0x4A00_1000 0x4A00_13FF 1KB Initiator Port IP0 0x4A00_1400 0x4A00_17FF 1KB Reserved 0x4A00_1800 0x4A00_1FFF 2KB Re...

Page 163: ...0 0x4A1A_7FFF 4KB Reserved Reserved 0x4A1A_8000 0x4A1A_9FFF 8KB Reserved 0x4A1A_A000 0x4A1A_AFFF 4KB Reserved Reserved 0x4A1A_B000 0x4A1A_BFFF 4KB Reserved 0x4A1A_C000 0x4A1A_CFFF 4KB Reserved Reserved 0x4A1A_D000 0x4A1A_DFFF 4KB Reserved Reserved 0x4A1A_E000 0x4A1A_FFFF 8KB Reserved 0x4A1B_0000 0x4A1B_0FFF 4KB Reserved Reserved 0x4A1B_1000 0x4A1B_1FFF 4KB Reserved 0x4A1B_2000 0x4A1B_2FFF 4KB Rese...

Page 164: ...U Subsystem This chapter describes the MPU Subsystem for the device Topic Page 3 1 ARM Cortex A8 MPU Subsystem 165 164 ARM MPU Subsystem SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 165: ...l conversion emulation interrupt handling and debug enhancements Cortex A8 is an ARMv7 compatible dual issue in order execution engine with integrated L1 and L2 caches with NEON SIMD Media Processing Unit An Interrupt Controller is included in the MPU subsystem to handle host interrupt requests in the system The MPU subsystem includes CoreSight compliant logic to allow the Debug Sub system access ...

Page 166: ...oreSight Architecture Clock Generation Through PRCM DFT Integrated PBIST controller to test L2 tag and data ram L1I and L1D data ram and OCM RAM 3 1 2 MPU Subsystem Integration The MPU subsystem integrates the following group of submodules ARM Cortex A8 Processor Provides a high processing capability including the NEON technology for mobile multimedia acceleration The ARM communicates through an A...

Page 167: ...ubsystem Figure 3 2 Microprocessor Unit MPU Subsystem Signal Interface 3 1 3 MPU Subsystem Clock and Reset Distribution 3 1 3 1 Clock Distribution The MPU subsystem includes an embedded DPLL which sources the clock for the ARM Cortex A8 processor A clock divider within the subsystem is used for deriving the clocks for other internal modules 167 SPRUH73H October 2011 Revised April 2013 ARM MPU Subs...

Page 168: ...U_INTC_FCLK This clock which is part of the INTC module is half the frequency of the ARM clock ARM_FCLK ICE Crusher Functional Clock ICECRUSHER_FCLK ICE Crusher clocking operates on the APB interface using the ARM core clocking This clock is half the frequency of the ARM clock ARM_FCLK I2Async Clock I2ASYNC_FCLK This clock is half the frequency of the ARM clock ARM_FCLK It matches the OCP interfac...

Page 169: ...are provided by the PRCM and controlled by the clock generator module Figure 3 4 Reset Scheme of the MPU Subsystem Table 3 2 Reset Scheme of the MPU Subsystem Signal Name I O Interface MPU_RST I PRCM NEON_RST I PRCM CORE_RST I PRCM MPU_RSTPWRON I PRCM EMU_RST I PRCM EMU_RSTPWRON I PRCM 169 SPRUH73H October 2011 Revised April 2013 ARM MPU Subsystem Submit Documentation Feedback Copyright 2011 2013 ...

Page 170: ...r and the L2 Cache Auxiliary Control Register are provided see the ARM Technical Reference Manual for a description of these registers Service ID R12 Description 0x100 Write value in R0 to Auxiliary Control Register 0x101 Write value in R0 to Non Secure Access Control Register 0x102 Write value in R0 to L2 Cache Auxiliary Control Register In general the procedure to use these secure monitor call i...

Page 171: ...d by an AXI2OCP bridge to the interrupt controller ROM RAM and 3 asynchronous OCP bridges 128 bits and 64 bits Low interrupt latency Closely coupled INTC to the ARM core with 128 interrupt lines Vectored Interrupt Controller Port Present JTAG based debug Supported via DAP Trace support Supported via TPIU External Coprocessor Not supported 3 1 5 Interrupt Controller The Host ARM Interrupt Controlle...

Page 172: ...are directly aligned with voltage domains and thus can be represented as a cross reference to the different voltage domains Table 3 4 shows the different power domains of the MPU subsystem and the modules inside Table 3 4 Overview of the MPU Subsystem Power Domain Functional Power Domain Physical Power Domain per System Module MPU subsystem domain ARM AXI2OCP I2Asynch Bridge ARM L1 and L2 peripher...

Page 173: ...e MPU Standby status can be checked with PRCM CM_IDLEST_MPU 0 ST_MPU bit For the MPU to be on the core referred here as the device core power must be on Device power management does not allow INTC to go to OFF state when MPU domain is on active or one of retention modes The NEON core has independent power off mode when not in use Enabling and disabling of NEON can be controlled by software CAUTION...

Page 174: ... Transitions The following subsections describe transitions of different power modes for MPU power domain Basic power on reset MPU into standby mode MPU out of standby mode MPU power on from a powered off state 3 1 7 2 1 Basic Power On Reset The power on reset follows the following sequence of operation and is applicable to initial power up and wakeup from device off mode Reset the INTC CORE_RST a...

Page 175: ... of DPLL 3 Initiate an interrupt through the INTC to wake up the ARM core from STANDBYWFI mode 3 1 7 2 4 MPU Power On From a Powered Off State 1 MPU Power On NEON Power On Core Power On INTC should follow the ordered sequence per power switch daisy chain to minimize the peaking of current during power up NOTE The core domain must be on and reset before the MPU can be reset 2 Follow the reset seque...

Page 176: ...on Subsystem PRU ICSS This chapter describes the PRU ICSS for the device Topic Page 4 1 Introduction 177 176 Programmable Real Time Unit and Industrial Communication Subsystem SPRUH73H October 2011 Revised April 2013 PRU ICSS Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 177: ...he next generation PRU PRUSSv2 compared to the AM1x and OMAP L13x Among the interfaces supported by the PRU ICSS are the real time industrial protocols used in master and slave mode such as EtherCAT PROFINET EtherNet IP PROFIBUS POWERLINK SERCOS III NOTE For the availability of EtherCAT in the AM335x family of devices see Table 1 1 Device Features 177 SPRUH73H October 2011 Revised April 2013 Progr...

Page 178: ...ter describes the graphics accelerator for the device Topic Page 5 1 Introduction 179 5 2 Integration 182 5 3 Functional Description 184 178 Graphics Accelerator SGX SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 179: ...d engine incorporating pixel and vertex shader functionality Advanced shader feature set in excess of Microsoft VS3 0 PS3 0 and OpenGL2 0 Industry standard API support Direct3D Mobile OpenGL ES 1 1 and 2 0 OpenVG v1 0 1 Fine grained task switching load balancing and power management Advanced geometry direct memory access DMA driven operation for minimum CPU interaction Programmable high quality im...

Page 180: ... POWERVR SGX architecture and supports a broad range of instructions Single programming model Multithreaded with 16 simultaneous execution threads and up to 64 simultaneous data instances Zero cost swapping in and out of threads Cached program execution model Dedicated pixel processing instructions Dedicated video encode decode instructions SIMD execution unit supporting operations in 32 bit IEEE ...

Page 181: ...facility Dependent texture reads 5 1 4 Unsupported Features There are no unsupported SGX530 features for this device 181 SPRUH73H October 2011 Revised April 2013 Graphics Accelerator SGX Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 182: ...SGX530 Clock and Reset Management The SGX530 uses separate functional and interface clocks The SYSCLK is the clock for the slave interface and runs at the L3F frequency The MEMCLK is the clock for the memories and master interface and also runs at the L3F frequency The CORECLK is the functional clock It can be sourced from either the L3F clock CORE_CLKOUTM4 or from the 192 MHz PER_CLKOUTM2 and can...

Page 183: ... SGX530 Pin List The SGX530 module does not include any external interface pins 183 SPRUH73H October 2011 Revised April 2013 Graphics Accelerator SGX Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 184: ...mmable data sequencer PDS Data master selector DMS Vertex data master VDM Pixel data master PDM General purpose data master USSE Tiling coprocessor Pixel coprocessor Texturing coprocessor Multilevel cache Figure 5 2 shows a block diagram of the SGX cores Figure 5 2 SGX Block Diagram 5 3 2 SGX Elements Description The coarse grain scheduler CGS is the main system controller for the POWERVR SGX arch...

Page 185: ...cache consisting of two modules the main cache and the mux arbiter demux decompression unit MADD The MADD is a wrapper around the main cache module designed to manage and format requests to and from the cache as well as providing Level 0 caching for texture and USSE requests The MADD can accept requests from the PDS USSE and texture address generator modules Arbitration as well as any required tex...

Page 186: ... device Topic Page 6 1 Functional Description 187 6 2 Basic Programming Model 190 6 3 ARM Cortex A8 Interrupts 199 6 4 PWM Events 203 6 5 Interrupt Controller Registers 204 186 Interrupts SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 187: ...rity Sorter FIQ Priority Sorter IRQ Input FIQ Input Processor PENDING_IRQp PENDING_FIQp www ti com Functional Description 6 1 Functional Description The interrupt controller processes incoming interrupts by masking and priority sorting to produce the interrupt signals for the processor to which it is attached Figure 6 1 shows the top level view of interrupt processing NOTE FIQ is not available on ...

Page 188: ...threshold a priority threshold of 0 is treated the same way as priority 1 PRIORITY and PRIORITYTHRESHOLD fields values can be set between 0x0 and 0x7F 0x0 is the highest priority and 0x7F is the lowest priority When priority masking is not necessary a priority threshold value of 0xFF disables the priority threshold mechanism This value is also the reset default for backward compatibility with prev...

Page 189: ...led the standby power is reduced but the IRQ or FIQ interrupt latency increases from four to six functional clock cycles This feature can be enabled dynamically according to the requirements of the device After reset this mode is disabled by default 6 1 4 Error Handling The following accesses will cause an error Privilege violation attempt to access PROTECTION register in user mode or any register...

Page 190: ...erences for the FIQ sequence are shown after a character in the code below 1 One or more unmasked incoming interrupts M_IRQ_n signals are received and IRQ or FIQ outputs IRQ FIQ are not currently asserted 2 If the INTC_ILRm 0 FIQNIRQ bit is cleared to 0 the MPU_INTC_IRQ output signal is generated If the FIQNIRQ bit is set to 1 the MPU_INTC_FIQ output signal is generated 3 The INTC performs the pri...

Page 191: ...NTC_SIR_IRQ INTC_SIR_FIQ register AND R10 R10 ACTIVEIRQ_MASK Apply the mask to get the active IRQ number Jump to relevant subroutine handler LDR PC PC R10 lsl 2 PC base address points this instruction 8 NOP To index the table by the PC Table of handler start addresses word IRQ0handler For IRQ0 of BANK0 word IRQ1handler word IRQ2handler 6 The subroutine handler executes code specific to the periphe...

Page 192: ...only register so no need to write back others bits MOV R0 NEWIRQAGR_MASK NEWFIQAGR_MASK Get the NEWIRQAGR NEWFIQAGR bit position LDR R1 INTC_CONTROL_ADDR STR R0 R1 Write the NEWIRQAGR NEWFIQAGR bit to allow new IRQs FIQ Data Synchronization Barrier MOV R0 0 MCR P15 0 R0 C7 C10 4 restore critical context MSR SPSR R11 Restore the SPSR from R11 LDMFD SP R0 R12 LR Restore working registers and Link re...

Page 193: ...ber N ISR in IRQ FIQ Mode Step 5 Save ARM critical context Identify interrupt source Branch to relevant interrupt subroutine handler Relevant Subroutine Handler in IRQ FIQ Mode Step 6 Handles the event functional procedure Deassert the interrupt M_IRQ_n at SOC peripheral module side ISR in IRQ FIQ Mode Step 7 Allow a new IRQ FIQ at INTC side by setting the NEWIRQAGR NEWFIQAGR bit to 1 Restore ARM ...

Page 194: ...ers 2 Save the INTC_THRESHOLD PRIORITYTHRESHOLD field before modifying it 3 Read the active interrupt priority in the INTC_IRQ_PRIORITY IRQPRIORITY INTC_FIQ_PRIORITY FIQPRIORITY field and write it to the PRIORITYTHRESHOLD 1 field 4 Read the active interrupt number in the INTC_SIR_IRQ 6 0 ACTIVEIRQ INTC_SIR_FIQ 6 0 ACTIVEFIQ field to identify the interrupt source 5 Write 1 to the appropriate INTC_C...

Page 195: ...the IRQ remains active and it is finally processed when the priority threshold falls to a priority sufficiently low to allow it to be processed The precaution of writing to New FIQ Agreement is not required during an IRQ ISR as FIQ sorting is not affected provided all FIQ priorities are higher than all IRQ priorities Step 3 Get the priority of the highest priority active IRQ LDR R1 INTC_IRQ_PRIORI...

Page 196: ..._end Step 1 Read modify write the CPSR to disable IRQs FIQs at ARM side MRS R0 CPSR Read the CPSR ORR R0 R0 0x80 0x40 Set the I F bit MSR CPSR R0 Write it back to disable IRQs Step 2 Restore the INTC_THRESHOLD register from R12 LDR R0 INTC_THRESHOLD_ADDR STR R12 R0 Step 3 Restore critical context MSR SPSR R11 Restore the SPSR from R11 LDMFD SP R0 R12 LR Restore working registers and Link register ...

Page 197: ...t active IRQ priority Set the IRQ priority to priority threshold Identify interrupt source Allow a new IRQ and FIQ at INTC side by setting the NEWIRQAGR and NEWFIQAGR bits to 1 Enable IRQ FIQ at ARM side Jump to relevant ISR handler Relevant Subroutine Handler in IRQ FIQ Mode Handles the event functional procedure Deassert the interrupt M_IRQ_n at SOC peripheral module side ISR in IRQ FIQ Mode All...

Page 198: ...iority The precaution of writing to New FIQ Agreement as well as New IRQ Agreement is not required during an IRQ ISR as FIQ sorting will not be affected provided all FIQ priorities are higher than all IRQ priorities 6 2 5 ARM A8 INTC Spurious Interrupt Handling The spurious flag indicates whether the result of the sorting a window of 10 INTC functional clock cycles after the interrupt assertion is...

Page 199: ...st_intr1_intr_pend exported from PRU ICSS 2 22 PRU_ICSS_EVTOUT2 pr1_host 2 output events pr1_host_intr2_intr_pend exported from PRU ICSS 2 23 PRU_ICSS_EVTOUT3 pr1_host 3 output events pr1_host_intr3_intr_pend exported from PRU ICSS 2 24 PRU_ICSS_EVTOUT4 pr1_host 4 output events pr1_host_intr4_intr_pend exported from PRU ICSS 2 25 PRU_ICSS_EVTOUT5 pr1_host 5 output events pr1_host_intr5_intr_pend e...

Page 200: ...TY DCAN1 dcan_uerr_intr_pend 58 ePWM0_TZINT eHRPWM0 TZ interrupt PWM epwm_tz_intr_pend Subsystem 59 ePWM1_TZINT eHRPWM1 TZ interrupt PWM epwm_tz_intr_pend Subsystem 60 ePWM2_TZINT eHRPWM2 TZ interrupt PWM epwm_tz_intr_pend Subsystem 61 eCAP2INT eCAP2 PWM Subsystem ecap_intr_intr_pend 62 GPIOINT3A GPIO 3 POINTRPEND1 63 GPIOINT3B GPIO 3 POINTRPEND2 64 MMCSD0INT MMCSD0 SINTERRUPTN 65 McSPI0INT McSPI0...

Page 201: ...TRPEND1 97 GPIOINT0B GPIO 0 POINTRPEND2 98 GPIOINT1A GPIO 1 POINTRPEND1 99 GPIOINT1B GPIO 1 POINTRPEND2 100 GPMCINT GPMC gpmc_sinterrupt 101 DDRERR0 EMIF sys_err_intr_pend 102 Reserved 103 Reserved 104 Reserved 105 Reserved 106 Reserved 107 Reserved 108 Reserved 109 Reserved 110 Reserved 111 Reserved 112 TCERRINT0 TPTC0 tptc_erint_pend_po 113 TCERRINT1 TPTC1 tptc_erint_pend_po 114 TCERRINT2 TPTC2 ...

Page 202: ...6 1 ARM Cortex A8 Interrupts continued Int Number Acronym name Source Signal Name 126 Reserved 127 Reserved 202 Interrupts SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 203: ...T2 UART2INT 4 UART3 UART3INT 5 UART4 UART4INT 6 UART5 UART5INT 7 3PGSW 3PGSWRXTHR0 8 3PGSW 3PGSWRXINT0 9 3PGSW 3PGSWTXINT0 10 3PGSW 3PGSWMISC0 11 McASP0 MCATXINT0 12 McASP0 MCARXINT0 13 McASP1 MCATXINT1 14 McASP1 MCARXINT1 15 Reserved Reserved 16 Reserved Reserved 17 GPIO 0 GPIOINT0A 18 GPIO 0 GPIOINT0B 19 GPIO 1 GPIOINT1A 20 GPIO 1 GPIOINT1B 21 GPIO 2 GPIOINT2A 22 GPIO 2 GPIOINT2B 23 GPIO 3 GPIOI...

Page 204: ...3 88h INTC_MIR_CLEAR0 Section 6 5 1 14 8Ch INTC_MIR_SET0 Section 6 5 1 15 90h INTC_ISR_SET0 Section 6 5 1 16 94h INTC_ISR_CLEAR0 Section 6 5 1 17 98h INTC_PENDING_IRQ0 Section 6 5 1 18 9Ch INTC_PENDING_FIQ0 Section 6 5 1 19 A0h INTC_ITR1 Section 6 5 1 20 A4h INTC_MIR1 Section 6 5 1 21 A8h INTC_MIR_CLEAR1 Section 6 5 1 22 ACh INTC_MIR_SET1 Section 6 5 1 23 B0h INTC_ISR_SET1 Section 6 5 1 24 B4h INT...

Page 205: ...SET3 Section 6 5 1 40 F4h INTC_ISR_CLEAR3 Section 6 5 1 41 F8h INTC_PENDING_IRQ3 Section 6 5 1 42 FCh INTC_PENDING_FIQ3 Section 6 5 1 43 100h to INTC_ILR0 to INTC_ILR127 Section 6 5 1 44 2FCh 205 SPRUH73H October 2011 Revised April 2013 Interrupts Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 206: ...d R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Rev R 50h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 4 INTC_REVISION Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h Reads returns 0 7 0 Rev R 50h IP revision 7 4 Major revision 3 0 Minor revision Examples 0x10 for 1 0 0x21 for 2 1 206 Interrupts SPRUH73H Octobe...

Page 207: ... after reset Table 6 5 INTC_SYSCONFIG Register Field Descriptions Bit Field Type Reset Description 4 3 Reserved R 0h Write 0 s for future compatibility Reads returns 0 1 SoftReset R W 0h Software reset Set this bit to trigger a module reset The bit is automatically reset by the hardware During reads it always returns 0 0x0 Read always_Always returns 0 0x1 Read never_never happens 0 Autoidle R W 0h...

Page 208: ...ed 7 6 5 4 3 2 1 0 Reserved ResetDone R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 6 INTC_SYSSTATUS Register Field Descriptions Bit Field Type Reset Description 7 1 Reserved R 0h Reserved for OCP socket status information Read returns 0 0 ResetDone R 0h Internal reset monitoring 0x0 rstOngoing Internal module reset is on going 0x1 rstComp Rese...

Page 209: ...8 17 16 SpuriousIRQ R W 1FFFFFFh 15 14 13 12 11 10 9 8 SpuriousIRQ R W 1FFFFFFh 7 6 5 4 3 2 1 0 SpuriousIRQ ActiveIRQ R W 1FFFFFFh R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 7 INTC_SIR_IRQ Register Field Descriptions Bit Field Type Reset Description 31 7 SpuriousIRQ R W 1FFFFFFh Spurious IRQ flag 6 0 ActiveIRQ R W 0h Active IRQ number 209 SPRUH...

Page 210: ... 19 18 17 16 SpuriousFIQ R 1FFFFFFh 15 14 13 12 11 10 9 8 SpuriousFIQ R 1FFFFFFh 7 6 5 4 3 2 1 0 SpuriousFIQ ActiveFIQ R 1FFFFFFh R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 8 INTC_SIR_FIQ Register Field Descriptions Bit Field Type Reset Description 31 7 SpuriousFIQ R 1FFFFFFh Spurious FIQ flag 6 0 ActiveFIQ R 0h Active FIQ number 210 Interrupts S...

Page 211: ...ad only W1toCl Write 1 to clear bit n value after reset Table 6 9 INTC_CONTROL Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h Write 0 s for future compatibility Reads returns 0 1 NewFIQAgr W 0h Reset FIQ output and enable new FIQ generation 0x0 Write nofun_no function effect 0x1 Write NewFiq_Reset FIQ output and enable new FIQ generation 0 NewIRQAgr W 0h New IRQ ge...

Page 212: ... 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved Protection R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 10 INTC_PROTECTION Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h Write 0 s for future compatibility Reads returns 0 0 Protection R W 0h Protection mode 0x0 ProtMDis Protection mode disable...

Page 213: ... Write 1 to clear bit n value after reset Table 6 11 INTC_IDLE Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h Write 0 s for future compatibility Reads returns 0 1 Turbo R W 0h Input synchroniser clock auto gating 0x0 SyncFree Input synchroniser clock is free running default 0x1 SyncAuto Input synchroniser clock is auto gated based on interrupt input activity 0 Func...

Page 214: ... 17 16 SpuriousIRQflag R 1FFFFFFh 15 14 13 12 11 10 9 8 SpuriousIRQflag R 1FFFFFFh 7 6 5 4 3 2 1 0 SpuriousIRQflag IRQPriority R 1FFFFFFh R 40h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 12 INTC_IRQ_PRIORITY Register Field Descriptions Bit Field Type Reset Description 31 7 SpuriousIRQflag R 1FFFFFFh Spurious IRQ flag 6 0 IRQPriority R 40h Current IRQ ...

Page 215: ...8 17 16 SpuriousFIQflag R 1FFFFFFh 15 14 13 12 11 10 9 8 SpuriousFIQflag R 1FFFFFFh 7 6 5 4 3 2 1 0 SpuriousFIQflag FIQPriority R 1FFFFFFh R 40h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 13 INTC_FIQ_PRIORITY Register Field Descriptions Bit Field Type Reset Description 31 7 SpuriousFIQflag R 1FFFFFFh Spurious FIQ flag 6 0 FIQPriority R 40h Current FIQ...

Page 216: ...3 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 PriorityThreshold R W FFh LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 14 INTC_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h Reads returns 0 7 0 PriorityThreshold R W FFh Priority threshold used values 0x 00 0x1f or 0x 00 0x3f 0xff disables the threshold 216 Interru...

Page 217: ...ster 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Itr R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 15 INTC_ITR0 Register Field Descriptions Bit Field Type Reset Description 31 0 Itr R 0h Interrupt status before masking 217 SPRUH73H October 2011 Revised April 2013 Interrupts Submit Documentation Feedback Copy...

Page 218: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mir R W FFFFFFFFh LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 16 INTC_MIR0 Register Field Descriptions Bit Field Type Reset Description 31 0 Mir R W FFFFFFFFh Interrupt mask 218 Interrupts SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 20...

Page 219: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MirClear W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 17 INTC_MIR_CLEAR0 Register Field Descriptions Bit Field Type Reset Description 31 0 MirClear W 0h Write 1 clears the mask bit to 0 reads return 0 219 SPRUH73H October 2011 Revised April 2013 Interrupts Submit Document...

Page 220: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MirSet W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 18 INTC_MIR_SET0 Register Field Descriptions Bit Field Type Reset Description 31 0 MirSet W 0h Write 1 sets the mask bit to 1 reads return 0 220 Interrupts SPRUH73H October 2011 Revised April 2013 Submit Documentation Fe...

Page 221: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IsrSet R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 19 INTC_ISR_SET0 Register Field Descriptions Bit Field Type Reset Description 31 0 IsrSet R W 0h Reads returns the currently active software interrupts Write 1 sets the software interrupt bits to 1 221 SPRUH73H Oc...

Page 222: ...7 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IsrClear W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 20 INTC_ISR_CLEAR0 Register Field Descriptions Bit Field Type Reset Description 31 0 IsrClear W 0h Write 1 clears the sofware interrupt bits to 0 reads return 0 222 Interrupts SPRUH73H October 2011 Revised April 2013 Submit...

Page 223: ...r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PendingIRQ R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 21 INTC_PENDING_IRQ0 Register Field Descriptions Bit Field Type Reset Description 31 0 PendingIRQ R 0h IRQ status after masking 223 SPRUH73H October 2011 Revised April 2013 Interrupts Submit Documentation F...

Page 224: ...r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PendingFIQ R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 22 INTC_PENDING_FIQ0 Register Field Descriptions Bit Field Type Reset Description 31 0 PendingFIQ R 0h FIQ status after masking 224 Interrupts SPRUH73H October 2011 Revised April 2013 Submit Documentation F...

Page 225: ...ster 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Itr R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 23 INTC_ITR1 Register Field Descriptions Bit Field Type Reset Description 31 0 Itr R 0h Interrupt status before masking 225 SPRUH73H October 2011 Revised April 2013 Interrupts Submit Documentation Feedback Copy...

Page 226: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mir R W FFFFFFFFh LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 24 INTC_MIR1 Register Field Descriptions Bit Field Type Reset Description 31 0 Mir R W FFFFFFFFh Interrupt mask 226 Interrupts SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 20...

Page 227: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MirClear W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 25 INTC_MIR_CLEAR1 Register Field Descriptions Bit Field Type Reset Description 31 0 MirClear W 0h Write 1 clears the mask bit to 0 reads return 0 227 SPRUH73H October 2011 Revised April 2013 Interrupts Submit Document...

Page 228: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MirSet W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 26 INTC_MIR_SET1 Register Field Descriptions Bit Field Type Reset Description 31 0 MirSet W 0h Write 1 sets the mask bit to 1 reads return 0 228 Interrupts SPRUH73H October 2011 Revised April 2013 Submit Documentation Fe...

Page 229: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IsrSet R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 27 INTC_ISR_SET1 Register Field Descriptions Bit Field Type Reset Description 31 0 IsrSet R W 0h Reads returns the currently active software interrupts Write 1 sets the software interrupt bits to 1 229 SPRUH73H Oc...

Page 230: ...7 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IsrClear W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 28 INTC_ISR_CLEAR1 Register Field Descriptions Bit Field Type Reset Description 31 0 IsrClear W 0h Write 1 clears the sofware interrupt bits to 0 reads return 0 230 Interrupts SPRUH73H October 2011 Revised April 2013 Submit...

Page 231: ...r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PendingIRQ R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 29 INTC_PENDING_IRQ1 Register Field Descriptions Bit Field Type Reset Description 31 0 PendingIRQ R 0h IRQ status after masking 231 SPRUH73H October 2011 Revised April 2013 Interrupts Submit Documentation F...

Page 232: ...r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PendingFIQ R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 30 INTC_PENDING_FIQ1 Register Field Descriptions Bit Field Type Reset Description 31 0 PendingFIQ R 0h FIQ status after masking 232 Interrupts SPRUH73H October 2011 Revised April 2013 Submit Documentation F...

Page 233: ...ster 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Itr R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 31 INTC_ITR2 Register Field Descriptions Bit Field Type Reset Description 31 0 Itr R 0h Interrupt status before masking 233 SPRUH73H October 2011 Revised April 2013 Interrupts Submit Documentation Feedback Copy...

Page 234: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mir R W FFFFFFFFh LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 32 INTC_MIR2 Register Field Descriptions Bit Field Type Reset Description 31 0 Mir R W FFFFFFFFh Interrupt mask 234 Interrupts SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 20...

Page 235: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MirClear W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 33 INTC_MIR_CLEAR2 Register Field Descriptions Bit Field Type Reset Description 31 0 MirClear W 0h Write 1 clears the mask bit to 0 reads return 0 235 SPRUH73H October 2011 Revised April 2013 Interrupts Submit Document...

Page 236: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MirSet W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 34 INTC_MIR_SET2 Register Field Descriptions Bit Field Type Reset Description 31 0 MirSet W 0h Write 1 sets the mask bit to 1 reads return 0 236 Interrupts SPRUH73H October 2011 Revised April 2013 Submit Documentation Fe...

Page 237: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IsrSet R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 35 INTC_ISR_SET2 Register Field Descriptions Bit Field Type Reset Description 31 0 IsrSet R W 0h Reads returns the currently active software interrupts Write 1 sets the software interrupt bits to 1 237 SPRUH73H Oc...

Page 238: ...7 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IsrClear W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 36 INTC_ISR_CLEAR2 Register Field Descriptions Bit Field Type Reset Description 31 0 IsrClear W 0h Write 1 clears the sofware interrupt bits to 0 reads return 0 238 Interrupts SPRUH73H October 2011 Revised April 2013 Submit...

Page 239: ...r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PendingIRQ R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 37 INTC_PENDING_IRQ2 Register Field Descriptions Bit Field Type Reset Description 31 0 PendingIRQ R 0h IRQ status after masking 239 SPRUH73H October 2011 Revised April 2013 Interrupts Submit Documentation F...

Page 240: ...r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PendingFIQ R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 38 INTC_PENDING_FIQ2 Register Field Descriptions Bit Field Type Reset Description 31 0 PendingFIQ R 0h FIQ status after masking 240 Interrupts SPRUH73H October 2011 Revised April 2013 Submit Documentation F...

Page 241: ...ster 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Itr R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 39 INTC_ITR3 Register Field Descriptions Bit Field Type Reset Description 31 0 Itr R 0h Interrupt status before masking 241 SPRUH73H October 2011 Revised April 2013 Interrupts Submit Documentation Feedback Copy...

Page 242: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mir R W FFFFFFFFh LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 40 INTC_MIR3 Register Field Descriptions Bit Field Type Reset Description 31 0 Mir R W FFFFFFFFh Interrupt mask 242 Interrupts SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 20...

Page 243: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MirClear W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 41 INTC_MIR_CLEAR3 Register Field Descriptions Bit Field Type Reset Description 31 0 MirClear W 0h Write 1 clears the mask bit to 0 reads return 0 243 SPRUH73H October 2011 Revised April 2013 Interrupts Submit Document...

Page 244: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MirSet W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 42 INTC_MIR_SET3 Register Field Descriptions Bit Field Type Reset Description 31 0 MirSet W 0h Write 1 sets the mask bit to 1 reads return 0 244 Interrupts SPRUH73H October 2011 Revised April 2013 Submit Documentation Fe...

Page 245: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IsrSet R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 43 INTC_ISR_SET3 Register Field Descriptions Bit Field Type Reset Description 31 0 IsrSet R W 0h Reads returns the currently active software interrupts Write 1 sets the software interrupt bits to 1 245 SPRUH73H Oc...

Page 246: ...7 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IsrClear W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 44 INTC_ISR_CLEAR3 Register Field Descriptions Bit Field Type Reset Description 31 0 IsrClear W 0h Write 1 clears the sofware interrupt bits to 0 reads return 0 246 Interrupts SPRUH73H October 2011 Revised April 2013 Submit...

Page 247: ...r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PendingIRQ R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 45 INTC_PENDING_IRQ3 Register Field Descriptions Bit Field Type Reset Description 31 0 PendingIRQ R 0h IRQ status after masking 247 SPRUH73H October 2011 Revised April 2013 Interrupts Submit Documentation F...

Page 248: ...r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PendingFIQ R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 46 INTC_PENDING_FIQ3 Register Field Descriptions Bit Field Type Reset Description 31 0 PendingFIQ R 0h FIQ status after masking 248 Interrupts SPRUH73H October 2011 Revised April 2013 Submit Documentation F...

Page 249: ...3 2 1 0 Priority Reserved FIQnIRQ R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 6 47 INTC_ILR0 to INTC_ILR127 Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h Write 0 s for future compatibility Reads returns 0 7 2 Priority R W 0h Interrupt priority 0 FIQnIRQ R W 0h Interrupt IRQ FiQ mapping 0x0 IntIRQ Interrupt ...

Page 250: ...m This chapter describes the memory subsystem of the device Topic Page 7 1 GPMC 251 7 2 OCMC RAM 398 7 3 EMIF 400 7 4 ELM 476 250 Memory Subsystem SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 251: ... page size of 512 bytes 1K bytes or more Support 512M Bytes maximum addressing capability which can be divided into seven independent chip select with programmable bank size and base address on 16M Bytes 32M Bytes 64M Bytes or 128M Bytes boundary Fully pipelined operation for optimal memory bandwidth usage Support external device clock frequency of 1 2 3 and 4 divider from L3 clock Support program...

Page 252: ... in the GPMC registers the GPMC is able to generate all control signals timing depending on the attached device and access type Given the chip select decoding and its associated configuration registers the GPMC selects the appropriate device type control signals timing Figure 7 1 shows the GPMC functional block diagram The GPMC consists of six blocks Interconnect port interface Address decoder GPM...

Page 253: ...GPMC Figure 7 1 GPMC Block Diagram 7 1 1 3 Unsupported GPMC Features The following module features are not supported in this device Table 7 1 Unsupported GPMC Features Feature Reason Chip Select 7 Not pinned out 32 bit devices Only 16 data lines pinned out WAIT 3 2 Not pinned out All CS regions must use WAIT0 or WAIT1 253 SPRUH73H October 2011 Revised April 2013 Memory Subsystem Submit Documentati...

Page 254: ...is device Figure 7 2 GPMC Integration 7 1 2 1 GPMC Connectivity Attributes The general connectivity attributes for the GPMC module are shown in Table 7 2 Table 7 2 GPMC Connectivity Attributes Attributes Type Power Domain Peripheral Domain Clock Domain PD_PER_L3S_GCLK Reset Signals PER_DOM_RST_N Idle Wakeup Signals Smart Idle Interrupt Requests 1 interrupt to MPU Subsystem GPMCINT DMA Requests 1 D...

Page 255: ...w Also used as Command Latch Enable for NAND protocol memories GPMC_BE1n O Upper Byte Enable active low GPMC_WPn O Write Protect active low GPMC_WAIT 1 0 I External wait signal for NOR and NAND protocol memories GPMC_DIR O GPMC D 15 0 signal direction control Low during transmit for write access data OUT from GPMC to memory High during receive for read access data IN from memory to GPMC 1 GPMC_CLK...

Page 256: ...Not Used Not Used GPMC_A 11 A10 A11 Not Used Not Used Not Used GPMC_A 10 A9 A10 A25 Not Used Not Used GPMC_A 9 A8 A9 A24 Not Used Not Used GPMC_A 8 A7 A8 A23 Not Used Not Used GPMC_A 7 A6 A7 A22 Not Used Not Used GPMC_A 6 A5 A6 A21 Not Used Not Used GPMC_A 5 A4 A5 A20 Not Used Not Used GPMC_A 4 A3 A4 A19 Not Used Not Used GPMC_A 3 A2 A3 A18 Not Used Not Used GPMC_A 2 A1 A2 A17 Not Used Not Used GP...

Page 257: ...ble BE0n Byte Enable latch enable latch enable GPMC_BE1n BE1n BE1n BE1n GPMC_CLK CLK CLK CLK OEn Output OEn Output OEn Output GPMC_OE_REn REn read enable REn read enable Enable Enable Enable GPMC_WAIT0 WAIT0 WAIT0 WAIT0 R B0n ready busy R B0n ready busy GPMC_WAIT1 WAIT1 WAIT1 WAIT1 R B1n ready busy R B1n ready busy GPMC_WEn WEn Write Enable WEn Write Enable WEn Write Enable WEn write enable WEn wr...

Page 258: ...al connections options Figure 7 3 shows a connection between the GPMC and a 16 bit synchronous address data multiplexed or AAD multiplexed but this protocol use less address pins external memory device Figure 7 4 shows a connection between the GPMC and a 16 bit synchronous nonmultiplexed external memory device Figure 7 5 shows a connection between the GPMC and a 8 bit NAND device Figure 7 3 GPMC t...

Page 259: ...pmc_csn 6 0 gpmc_advn_ale gpmc_oen gpmc_wen gpmc_be0n_cle gpmc_be1n gpmc_wpn gpmc_wait 1 0 External device memory D 15 0 ADVn WAIT WEn OEn WPn CEn A 26 0 16 A 27 1 CSn 6 0 ADVn_ALE OEn_REn WEn BE0n_CLE BE0n CLE BE1n BE1n WPn WAIT 1 0 CLK gpmc_clk CLK D 15 0 www ti com GPMC Figure 7 4 GPMC to 16 Bit Non multiplexed Memory Figure 7 5 GPMC to 8 Bit NAND Device 259 SPRUH73H October 2011 Revised April ...

Page 260: ...ests are synchronous burst multiple read or multiple write When neither burst nor page mode is supported by external memory or ASIC devices system burst read or write requests are translated to successive single synchronous or asynchronous accesses single reads or single writes 8 bit wide devices are supported only in single synchronous or single asynchronous read or write mode To simulate a progr...

Page 261: ... and the finite state machine FSM immediately and unconditionally The GPMC_SYSSTATUS 0 RESETDONE bit indicates that the software reset is complete when its value is 1 The software must ensure that the software reset completes before doing GPMC operations 7 1 3 3 3 GPMC Power Management GPMC power is supplied by the CORE power domain and GPMC power management complies with system power management g...

Page 262: ... e_DMA_53 7 1 3 3 6 L3 Slow Interconnect Interface The GPMC L3 Slow interconnect interface is a pipelined interface including an 16 32 bit word write buffer Any system host can issue external access requests through the GPMC The device system can issue the following requests through this interface One 8 bit 16 bit 32 bit interconnect access read write Two incrementing 32 bit interconnect accesses ...

Page 263: ...ct an address address data multiplexed device program the following register fields GPMC_CONFIG1_i 11 10 DEVICETYPE field 00 GPMC_CONFIG1_i 9 8 MUXADDDATA bit 01b To select an address data nonmultiplexed device program the following register fields GPMC_CONFIG1_i 11 10 DEVICETYPE field 00 GPMC_CONFIG1_i 9 8 MUXADDDATA bit 00 7 1 3 3 8 Address Decoder and Chip Select Configuration Addresses are dec...

Page 264: ...ing as described in Figure 7 6 with A0 as the device system byte address line Base address is programmed through the GPMC_CONFIG7_i 5 0 BASEADDRESS bit field The register mask is used to exclude some address lines from the decoding A register mask bit field cleared to 0 suppresses the associated address line from the address comparison incoming address bit line is don t care The register mask valu...

Page 265: ...e device can be interfaced in asynchronous or synchronous mode in single data phase no 8 bit wide device burst mode If the 8 bit wide device is set in the chip select configuration register ReadMultiple and WriteMultiple bit fields are considered don t care and only single accesses are performed A 16 bit wide device can be interfaced in asynchronous or synchronous mode with single or multiple data...

Page 266: ...example asynchronous read page mode the effective access time is a logical AND combination of PAGEBURSTACCESSTIME timing completion and the wait deasserted state Wait monitoring pipelining is also applicable to multiple accesses access within a page WAIT monitored as active freezes the CYCLETIME counter For an access within a page when the CYCLETIME counter is by definition in a lock state WAIT mo...

Page 267: ...ACCESSTIME must be set so that the wait pin is at a valid state two GPMC clock cycles before WRACCESSTIME completes The advance pipelining of the two GPMC clock cycles is the result of the internal synchronization requirements for the WAIT signal WAIT monitored as active freezes the CYCLETIME counter This informs the GPMC that the data bus is not captured by the external device The control signals...

Page 268: ... wait pin monitoring is enabled GPMC_CONFIG1_i 22 WAITREADMONITORING bit the effective access time is a logical AND combination of the RDACCESSTIME timing completion and the WAIT deasserted state detection Depending on the programmed WAITMONITORINGTIME value the wait pin should be at a valid level either asserted or deasserted In the same clock cycle the data is valid if WAITMONITORINGTIME 0 at RD...

Page 269: ...b or 01b 7 1 3 3 8 3 5 Wait Monitoring During a Synchronous Write Access During synchronous accesses with wait pin monitoring enabled the WAITWRITEMONITORING bit the wait pin is captured synchronously with GPMC_CLK using the rising edge of this clock If enabled external wait pin monitoring can be used in combination with WRACCESSTIME to delay the effective memory device GPMC_CLK capture edge Wait ...

Page 270: ...us in high impedance delay The bus turnaround is a time out counter starting after CSn or OEn de assertion time whichever occurs first and delays the next access start cycle time The counter is programmed through the GPMC_CONFIG6_i 3 0 BUSTURNAROUND bit field After a read access to a chip select with a non zero BUSTURNAROUND the next access is delayed until the BUSTURNAROUND delay completes if the...

Page 271: ... New read write access www ti com GPMC Figure 7 9 Read to Read for an Address Data Multiplexed Device On Different CS Without Bus Turnaround CS0n Attached to Fast Device Figure 7 10 Read to Read Write for an Address Data Multiplexed Device On Different CS With Bus Turnaround 271 SPRUH73H October 2011 Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright 2011 2013 Texas Instru...

Page 272: ...LTIPLE 0 or GPMC_CONFIG1_i 28 WRITEMULTIPLE 0 All control signals are kept in their default states during these idle GPMC_FCLK cycles This prevents back to back accesses to the same chip select without idle cycles between accesses 7 1 3 3 8 3 7 3 Idle Cycles Between Accesses to Different Chip Select CYCLE2CYCLEDIFFCSEN CYCLE2CYCLEDELAY Because of the pipelined behavior of the system successive acc...

Page 273: ...7 10 Idle Cycle Insertion Configuration BUSTURN CYCLE2 CYCLE2 First Second Idle Cycle Insertion AROUND Addr Data CYCLE CYCLE Access Access Chip Select Between the Two Timing Multiplexed SAMECSEN DIFFCSEN Type Type Accesses Parameter Parameter Parameter No idle cycles are inserted R W 0 R W Any Any 0 x if the two accesses are well pipelined No idle cycles are inserted R 0 R Same Nonmuxed x 0 if the...

Page 274: ... sent to the external memory device by the GPMC For more information about external device reset see Chapter 8 Power Reset and Clock Management PRCM The PRCM module provides an input pin global_rst_n to the GPMC The global_rst_n pin is activated during device warm reset and cold reset The global_rst_n pin initializes the internal state machine and the internal configuration registers 7 1 3 3 8 3 1...

Page 275: ...mes for read and write accesses To ensure a correct duty cycle of GPMC_CLK between accesses RDCYCLETIME and WRCYCLETIME are expressed in GPMC_FCLK cycles and must be multiples of the GPMC_CLK cycle RDCYCLETIME and WRCYCLETIME bit fields can be set with a granularity of 1 or 2 throught GPMC_CONFIG1_i 4 TIMEPARAGRANULARITY When either RDCYCLETIME or WRCYCLETIME completes if they are not already deas...

Page 276: ...on ADVRDOFFTIME and ADVWROFFTIME can be used to control an address and byte enable valid hold time control after ADVn_ALE de assertion ADVRDOFFTIME and ADVWROFFTIME are applicable to both synchronous and asynchronous modes ADVn_ALE signal transitions as controlled through ADVONTIME ADVRDOFFTIME and ADVWROFFTIME can be delayed by half a GPMC_FCLK period by enabling the GPMC_CONFIG3_i 7 ADVEXTRADELA...

Page 277: ...r setup and hold time relative to GPMC_CLK If enabled OEEXTRADELAY applies to all parameters controlling OEn_REn transitions OEEXTRADELAY must be used carefully to avoid control signal overlap between successive accesses to different chip selects This implies the need to program RDCYCLETIME and WRCYCLETIME to be greater than OEn_REn signal deassertion time including the extra half GPMC_FCLK period...

Page 278: ...lows setup and hold control of control signal assertion time The use of a divided GPMC_CLK allows setup and hold control of control signal assertion and deassertion times When GPMC_CLK runs at the GPMC_FCLK frequency so that GPMC_CLK edge and control signal transitions refer to the same GPMC_FCLK edge the control signal transitions can be delayed by half of a GPMC_FCLK period to provide minimum se...

Page 279: ...PMC_CONFIG1_i 4 TIMEPARAGRANULARITY 7 1 3 3 9 9 1 Page Burst Access Time on Read Access In asynchronous page read mode the delay between successive word captures in a page is controlled through the PAGEBURSTACCESSTIME bit field The PAGEBURSTACCESSTIME parameter must be programmed to the rounded greater value in GPMC_FCLK cycles of the read access time of the attached device In synchronous burst re...

Page 280: ...cess see the descriptions of GPMC_CLK RdAccessTime WrAccessTime and wait pin monitoring For more information about timing parameter settings see the sample timing diagrams in this chapter The address bus and BE 1 0 n are fixed for the duration of a synchronous burst read access but they are updated for each beat of an asynchronous page read access 7 1 3 3 10 1 Asynchronous Access Description This ...

Page 281: ...erates a read access to an address data multiplexed device it drives the address bus until OEn assertion time For details see Section 7 1 3 3 8 2 3 Address bits A 16 1 from a GPMC perspective A 15 0 from an external device perspective are placed on the address data bus and the remaining address bits GPMC_A 25 16 are placed on the address bus The address phase ends at OEn assertion when the DIR sig...

Page 282: ...asserted The end of the access is defined by the GPMC_CONFIG5_i 4 0 RDCYCLETIME parameter In the GPMC when a 16 bit wide device is attached to the controller a 32 bit word write access is split into two 16 bit word write accesses For more information about GPMC access size and type adaptation see Section 7 1 3 3 10 5 Between two successive accesses if a OEn pulse is needed The GPMC_CONFIG6_i 11 8 ...

Page 283: ...see Section 7 1 3 3 8 2 3 The CSn and ADVn signals are controlled in the same way as for asynchronous single read operation on an address data multiplexed device Write enable signal WEn WEn assertion indicates a write cycle WEn assertion time is controlled by the GPMC_CONFIG4_i 19 16 WEONTIME field WEn deassertion time is controlled by the GPMC_CONFIG4_i 28 24 WEOFFTIME field Direction signal DIR ...

Page 284: ...e page access in asynchronous mode is not supported for address data multiplexed devices If GPMC_CONFIG1_i 28 WRITEMULTIPLE is enabled 1 with GPMC_CONFIG1_i 27 WRITETYPE as asynchronous 0 the GPMC processes single asynchronous accesses For accesses on non multiplexed devices see Section 7 1 3 3 10 3 7 1 3 3 10 1 2 Access on Address Address Data AAD Multiplexed Devices 7 1 3 3 10 1 2 1 Asynchronous...

Page 285: ...Address valid signal ADVn ADVn is asserted and deasserted twice during a read transaction ADVn first assertion time is controlled by the GPMC_CONFIG3_i 6 4 ADVAADMUXONTIME field ADVn first deassertion time is controlled by the GPMC_CONFIG3_i 26 24 ADVAADMUXRDOFFTIME field ADVn second assertion time is controlled by the GPMC_CONFIG3_i 3 0 ADVONTIME field ADVn second deassertion time is controlled b...

Page 286: ...VAADMUXONTIME OEAADMUXOFFTIME OEAADMUXONTIME GPMC www ti com 7 1 3 3 10 1 2 3 Asynchronous Single Write Operation on an AAD Multiplexed Device Figure 7 16 shows an asynchronous single write operation on an AAD multiplexed device Figure 7 16 Asynchronous Single Write on an AAD Multiplexed Device 286 Memory Subsystem SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 20...

Page 287: ...irst address phase are driven onto the data bus until OEn deassertion Data is driven onto the address data bus at the clock edge defined by the GPMC_CONFIG6_i 19 16 WRDATAONADMUXBUS parameter 7 1 3 3 10 1 2 4 Asynchronous Multiple Page Read Operation on an AAD Multiplexed Device Write multiple page access in asynchronous mode is not supported for AAD multiplexed devices If GPMC_CONFIG1_i 28 WRITEM...

Page 288: ... 17 A 16 1 D 15 0 WRDATAONADMUXBUS GPMC www ti com 7 1 3 3 10 2 1 Synchronous Single Read Figure 7 17 and Figure 7 18 show a synchronous single read operation with GPMCFCLKDIVIDER equal to 0 and 1 respectively Figure 7 17 Synchronous Single Read GPMCFCLKDIVIDER 0 288 Memory Subsystem SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorp...

Page 289: ...e to CSn assertion CSn deassertion time is controlled by the GPMC_CONFIG2_i 12 8 CSRDOFFTIME field and ensures address hold time to CSn deassertion Address valid signal ADVn ADVn assertion time is controlled by the GPMC_CONFIG3_i 3 0 ADVONTIME field ADVn deassertion time is controlled by the GPMC_CONFIG3_i 12 8 ADVRDOFFTIME field Output enable signal OEn OEn assertion indicates a read cycle OEn as...

Page 290: ... by the GPMC_CONFIG3_i 26 24 ADVAADMUXRDOFFTIME field ADVn second assertion time is controlled by the GPMC_CONFIG3_i 3 0 ADVONTIME field ADVn second deassertion time is controlled by the GPMC_CONFIG3_i 12 8 ADVRDOFFTIME field Output Enable signal OEn is asserted and deasserted twice during a read transaction OEn second assertion indicates a read cycle OEn first assertion time is controlled by the ...

Page 291: ...E PAGEBURSTACCESSTIME PAGEBURSTACCESSTIME www ti com GPMC 7 1 3 3 10 2 2 Synchronous Multiple Burst Read 4 8 16 Word16 Burst With Wraparound Capability Figure 7 19 and Figure 7 20 show a synchronous multiple read operation with GPMCFCLKDivider equal to 0 and 1 respectively Figure 7 19 Synchronous Multiple Burst Read GPMCFCLKDIVIDER 0 291 SPRUH73H October 2011 Revised April 2013 Memory Subsystem Su...

Page 292: ...ad data are provided by the memory device each one or two GPMC_CLK cycles The PAGEBURSTACCESSTIME parameter must be set accordingly with GPMC_CONFIG1_i 1 0 GPMCFCLKDIVIDER and the memory device internal configuration Depending on the device page length the GPMC checks device page crossing during a new burst request and purposely insert initial latency of RDACCESSTIME when required Total access tim...

Page 293: ...single or burst accesses see Figure 7 21 Figure 7 21 Synchronous Single Write on an Address Data Multiplexed Device When the GPMC generates a write access to an address data multiplexed device it drives the data bus with address bits A 16 1 until 19 16 WRDATAONADMUXBUS time First data of the burst is driven on the address data bus at WRDATAONADMUXBUS time 293 SPRUH73H October 2011 Revised April 20...

Page 294: ...e Burst Write Synchronous burst write mode provides synchronous single or consecutive accesses Figure 7 22 shows a synchronous burst write access when the chip select is configured in address data multiplexed mode Figure 7 22 Synchronous Multiple Write Burst Write in Address Data Multiplexed Mode Figure 7 23 shows the same synchronous burst write access when the chip select is configured in addres...

Page 295: ...transactions corresponding to the GPMC_CONFIG5_i 27 24 PAGEBURSTACCESSTIME multiplied by the number of remaining data transactions When the GPMC generates a read access to an address data multiplexed device it drives the address bus until OEn assertion time For details see Section 7 1 3 3 8 2 3 Chip select signal CSn CSn assertion time is controlled by the GPMC_CONFIG2_i 3 0 CSONTIME field and ens...

Page 296: ...is controlled by the GPMC_CONFIG4_i 15 13 OEAADMUXOFFTIME field OEn second assertion time is controlled by the GPMC_CONFIG4_i 3 0 OEONTIME field OEn second deassertion time is controlled by the GPMC_CONFIG4_i 12 8 OEOFFTIME field First write data is driven by the GPMC at GPMC_CONFIG6_i 19 16 WRDATAONADMUXBUS when in address data mux configuration The next write data of the burst is driven on the b...

Page 297: ...le Read on an Address Data Nonmultiplexed Device The 27 bit address is driven onto the address bus A 27 1 and the 16 bit data is driven onto the data bus D 15 0 Read data is latched at GPMC_CONFIG1_5 20 16 RDACCESSTIME completion time The end of the access is defined by the GPMC_CONFIG1_5 4 0 RDCYCLETIME parameter CSn ADVn OEn and DIR signals are controlled in the same way as address data multiple...

Page 298: ...ite operation on a nonmultiplexed device Figure 7 25 Asynchronous Single Write on an Address Data Nonmultiplexed Device The 27 bit address is driven onto the address bus A 27 1 and the 16 bit data is driven onto the data bus D 15 0 CSn ADVn WEn and DIR signals are controlled in the same way as address data multiplexed accesses see Section 7 1 3 3 10 1 1 3 298 Memory Subsystem SPRUH73H October 2011...

Page 299: ...CCESSTIME multiplied by the number of remaining data transactions Read data is latched at GPMC_CONFIG5_i 20 16 RDACCESSTIME completion time The end of the access is defined by the GPMC_CONFIG5_i 4 0 RDCYCLETIME parameter During consecutive accesses the GPMC increments the address after each data read completes Delay between successive read data in the page is controlled by the GPMC_CONFIG5_i 27 24...

Page 300: ...g to the device width the GPMC splits the system burst request into multiple bursts Within the specified 4 8 or 16 word value the ATTACHEDDEVICEPAGELENGTH field value must correspond to the maximum length burst supported by the memory device configured in fixed length burst mode as opposed to continuous burst mode To get optimal performance from memory devices that natively support 16 Word16 lengt...

Page 301: ... These devices do not require additional WAIT signal capability or a minimum CSn high pulse width between consecutive accesses to ensure that the correct internal refresh operation is scheduled 7 1 3 3 12 NAND Access Description NAND 8 bit and 16 bit memory devices using a standard NAND asynchronous address data multiplexing scheme can be supported on any chip select with the appropriate asynchron...

Page 302: ...ents WRAPBURST GPMC_CONFIG1_i 0 No wrap READMULTIPLE GPMC_CONFIG1_i 0 Single access READTYPE GPMC_CONFIG1_i 0 Asynchronous mode WRITEMULTIPLE GPMC_CONFIG1_i 0 Single access WRITETYPE GPMC_CONFIG1_i 0 Asynchronous mode CLKACTIVATIONTIME GPMC_CONFIG1_i 0b00 ATTACHEDDEVICEPAGELENGTH GPMC_CONFIG1_i Don t care Single access mode WAITREADMONITORING GPMC_CONFIG1_i 0 Wait not monitored by GPMC access engi...

Page 303: ..._NAND_COMMAND_i and GPMC_NAND_ADDRESS_i registers are 32 bit word locations which means any 32 bit word or 16 bit word access is split into 4 or 2 byte accesses if an 8 bit wide NAND device is attached For multiple command phase or multiple address phase the software driver can use 32 bit word or 16 bit word access to these registers but it must account for the splitting and little endian ordering...

Page 304: ...arameters WE is controlled by the WEONTIME and WEOFFTIME timing parameters ALE and REn OEn are maintained inactive Figure 7 27 shows the NAND command latch cycle CLE is shared with the BE0n output signal and has an inverted polarity from BE0n The NAND qualifier deals with this During the asynchronous NAND data access cycle BE0n also BE1n must not toggle because it is shared with CLE NAND Flash mem...

Page 305: ...iming parameters ALE is controlled by the ADVONTIME and ADVWROFFTIME timing parameters WEn is controlled by the WEONTIME and WEOFFTIME timing parameters CLE and REn OEn are maintained inactive Figure 7 28 shows the NAND address latch cycle ALE is shared with the ADVn output signal and has an inverted polarity from ADVn The NAND qualifier deals with this During the asynchronous NAND data access cyc...

Page 306: ...cess CSn is controlled by the CSONTIME and CSRDOFFTIME timing parameters REn is controlled by the OEONTIME and OEOFFTIME timing parameters To take advantage of REn high to data invalid minimum timing value the RDACCESSTIME can be set so that data are effectively captured after REn deassertion This allows optimization of NAND read access cycle time completion For optimal timing parameter settings s...

Page 307: ...and programming write access If such write to read transactions are used a minimum CSn high pulse width must be set For this CYCLE2CYCLESAMECSEN and CYCLE2CYCLEDELAY must be set according to the appropriate timing requirement to prevent any timing violation NAND devices usually have an important REn high to data bus in tristate mode This requires a bus turnaround setting BUSTURNAROUND 1 so that th...

Page 308: ...g is so long up to 50 µs that accesses occurring when the ready pin is sampled inactive can stall GPMC access and eventually cause a system time out If a read access to a NAND flash is done using the wait monitoring mode the device is blocked during a page opening and so is the GPMC If the correct settings are used other chip selects can be used while the memory processes the page opening command ...

Page 309: ...accumulation This parity accumulation is either accomplished on the programmed number of bytes or 16 bit words read from the memory device or written to the memory device in stream mode Because the ECC engine includes only one accumulation context it can be allocated to only one chip select at a time through the GPMC_ECC_CONFIG 3 1 ECCCS bit field Even if two CS use different ECC algorithms one th...

Page 310: ...sed for ECC computing accumulation can be selected from between two programmable values The ECCjRESULTSIZE bits j 1 to 9 in the GPMC_ECC_SIZE_CONFIG register select which programmable size value ECCSIZE0 or ECCSIZE1 must be used for this ECC result stored in GPMC_ECCj_RESULT register The ECCSIZE0 and ECCSIZE1 fields allow selection of the number of bytes or 16 bit words used for ECC computation ac...

Page 311: ...bit2 bit1 bit0 bit7 bit5 bit3 bit2 bit1 bit7 bit5 bit3 bit2 bit1 bit7 bit5 bit3 bit1 bit7 bit5 bit3 bit1 bit7 bit5 bit3 bit1 bit7 bit5 bit3 bit1 P1o P2o P2o P1o P1o P1o www ti com GPMC Table 7 12 ECC Enable Settings Bit Field Register Value Comments ECCCS GPMC_ECC_CONFIG 0 3h Selects the chip select where ECC is computed ECC16B GPMC_ECC_CONFIG 0 1 Selects column number for ECC calculation ECCCLEAR...

Page 312: ...0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Row 0 Row 1 Row 2 Row 3 Row 252 Row 253 Row 254 Row 255 P1o P2o P2o P1o P1o P1o P8e P8e P8e P8e P16e P16e bit7 bit5 bit3 bit1 bit7 bit5 bit3 bit1 bit7 bit5 bit3 bit1 bit7 bit5 bit3 bit1 bit7 bit5 bit3 bit1 bit7 bit5 bit3 bit1 bit7 bit5 bit3 bit1 bit7 bit5 bit3 bit1 P1o P2o P2o P1o P1o P1o bit7 bit5 bit3 bit1 bit7 bit5 bit3 bit1 bit7 bit5 bit3 bit1 bit7 bit...

Page 313: ...or the spare area are required Results are stored in the GPMC_ECCj_RESULT registers j 1 to 9 Figure 7 34 ECC Computation for a 512 Byte Data Stream Read or Write 7 1 3 3 12 3 1 4 ECC Comparison and Correction To detect an error the computed ECC result must be XORed with the parity value stored in the spare area of the accessed page If the result of this logical XOR is all 0s no error is detected a...

Page 314: ...bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P1o P1e P1o P1e P1o P1e P1o P1e P2o P2e P2o P2e P4o P4e bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit15 b...

Page 315: ...always written read out in the same order BCH relevant accesses are selected by the GPMCs chip select Each page may hold up to 4 Kbytes of data spare bytes not included This means up to 8 x 512 byte BCH messages Since all the data is written read out first followed by the BCH ECC this means that the BCH engine must be able to hold 8 104 bit remainders or syndromes or smaller 52 bit ones at the sam...

Page 316: ...all follow the following rules Bit endianness within a byte is little endian that is the bytes LS bit is also the lowest degree polynomial parameter a byte b7 b0 with b0 the LS bit represents a segment of polynomial b7 x b6 x b0 x The message is mapped in the NAND starting with the highest order parameters that is in the lowest addresses of a NAND page Byte endianness within the NANDs 16 bit words...

Page 317: ... Offset 4 Bit Most Significant Nibble 4 Bit Less Significant Nibble 1 MSB Nibble S 1 Nibble S 2 2 Nibble S 3 Nibble S 4 S 2 2 Nibble 3 Nibble 2 S 2 1 Nibble 1 Nibble 0 LSB Table 7 17 Misaligned Nibble Mapping of Message in 8 bit NAND 8 Bit Word Byte Offset 4 Bit Most Significant Nibble 4 Bit Less Significant Nibble 1 MSB Nibble S 1 Nibble S 2 2 Nibble S 3 Nibble S 4 S 1 2 2 Nibble 2 Nibble 1 S 1 2...

Page 318: ...S 3 2 4 Nibble 2 Nibble 1 Nibble 4 Nibble 3 S 3 2 2 Nibble 0 LSB Note that many other cases exist than the ones represented above for example where the message does not start on a word boundary 7 1 3 3 12 3 2 4 Memory Mapping of the ECC The ECC or remainder is presented by the BCH module as a single 104 bit or 52 bit little endian vector It is up to the software to fetch those 13 bytes or 6 bytes ...

Page 319: ...12 3 3 For each mode A sequence describes the mode in pseudo language with for each section the size and the buffer used for ECC processing if ON The programmable lengths are size size0 and size1 A checksum condition is given If the checksum condition is not respected for a given mode the modules behavior is unpredictable S is the number of sectors in the page size0 and size1 are the section sizes...

Page 320: ...eat with buffer 0 to S 1 size0 nibbles spare processing ON 1 nibble pad spare processing OFF size1 nibbles spare processing OFF Checksum Spare area size nibbles S size0 1 size1 7 1 3 3 12 3 2 9 Mode 0x2 Page processing sequence Repeat with buffer 0 to S 1 512 byte data processing ON Repeat with buffer 0 to S 1 size0 nibbles spare processing OFF size1 nibbles spare processing ON Checksum Spare area...

Page 321: ...re area size nibbles size0 S 1 size1 7 1 3 3 12 3 2 13 Mode 0x4 Page processing sequence Repeat with buffer 0 to S 1 512 byte data processing ON One time no buffer used size0 nibbles spare processing OFF Repeat with buffer 0 to S 1 size1 nibbles spare processing ON Checksum Spare area size nibbles size0 S size1 7 1 3 3 12 3 2 14 Mode 0x9 Page processing sequence Repeat with buffer 0 to S 1 512 byt...

Page 322: ...ffer 0 to S 1 size0 nibbles spare processing ON Repeat with buffer 0 to S 1 1 nibble padding spare processing OFF size1 nibbles spare processing ON Checksum Spare area size nibbles S size0 1 size1 7 1 3 3 12 3 2 17 Mode 0x6 Page processing sequence Repeat with buffer 0 to S 1 512 byte data processing ON Repeat with buffer 0 to S 1 size0 nibbles spare processing ON Repeat S times no buffer used siz...

Page 323: ...ction Unprotected by the ECC in nibbles E is the size of the ECC itself in nibbles S is the number of Sectors per page 2 in the current diagrams Each time the processing of a BCH block is complete ECC calculation for write encoding syndrome generation for read decoding indicated by red arrows the update pointer is pulsed Note that the processing for block 0 can be the first or the last to complete...

Page 324: ...d Per sector spares Spares not covered by ECC ECC right aligned per sector Sector spares Sector spares Sector spares Sector spares size0 Data0 Data1 Prot0 Ecc0 Prot1 Ecc1 Sector spares Sector spares 0 1 0 1 0 0 inactive inactive 1 1 Write Read 1 10 Mode Size0 Size1 P 1 E P E Per sector spares Spares covered by sector ECC per sector left padded ECC Pad Pad i Sector data Sector data Sector data Sect...

Page 325: ...CC All ECC at the end left padded size0 size1 size1 size0 size1 size1 Data0 Data1 Protected pooled Ecc0 Ecc1 Pooled page spares 0 1 0 1 0 1 inactive 0 Write Read 7 8 P 1 E P E Mode Size0 Size1 Pooled spares Spares covered by ECC0 All ECC at the end left padded Pad Pad 0 i i Ecc0 Ecc1 Pad Pad Sector data Sector data Sector data Sector data Sector data Sector data Sector data Sector data M5 M6 M7 M8...

Page 326: ...ll ECC at the end left padded Prot0 Prot1 1 0 1 0 ECC size0 Data0 Data1 Sector data non ECC spares 0 1 Read 9 SU E Mode Size0 Size1 Per sector spares separate ECC Spares not covered by ECC All ECC at the end left padded ECC Unprot0 Unprot1 inactive Ecc0 Ecc1 Pad Pad 1 1 size1 size1 1 0 i i Sector data Sector data Sector data Sector data Sector data Sector data Sector data M9 M 10 M 11 M 12 0 1 ina...

Page 327: ...e prefetch and write posting engine is a single context engine that can be allocated to only one chip select at a time for a read prefetch or a write posting process The engine does not support atomic command and address phase programming and is limited to linear memory read or write access In consequence it is limited to NAND data stream access The engine relies on the MPU NAND software driver to...

Page 328: ...accessed with Byte 16 bit word or 32 bit word access size according to little endian format even though the FIFO input is 32 bit wide The FIFO control is made easier through the use of interrupts or DMA requests associated with the FIFOTHRESHOLD bit field The GPMC_PREFETCH_STATUS 30 24 FIFOPOINTER field monitors the number of available bytes to be read in prefetch mode or the number of free empty ...

Page 329: ...etion To prevent GPMC stall during this NAND address phase set the STARTENGINE bit field before NAND address phase completion when in synchronized mode The prefetch engine will start when an active to inactive wait signal transition is detected The STARTENGINE bit is automatically cleared on prefetch process completion The prefetch engine issues a read request to fill the FIFO with the amount of d...

Page 330: ...engine is active started and an interrupt is only triggered when COUNTVALUE reaches 0 that is when the prefetch engine automatically goes from an active to an inactive state The number of bytes to be prefetched programmed in TRANSFERCOUNT must be a multiple of the programmed FIFOTHRESHOLD to trigger the correct number of interrupts allowing a deterministic and transparent FIFO control If this guid...

Page 331: ...lid data are available from the FIFO and until the programmed GPMC_PREFETCH_CONFIG2 13 0 TRANSFERCOUNT accesses have been completed The STARTENGINE bit clears automatically when posting completes When all data have been written to the NAND memory device the MPU NAND software driver must issue the second cycle program command and monitor the status for programming process completion The closing pro...

Page 332: ...it is set To clear the interrupt the MPU must clear the TERMINALCOUNTSTATUS bit The TERMINALCOUNTSTATUS bit must always be cleared prior to asserting the TERMINALCOUNTEVENTENABLE bit to clear any out of date logged interrupt event NOTE The COUNTVALUE value is only valid if the write posting engine is active and started and an interrupt is only issued when COUNTVALUE reaches 0 that is when the post...

Page 333: ...pability is limited to the prefetch and write posting engine accesses and MPU accesses to a NAND memory device through the defined chip select memory region or through the GPMC_NAND_DATA_i are never optimized The GPMC_PREFETCH_CONFIG1 27 ENABLEOPTIMIZEDACCESS bit must be set to enable optimized accesses To optimize access time the GPMC_PREFETCH_CONFIG1 30 28 CYCLEOPTIMIZATION field defines the num...

Page 334: ...ed while the prefetch and write posting engine is active priority is given to the new request The request processed thereafter is the prefetch and write posting engine request even if another interconnect request is passed in the mean time The engine keeps control of the bus for an additional number of requests programmed in the GPMC_PREFETCH_CONFIG1 19 16 PFPWWEIGHTEDPRIO bit field Control is the...

Page 335: ... Figure 7 42 shows a programming model top level diagram for the GPMC Each block of the diagram is described in one of the following subsections through a set of registers to configure Table 7 24 and Table 7 25 list each step in the model 335 SPRUH73H October 2011 Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 336: ...s configuration 12 Wait pin configuration 13 Enable chip select 8 NAND chip select configuration 10 ECC engine 9 Read operations asynchronous 9 Write operations asynchronous 11 Prefetch and write posting engine GPMC www ti com Figure 7 42 Programming Model Top Level Diagram 336 Memory Subsystem SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instrum...

Page 337: ...rations Asynchronous See Table 7 34 Read Operations Asynchronous See Table 7 34 ECC Engine See Table 7 35 Prefetch and Write Posting Engine See Table 7 36 Wait Pin Configuration See Table 7 37 Enable Chip Select See Table 7 38 7 1 3 5 GPMC Initialization Table 7 26 describes the settings required to reset the GPMC Table 7 26 Reset GPMC Sub process Name Register Bitfield Value Start a software rese...

Page 338: ... READMULTIPLE x Set a synchronous or asynchronous mode for read GPMC_CONFIG1_i 29 READTYPE x operations Set a single or multiple access for write operations GPMC_CONFIG1_i 28 WRITEMULTIPLE x Set a synchronous or asynchronous mode for write GPMC_CONFIG1_i 27 WRITETYPE x operations Table 7 28 NOR Chip Select Configuration Sub process Name Register Bitfield Value Select the chip select base address G...

Page 339: ...7 34 Asynchronous Read and Write Operations Sub process Name Register Bitfield Value Configure adequate timing parameters in asynchronous See Section 7 1 3 9 modes Table 7 35 ECC Engine Sub process Name Register Bitfield Value Select the ECC result register where the first ECC GPMC_ECC_CONTROL 3 0 ECCPOINTER x computation is stored Only applies to Hamming Write 1 to Clear all ECC result registers ...

Page 340: ...d Sub process Name Register Bitfield Value Enable the ECC computation GPMC_ECC_SIZE_CONFIG 0 ECCENABLE 1 340 Memory Subsystem SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 341: ...in synchronized mode WAITPINSELECTOR Enter a number of clock cycles removed to timing GPMC_PREFETCH_CONFIG1 30 28 parameters For all back to back accesses to the NAND x CYCLEOPTIMIZATION flash but not the first one Enable the prefetch postwite engine GPMC_PREFETCH_CONFIG1 7 ENABLEENGINE 1 Select the number of bytes to be read or written by the GPMC_PREFETCH_CONFIG2 13 0 x engine to the selected ch...

Page 342: ...e Page Burst Burst Access Access Access Access Access Access Access Access GPMC_CONFIG1_i 30 READMULTIPLE 0 1 N S 0 1 GPMC_CONFIG1_i 29 READTYPE 0 0 N S 1 1 GPMC_CONFIG1_i 28 WRITEMULTIPLE 0 N S 0 1 GPMC_CONFIG1_i 27 WRITETYPE 0 N S 1 1 Table 7 40 Access Type Parameters Check List Table Access Type Register Bit Bit Field Name Non Mux Address Data Mux AAD Mux GPMC_CONFIG1_i 9 8 MUXADDDATA 0 2h 1 34...

Page 343: ...ion No Write Access No read access www ti com GPMC 7 1 3 9 GPMC Timing Parameters Figure 7 43 shows a programming model diagram for the NOR interfacing timing parameters Table 7 41 lists bit fields to configure adequate timing parameter in various memory modes Figure 7 43 NOR Interfacing Timing Parameters Diagram 343 SPRUH73H October 2011 Revised April 2013 Memory Subsystem Submit Documentation Fe...

Page 344: ...y y y y GPMC_CONFIG3_i 30 28 ADVAADMUXWROFFTIME y y y y GPMC_CONFIG3_i 26 24 ADVAADMUXRDOFFTIME y y y y y GPMC_CONFIG3_i 6 4 ADVAADMUXONTIME y y y y y y y y GPMC_CONFIG3_i 20 16 ADVWROFFTIME y y y y y y GPMC_CONFIG3_i 12 8 ADVRDOFFTIME y y y y y y y GPMC_CONFIG3_i 7 ADVEXTRADELAY y y y y y y y y y y GPMC_CONFIG3_i 3 0 ADVONTIME y y y y y y y y y y GPMC_CONFIG4_i 15 13 OEAADMUXOFFTIME y y y y y y y...

Page 345: ...d Access Access Access Access multiplexed access Access Access GPMC_CONFIG6_i 11 8 CYCLE2CYCLEDELAY y y y y y y y y y y GPMC_CONFIG6_i 7 CYCLE2CYCLESAMECSEN y y y y y y y y y y GPMC_CONFIG6_i 6 CYCLE2CYCLEDIFFCSEN y y y y y y y y y y GPMC_CONFIG6_i 3 0 BUSTURNAROUND y y y y y y y y y y GPMC_CONFIG7_i 6 CSVALID y y y y y y y y y y 345 SPRUH73H October 2011 Revised April 2013 Memory Subsystem Submit...

Page 346: ...ycle time Write cycle time I ns Delay time GPMC_CSn valid to GPMC_OEn valid J ns Setup time GPMC_AD 15 0 valid to GPMC_OEn invalid K ns Pulse duration GPMC_OEn valid time L ns Cycle time Read cycle time M ns Delay time GPMC_OEn invalid to GPMC_CSn invalid The configuration parameters are calculated through the following formulas A WEOffTime WEOnTime TimeParaGranularity 1 GPMC_FCLK period B WEOnTim...

Page 347: ..._CSn low B ns Delay time address bus valid to GPMC_CLK first edge Delay time GPMC_BE0n_CLE GPMC_BE1n valid to GPMC_CLK first edge C ns Pulse duration GPMC_BE0n_CLE GPMC_BE1n low D ns Delay time GPMC_CLK rising edge to GPMC_BE0n_CLE GPMC_BE1n invalid Delay time GPMC_CLK rising edge to GPMC_ADVn_ALE invalid E ns Delay time GPMC_CLK rising edge to GPMC_CSn invalid Delay time GPMC_CLK rising edge to G...

Page 348: ...GPMCFCLKDIVIDER 0x0 F 0 5 CSEXTRADELAY GPMC_FCLK period Case where GPMCFCLKDIVIDER 0x1 F 0 5 CSEXTRADELAY GPMC_FCLK period when CLKACTIVATIONTIME and CSONTIME are odd or CLKACTIVATIONTIME and CSONTIME are even F 1 0 5 CSEXTRADELAY GPMC_FCLK period otherwise Case where GPMCFCLKDIVIDER 0x2 F 0 5 CSEXTRADELAY GPMC_FCLK period when CSONTIME CLKACTIVATIONTIME is a multiple of 3 F 1 0 5 CSEXTRADELAY GPM...

Page 349: ...XTRADELAY GPMC_FCLK period when ADVONTIME CLKACTIVATIONTIME is a multiple of 3 G 1 0 5 ADVEXTRADELAY GPMC_FCLK period when ADVONTIME CLKACTIVATIONTIME 1 is a multiple of 3 G 2 0 5 ADVEXTRADELAY GPMC_FCLK period when ADVONTIME CLKACTIVATIONTIME 2 is a multiple of 3 For ADVn rising edge ADVn de activated in reading mode Case where 1 0 GPMCFCLKDIVIDER 0x0 G 0 5 ADVEXTRADELAY GPMC_FCLK period Case whe...

Page 350: ...3 For OEn rising edge OEn de activated Case where 1 0 GPMCFCLKDIVIDER 0x0 H 0 5 OEEXTRADELAY GPMC_FCLK period Case where GPMCFCLKDIVIDER 0x1 H 0 5 OEEXTRADELAY GPMC_FCLK period when CLKACTIVATIONTIME and OEOFFTIME are odd or CLKACTIVATIONTIME and OEOFFTIME are even H 1 0 5 OEEXTRADELAY GPMC_FCLK period otherwise Case where GPMCFCLKDIVIDER 0x2 H 0 5 OEEXTRADELAY GPMC_FCLK period when OEOFFTIME CLKA...

Page 351: ... 3 I 2 0 5 WEEXTRADELAY GPMC_FCLK period when WEONTIME CLKACTIVATIONTIME 2 is a multiple of 3 351 SPRUH73H October 2011 Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 352: ...WEOFFTIME CLKACTIVATIONTIME 1 is a multiple of 3 I 2 0 5 WEEXTRADELAY GPMC_FCLK period when WEOFFTIME CLKACTIVATIONTIME 2 is a multiple of 3 For GPMC_ADVn low pulse duration Read operation K ADVRDOFFTIME ADVONTIME TIMEPARAGRANULARITY 1 GPMC_FCLK period Write operation K ADVWROFFTIME ADVONTIME TIMEPARAGRANULARITY 1 GPMC_FCLK period For GPMC_WAIT invalid to first data latching GPMC_CLK edge L WAITMO...

Page 353: ...0n_CLE GPMC_BE1n valid time O ns Delay time GPMC_CSn valid to GPMC_ADVn_ALE valid The configuration parameters are calculated through the following formulas Note that these formulas are not exhaustive GPMC_CSn low pulse For single read A CSRDOFFTIME CSONTIME TIMEPARAGRANULARITY 1 GPMC_FCLK period For burst read A CSRDOFFTIME CSONTIME N 1 PAGEBURSTACCESSTIME TIMEPARAGRANULARITY 1 GPMC_FCLK period w...

Page 354: ... read N RDCYCLETIME TIMEPARAGRANULARITY 1 GPMC_FCLK period For burst read N RDCYCLETIME N 1 PAGEBURSTACCESSTIME TIMEPARAGRANULARITY 1 GPMC_FCLK period where N page burst access number For burst write N WRCYCLETIME N 1 PAGEBURSTACCESSTIME TIMEPARAGRANULARITY 1 GPMC_FCLK period where N page burst access number O WRCYCLETIME N 1 PAGEBURSTACCESSTIME CSONTIME TIMEPARAGRANULARITY 1 0 5 ADVEXTRADELAY CSE...

Page 355: ...xed mode Size 512M bits Data Bus 16 bits wide Speed 104 MHz clock frequency Read access time 80 ns 7 1 4 1 2 Typical GPMC Setup Table 7 45 lists some of the I Os of the GPMC module Table 7 45 GPMC Signals Signal Name I O Description GPMC_FCLK Internal Functional and interface clock Acts as the time reference GPMC_CLK O External clock provided to the external device for synchronous operations GPMC_...

Page 356: ... ti com Figure 7 47 shows the typical connection between the GPMC module and an attached NOR Flash memory Figure 7 47 GPMC Connection to an External NOR Flash Memory The following sections demonstrate how to calculate GPMC parameters for three access types Synchronous burst read Asynchronous read Asynchronous single write 356 Memory Subsystem SPRUH73H October 2011 Revised April 2013 Submit Documen...

Page 357: ...attached device are used to calculate the timing parameters on the GPMC side Read Access time GPMC side Time required to activate the clock read access time requested on the memory side data setup time required for optimal capture of a burst of data Data setup time GPMC side Ensures a good capture of a burst of data as opposed to taking a burst of data out One word of data is processed in one cloc...

Page 358: ...ndmax ClkActivationTime 94 03 9 615 roundmax RdAccessTime ACCESSTIME Ah tIACC DataSetupTime 80 4 415 94 03 9 615 PageBurstAccessTime roundmax tBACC roundmax 5 2 1 PAGEBURSTACCESSTIME 1 101 03 94 03 RdCycleTime AccessTime max tCEZ tOEZ 11 RDCYCLETIME Bh 7 CsOnTime tCES 0 0 CSONTIME 0 CsReadOffTime RdCycleTime 11 CSRDOFFTIME Bh AdvOnTime tAVC 0 0 ADVONTIME 0 AdvRdOffTime tAVD tAVC 12 2 ADVRDOFFTIME ...

Page 359: ... on the memory side the external memory makes the data available to the output bus This is the memory side read access time defined in Table 7 49 the number of clock cycles between the address capture ADVn rising edge and the data valid on the output bus The GPMC requires some hold time to allow the data to be captured correctly and the access to be finished To read the data correctly the GPMC mus...

Page 360: ...ode AccessTime round max tCE 80 9 ACCESSTIME 9h PageBurstAccessTime n a single access RdCycleTime AccessTime 1cycle tOEZ 96 615 11 RDCYCLETIME Bh CsOnTime tCAS 0 0 CSONTIME 0 CsReadOffTime AccessTime 1 cycle 89 615 10 CSRDOFFTIME Ah AdvOnTime tAAVDS 3 1 ADVONTIME 1 AdvRdOffTime tAAVDS tAVDP 9 1 ADVRDOFFTIME 1 OeOnTime AdvRdOffTime OeOnTime 3 for instance OEONTIME 3h multiplexed mode OeOffTime Acce...

Page 361: ...onous Single Write Memory Side AC Characteristics on the Description Duration ns Memory Side tWC Write cycle time 60 tAVDP ADVn low time 6 tWP Write pulse width 25 tWPH Write pulse width high 20 tCS CSn setup time to WEn 3 tCAS CSn setup time to ADVn 0 tAVSC ADVn setup time 3 For asynchronous single write access write cycle time is WrCycleTime WeOffTime AccessCompletion WeOffTime 1 For the AccesCo...

Page 362: ...de Applicable only to AccessTime WAITMONITORING the value is the same as for read access PageBurstAccessTime n a single access WrCycleTime WeOffTime AccessCompletion 57 615 6 WRCYCLETIME 6h CsOnTime tCAS 0 0 CSONTIME 0 CsWrOffTime WeOffTime 1 57 615 6 CSWROFFTIME 6h AdvOnTime tAVSC 3 1 ADVONTIME 1 AdvWrOffTime tAVSC tAVDP 9 1 ADVWROFFTIME 1 WeOnTime tCS 3 1 WEONTIME 1 WeOffTime tCS tWP tWPH 48 5 W...

Page 363: ... interface are other advantages of NAND Table 7 52 summarizes the NAND interface signals level applied to external device or memories Table 7 52 NAND Interface Bus Operations Summary Bus Operation CLE ALE CEn WEn REn WPn Read cmd input H L L RE H x Read add input L H L RE H x Write cmd input H L L RE H H Write add input L H L RE H H Data input L L L RE H H Data output L L L H FE x Busy during read...

Page 364: ...inued Bus Operation CLK ADVn CSn OEn WEn WAIT DQ 15 0 Output disable x x L H H Asserted High Z Standby x x H x x High Z High Z 364 Memory Subsystem SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 365: ... protocols when communicating with external memory or external devices Asynchronous read write access Asynchronous read page access 4 8 16 Word16 Synchronous read write access Synchronous read burst access without wrap capability 4 8 16 Word16 Synchronous read burst access with wrap capability 4 8 16 Word16 7 1 4 2 6 GPMC Features and Settings This section lists GPMC features and settings Supporte...

Page 366: ..._CONFIG5_i 1 Section 7 1 5 15 74h 30h i GPMC_CONFIG6_i 1 Section 7 1 5 16 78h 30h i GPMC_CONFIG7_i 1 Section 7 1 5 17 7Ch 30h i GPMC_NAND_COMMAND_i 1 Section 7 1 5 18 80h 30h i GPMC_NAND_ADDRESS_i 1 Section 7 1 5 19 84h 30h i GPMC_NAND_DATA_i 1 Section 7 1 5 20 1E0h GPMC_PREFETCH_CONFIG1 Section 7 1 5 21 1E4h GPMC_PREFETCH_CONFIG2 Section 7 1 5 22 1ECh GPMC_PREFETCH_CONTROL Section 7 1 5 23 1F0h G...

Page 367: ... W LEGEND R W Read Write R Read only n value after reset Table 7 56 GPMC_SYSCONFIG Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 3 SIDLEMODE Idle mode 0 Force idle An idle request is acknowledged unconditionally 1h No idle An idle request is never acknowledged 2h Smart idle Acknowledgement to an idle request is given based on the internal activity of the module 3h Reser...

Page 368: ...ESETDONE R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 7 57 GPMC_SYSSTATUS Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 RESETDONE Internal reset monitoring R0 Internal module reset in on going R1 Reset completed 368 Memory Subsystem SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorpo...

Page 369: ...n WAIT0 input pin has not been detected W0 WAIT0EDGEDETECTIONSTATUS bit unchanged R1 A transition on WAIT0 input pin has been detected W1 WAIT0EDGEDETECTIONSTATUS bit is reset 7 2 Reserved 0 Reserved 1 TERMINALCOUNTSTATUS Status of the TerminalCountEvent interrupt R0 Indicates that CountValue is greater than 0 W0 TERMINALCOUNTSTATUS bit unchanged R1 Indicates that CountValue is equal to 0 W1 TERMI...

Page 370: ...etection interrupt 0 Wait1EdgeDetection interrupt is masked 1 Wait1EdgeDetection event generates an interrupt if occurs 8 WAIT0EDGEDETECTIONENABLE Enables the Wait0 Edge Detection interrupt 0 Wait0EdgeDetection interrupt is masked 1 Wait0EdgeDetection event generates an interrupt if occurs 7 2 Reserved 0 Reserved 1 TERMINALCOUNTEVENTENABLE Enables TerminalCountEvent interrupt issuing in pre fetch ...

Page 371: ...d 1FFh corresponds to 511 GPMC FCLK cycles 3 1 Reserved 0 Reserved 0 TIMEOUTENABLE Enable bit of the TimeOut feature 0 TimeOut feature is disabled 1 TimeOut feature is enabled 7 1 5 7 GPMC_ERR_ADDRESS The GPMC_ERR_ADDRESS register stores the address of the illegal access when an error occurs Figure 7 57 GPMC_ERR_ADDRESS 31 30 0 Rsvd ILLEGALADD R 0 R W 0 LEGEND R W Read Write R Read only n value af...

Page 372: ...d of the transaction that caused the error 7 5 Reserved 0 Reserved 4 ERRORNOTSUPPADD Not supported Address error 0 No error occurs 1 The error is due to a non supported Address 3 ERRORNOTSUPPMCMD Not supported Command error 0 No error occurs 1 The error is due to a non supported Command 2 ERRORTIMEOUT Time out error 0 No error occurs 1 The error is due to a time out 1 Reserved 0 Reserved 0 ERRORVA...

Page 373: ...n WAIT1 0 WAIT1 active low 1 WAIT1 active high 8 WAIT0PINPOLARITY Selects the polarity of input pin WAIT0 0 WAIT0 active low 1 WAIT0 active high 7 5 Reserved 0 Reserved 4 WRITEPROTECT Controls the WP output pin level 0 WP output pin is low 1 WP output pin is high 3 2 Reserved 0 Reserved 1 LIMITEDADDRESS Limited Address device support 0 No effect GPMC controls all addresses 1 A26 A11 are not modifi...

Page 374: ... Reserved 9 WAIT1STATUS Is a copy of input pin WAIT1 Reset value is WAIT1 input pin sampled at IC reset 0 WAIT1 asserted inactive state 1 WAIT1 de asserted 8 WAIT0STATUS Is a copy of input pin WAIT0 Reset value is WAIT0 input pin sampled at IC reset 0 WAIT0 asserted inactive state 1 WAIT0 de asserted 7 1 Reserved 0 Reserved 0 EMPTYWRITEBUFFERSTATUS Stores the empty status of the write buffer 0 Wri...

Page 375: ...t 0 Synchronous wrapping burst not supported 1 Synchronous wrapping burst supported 30 READMULTIPLE Selects the read single or multiple access 0 single access 1 multiple access burst if synchonous page if asynchronous 29 READTYPE Selects the read mode operation 0 Read Asynchronous 1 Read Synchronous 28 WRITEMULTIPLE Selects the write single or multiple access 0 Single access 1 Multiple access burs...

Page 376: ...Reserved 3h Reserved 11 10 DEVICETYPE Selects the attached device type 0 NOR Flash like asynchronous and synchronous devices 1h Reserved 2h NAND Flash like devices stream mode 3h Reserved 9 8 MUXADDDATA Enables the Address and data multiplexed protocol Reset value is SYSBOOT 11 10 input pin sampled at IC reset for CS 0 and 0 for CS 1 6 0 Non multiplexed attached device 1h AAD multiplexed protocol ...

Page 377: ...esses 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK cycle 1Fh 31 GPMC_FCLK cycles 15 13 Reserved 0 Reserved 12 8 CSRDOFFTIME CS de assertion time from start cycle time for read accesses 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK cycle 1Fh 31 GPMC_FCLK cycles 7 CSEXTRADELAY CS Add Extra Half GPMC FCLK cycle 0 CS i Timing control signal is not delayed 1 CS i Timing control signal is delayed of half GPMC_FCLK clock cyc...

Page 378: ...ycle 7h 7 GPMC_FCLK cycles 27 Reserved 0 Reserved 26 24 ADVAADMUXRDOFFTIME ADV assertion for first address phase when using the AAD Mux protocol 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK cycle 7h 7 GPMC_FCLK cycles 23 21 Reserved 0 Reserved 20 16 ADVWROFFTIME ADV de assertion time from start cycle time for write accesses 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK cycle 1Fh 31 GPMC_FCLK cycles 15 13 Reserved 0 Re...

Page 379: ...n using the AAD Multiplexed protocol 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK cycle 7h 7 GPMC_FCLK cycles 3 0 ADVONTIME ADV assertion time from start cycle time 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK cycle Fh 15 GPMC_FCLK cycles 379 SPRUH73H October 2011 Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 380: ...PMC FCLK cycle 0 WE Timing control signal is not delayed 1 WE Timing control signal is delayed of half GPMC_FCLK clock cycle 22 20 Reserved 0 Reserved 19 16 WEONTIME WE assertion time from start cycle time 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK cycle Fh 15 GPMC_FCLK cycles 15 13 OEAADMUXOFFTIME OE de assertion time for the first address phase in an AAD Multiplexed access 0 0 GPMC_FCLK cycle 1h 1 GPMC_...

Page 381: ... phase in an AAD Multiplexed access 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK cycle 7h 7 GPMC_FCLK cycles 3 0 OEONTIME OE assertion time from start cycle time 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK cycle Fh 15 GPMC_FCLK cycles 381 SPRUH73H October 2011 Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 382: ...E Delay between successive words in a multiple access 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK cycle Fh 15 GPMC_FCLK cycles 23 21 Reserved 0 Reserved 20 16 RDACCESSTIME Delay between start cycle time and first data valid 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK cycle 1Fh 31 GPMC_FCLK cycles 15 13 Reserved 0 Reserved 12 8 WRCYCLETIME Total write cycle time 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK cycle 1Fh 31 GPMC_F...

Page 383: ...pecifies on which GPMC FCLK rising edge the first data of the synchronous burst write is driven in the add data multiplexed bus 15 12 Reserved 0 Reserved 11 8 CYCLE2CYCLEDELAY Chip select high pulse delay between two successive accesses 0 0 GPMC_FCLK cycle 1h 1 GPMC_FCLK cycle Fh 15 GPMC_FCLK cycles 7 CYCLE2CYCLESAMECSEN Add Cycle2CycleDelay between two successive accesses to the same chip select ...

Page 384: ...ed as they create holes in the chip select address space 0 Chip select size of 256 Mbytes 8h Chip select size of 128 Mbytes Ch Chip select size of 64 Mbytes Eh Chip select size of 32 Mbytes Fh Chip select size of 16 Mbytes 7 Reserved 0 Reserved 6 CSVALID Chip select enable reset value is 1 for CS 0 and 0 for CS 1 5 0 CS disabled 1 CS enabled 5 0 BASEADDRESS 0 3Fh Chip select base address CSi base ...

Page 385: ... GPMC_NAND_ADDRESS_i Field Descriptions Bit Field Value Description 31 0 GPMC_NAND_ADDRESS_i 0 FFFF FFFFh Writing data at the GPMC_NAND_ADDRESS_i location places the data as the NAND partial address value on the bus using a regular asynchronous write access 7 1 5 20 GPMC_NAND_DATA_i This register is not a true register just an address location Figure 7 70 GPMC_NAND_DATA_i 31 0 GPMC_NAND_DATA_i R W...

Page 386: ... GPMC_FCLK cycles 27 ENABLEOPTIMIZEDACCESS Enables access cycle optimization 0 Access cycle optimization is disabled 1 Access cycle optimization is enabled 26 24 ENGINECSSELECTOR Selects the CS where Prefetch Postwrite engine is active 0 CS0 1h CS1 2h CS2 3h CS3 4h CS4 5h CS5 6h CS6 7h CS7 23 PFPWENROUNDROBIN Enables the PFPW RoundRobin arbitration 0 Prefetch Postwrite engine round robin arbitrati...

Page 387: ...2h Reserved 3h Reserved 3 SYNCHROMODE Selects when the engine starts the access to CS 0 Engine starts the access to CS as soon as STARTENGINE is set 1 Engine starts the access to CS as soon as STARTENGINE is set AND wait to non wait edge detection on the selected wait pin 2 DMAMODE Selects interrupt synchronization or DMA request synchronization 0 Interrupt synchronization is enabled Only interrup...

Page 388: ...7 1 5 23 GPMC_PREFETCH_CONTROL Figure 7 73 GPMC_PREFETCH_CONTROL 31 16 Reserved R 0 15 1 0 Reserved STARTENGINE R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 7 77 GPMC_PREFETCH_CONTROL Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 STARTENGINE Resets the FIFO pointer and starts the engine R0 Engine is stopped W0 Stops the engine R1 Engine is runni...

Page 389: ...written 23 17 Reserved 0 Reserved 16 FIFOTHRESHOLDSTATUS Set when FIFOPointer exceeds FIFOThreshold value 0 FIFOPointer smaller or equal to FIFOThreshold Writing to this bit has no effect 1 FIFOPointer greater than FIFOThreshold Writing to this bit has no effect 15 14 Reserved 0 Reserved 13 0 COUNTVALUE Number of remaining bytes to be read or to be written by the engine according to the TransferCo...

Page 390: ...error correction t 16 3h Reserved 11 8 ECCWRAPMODE 0 Fh Spare area organization definition for the BCH algorithm See the BCH syndrome parity calculator module functional specification for more details 7 ECC16B Selects an ECC calculated on 16 columns 0 ECC calculated on 8 columns 1 ECC calculated on 16 columns 6 4 ECCTOPSECTOR Number of sectors to process with the BCH algorithm 0 1 sector 512kB pag...

Page 391: ... of the ECC pointer Writes to this field select the ECC result register where the first ECC computation will be stored Writing values not listed disables the ECC engine ECCEnable bit of GPMC_ECC_CONFIG cleared to 0 0 Writing 0 disables the ECC engine ECCENABLE bit of GPMC_ECC_CONFIG cleared to 0 1h ECC result register 1 selected 2h ECC result register 2 selected 3h ECC result register 3 selected 4...

Page 392: ...ytes 2h 6 Bytes 3h 8 Bytes FFh 512 Bytes 21 20 Reserved 0 Reserved 19 12 ECCSIZE0 Defines ECC size 0 0 2 Bytes 1h 4 Bytes 2h 6 Bytes 3h 8 Bytes FFh 512 Bytes 11 9 Reserved 0 Reserved 8 ECC9RESULTSIZE Selects ECC size for ECC 9 result register 0 ECCSIZE0 selected 1 ECCSIZE1 selected 7 ECC8RESULTSIZE Selects ECC size for ECC 8 result register 0 ECCSIZE0 selected 1 ECCSIZE1 selected 6 ECC7RESULTSIZE ...

Page 393: ...elects ECC size for ECC 3 result register 0 ECCSIZE0 selected 1 ECCSIZE1 selected 1 ECC2RESULTSIZE Selects ECC size for ECC 2 result register 0 ECCSIZE0 selected 1 ECCSIZE1 selected 0 ECC1RESULTSIZE Selects ECC size for ECC 1 result register 0 ECCSIZE0 selected 1 ECCSIZE1 selected 393 SPRUH73H October 2011 Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright 2011 2013 Texas ...

Page 394: ...Parity bit 256 23 P128O 0 1 Odd Row Parity bit 128 22 P64O 0 1 Odd Row Parity bit 64 21 P32O 0 1 Odd Row Parity bit 32 20 P16O 0 1 Odd Row Parity bit 16 19 P8O 0 1 Odd Row Parity bit 8 18 P4O 0 1 Odd Column Parity bit 4 17 P2O 0 1 Odd Column Parity bit 2 16 P1O 0 1 Odd Column Parity bit 1 15 12 Reserved 0 Reserved 11 P2048E 0 1 Even Row Parity bit 2048 only used for ECC computed on 512 Bytes 10 P1...

Page 395: ...rite R Read only n value after reset Table 7 84 GPMC_BCH_RESULT1_i Field Descriptions Bit Field Value Description 31 0 BCH_RESULT1_i 0 FFFF FFFFh BCH ECC result bits 32 to 63 7 1 5 31 GPMC_BCH_RESULT2_i Figure 7 81 GPMC_BCH_RESULT2_i 31 0 BCH_RESULT2_i R W 0 LEGEND R W Read Write R Read only n value after reset Table 7 85 GPMC_BCH_RESULT2_i Field Descriptions Bit Field Value Description 31 0 BCH_R...

Page 396: ...ead only n value after reset Table 7 87 GPMC_BCH_SWDATA Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 0 BCH_DATA 0 FFFFh Data to be included in the BCH calculation Only bits 0 to 7 are taken into account if the calculator is configured to use 8 bits data GPMC_ECC_CONFIG 7 ECC16B 0 7 1 5 34 GPMC_BCH_RESULT4_i Figure 7 84 GPMC_BCH_RESULT4_i 31 0 BCH_RESULT4_i R W 0 LEGE...

Page 397: ... FFFFh BCH ECC result bits 160 to 191 7 1 5 36 GPMC_BCH_RESULT6_i Figure 7 86 GPMC_BCH_RESULT6_i 31 0 BCH_RESULT6_i R W 0 LEGEND R W Read Write R Read only n value after reset Table 7 90 GPMC_BCH_RESULT6_i Field Descriptions Bit Field Value Description 31 0 BCH_RESULT6_i 0 FFFF FFFFh BCH ECC result bits 192 to 207 397 SPRUH73H October 2011 Revised April 2013 Memory Subsystem Submit Documentation F...

Page 398: ...ed interface to the L3 interconnect 32 or 64 bit width Initial latency max 2 cycles due to OCP to memory core wrapper Multiple memory bank control based on address MSBs Full OCP IP 2 0 Burst support No wait state 7 2 1 2 Unsupported OCMC RAM Features For this device the OCMC RAM implementation does not support parity 398 Memory Subsystem SPRUH73H October 2011 Revised April 2013 Submit Documentatio...

Page 399: ...omain PD_PER_L3_GCLK Reset Signals PER_DOM_RST_N Idle Wakeup Signals Smart Idle Interrupt Requests None DMA Requests None Physical Address L3 Fast slave port 7 2 2 2 OCMC RAM Clock and Reset Management The OCMC module uses a single clock for the module and its OCP interface Table 7 92 OCMC RAM Clock Signals Clock Signal Max Freq Reference Source Comments prcm_ocmc_clock 200 MHz CORE_CLKOUTM4 pd_pe...

Page 400: ...nks DDR2 1 2 4 and 8 DDR3 1 2 4 and 8 mDDR 1 2 and 4 Supports 256 512 1024 and 2048 word page sizes Supports burst length of 8 sequential burst Write read leveling calibration and data eye training in conjunction with DID Self Refresh and Power Down modes for low power Flexible OCP to DDR address mapping to support Partial Array Self Refresh in LPDDR1 DDR2 and DDR3 Temperature Controlled Self Refr...

Page 401: ...its pinned out Multiple DDR banks Only 1 CS ODT pinned out DDR2 CAS Latency 2 Not supported by DID Hardware leveling Silicon bug Must use software leveling procedure See AM335x ARM Cortex A8 Microprocessors MPUs Silicon Errata literature number SPRZ360 401 SPRUH73H October 2011 Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 402: ...nchronous because synchronization is managed in the EMIF4 internal FIFO EMIF4 is set in asynchronous mode Table 7 95 EMIF Clock Signals Clock Signal Maximum Frequency Reference Source Comments ocp_clk 200 MHz CORE_CLKOUTM4 pd_per_l3_gclk Interface clock From PRCM m_clk 152 MHz DDR PLL CLKOUT 2 pd_per_emif_gclk EMIF functional clock From PRCM 400 MHz DDR PLL CLKOUT clkout_po cmd0_dfi_clk From DDR P...

Page 403: ... 0 I O Complimentary data strobes DDR_DQM 1 0 O Data masks DDR_D 15 0 I O Data DDR_ODT O On die termination DDR_RESETn O DDR device reset DDR_VREF I I O Voltage reference DDR_VTP I VTP compensation pin 403 SPRUH73H October 2011 Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 404: ...DR_DQS 1 0 and DDR_DQSn 1 0 and data mask DDR_DQM 1 0 One chip select signal DDR_CSN0 and one clock enable signal DDR_CKE One on die termination output signals DDR_ODT Figure 7 88 DDR2 3 mDDR Memory Controller Signals Table 7 97 DDR2 3 mDDR Memory Controller Signal Descriptions Pin Description DDR_D 15 0 Bidirectional data bus Input for data reads and output for data writes DDR_A 15 0 External add...

Page 405: ...e muliplier pre divier and post divider to get the desired DDR_CLK frequency For detailed information on DDR PLL see Section 8 1 Power Management and Clock Module PRCM 7 3 3 3 DDR2 3 mDDR Memory Controller Subsytem Overview The DDR2 3 mDDR memory controller can gluelessly interface to most standard DDR2 3 mDDR SDRAM devices and supports such features as self refresh mode and prioritized refresh In...

Page 406: ... Interface To move data efficiently from on chip resources to external DDR2 3 mDDR SDRAM device the DDR2 3 mDDR memory controller makes use of a command FIFO a write data FIFO a return command FIFO and two Read Data FIFOs Purpose of each FIFO is described below Figure 7 90 shows the block diagram of the DDR2 3 mDDR memory controller FIFOs Commands write data and read data arrive at the DDR2 memory...

Page 407: ...FIFO stores all the return transactions that are to be issued to the OCP return interface These include the write status return and the read data return commands There are two Read Data FIFOs that store the read data to be sent to the OCP return interface One Read Data FIFO stores read data from the memory mapped registers and other Read Data FIFO stores read data from external memory 7 3 3 3 2 Da...

Page 408: ...rding the Voltage temperature and process VTP on a chip to be shared with the device s IO drivers Requires a Clock input from the core running at 20MHz or less 56 Clock cycles are needed to guarantee the VTP outputs are initially set after reset is removed Can be used in static or dynamic update mode of operation The VTP controller has internal noise filtering which allows it to control spurious u...

Page 409: ... at the SDRAM the following register can be programmed Data Macro 0 1 Write DQS Slave Ratio Register 256 x command delay DDR_DQS delay DDR_CLK Clock period Aligning ADDR CMD w r t DDR_CLK Aligning DDR_DQ 15 0 w r t DDR_DQS during Write Operation Offset DDR_D 15 0 w r t DDR_DQS during Read Operation Align FIFO WE Window 7 3 3 4 Address Mapping The DDR2 3 mDDR memory controller views external DDR2 3...

Page 410: ...of physical devices or whether the devices are mapped across 1 or 2 DDR2 3 mDDR memory controller chip selects 7 3 3 4 1 Address Mapping when REG_IBANK_POS 0 and REG_EBANK_POS 0 For REG_IBANK_POS 0 and REG_EBANK_POS 0 the effect of address mapping scheme is that as the source address increments across DDR2 3 mDDR memory device page boundaries the DDR2 3 mDDR controller moves onto the same page in ...

Page 411: ...ited to 2 banks However it can still interleave banks between the two chip selects Thus the DDR2 3 mDDR controller can keep a maximum of 16 banks eight internal banks across 2 chip selects open at a time but can only interleave among four of them Table 7 102 OCP Address to DDR2 3 mDDR Address Mapping for REG_IBANK_POS 2 and REG_EBANK_POS 0 Logical Address Bank Address 2 1 Row Address Chip Select B...

Page 412: ...y RSIZE of of bits defined by IBANK of of bits defined by PAGESIZE SDRCR SDRCR SDRCR of SDRCR EBANK 0 0 bits RSIZE 0 9 bits IBANK 0 0 bits PAGESIZE 0 8 bits EBANK 1 1 bit RSIZE 1 10 bits IBANK 1 1 bit PAGESIZE 1 9 bits RSIZE 2 11 bits IBANK 2 2 bits PAGESIZE 2 10 bits RSIZE 3 12 bits IBANK 3 3 bits PAGESIZE 3 11 bits RSIZE 4 13 bits RSIZE 5 14 bits RSIZE 6 15 bits RSIZE 7 16 bits 7 3 3 4 6 Address...

Page 413: ...NK 0 0 bits RSIZE 0 9 bits IBANK 0 0 bits PAGESIZE 0 8 bits EBANK 1 1 bit IBANK 1 0 bits RSIZE 1 10 bits IBANK 1 1 bit PAGESIZE 1 9 bits IBANK 2 1 bit RSIZE 2 11 bits IBANK 2 1 bit PAGESIZE 2 10 bits IBANK 3 2 bits RSIZE 3 12 bits IBANK 3 1 bit PAGESIZE 3 11 bits RSIZE 4 13 bits RSIZE 5 14 bits RSIZE 6 15 bits RSIZE 7 16 bits 7 3 3 4 8 Address Mapping when REG_IBANK_POS 3 and REG_EBANK_POS 1 For R...

Page 414: ...ts the highest priority read from pending reads and the highest priority write from pending writes If two or more commands have the highest priority the memory controller selects the oldest command As a result the memory controller might now have a final read and a final write command The memory controller will pick either the read or the write command depending on the value programmed in the Read...

Page 415: ... allowable memory transfers It is suggested that system level prioritization be set to avoid placing high bandwidth masters on the highest priority levels These bits can be left as FEh unless advanced bandwidth prioritization control is required 7 3 3 5 3 Possible Race Condition A race condition may exist when certain masters write data to the DDR2 3 mDDR memory controller For example if master A ...

Page 416: ... Scheduling The DDR2 3 mDDR memory controller issues autorefresh REFR commands to DDR2 3 mDDR SDRAM devices at a rate defined in the refresh rate REFRESH_RATE bit field in the SDRAM refresh control register SDRFC A refresh interval counter is loaded with the value of the REFRESH_RATE bit field and decrements by 1 each cycle until it reaches zero Once the interval counter reaches zero it reloads wi...

Page 417: ...ount number of DDR clock cycles OCP 0x5 0x0 0x0 Write Data FIFO is full Count number of DDR clock cycles OCP 0x6 0x0 0x0 Read Data FIFO is full Count number of DDR clock cycles OCP 0x7 0x0 0x0 Return Command FIFO is full 0x8 0x0 or 0x1 0x0 or 0x1 Count number of priority elevations Count number of DDR clock cycles that a 0x9 0x0 0x0 command was pending Count number of DDR clock cycles for 0xA 0x0 ...

Page 418: ... Leveling Ramp Control register RDWR_LVL_RMP_CTRL Whenever a pulse is received the memory controller would use the intervals programmed in the Read Write Leveling Ramp Control register until the REG_RDWRLVLINC_RMP_WIN in the Read Write Leveling Ramp Window register expires After the expiration of REG_RDWRLVLINC_RMP_WIN the memory controller switches back to use the intervals programmed in the Read...

Page 419: ...ry controller automatically stops the clocks DDR_CLK to the SDRAM The memory controller maintains DDR_CKE low to maintain the self refresh state When the SDRAM is in self refresh the memory controller services register accesses as normal If the REG_LP_MODE field is set not equal to 2 or an SDRAM access is requested while it is in self refresh and T_CKE 1 cycles have elapsed since the SELF REFRESH ...

Page 420: ...x1 Disable DLL Starts an auto refresh cycle in the next cycle Performs one write incremental leveling Performs read DQS incremental training Performs read data eye incremental training Enters its idle state and can issue any other commands except a write or a read A write or a read will only be issued after T_XSRD 1 clock cycles have elapsed since DDR_CKE is driven high The value of T_XSRD is take...

Page 421: ...h or Power Down mode and REG_DPD_EN field is set to 1 the memory controller will exit those modes and go into deep power down mode When the SDRAM is in deep power down the memory controller services register accesses as normal If the REG_DPD_EN field is set to 0 or an SDRAM access is requested the memory controller will bring the SDRAM out of deep power down Exit sequence for LPDDR1 The memory con...

Page 422: ...external master restores all of the above memory mapped registers The external master restores all of the above memory mapped registers The system can now perform access to the external memory 7 3 3 11 6 EMIF PHY Clock Gating The clock to the DDR2 3 mDDR PHY can be gated off to achieve power saving For more information see the EMIF0 1 Clock Gate Control register EMIF_CLK_GATE 7 3 4 Use Cases For d...

Page 423: ...ACh IRQSTATUS_SYS Section 7 3 5 26 B4h IRQENABLE_SET_SYS Section 7 3 5 27 BCh IRQENABLE_CLR_SYS Section 7 3 5 28 C8h ZQ_CONFIG Section 7 3 5 29 D4h RDWR_LVL_RMP_WIN Read Write Leveling Ramp Window Register Section 7 3 5 30 D8h RDWR_LVL_RMP_CTRL Read Write Leveling Ramp Control Register Section 7 3 5 31 DCh RDWR_LVL_CTRL Read Write Leveling Control Register Section 7 3 5 32 E4h DDR_PHY_CTRL_1 Secti...

Page 424: ...sion R 0h R 3h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 7 111 EMIF_MOD_ID_REV Register Field Descriptions Bit Field Type Reset Description 31 30 reg_scheme R 1h Used to distinguish between old and current schemes 29 28 Reserved R 0h 27 16 reg_module_id R 44h EMIF module ID 15 11 reg_rtl_version R 1h RTL Version 10 8 reg_major_revision R 4h Major Revis...

Page 425: ...hat defines whether the EMIF is in big or little endian mode 0 Little endian 1 Big endian 30 reg_dual_clk_mode R 0h Dual Clock mode Reflects the value on the config_dual_clk_mode port that defines whether the ocp_clk and m_clk are asynchronous 0 ocp_clk m_clk 1 Asynchronous ocp_clk and m_clk 29 reg_fast_init R 0h Fast Init Reflects the value on the config_fast_init port that defines whether the EM...

Page 426: ...the tables for OCP Address to DDR2 3 mDDR Address Mapping 26 24 reg_ddr_term R W 0h DDR2 and DDR3 termination resistor value Set to 0 to disable termination For DDR2 set to 1 for 75 ohm set to 2 for 150 ohm and set to 3 for 50 ohm For DDR3 set to 1 for RZQ 4 set to 2 for RZQ 2 set to 3 for RZQ 6 set to 4 for RZQ 12 and set to 5 for RZQ 8 All other values are reserved 23 reg_ddr2_ddqs R W 0h DDR2 d...

Page 427: ...w bits set to 4 for 13 row bits set to 5 for 14 row bits set to 6 for 15 row bits and set to 7 for 16 row bits This field is only used when reg_ibank_pos field in SDRAM Config register is set to 1 2 or 3 or reg_ebank_pos field in SDRAM Config_2 register is set to 1 6 4 reg_ibank R W 0h Internal Bank setup Defines number of banks inside connected SDRAM devices Set to 0 for 1 bank set to 1 for 2 ban...

Page 428: ...7 114 SDRAM_CONFIG_2 Register Field Descriptions Bit Field Type Reset Description 31 Reserved R 0h 30 Reserved R W 0h Reserved 29 28 Reserved R 0h 27 reg_ebank_pos R W 0h External bank position Set to 0 to assign external bank address bits from lower OCP address as shown in the tables for OCP Address to DDR2 3 mDDR Address Mapping Set to 1 to assign external bank address bits from higher OCP addre...

Page 429: ...Set to 1 for auto Self Refresh enable Set to 0 for manual Self Refresh reference indicated by the reg_srt field A write to this field will cause the EMIF to start the SDRAM initialization sequence 27 Reserved R 0h 26 24 reg_pasr R W 0h Partial Array Self Refresh These bits get loaded into the Extended Mode Register of an LPDDR1 or DDR3 during initialization For LPDDR1 set to 0 for full array set t...

Page 430: ... W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 7 116 SDRAM_REF_CTRL_SHDW Register Field Descriptions Bit Field Type Reset Description 31 16 Reserved R 0h 15 0 reg_refresh_rate_shdw R W 0h Shadow field for reg_refresh_rate This field is loaded into reg_refresh_rate field in SDRAM Refresh Control register when SIdleAck is asserted This register is not auto corrected ...

Page 431: ...inimum number of DDR clock cycles from Activate to Read or Write minus one 20 17 reg_t_wr R W 0h Minimum number of DDR clock cycles from last Write transfer to Pre charge minus one The SDRAM initialization sequence will be started when the value of this field is changed from the previous value and the EMIF is in DDR2 mode 16 12 reg_t_ras R W 0h Minimum number of DDR clock cycles from Activate to P...

Page 432: ... is loaded into reg_t_rcd field in SDRAM Timing 1 register when SIdleAck is asserted 20 17 reg_t_wr_shdw R W 0h Shadow field for reg_t_wr This field is loaded into reg_t_wr field in SDRAM Timing 1 register when SIdleAck is asserted initialization sequence will be started when the value of this field is changed from the previous value and the EMIF is in DDR2 mode 16 12 reg_t_ras_shdw R W 0h Shadow ...

Page 433: ...y command other than a Read command minus one For DDR2 and LPDDR1 this field must satisfy greater of tXP or tCKE 27 25 reg_t_odt R W 0h Minimum number of DDR clock cycles from ODT enable to write data driven for DDR2 and DDR3 reg_t_odt must be equal to tAOND 24 16 reg_t_xsnr R W 0h Minimum number of DDR clock cycles from Self Refresh exit to any command other than a Read command minus one 15 6 reg...

Page 434: ...n SDRAM Timing 2 register when SIdleAck is asserted 27 25 reg_t_odt_shdw R W 0h Shadow field for reg_t_odt This field is loaded into reg_t_odt field in SDRAM Timing 2 register when SIdleAck is asserted 24 16 reg_t_xsnr_shdw R W 0h Shadow field for reg_t_xsnr This field is loaded into reg_t_xsnr field in SDRAM Timing 2 register when SIdleAck is asserted 15 6 reg_t_xsrd_shdw R W 0h Shadow field for ...

Page 435: ...mum number of DDR clock cycles for PHY DLL to unlock A value of N will be equal to N x 128 clocks 27 24 Reserved R 0h 23 21 Reserved R W 0h Reserved 20 15 reg_zq_zqcs R W 0h Number of DDR clock clock cycles for a ZQCS command minus one 14 13 Reserved R W 0h Reserved 12 4 reg_t_rfc R W 0h Minimum number of DDR clock cycles from Refresh or Load Mode to Refresh or Activate minus one 3 0 reg_t_ras_max...

Page 436: ...l_ul_shdw R W 0h Shadow field for reg_t_pdll_ul This field is loaded into reg_t_pdll_ul field in SDRAM Timing 3 register when SIdleAck is asserted 27 24 Reserved R 0h 23 21 Reserved R W 0h Reserved 20 15 reg_zq_zqcs_shdw R W 0h Shadow field for reg_zq_zqcs This field is loaded into reg_zq_zqcs field in SDRAM Timing 3 register when SIdleAck is asserted 14 13 Reserved R W 0h Reserved 12 4 reg_t_rfc_...

Page 437: ...ower Down mode Set to 1 for 16 clocks Set to 2 for 32 clocks Set to 3 for 64 clocks Set to 4 for 128 clocks Set to 5 for 256 clocks Set to 6 for 512 clocks Set to 7 for 1024 clocks Set to 8 for 2048 clocks Set to 9 for 4096 clocks Set to 10 for 8192 clocks Set to 11 for 16384 clocks Set to 12 for 32768 clocks Set to 13 for 65536 clocks Set to 14 for 131072 clocks Set to 15 for 262144 clocks Note A...

Page 438: ...eld at least one dummy read access to SDRAM is required for the new value to take affect 3 0 reg_cs_tim R W 0h Power Management timer for Clock Stop The EMIF will put the external SDRAM in Clock Stop mode after the EMIF is idle for these number of DDR clock cycles and if reg_lp_mode field is set to 1 Set to 0 to immediately enter Clock Stop mode Set to 1 for 16 clocks Set to 2 for 32 clocks Set to...

Page 439: ...ster Field Descriptions Bit Field Type Reset Description 31 12 Reserved R 0h 11 8 reg_pd_tim_shdw R W 0h Shadow field for reg_pd_tim This field is loaded into reg_pd_tim field in Power Management Control register when SIdleAck is asserted 7 4 reg_sr_tim_shdw R W 0h Shadow field for reg_sr_tim This field is loaded into reg_sr_tim field in Power Management Control register when SIdleAck is asserted ...

Page 440: ...R W 0xFF Priority Raise Counter for class of service 1 Number of m_clk cycles after which the EMIF momentarily raises the priority of the class of service 1 commands in the Command FIFO A value of N will be equal to N x 16 clocks 15 8 REG_COS_COUNT_2 R W 0xFF Priority Raise Counter for class of service 2 Number of m_clk cycles after which the EMIF momentarily raises the priority of the class of se...

Page 441: ...rite R Read only W1toCl Write 1 to clear bit n value after reset Table 7 126 Interface Configuration Value 1 Register Field Descriptions Bit Field Type Reset Description 31 30 REG_SYS_BUS_WIDTH R 2 L3 OCP data bus width for a particular configuration 0 32 bit wide 1 64 bit wide 2 128 bit wide 3 256 bit wide 29 16 Reserved R 0 Reserved for future use 15 8 REG_WR_FIFO_DEPTH R 0x14 Write Data FIFO de...

Page 442: ...D R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 7 127 Interface Configuration Value 2 Register Field Descriptions Bit Field Type Reset Description 31 24 Reserved R 0 Reserved for future use 23 16 REG_RREG_FIFO_DEPT R 0x2 Register Read Data FIFO depth for a particular configuration H 15 8 REG_RSD_FIFO_DEPTH R 0x16 SDRAM Read Data FIFO depth for a particular config...

Page 443: ...D R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 7 128 PERF_CNT_1 Register Field Descriptions Bit Field Type Reset Description 31 0 reg_counter1 R 0h 32 bit counter that can be configured as specified in the Performance Counter Config Register and Performance Counter Master Region Select Register 443 SPRUH73H October 2011 Revised April 2013 Memory Subsystem Submit...

Page 444: ...D R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 7 129 PERF_CNT_2 Register Field Descriptions Bit Field Type Reset Description 31 0 reg_counter2 R 0h 32 bit counter that can be configured as specified in the Performance Counter Config Register and Performance Counter Master Region Select Register 444 Memory Subsystem SPRUH73H October 2011 Revised April 2013 Submit...

Page 445: ...reg_cntr2_mconnid_en R W 0h MConnID filter enable for Performance Counter 2 register 30 reg_cntr2_region_en R W 0h Chip Select filter enable for Performance Counter 2 register 29 20 Reserved R 0h 19 16 reg_cntr2_cfg R W 1h Filter configuration for Performance Counter 2 For details see the table titled Filter Configurations for Performance Counters 15 reg_cntr1_mconnid_en R W 0h MConnID filter enab...

Page 446: ...ly W1toCl Write 1 to clear bit n value after reset Table 7 131 PERF_CNT_SEL Register Field Descriptions Bit Field Type Reset Description 31 24 reg_mconnid2 R W 0h MConnID for Performance Counter 2 register 23 18 Reserved R 0h 17 16 reg_region_sel2 R W 0h MAddrSpace for Performance Counter 2 register 15 8 reg_mconnid1 R W 0h MConnID for Performance Counter 1 register 7 2 Reserved R 0h 1 0 reg_regio...

Page 447: ..._total_time R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 7 132 PERF_CNT_TIM Register Field Descriptions Bit Field Type Reset Description 31 0 reg_total_time R 0h 32 bit counter that continuously counts number for m_clk cycles elapsed after EMIF is brought out of reset 447 SPRUH73H October 2011 Revised April 2013 Memory Subsystem Submit Documentation ...

Page 448: ...33 READ_IDLE_CTRL Register Field Descriptions Bit Field Type Reset Description 31 20 Reserved R 0h 19 16 reg_read_idle_len R W 5h The Read Idle Length field determines the minimum size reg_read_idle_len 1 clock cycles of Read Idle window for the read idle detection as well as the force read idle time 15 9 Reserved R 0h 8 0 reg_read_idle_interval R W 0h The Read Idle Interval field determines the m...

Page 449: ...o clear bit n value after reset Table 7 134 READ_IDLE_CTRL_SHDW Register Field Descriptions Bit Field Type Reset Description 31 20 Reserved R 0h 19 16 reg_read_idle_len_shdw R W 5h Shadow field for reg_read_idle_len This field is loaded into reg_read_idle_len field in Read Idle Control register when SIdleAck is asserted 15 9 Reserved R 0h 8 0 reg_read_idle_interval_sh R W 0h Shadow field for reg_r...

Page 450: ...te R Read only W1toCl Write 1 to clear bit n value after reset Table 7 135 IRQSTATUS_RAW_SYS Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 Reserved R W 0h Reserved 1 reg_ta_sys R W 0h Raw status of system OCP interrupt Write 1 to set the raw status mostly for debug Writing a 0 has no effect 0 reg_err_sys R W 0h Raw status of system OCP interrupt Write 1 to set t...

Page 451: ...136 IRQSTATUS_SYS Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 Reserved R W 0h Reserved 1 reg_ta_sys R W 0h Enabled status of system OCP interrupt Write 1 to clear the status after interrupt has been serviced raw status gets cleared i e even if not enabled Writing a 0 has no effect 0 reg_err_sys R W 0h Enabled status of system OCP interrupt Write 1 to clear the...

Page 452: ... 137 IRQENABLE_SET_SYS Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 Reserved R W 0h Reserved 1 reg_en_ta_sys R W 0h Enable set for system OCP interrupt Writing a 1 will enable the interrupt and set this bit as well as the corresponding Interrupt Enable Clear Register Writing a 0 has no effect 0 reg_en_err_sys R W 0h Enable set for system OCP interrupt Writing a...

Page 453: ...8 IRQENABLE_CLR_SYS Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 Reserved R W 0h Reserved 1 reg_en_ta_sys R W 0h Enable clear for system OCP interrupt Writing a 1 will disable the interrupt and clear this bit as well as the corresponding Interrupt Enable Set Register Writing a 0 has no effect 0 reg_en_err_sys R W 0h Enable clear for system OCP interrupt Writing...

Page 454: ...to be ZQ calibrated simultaneously Setting this bit requires both chip selects to have a seerate calibration resistor per device 28 reg_zq_sfexiten R W 0h ZQCL on Self Refresh Active Power Down and Precharge Power Down exit enable Writing a 1 enables the issuing of ZQCL on Self Refresh Active Power Down and Precharge Power Down exit 27 20 Reserved R 0h 19 18 reg_zq_zqinit_mult R W 0h Indicates the...

Page 455: ...REG_RDWRLVLINC_RMP_WIN R LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 7 140 Read Write Leveling Ramp Window Register Field Descriptions Bit Field Type Reset Description 31 13 Reserved R Reserved 12 0 REG_RDWRLVLINC_RM R Incremental leveling ramp window in number of refresh periods P_WIN The value programmed is minus one the required value Refresh period i...

Page 456: ...P_PRE ramp window The value programmed is minus one the required value Refresh period is defined by reg_refresh_rate in SDRAM Refresh Control register 23 16 REG_RDLVLINC_RMP_I R W Incremental read data eye training interval during ramp window NT Number of reg_rdwrlvlinc_rmp_pre intervals between incremental read data eye training A value of 0 will disable incremental read data eye training during ...

Page 457: ...elf clear to 0 30 24 REG_RDWRLVLINC_PR Incremental leveling pre scalar in number of refresh periods E The value programmed is minus one the required value Refresh period is defined by reg_refresh_rate in SDRAM Refresh Control register 23 16 REG_RDLVLINC_INT R W Incremental read data eye training interval Number of reg_rdwrlvlinc_pre intervals between incremental read data eye training A value of 0...

Page 458: ... 0h Reserved 15 reg_phy_rst_n R W 0h Writing a 1 to this bit will hold the PHY macros in reset Writing a 0 will bring PHY macros out of reset 14 Reserved R W 0h Reserved 13 12 reg_phy_idle_local_odt R W 0h Value to drive on the 2 bit local_odt On Die Termination PHY outputs when reg_phy_dynamic_pwrdn_enable is asserted and a read is not in progress and reg_phy_dynamic_pwrdn_enable Typically this i...

Page 459: ...n number of DDR clock cycles The value applied should be equal to the required value minus one The maximum read latency supported by the DDR PHY is equal to CAS latency plus 7 clock cycles The minimum read latency must be equal to CAS latency plus 2 clock cycle 459 SPRUH73H October 2011 Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorpor...

Page 460: ...he IO receiver when not _pwrdn performing a read 0 IO receivers always powered up 1 IO receivers only powered up during a read 19 16 Reserved R W 0h Reserved 15 reg_phy_rst_n R W 0h Writing a 1 to this bit will hold the PHY macros in reset Writing a 0 will bring PHY macros out of reset 14 Reserved R W 0h Reserved 13 12 reg_phy_idle_local_odt R W 0h Value to drive on the 2 bit local_odt PHY outputs...

Page 461: ...M in number of DDR clock cycles The value applied should be equal to the required value minus one The maximum read latency supported by the DDR PHY is equal to CAS latency plus 7 clock cycles The minimum read latency must be equal to CAS latency plus 2 clock cycle 461 SPRUH73H October 2011 Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incor...

Page 462: ...e 13 12 REG_PRI_6_COS R W Class of service for commands with priority of 6 Value can be 1 or 2 Setting a value of 0 or 3 will not assign any class of service 11 10 REG_PRI_5_COS R W Class of service for commands with priority of 5 Value can be 1 or 2 Setting a value of 0 or 3 will not assign any class of service 9 8 REG_PRI_4_COS R W Class of service for commands with priority of 4 Value can be 1 ...

Page 463: ...vice 1 mapping MAP_EN Set 0 to disable mapping 30 23 REG_CONNID_1_COS_1 R W Connection ID value 1 for class of service 1 22 20 REG_MSK_1_COS_1 R W Mask for connection ID value 1 for class of service 1 0 disable masking 1 mask connection ID bit 0 2 mask connection ID bits 1 0 3 mask connection ID bits 2 0 4 mask connection ID bits 3 0 5 mask connection ID bits 4 0 6 mask connection ID bits 5 0 7 ma...

Page 464: ...ype Reset Description 31 REG_CONNID_COS_2_ R W Set 1 to enable connection ID to class of service 2 mapping MAP_EN Set 0 to disable mapping 30 23 REG_CONNID_1_COS_2 R W Connection ID value 1 for class of service 2 22 20 REG_MSK_1_COS_2 R W Mask for connection ID Value 1 for class of service 2 0 disable masking 1 mask connection ID bit 0 2 mask connection ID bits 1 0 3 mask connection ID bits 2 0 4 ...

Page 465: ...scription 1 0 REG_MSK_3_COS_2 R W Mask for connection ID Value 3 for class of service 2 0 disable masking 1 mask connection ID bit 0 2 mask connection ID bits 1 0 3 mask connection ID bits 2 0 465 SPRUH73H October 2011 Revised April 2013 Memory Subsystem Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 466: ...reset Table 7 148 Read Write Execution Threshold Register Field Descriptions Bit Field Type Reset Description 31 13 Reserved R Reserved 12 8 REG_WR_THRSH R W Write Threshold Number of SDRAM write bursts after which the EMIF arbitration will switch to executing read commands The value programmed is always minus one the required number 7 5 Reserved R Reserved 4 0 REG_RD_THRSH R W Read Threshold Numb...

Page 467: ...and 0x0 0x060 1 Invert Clockout Selection Register CMD2_REG_PHY_CTRL_SLAVE_RATIO_0 W DDR PHY Command 0x80 0x084 2 Address Command Slave Ratio Register CMD2_REG_PHY_DLL_LOCK_DIFF_0 W DDR PHY Command 0x4 0x090 2 Address Command DLL Lock Difference Register CMD2_REG_PHY_INVERT_CLKOUT_0 W DDR PHY Command 0x0 0x094 2 Invert Clockout Selection Register DATA0_REG_PHY_RD_DQS_SLAVE_RATIO W DDR PHY Data Mac...

Page 468: ...eling Init Ratio Register DATA1_REG_PHY_WRLVL_INIT_MODE_0 W DDR PHY Data Macro 0x0 0x19C 1 Write Leveling Init Mode Ratio Selection Register DATA1_REG_PHY_GATELVL_INIT_RATIO_0 W DDR PHY Data Macro 0x0 0x1A0 1 DQS Gate Training Init Ratio Register DATA1_REG_PHY_GATELVL_INIT_MODE_0 W DDR PHY Data Macro 0x0 0x1A8 1 DQS Gate Training Init Mode Ratio Selection Register DATA1_REG_PHY_FIFO_WE_SLAVE_RATI ...

Page 469: ...be scaled by this number over 256 to get the delay value for the slave delay line 7 3 6 2 DDR PHY Command 0 1 2 Address Command DLL Lock Difference Register CMD0 1 2_REG_PHY_DLL_LOCK_DIFF_0 The DDR PHY Command 0 1 2 Address Command DLL Lock Difference Register CMD0 1 2_REG_PHY_DLL_LOCK_DIFF_0 is shown in the figure and table below Figure 7 130 DDR PHY Command 0 1 2 Address Command DLL Lock Differe...

Page 470: ...O_0 The DDR PHY Data Macro 0 1 Read DQS Slave Ratio Register DATA0 1_REG_PHY_RD_DQS_SLAVE_RATIO_0 is shown in the figure and table below Figure 7 132 DDR PHY Data Macro 0 1 Read DQS Slave Ratio Register DATA0 1_REG_PHY_RD_DQS_SLAVE_RATIO_0 31 i 19 16 Reserved Reserved R 0h R 0h 15 10 9 0 Reserved RD_DQS_SLAVE_RATIO_CS0 R 0h W 40h LEGEND R W Read Write R Read only n value after reset Table 7 153 DD...

Page 471: ...cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line 7 3 6 6 DDR PHY Data Macro 0 1 Write Leveling Init Ratio Register DATA0 1_REG_PHY_WRLVL_INIT_RATIO_0 The DDR PHY Data Macro 0 1 Write Leveling Init Ratio Register DATA0 1_REG_PHY_WRLVL_INIT_RATIO_0 is showin in the figure and table below Figure 7 133 DDR PHY Data Macro 0 1 Wri...

Page 472: ...o value based in register DATA0 1_REG_PHY_WRLVL_INIT_RATIO_0 value programmed by the user 7 3 6 8 DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register DATA0_REG_PHY_GATELVL_INIT_RATIO_0 The DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register DATA0_REG_PHY_GATELVL_INIT_RATIO_0 is shown in the figure and table below Figure 7 135 DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register...

Page 473: ...value based on Write Leveling of the same data slice 1 selects a starting ratio value based on DATA0 1_REG_PHY_GATELVL_INIT_RATIO_0 value programmed by the user 7 3 6 10 DDR PHY Data Macro 0 1 DQS Gate Slave Ratio Register DATA0 1_REG_PHY_FIFO_WE_SLAVE_RATIO_0 The DDR PHY Data Macro 0 1 DQS Gate Slave Ratio Register DATA0 1_REG_PHY_FIFO_WE_SLAVE_RATIO_0 is shown in the figure and table below Figur...

Page 474: ...ue after reset Table 7 161 DDR PHY Data Macro 0 1 Write Data Slave Ratio Register DATA0 1_REG_PHY_WR_DATA_SLAVE_RATIO_0 Field Descriptions Bit Field Value Description 31 20 Reserved 40h Reserved 19 10 Reserved 0 9 0 WR_DATA_SLAVE_RATIO_CS0 40h Ratio value for write data slave DLL for CS0 This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of ...

Page 475: ... W Read Write R Read only n value after reset Table 7 162 DDR PHY Data Macro 0 1 Delay Selection Register DATA0 1_REG_PHY_USE_RANK0_DELAYS Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 PHY_USE_RANK Delay Selection 0_DELAYS_0 0 Each Rank uses its own delay Recommended This is applicable only in case of DDR3 1 Rank 0 delays are used for all ranks This must be set to 1 for...

Page 476: ... supported The ELM relies on a static and fixed definition of the generator polynomial for each error correction level that corresponds to the generator polynomials defined in the GPMC there are three fixed polynomial for the three correction error levels A larger number of errors than the programmed error correction level may be detected but the ELM cannot correct them all The offending block is ...

Page 477: ...error locations outputs Figure 7 140 ELM Integration 7 4 2 1 ELM Connectivity Attributes The general connectivity for the ELM module in this device is summarized in Table 7 163 Table 7 163 ELM Connectivity Attributes Attributes Type Power Domain Peripheral Domain Clock Domain L4PER_L4LS_GCLK Reset Signals PER_DOM_RST_N Idle Wakeup Signals Smart Idle Interrupt Requests 1 interrupt to MPU Subsystem ...

Page 478: ...aster Standby modes N A Global Wake up Enable N A Wake up Sources Enable N A CAUTION The PRCM module has no hardware means of reading CLOCKACTIVITY settings Thus software must ensure consistent programming between the ELM CLOCKACTIVITY and ELM clock PRCM control bits 7 4 3 3 ELM Interrupt Requests Table 7 166 lists the event flags and their masks that can cause module interrupts Table 7 166 Events...

Page 479: ... 1 when in page mode The CPU initiates error location processing by writing a syndrome polynomial into one of the eight possible register sets Each of these register sets includes seven registers ELM_SYNDROME_FRAGMENT_0_i to ELM_SYNDROME_FRAGMENT_6_i The first six registers can be written in any order but ELM_SYNDROME_FRAGMENT_6_i must be written last because it includes the validity bit which ins...

Page 480: ...re available a round robin arbitration is used to select one for processing In continuous mode that is all bits in ELM_PAGE_CTRL are reset an interrupt is triggered whenever a ELM_IRQSTATUS i LOC_VALID_i bit is asserted The CPU must read the ELM_IRQSTATUS register to determine which polynomial is processed and retrieve the exit status and error locations ELM_LOCATION_STATUS_i and ELM_ERROR_LOCATIO...

Page 481: ..._5_i Set value ELM_SYNDROME_FRAGMENT_6_i Set value Initiates the computation process ELM_SYNDROME_FRAGMENT_6_i 16 0x1 SYNDROME_VALID 7 4 4 1 2 Read Results The engine goes through the entire error location process and results can be read Table 7 169 and Table 7 170 describe the processing completion for continuous and page modes respectively Table 7 169 ELM Processing Completion for Continuous Mod...

Page 482: ...S_i 4 0 ECC_NB_ERRORS Read the error location bit addresses for syndrome ELM_ERROR_LOCATION_0_i 12 0 polynomial i of the ECC_NB_ERRORS first ECC_ERROR_LOCATION registers ELM_ERROR_LOCATION_1_i 12 0 ECC_ERROR_LOCATION ELM_ERROR_LOCATION_15_i 12 0 ECC_ERROR_LOCATION endif End Repeat Clear the ELM_IRQSTATUS register ELM_IRQSTATUS 0x1FF Next page can be correctly processed after a page is fully proces...

Page 483: ... Read the number of errors ELM_LOCATION_STATUS_i 4 0 ECC_NB_ERRORS i 0 0x4 Four errors detected Read the error location bit addresses for syndrome ELM_ERROR_LOCATION_0_i i 0 0x1AF polynomial 0 of the 4 first registers ELM_ERROR_LOCATION_1_i i 0 0x426 Errors are located in the data buffer at decimal ELM_ERROR_LOCATION_2_i i 0 0x775 addresses 431 1062 1909 3452 ELM_ERROR_LOCATION_3_i i 0 0xD7C Clear...

Page 484: ...pped is bit 4 from the 49th byte read from memory It is up to the processor to correctly map this word to the copied buffer and to flip this bit The same process must be repeated for all detected errors 7 4 4 3 Use Case ELM Used in Page Mode In this example the ELM module is programmed for an 16 bit error correction capability in page mode After reading a 528 byte NAND flash sector 512B data plus ...

Page 485: ...put syndrome polynomial 3 ELM_SYNDROME_FRAGMENT_0_i i 3 0x0 ELM_SYNDROME_FRAGMENT_1_i i 3 0x0 ELM_SYNDROME_FRAGMENT_2_i i 3 0x0 ELM_SYNDROME_FRAGMENT_3_i i 3 0x0 ELM_SYNDROME_FRAGMENT_4_i i 3 0x0 ELM_SYNDROME_FRAGMENT_5_i i 3 0x0 ELM_SYNDROME_FRAGMENT_6_i i 3 0x0 Initiates the computation process for syndrome ELM_SYNDROME_FRAGMENT_6_i 16 0x1 polynomial 0 SYNDROME_VALID i 0 Initiates the computatio...

Page 486: ...STATUS_i 4 0 ECC_NB_ERRORS 0x1 polynomial 2 i 2 1 error detected Read the number of errors for syndrome ELM_LOCATION_STATUS_i 4 0 ECC_NB_ERRORS 0x0 polynomial 3 i 3 0 errors detected Read the error location bit addresses for syndrome ELM_ERROR_LOCATION_0_i i 0 0x1FE polynomial 0 of the 4 first registers ELM_ERROR_LOCATION_1_i i 0 0x617 ELM_ERROR_LOCATION_2_i i 0 0x650 ELM_ERROR_LOCATION_3_i i 0 0x...

Page 487: ...SYNDROME_FRAGMENT_1_i ELM_SYNDROME_FRAGMENT_1_i Section 7 4 5 9 40h i Register 408h ELM_SYNDROME_FRAGMENT_2_i ELM_SYNDROME_FRAGMENT_2_i Section 7 4 5 10 40h i Register 40Ch ELM_SYNDROME_FRAGMENT_3_i ELM_SYNDROME_FRAGMENT_3_i Section 7 4 5 11 40h i Register 410h ELM_SYNDROME_FRAGMENT_4_i ELM_SYNDROME_FRAGMENT_4_i Section 7 4 5 12 40h i Register 414h ELM_SYNDROME_FRAGMENT_5_i ELM_SYNDROME_FRAGMENT_5...

Page 488: ... ELM_SYSCONFIG Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 CLOCKACTIVITY OCP Clock activity when module is in IDLE mode during wake up mode period OCP 0 OCP Clock can be switch off 1 OCP Clock is maintained during wake up period 7 5 Reserved 0 Reserved 4 3 SIDLEMODE Slave interface power management IDLE req ack control 0 FORCE Idle IDLE request is acknowledged uncondi...

Page 489: ...er reset Table 7 177 ELM System Status Register ELM_SYSSTATUS Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 RESETDONE Internal reset monitoring OCP domain Undefined since From hardware perspective the reset state is 0 From software user perspective when the accessible module is 1 0 Reset is on going 1 Reset is done completed 489 SPRUH73H October 2011 Revised April 2013 ...

Page 490: ...ear interrupt 7 LOC_VALID_7 Error location status for syndrome polynomial 7 0 Read No syndrome processed or process in progress 1 Read Error location process completed 0 Write No effect 1 Write Clear interrupt 6 LOC_VALID_6 Error location status for syndrome polynomial 6 0 Read No syndrome processed or process in progress 1 Read Error location process completed 0 Write No effect 1 Write Clear inte...

Page 491: ...C_VALID_1 Error location status for syndrome polynomial 1 0 Read No syndrome processed or process in progress 1 Read Error location process completed 0 Write No effect 1 Write Clear interrupt 0 LOC_VALID_0 Error location status for syndrome polynomial 0 0 Read No syndrome processed or process in progress 1 Read Error location process completed 0 Write No effect 1 Write Clear interrupt 491 SPRUH73H...

Page 492: ...nomial 7 0 Disable interrupt 1 Enable interrupt 6 LOCATION_MASK_6 Error location interrupt mask bit for syndrome polynomial 6 0 Disable interrupt 1 Enable interrupt 5 LOCATION_MASK_5 Error location interrupt mask bit for syndrome polynomial 5 0 Disable interrupt 1 Enable interrupt 4 LOCATION_MASK_4 Error location interrupt mask bit for syndrome polynomial 4 0 Disable interrupt 1 Enable interrupt 3...

Page 493: ... Write R Read only n value after reset Table 7 180 ELM Location Configuration Register ELM_LOCATION_CONFIG Field Descriptions Bit Field Value Description 31 27 Reserved 0 Reserved 26 16 ECC_SIZE 0 7FFh Maximum size of the buffers for which the error location engine is used in number of nibbles 4 bits entities 15 2 Reserved 0 Reserved 1 0 ECC_BCH_LEVEL Error correction level 0 4 bits 1h 8 bits 2h 1...

Page 494: ...if syndrome polynomial 6 is part of the page in page mode Must be 0 in continuous mode 5 SECTOR_5 0 1 Set to 1 if syndrome polynomial 5 is part of the page in page mode Must be 0 in continuous mode 4 SECTOR_4 0 1 Set to 1 if syndrome polynomial 4 is part of the page in page mode Must be 0 in continuous mode 3 SECTOR_3 0 1 Set to 1 if syndrome polynomial 3 is part of the page in page mode Must be 0...

Page 495: ...ENT_1_i Register 31 0 SYNDROME_1 R W 0 LEGEND R W Read Write R Read only n value after reset Table 7 183 ELM_SYNDROME_FRAGMENT_1_i Register Field Descriptions Bit Field Value Description 31 0 SYNDROME_1 0 FFFF FFFFh Syndrome bits 32 to 63 7 4 5 10 ELM_SYNDROME_FRAGMENT_2_i Register The ELM_SYNDROME_FRAGMENT_2_i Register is shown in Figure 7 150 and described in Table 7 184 Figure 7 150 ELM_SYNDROM...

Page 496: ...ENT_4_i Register 31 0 SYNDROME_4 R W 0 LEGEND R W Read Write R Read only n value after reset Table 7 186 ELM_SYNDROME_FRAGMENT_4_i Register Field Descriptions Bit Field Value Description 31 0 SYNDROME_4 0 FFFF FFFFh Syndrome bits 128 to 159 7 4 5 13 ELM_SYNDROME_FRAGMENT_5_i Register The ELM_SYNDROME_FRAGMENT_5_i Register is shown in Figure 7 153 and described in Table 7 187 Figure 7 153 ELM_SYNDR...

Page 497: ...TUS_i Register The ELM_LOCATION_STATUS_i Register is shown in Figure 7 155 and described in Table 7 189 Figure 7 155 ELM_LOCATION_STATUS_i Register 31 9 8 7 5 4 0 Reserved ECC_CORRECTABL Reserved ECC_NB_ERRORS R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 7 189 ELM_LOCATION_STATUS_i Register Field Descriptions Bit Field Value Description 31 9 Reserved 0 Reserved 8 ECC...

Page 498: ...0 Reserved ECC_ERROR_LOCATION R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 7 190 ELM_ERROR_LOCATION_0 15_i Registers Field Descriptions Bit Field Value Description 31 13 Reserved 0 Reserved 12 0 ECC_ERROR_LOCATION 0 1FFFh Error location bit address 498 Memory Subsystem SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instrument...

Page 499: ...anagement PRCM This chapter describes the PRCM of the device Topic Page 8 1 Power Reset and Clock Management 500 499 SPRUH73H October 2011 Revised April 2013 Power Reset and Clock Management PRCM Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 500: ... managed by a policy manager For example a clock for a clock domain is managed by a dedicated clock manager within the power reset and clock management PRCM module The clock manager considers the joint clocking constraints of all the modules belonging to that clock domain and hence receiving that clock 8 1 3 Clock Management The PRCM module along with the control module manages the gating that is ...

Page 501: ...PRCM and slave modules 8 1 3 2 1 Master Standby Protocol Master standby protocol is used to indicate that a master module must initiate a transaction on the device interconnect and requests specific functional and interface clocks for the purpose The PRCM module ensures that the required clocks are active when the master module requests the PRCM module to enable them This is called a module wake u...

Page 502: ... clocks to the module A slave module is said to be in IDLE state when its clocks are gated by the PRCM module Similarly an idled slave module may need to be wakened because of a service request from a master module or as a result of an event called a wake up event for example interrupt or DMA request received by the slave module In this situation the PRCM module enables the clocks to the module an...

Page 503: ...it VALUE Idle Status Description The module is fully functional The 0x0 Functional interface and functional clocks are active The module is performing a wake up or a 0x1 In transition sleep transition The module interface clock is idled The 0x2 Interface idle module may remain functional if using a separate functional clock The module is fully idle The interface and 0x3 Full idle functional clocks...

Page 504: ...l as interface clock OR Idle status TRANS SWakeup is asserted Clock Domain is ready Idle status FUNCT Clock associated with IDLE AND Idle status IDLE protocol as functional clock OR Idle status TRANS SWakeup is asserted Clock domain is ready Optional clock AND OptFclken Enabled 1 8 1 3 3 Clock Domain A clock domain is a group of modules fed by clock signals controlled by the same clock manager in ...

Page 505: ...CLKSTCTRL x CLKACTIVITY_ FCLK Clock name_FCLK bit in the PRCM module identifies the state of the functional clock s within the clock domain Table shows the possible states of the functional clock Table 8 7 Clock Domain Functional Clock States CLKACTIVITY BIT Value Status Description The functional clock of the clock domain is 0x0 Gated inactive The functional clock of the clock domain is 0x1 Activ...

Page 506: ...ional clock in the clock domain is gated Each clock domain transition behavior is managed by an associated register bit field in the CM_ Clock domain _CLKSTCTRL x CLKTRCTRL PRCM module Table 8 9 Clock Transition Mode Settings CLKTRCTRL Bit Value Selected Mode Description Sleep transition cannot be initiated 0x0 NO_SLEEP Wakeup transition may however occur A software forced sleep transition The 0x1...

Page 507: ... grouped into power domains A power domain can be split into a logic area and a memory area Table 8 10 States of a Memory Area in a Power Domain State Description ON The memory array is powered and fully functional OFF The memory array is powered down Table 8 11 States of a Logic Area in a Power Domain State Description ON Logic is fully powered OFF Logic power switches are off All the logic DFF i...

Page 508: ...N 8 1 4 2 1 Power Management Techniques The following section describes the state of the art power management techniques supported by the device 8 1 4 2 1 1 Adaptive Voltage Scaling AVS is a power management technique based in Smart Reflex that is used for automatic control of the operating voltages of the device to reduce active power consumption With Smart Reflex power supply voltage is adapted ...

Page 509: ...PD_GFX ON or OFF depending on use case PD_WKUP ON DDR is active Standby DDR memory is in self refresh and Power supplies contents are preserved Wakeup from any All power supplies are ON GPIO CortexA8 context register contents VDD_MPU 0 95 V nom are lost and must be saved before entering standby On exit context must be VDD_CORE 0 95 V nom restored from DDR For wakeup boot Clocks ROM executes and br...

Page 510: ... of this mode which distinguish it from Active mode are All modules are clock gated except GPIOs PLLs may be placed in bypass mode if downstream clocking does not require full performance Voltage domains VDD_MPU and VDD_CORE voltage levels can be reduced to OPP50 levels because the required performance of the entire device is reduced MPU power domain PD_MPU is in OFF state DDR memory is in low pow...

Page 511: ... do not require a full cold boot which greatly reduces wakeup latencies over RTC only mode Further power reduction can be achieved in this mode if the RTC function is not required See Section 8 1 4 3 6 Internal RTC LDO Before entering DeepSleep0 mode peripheral and MPU context must be saved in the DDR Upon wakeup the boot ROM executes and checks to see if it has resumed from a DeepSleep0 state If ...

Page 512: ... the RTC digital core The RTC LDO must be disabled for internal power sequencing even though the RTC is not used Grounding the reset signal will ensure the RTC stays in reset Disabling the internal LDO will allow the application to achieve lower power consumption in all the low power modes If your application uses the RTC functionality and never needs RTC only mode the hardware scenario is similar...

Page 513: ...B Wakeup System Sleep USB Controller USB Mode Supported USB Wakeup Use Case State State Event 1 USB Connect DS0 POWER OFF Host No N A 2 DS0 POWER OFF Device Yes VBUS2GPIO 3 DS1 Standby Clock Gated Host Yes PHY WKUP 4 DS1 Standby Clock Gated Device Yes VBUS2GPIO 5 USB Suspend DS0 POWER OFF Host No N A Resume 6 DS0 POWER OFF Device No N A 7 DS1 Standby Clock Gated Host Yes PHY WKUP 8 DS1 Standby Clo...

Page 514: ...of the MPU and Cortex A8 processors The power management sequence kicks off with Cortex A8 MPU executing a WFI instruction with the following steps 1 During Active power mode the Cortex A8 MPU executes a WFI instruction to enter IDLE mode 2 Cortex M3 gets an interrupts and gets active It powers down the MPU power domain if required 3 Registers interrupt for the Wake up peripheral which is listed i...

Page 515: ...M3 The Cortex M3 handles all of the low level power management control of the AM335x A firmware binary is provided by Texas Instruments that includes all of the necessary functions to achieve low power modes Inter Processor Communication IPC registers ipc_msg_regx located in the Control Module Registers are available to communicate with the Cortex M3 so the user can provide certain configuration p...

Page 516: ...0x2 denotes CM3 could not properly initialize When other tasks are to be done FAIL 0x3 indicates some error in carrying out the FAIL 0x3 task Check trace vector for details CM3 INTC will catch the next WFI of A8 and continue with the pre defined WAIT4OK 0x4 sequence Table 8 16 CMD_ID Field CMD_ID Value Description 1 Initiates force_sleep on interconnect clocks CMD_RTC 0x1 2 Turns off MPU and PER p...

Page 517: ...a wake interrupt to CortexM3 via Cortex A8 MPU s WKUP signal INTR2 shown on the diagram 7 After MPU power domain is clock gated PRCM will provide an interrupt to CortexM3 using INTR1 shown in the block diagram 8 CortexM3 starts execution and performs low level power sequencing to turn off certain power domain and eventually executes WFI 9 Hardware oscillator control circuit disables the oscillator...

Page 518: ...tandby idle and wake up modes CM and PRM Emulation signals 8 1 5 1 Interface Descriptions This section lists and shortly describes the different interfaces that allow PRCM to communicate with other modules or external devices 8 1 5 1 1 OCP Interfaces The PRCM has 1 target OCP interfaces compliant with respect to the OCP IP2 standard The OCP port for the PRCM module is used to control power reset a...

Page 519: ...evice PRCM gathers external clocks and internally generated clocks for distribution to the other modules in the device PRCM manages the system clock generation 8 1 6 1 Terminology The PRCM produces 2 types of clock Interface clocks these clocks primarily provide clocking for the system interconnect modules and the portions of device s functional modules which interface to the system interconnect m...

Page 520: ...olution frequency synthesizer PLL with built in level shifters which allows the generation of PLL locked frequencies up to 2 GHz ADPLLS has a predivide feature which allows user to divide for instance a 24 or 26 MHz reference clock to 1 MHz and then multiply up to 2 GHz maximum All PLLs will come up in bypass mode at reset SW needs to program all the PLL settings appropriately and then wait for PL...

Page 521: ...Low CLKINPHIF M3 ULOWCLKEN 1 CLKOUTHIF Low ULOWCLKEN 0 Note Since M3 divider is running on the internal LDO domain in the case when CLKINPHIFSEL 1 CLKOUTHIF could be active only when internal LDO is ON Hence whenever LDOPWDN goes low to high to powerdown LDO happens when TINITZ activated when entering slow relock bypass mode output CLKOUTHIF will glitch and stop To avoid this glitch it is recommen...

Page 522: ...trolled oscillator DCO before the post divider The PLL output clock is synthesized by an internal oscillator which is phase locked to the refclk There are two oscillators built within ADPLLLJ The oscillators are user selectable based on the synthesized output clock frequency requirement In locked condition CLKDCO CLKINP M N 1 The ADPLLLJ lock frequency is defined as follows fDPLL M CLKINP N 1 The ...

Page 523: ...due to the clock s fundamental or any of its harmonics When SSC is enabled the clock s spectrum is spread by the amount of frequency spread and the attenuation is given by the ratio of the frequency spread Δf and the modulation frequency fm i e 10 log10 Df fm 10 dB SSC is performed by changing the feedback divider M in a triangular pattern Implying the frequency of the output clock would vary in a...

Page 524: ...eqDividerMantissa DeltaMStep IF ModFreqDividerExponent 3 DeltaMStep is split into integer part and fractional part Integer part is controlled by 2 bit signal DeltaMStepInteger through the CM_SSC_DELTAMSTEP_DPLL_xxx DELTAMSTEP_INTEGER bit field Fractional part is controlled by 18 bit signal DeltaMStepFraction through the CM_SSC_DELTAMSTEP_DPLL_xxx DELTAMSTEP_FRACTION bit field The frequency spread ...

Page 525: ...U PLLs L3F_CLK L4F_CLK PRU ICSS_IEP_CLK Debugss_clka CPTS_RFT_CLK Enet switch IEEE1588v2 PRU ICSS OCP_CLKL L3S_CLK L4_PER_CLK L4_WKUP_CLK MHZ_250_CLK RGMII gigabit MHZ_125_CLK Enet switch bus interface MHZ_50_CLK RGMII 100 Mbps and RMII MHZ_5_CLK RGMII 10 Mbps www ti com Power Reset and Clock Management Figure 8 10 Core PLL ALT_CLKs are to be used for internal test purpose and should not be used i...

Page 526: ...NA RGMII UTM5 MHZ_125_CLK CORE_CLKO Ethernet Switch Bus 2 Mstr Xtal 2 2 125 2 50 UTM5 Clk MHZ_50_CLK 100 CORE_CLKO mbps RGMII or 10 100 5 Mstr Xtal 5 5 50 2 50 UTM5 RMII MHZ_5_CLK 10 mbps MHZ_50_CLK 10 Mstr Xtal 50 10 5 10 5 RGMII HSDIVIDER CORE_CLKOUTM6 Mstr Xtal 4 500 1 100 M6 1 Not all interfaces and peripheral modules are available in OPP50 For more information see the device specific datashee...

Page 527: ...g CM_CLKSEL_DPLL_CORE DPLL_MULT and DPLL_DIV to the desired values 4 Configure M4 M5 and M6 dividers by setting HSDIVIDER_CLKOUT1_DIV bits in CM_DIV_M4_DPLL_CORE CM_DIV_M5_DPLL_CORE and CM_DIV_M6_DPLL_CORE to the desired values 5 Switch over to lock mode by setting CM_CLKMODE_DPLL_CORE DPLL_EN to 0x7 6 Wait for CM_IDLEST_DPLL_CORE ST_DPLL_CLK 1 to ensure PLL is locked CM_IDLEST_DPLL_CORE ST_MN_BYP...

Page 528: ...ixed 2 divider and a fixed 732 4219 divider to create an accurate 32 768 KHz clock for Timer and debounce use Table 8 24 Per PLL Typical Frequencies MHz Power On Reset PLL OPP100 OPP50 1 2 Bypass Clock Source Freq Freq DIV Value Freq DIV Value DIV Value MHz MHz PLL Lock frequency PLL 960 960 USB_PHY_CLK CLKDCOLDO Held Low 960 960 CLKOUT of ADPLLLJ CLKOUT uses PLL s N2 is 0 on Mstr Xtal PER_CLKOUTM...

Page 529: ...d Divide values by setting CM_CLKSEL_DPLL_PER DPLL_MULT and DPLL_DIV to the desired values 4 Configure M2 divider by setting CM_DIV_M2_DPLL_PER DPLL_CLKOUT_DIV to the desired value 5 Switch over to lock mode by setting CM_CLKMODE_DPLL_PER DPLL_EN to 0x7 6 Wait for CM_IDLEST_DPLL_PER ST_DPLL_CLK 1 to ensure PLL is locked CM_IDLEST_DPLL_PER ST_MN_BYPASS should also change to 0 to denote the PLL is o...

Page 530: ...Subsystem clock when the PLL is in bypass mode 8 1 6 9 1 Configuring the MPU PLL The following steps detail how to configure the MPU PLL 1 Switch PLL to bypass mode by setting CM_CLKMODE_DPLL_MPU DPLL_EN to 0x4 2 Wait for CM_IDLEST_DPLL_MPU ST_MN_BYPASS 1 to ensure PLL is in bypass CM_IDLEST_DPLL_MPU ST_DPLL_CLK should also change to 0 to denote the PLL is unlocked 3 Configure Multiply and Divide ...

Page 531: ... CLKINP is selected it is sourced through the ADPLLS 1 N2 1 divider The PRCM register defaults to 0 on power up to select the CLKINP source The CLKINPULOW input is sourced from the CORE_CLKOUTM6 from the Core PLL or PER_CLKOUTM2 from the Per PLL This PLL output clock can be used as an alternate clock source in low power active use cases for the pixel clock when the Display PLL is in bypass mode 8 ...

Page 532: ... PLL locked at 532 MHz and M2 Divider 1 so as to expect CLKOUT 266 MHz The ULOWCLKEN input from a programmable PRCM register selects whether CLKINP or CLKINPULOW is the bypass clock source This is a glitch free switch When CLKINP is selected it is sourced through the ADPLLS 1 N2 1 divider The PRCM register defaults to 0 on power up to select the CLKINP source The CLKINPULOW input may be sourced fr...

Page 533: ...hese signals for time critical external circuits is discouraged because of unpredictable jitter performance For more information see the device datasheet AM335x ARM Cortex A8 Microprocessors MPUs literature number SPRS717 CLKOUT1 is created from the master oscillator CLKOUT2 can be sourced from the 32 KHz crystal oscillator or any of the PLL except MPU PLL outputs The selected output can be furthe...

Page 534: ... Master Osc based PER PLL Hence in low power modes DMTIMER1 in the WKUP domain can use the 32K RC oscillator for generating the OS operating system 1ms tick generation and timer based wakeup Since most applications expect an accurate 1ms OS tick which the inaccurate 32K RC 16 60 KHz oscillator cannot provide a separate 32768 Hz oscillator 32K Osc is provided as another option Figure 8 17 Timer Clo...

Page 535: ...Deassertion is synchronous to the clock which runs a counter used to stall or delay reset de assertion upon source deactivation This clock will be CLK_M_OSC used by all the reset managers All modules receiving a PRCM generated reset are expected to treat the reset as asynchronous and implement local re synchronization upon de activation as needed One or more Reset Managers are required per power d...

Page 536: ...this document for signal and port names They include _RST in a signal or port name is used to denote reset signal _PWRON_RST in a signal or port name is used to denote a cold reset source 8 1 7 3 Global Power On Reset Cold Reset There are several cold reset sources See Table 8 25 for a summary of the different reset sources 8 1 7 3 1 Power On Reset PORz The source of power on reset is PORz signal ...

Page 537: ...SPRS717 8 1 7 3 3 Bad Device Reset This reset is asserted whenever the DEVICE_TYPE encodes an unsupported device type such as the code for a bad device 8 1 7 3 4 Global Cold Software Reset GLOBAL_COLD_SW_RST The source for GLOBAL_COLD_SW_RST is generated internally by the PRM It is activated upon setting the PRM_RSTCTRL RST_GLOBAL_COLD_SW bit in the PRM memory map This bit is self clearing i e it ...

Page 538: ...t this signal be used as input only do not connect to other devices as a reset to implement a push button reset circuit to the AM335x or an output only to be able to reset other devices after an AM335x reset completes 8 1 7 4 1 1 Warm Reset Input Reset Output nRESETIN_OUT Any global reset source internal or external causes nRESETIN_OUT to be driven and maintained at the boundary of the device for ...

Page 539: ...us section 2 All IOs except test and emulation will go to tri state immediately 3 Chip clocks are not affected as both PLL and dividers are intact 4 nRESETIN_OUT gets de asserted after 30 cycles 5 PRCM de asserts reset to the host processor and all other peripherals without local CPUs 6 Note that all IPs with local CPUs will have local reset asserted by default at Warm Reset and reset de assertion...

Page 540: ..._WARM_RST 8 1 7 4 4 Test Reset TRSTz This reset is triggered from TRSTz pin on JTAG interface This is a non blockable reset and it resets test and emulation logic NOTE A PORz reset assertion should cause entire device to reset including all test and emulation logic regardless of the state of TRSTz Therefore PORz assertion will achieve full reset of the device even if TRSTz pin is pulled permanentl...

Page 541: ... 5 Reset Characteristics The following table shows characteristic of each reset source 541 SPRUH73H October 2011 Revised April 2013 Power Reset and Clock Management PRCM Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 542: ...isters Reset out Assertion Y Y Y 5 Y 5 Y 5 Y 5 N nRESETIN_OUT Pin Resets RTC N N N N N N N 1 The ROM software does not utilize this feature of DRAM content preservation Hence the AM335x re boots like a cold boot for warm reset as well 2 CORE PLL is an exception when EMAC switch reset isolation is enabled 3 Only true if GMAC switch reset isolation is enabled in control registers otherwise will be r...

Page 543: ... otherwise defined in this document 8 1 7 7 Reset Priority If more than one of these reset sources are asserted simultaneously then the following priority order should be used 1 POR 2 TRSTz 3 External warm reset 4 Emulation 5 Reset requestors 6 Software resets 8 1 7 8 Trace Functionality Across Reset Other than POR TRSTz and SW cold reset none of the other resets will affect trace functionality Th...

Page 544: ...hould have their output drivers tri state and internal pulls enabled during assertion of all reset sources JTAG i f IO is affected only by TRSTz Note The PRUs and Cortex M3 processor are held under reset after global warm reset by assertion of software source of reset Other domains are held under reset after global warm reset until the MPU software enables their respective interface clock 8 1 10 V...

Page 545: ...ns are switched via internal power switches At power on reset all domains except always on will be in the power domain OFF state Table 8 27 Power Domain State Table POWER DOMAIN MODE WAKEUP MPU GFX PER RTC EFUSE No Voltage N A N A N A N A N A N A Supply Power On Reset ON OFF OFF OFF OFF OFF ALL OTHER FUNCTIONAL ON DON T CARE DON T CARE DON T CARE DON T CARE DON T CARE MODES Internal Power NO YES Y...

Page 546: ...troller L3 L4_PER L4_Fast L4_FW Peripherals PRU ICSS LCD controller Ethernet Switch USB Controller GPMC MMC0 2 DMTIMER2 7 PD_PER Uart1 5 SPI0 1 I2C1 2 DCAN0 1 McASP0 1 ePWM0 2 eCAP0 2 eQeP0 1 GPIO1 3 ELM Mailbox0 Spinlock OCP_WP Others USB2PHYCORE VDD digital section USB2PHYCM VDD digital section PD_GFX SGX530 PD_MPU CPU L1 L2 of MPU VDD_MPU Interrupt controller of MPU Subsystem PD_WKUP Digital Po...

Page 547: ...s power domain will assert isolation enable for the domain 7 PRCM will assert warm and cold reset to the power domain 8 PSCON will assert control signals to switch off power using on die switches 9 On die switches will send acknowledge back to PSCON 8 1 11 2 Power Domain Power Up Sequence The following sequence of steps occurs during power up of a power domain This sequence is not relevant to alwa...

Page 548: ... 8 1 12 1 17 4Ch CM_PER_SPI0_CLKCTRL Section 8 1 12 1 18 50h CM_PER_SPI1_CLKCTRL Section 8 1 12 1 19 60h CM_PER_L4LS_CLKCTRL Section 8 1 12 1 20 64h CM_PER_L4FW_CLKCTRL Section 8 1 12 1 21 68h CM_PER_MCASP1_CLKCTRL Section 8 1 12 1 22 6Ch CM_PER_UART1_CLKCTRL Section 8 1 12 1 23 70h CM_PER_UART2_CLKCTRL Section 8 1 12 1 24 74h CM_PER_UART3_CLKCTRL Section 8 1 12 1 25 78h CM_PER_UART4_CLKCTRL Secti...

Page 549: ...M_PER_SPINLOCK_CLKCTRL Section 8 1 12 1 51 110h CM_PER_MAILBOX0_CLKCTRL Section 8 1 12 1 52 11Ch CM_PER_L4HS_CLKSTCTRL Section 8 1 12 1 53 120h CM_PER_L4HS_CLKCTRL Section 8 1 12 1 54 12Ch CM_PER_OCPWP_L3_CLKSTCT Section 8 1 12 1 55 RL 130h CM_PER_OCPWP_CLKCTRL Section 8 1 12 1 56 140h CM_PER_PRU_ICSS_CLKSTCTR Section 8 1 12 1 57 L 144h CM_PER_CPSW_CLKSTCTRL Section 8 1 12 1 58 148h CM_PER_LCDC_CL...

Page 550: ...TCTRL Register Field Descriptions Bit Field Type Reset Description 31 29 Reserved R 0h 28 CLKACTIVITY_TIMER6_ R 0h This field indicates the state of the TIMER6 CLKTIMER clock in the GCLK domain 0x0 Inact Corresponding clock is gated 0x1 Act Corresponding clock is active 27 CLKACTIVITY_TIMER5_ R 0h This field indicates the state of the TIMER5 CLKTIMER clock in the GCLK domain 0x0 Inact Correspondin...

Page 551: ...IVITY_TIMER7_ R 0h This field indicates the state of the TIMER7 CLKTIMER clock in the GCLK domain 0x0 Inact Corresponding clock is gated 0x1 Act Corresponding clock is active 12 Reserved R 0h 11 CLKACTIVITY_CAN_CLK R 0h This field indicates the state of the CAN_CLK clock in the domain 0x0 Inact Corresponding clock is gated 0x1 Act Corresponding clock is active 10 CLKACTIVITY_UART_GF R 0h This fiel...

Page 552: ... R Read only W1toCl Write 1 to clear bit n value after reset Table 8 31 CM_PER_L3S_CLKSTCTRL Register Field Descriptions Bit Field Type Reset Description 31 26 Reserved R 0h 25 11 Reserved R 0h 10 Reserved R 0h 9 Reserved R 0h 8 Reserved R 0h 7 5 Reserved R 0h 4 Reserved R 0h 3 CLKACTIVITY_L3S_GCL R 1h This field indicates the state of the L3S_GCLK clock in the domain K 0x0 Inact 0x1 Act 2 Reserve...

Page 553: ...Write 1 to clear bit n value after reset Table 8 32 CM_PER_L4FW_CLKSTCTRL Register Field Descriptions Bit Field Type Reset Description 31 26 Reserved R 0h 25 11 Reserved R 0h 10 Reserved R 0h 9 Reserved R 0h 8 CLKACTIVITY_L4FW_GC R 1h This field indicates the state of the L4FW clock in the domain LK 0x0 Inact Corresponding clock is gated 0x1 Act Corresponding clock is active 7 2 Reserved R 0h 1 0 ...

Page 554: ... 7 CLKACTIVITY_MCASP_ R 0h This field indicates the state of the MCASP_GCLK clock in the GCLK domain 0x0 Inact 0x1 Act 6 CLKACTIVITY_CPTS_RF R 0h This field indicates the state of the T_GCLK CLKACTIVITY_CPTS_RFT_GCLK clock in the domain 0x0 Inact 0x1 Act 5 Reserved R 0h 4 CLKACTIVITY_L3_GCLK R 1h This field indicates the state of the L3_GCLK clock in the domain 0x0 Inact 0x1 Act 3 CLKACTIVITY_MMC_...

Page 555: ...eset insensitive when CPSW RESET_ISO is enabled 0x0 Func Module is fully functional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks ...

Page 556: ... status 0x0 Func Module is fully functional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disab...

Page 557: ... status 0x0 Func Module is fully functional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disab...

Page 558: ...dle status 0x0 Func Module is fully functional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is di...

Page 559: ...rans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except if...

Page 560: ...P 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error ex...

Page 561: ...Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 2h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except i...

Page 562: ... 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error exc...

Page 563: ...1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except...

Page 564: ...luding OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an...

Page 565: ...ns Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except if r...

Page 566: ...Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except i...

Page 567: ...Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except i...

Page 568: ...Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except i...

Page 569: ...Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except i...

Page 570: ...ans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 2h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except if ...

Page 571: ...ans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 2h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except if ...

Page 572: ... 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error exc...

Page 573: ...1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except...

Page 574: ...1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except...

Page 575: ...1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except...

Page 576: ...1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except...

Page 577: ... 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error exc...

Page 578: ... 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error exc...

Page 579: ... 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error exc...

Page 580: ... 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error exc...

Page 581: ... is enabled 17 16 IDLEST R 3h Module idle status 0x0 Func Module is fully functional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks...

Page 582: ... is enabled 17 16 IDLEST R 3h Module idle status 0x0 Func Module is fully functional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks...

Page 583: ... is enabled 17 16 IDLEST R 3h Module idle status 0x0 Func Module is fully functional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks...

Page 584: ...Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except i...

Page 585: ...including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in...

Page 586: ...including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in...

Page 587: ...CP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error e...

Page 588: ...g OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an erro...

Page 589: ...CP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error e...

Page 590: ...CP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error e...

Page 591: ...OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 2h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error ...

Page 592: ...rans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 2h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except if...

Page 593: ...Module idle status 0x0 Func Module is fully functional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 2h Control the way mandatory clocks are managed 0x0 DISABLED Modu...

Page 594: ...Module idle status 0x0 Func Module is fully functional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Modu...

Page 595: ... 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error exc...

Page 596: ... 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error exc...

Page 597: ...luding OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an...

Page 598: ...luding OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an...

Page 599: ...idle status 0x0 Func Module is fully functional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is d...

Page 600: ...idle status 0x0 Func Module is fully functional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is d...

Page 601: ...g OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an erro...

Page 602: ...g OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an erro...

Page 603: ... Bit Field Type Reset Description 31 7 Reserved R 0h 6 CLKACTIVITY_CPSW_5 R 1h This field indicates the state of the CPSW_5MHZ_GCLK clock in the MHZ_GCLK domain 0x0 Inact 0x1 Act 5 CLKACTIVITY_CPSW_50 R 1h This field indicates the state of the CPSW_50MHZ_GCLK clock in MHZ_GCLK the domain 0x0 Inact 0x1 Act 4 CLKACTIVITY_CPSW_25 R 1h This field indicates the state of the CPSW_250MHZ_GCLK clock in 0M...

Page 604: ...Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 2h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except i...

Page 605: ...Write 1 to clear bit n value after reset Table 8 84 CM_PER_OCPWP_L3_CLKSTCTRL Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 CLKACTIVITY_OCPWP_ R 0h This field indicates the state of the OCPWP L4 clock in the domain L4_GCLK 0x0 Inact 0x1 Act 4 CLKACTIVITY_OCPWP_ R 0h This field indicates the state of the OCPWP L3 clock in the domain L3_GCLK 0x0 Inact 0x1 Act 3 2 ...

Page 606: ...idle status 0x0 Func Module is fully functional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 2h Control the way mandatory clocks are managed 0x0 DISABLED Module is d...

Page 607: ...M_PER_PRU_ICSS_CLKSTCTRL Register Field Descriptions Bit Field Type Reset Description 31 7 Reserved R 0h 6 CLKACTIVITY_PRU_ICS R 0h This field indicates the state of the PRU ICSS UART clock in the S_UART_GCLK domain 0x0 Inact 0x1 Act 5 CLKACTIVITY_PRU_ICS R 0h This field indicates the state of the PRU ICSS IEP clock in the S_IEP_GCLK domain 0x0 Inact 0x1 Act 4 CLKACTIVITY_PRU_ICS R 0h This field i...

Page 608: ...R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 87 CM_PER_CPSW_CLKSTCTRL Register Field Descriptions Bit Field Type Reset Description 31 5 Reserved R 0h 4 CLKACTIVITY_CPSW_12 R 0h This field indicates the state of the CPSW 125 MHz OCP clock in the 5MHz_GCLK domain 0x0 Inact 0x1 Act 3 2 Reserved R 0h 1 0 CLKTRCTRL R W 2h Controls the clock state transition of the ...

Page 609: ...to clear bit n value after reset Table 8 88 CM_PER_LCDC_CLKSTCTRL Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 CLKACTIVITY_LCDC_L4 R 0h This field indicates the state of the LCDC L4 OCP clock in the _OCP_GCLK domain 0x0 Inact 0x1 Act 4 CLKACTIVITY_LCDC_L3 R 0h This field indicates the state of the LCDC L3 OCP clock in the _OCP_GCLK domain 0x0 Inact 0x1 Act 3 2 ...

Page 610: ...ding OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an e...

Page 611: ...ols the clock state transition of the 24MHz clock domain 0x0 NO_SLEEP NO_SLEEP Sleep transition cannot be initiated Wakeup transition may however occur 0x1 SW_SLEEP SW_SLEEP Start a software forced sleep transition on the domain 0x2 SW_WKUP SW_WKUP Start a software forced wake up transition on the domain 0x3 Reserved Reserved 8 1 12 2 CM_WKUP Registers Table 8 91 lists the memory mapped registers ...

Page 612: ... allows monitoring the master clock activity Section 8 1 12 2 14 This register is read only and automatically updated warm reset insensitive 38h CM_SSC_DELTAMSTEP_DPLL_D Control the DeltaMStep parameter for Spread Spectrum Section 8 1 12 2 15 DR Clocking technique DeltaMStep is split into fractional and integer part warm reset insensitive 3Ch CM_SSC_MODFREQDIV_DPLL_D Control the Modulation Frequen...

Page 613: ...cillator output of the PER DPLL 80h CM_DIV_M4_DPLL_CORE This register provides controls over the CLKOUT1 o p of Section 8 1 12 2 33 the HSDIVIDER 84h CM_DIV_M5_DPLL_CORE This register provides controls over the CLKOUT2 o p of Section 8 1 12 2 34 the HSDIVIDER 88h CM_CLKMODE_DPLL_MPU This register allows controlling the DPLL modes Section 8 1 12 2 35 8Ch CM_CLKMODE_DPLL_PER This register allows con...

Page 614: ...rols the SW supervised clock domain state transition between ON ACTIVE and ON INACTIVE states It also hold one status bit per clock input of the domain D4h CM_WKUP_WDT1_CLKCTRL This register manages the WDT1 clocks Section 8 1 12 2 53 D8h CM_DIV_M6_DPLL_CORE This register provides controls over the CLKOUT3 o p of Section 8 1 12 2 54 the HSDIVIDER warm reset insensitive 614 Power Reset and Clock Ma...

Page 615: ...in K 0x0 Inact Corresponding clock is gated 0x1 Act Corresponding clock is active 13 CLKACTIVITY_TIMER1_ R 0h This field indicates the state of the TIMER1 clock in the domain GCLK 0x0 Inact Corresponding clock is gated 0x1 Act Corresponding clock is active 12 CLKACTIVITY_UART0_G R 0h This field indicates the state of the UART0 clock in the domain FCLK 0x0 Inact Corresponding clock is gated 0x1 Act...

Page 616: ...he domain _GCLK 0x0 Inact Corresponding clock is gated 0x1 Act Corresponding clock is active 1 0 CLKTRCTRL R W 2h Controls the clock state transition of the always on clock domain 0x0 NO_SLEEP NO_SLEEP Sleep transition cannot be initiated Wakeup transition may however occur 0x1 SW_SLEEP SW_SLEEP Start a software forced sleep transition on the domain 0x2 SW_WKUP SW_WKUP Start a software forced wake...

Page 617: ...nctional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module r...

Page 618: ... is enabled 17 16 IDLEST R 3h Module idle status 0x0 Func Module is fully functional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks...

Page 619: ... value after reset Table 8 95 CM_WKUP_L4WKUP_CLKCTRL Register Field Descriptions Bit Field Type Reset Description 31 19 Reserved R 0h 18 Reserved R 0h 17 16 IDLEST R 0h Module idle status 0x0 Func Module is fully functional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate funct...

Page 620: ...nal including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 2h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module result...

Page 621: ...S Optional functional clock is disabled 0x1 FCLK_EN Optional functional clock is enabled 18 STBYST R 0h Module standby status 0x0 Func Module is functional not in standby 0x1 Standby Module is in standby 17 16 IDLEST R 0h Module idle status 0x0 Func Module is fully functional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode o...

Page 622: ...set Description 31 26 Reserved R 0h 25 11 Reserved R 0h 10 8 Reserved R 0h 7 5 Reserved R 0h 4 CLKACTIVITY_DEBUG_C R 1h This field indicates the state of the Debugss CLKA clock in the LKA domain 3 CLKACTIVITY_L3_AON_ R 1h This field indicates the state of the L3_AON clock in the domain GCLK 0x0 Inact Corresponding clock is gated 0x1 Act Corresponding clock is active 2 CLKACTIVITY_DBGSYS R 0h This ...

Page 623: ... 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved AUTO_DPLL_MODE R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 99 CM_AUTOIDLE_DPLL_MPU Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 0 AUTO_DPLL_MODE R W 0h This feature is not supported 623 SPRUH73H October 2011 Revise...

Page 624: ... 0h 7 6 5 4 3 2 1 0 Reserved ST_DPLL_CLK R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 100 CM_IDLEST_DPLL_MPU Register Field Descriptions Bit Field Type Reset Description 31 9 Reserved R 0h 8 ST_MN_BYPASS R 0h DPLL MN_BYPASS status 0x0 NO_MNBYPASS DPLL is not in MN_Bypass 0x1 MN_BYPASS DPLL is in MN_Bypass 7 1 Reserved R 0h 0 ST_DPLL_CLK R 0h D...

Page 625: ...ed DELTAMSTEP_INTEGER DELTAMSTEP_FRACTION R 0h R W 0h R W 0h 15 14 13 12 11 10 9 8 DELTAMSTEP_FRACTION R W 0h 7 6 5 4 3 2 1 0 DELTAMSTEP_FRACTION R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 101 CM_SSC_DELTAMSTEP_DPLL_MPU Register Field Descriptions Bit Field Type Reset Description 31 20 Reserved R 0h 19 18 DELTAMSTEP_INTEGER R W 0h Integer part ...

Page 626: ... 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved MODFREQDIV_EXPONENT R 0h R W 0h 7 6 5 4 3 2 1 0 Reserved MODFREQDIV_MANTISSA R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 102 CM_SSC_MODFREQDIV_DPLL_MPU Register Field Descriptions Bit Field Type Reset Description 31 11 Reserved R 0h 10 8 MODFREQDIV_EXPONE R W 0h Set the E...

Page 627: ...riptions Bit Field Type Reset Description 31 24 Reserved R 0h 23 DPLL_BYP_CLKSEL R W 0h Selects CLKINP or CLKINPULOW as Bypass Clock 0x0 Sel0 Selects CLKINP Clock as BYPASS Clock 0x1 Sel1 Selects CLKINPULOW as Bypass Clock 22 19 Reserved R 0h 18 8 DPLL_MULT R W 0h DPLL multiplier factor 2 to 2047 This register is automatically cleared to 0 when the DPLL_EN field in the CLKMODE_DPLL register is set...

Page 628: ... 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved AUTO_DPLL_MODE R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 104 CM_AUTOIDLE_DPLL_DDR Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 0 AUTO_DPLL_MODE R W 0h AUTO_DPLL_MODE is not supported 628 Power Reset and Clock Man...

Page 629: ... 0h 7 6 5 4 3 2 1 0 Reserved ST_DPLL_CLK R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 105 CM_IDLEST_DPLL_DDR Register Field Descriptions Bit Field Type Reset Description 31 9 Reserved R 0h 8 ST_MN_BYPASS R 0h DPLL MN_BYPASS status 0x0 NO_MNBYPASS DPLL is not in MN_Bypass 0x1 MN_BYPASS DPLL is in MN_Bypass 7 1 Reserved R 0h 0 ST_DPLL_CLK R 0h D...

Page 630: ...DELTAMSTEP_INTEGER DELTAMSTEP_FRACTION R 0h R W 0h R W 0h 15 14 13 12 11 10 9 8 DELTAMSTEP_FRACTION R W 0h 7 6 5 4 3 2 1 0 DELTAMSTEP_FRACTION R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 106 CM_SSC_DELTAMSTEP_DPLL_DDR Register Field Descriptions Bit Field Type Reset Description 31 20 Reserved R 0h 19 18 DELTAMSTEP_INTEGER R W 0h Integer part for...

Page 631: ... 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved MODFREQDIV_EXPONENT R 0h R W 0h 7 6 5 4 3 2 1 0 Reserved MODFREQDIV_MANTISSA R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 107 CM_SSC_MODFREQDIV_DPLL_DDR Register Field Descriptions Bit Field Type Reset Description 31 11 Reserved R 0h 10 8 MODFREQDIV_EXPONE R W 0h Set the E...

Page 632: ...criptions Bit Field Type Reset Description 31 24 Reserved R 0h 23 DPLL_BYP_CLKSEL R W 0h Select CLKINP orr CLKINPULOW as bypass clock 0x0 Sel0 Selects CLKINP Clock as BYPASS Clock 0x1 Sel1 Selects CLKINPULOW as Bypass Clock 22 19 Reserved R 0h 18 8 DPLL_MULT R W 0h DPLL multiplier factor 2 to 2047 This register is automatically cleared to 0 when the DPLL_EN field in the CLKMODE_DPLL register is se...

Page 633: ...21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved AUTO_DPLL_MODE R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 109 CM_AUTOIDLE_DPLL_DISP Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 0 AUTO_DPLL_MODE R W 0h AUTO_DPLL_MODE is not supported 633 SPRUH73H October 2011 ...

Page 634: ... R 0h 7 6 5 4 3 2 1 0 Reserved ST_DPLL_CLK R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 110 CM_IDLEST_DPLL_DISP Register Field Descriptions Bit Field Type Reset Description 31 9 Reserved R 0h 8 ST_MN_BYPASS R 0h DPLL MN_BYPASS status 0x0 NO_MNBYPASS DPLL is not in MN_Bypass 0x1 MN_BYPASS DPLL is in MN_Bypass 7 1 Reserved R 0h 0 ST_DPLL_CLK R 0...

Page 635: ...d DELTAMSTEP_INTEGER DELTAMSTEP_FRACTION R 0h R W 0h R W 0h 15 14 13 12 11 10 9 8 DELTAMSTEP_FRACTION R W 0h 7 6 5 4 3 2 1 0 DELTAMSTEP_FRACTION R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 111 CM_SSC_DELTAMSTEP_DPLL_DISP Register Field Descriptions Bit Field Type Reset Description 31 20 Reserved R 0h 19 18 DELTAMSTEP_INTEGER R W 0h Integer part ...

Page 636: ...0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved MODFREQDIV_EXPONENT R 0h R W 0h 7 6 5 4 3 2 1 0 Reserved MODFREQDIV_MANTISSA R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 112 CM_SSC_MODFREQDIV_DPLL_DISP Register Field Descriptions Bit Field Type Reset Description 31 11 Reserved R 0h 10 8 MODFREQDIV_EXPONE R W 0h Set th...

Page 637: ...escriptions Bit Field Type Reset Description 31 24 Reserved R 0h 23 DPLL_BYP_CLKSEL R W 0h Select CLKINP or CLKINPULOW as bypass clock 0x0 Sel0 Selects CLKINP Clock as BYPASS Clock 0x1 Sel1 Selects CLKINPULOW as Bypass Clock 22 19 Reserved R 0h 18 8 DPLL_MULT R W 0h DPLL multiplier factor 2 to 2047 This register is automatically cleared to 0 when the DPLL_EN field in the CLKMODE_DPLL register is s...

Page 638: ... 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved AUTO_DPLL_MODE R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 114 CM_AUTOIDLE_DPLL_CORE Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 0 AUTO_DPLL_MODE R W 0h This feature is not supported 638 Power Reset and Clock M...

Page 639: ... R 0h 7 6 5 4 3 2 1 0 Reserved ST_DPLL_CLK R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 115 CM_IDLEST_DPLL_CORE Register Field Descriptions Bit Field Type Reset Description 31 9 Reserved R 0h 8 ST_MN_BYPASS R 0h DPLL MN_BYPASS status 0x0 NO_MNBYPASS DPLL is not in MN_Bypass 0x1 MN_BYPASS DPLL is in MN_Bypass 7 1 Reserved R 0h 0 ST_DPLL_CLK R 0...

Page 640: ...d DELTAMSTEP_INTEGER DELTAMSTEP_FRACTION R 0h R W 0h R W 0h 15 14 13 12 11 10 9 8 DELTAMSTEP_FRACTION R W 0h 7 6 5 4 3 2 1 0 DELTAMSTEP_FRACTION R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 116 CM_SSC_DELTAMSTEP_DPLL_CORE Register Field Descriptions Bit Field Type Reset Description 31 20 Reserved R 0h 19 18 DELTAMSTEP_INTEGER R W 0h Integer part ...

Page 641: ...0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved MODFREQDIV_EXPONENT R 0h R W 0h 7 6 5 4 3 2 1 0 Reserved MODFREQDIV_MANTISSA R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 117 CM_SSC_MODFREQDIV_DPLL_CORE Register Field Descriptions Bit Field Type Reset Description 31 11 Reserved R 0h 10 8 MODFREQDIV_EXPONE R W 0h Set th...

Page 642: ... value after reset Table 8 118 CM_CLKSEL_DPLL_CORE Register Field Descriptions Bit Field Type Reset Description 31 23 Reserved R 0h 22 19 Reserved R 0h 18 8 DPLL_MULT R W 0h DPLL multiplier factor 2 to 2047 This register is automatically cleared to 0 when the DPLL_EN field in the CLKMODE_DPLL register is set to select MN Bypass mode equal to input M of DPLL M 2 to 2047 DPLL multiplies by M 0x0 Res...

Page 643: ...1 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved AUTO_DPLL_MODE R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 119 CM_AUTOIDLE_DPLL_PER Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 0 AUTO_DPLL_MODE R W 0h AUTO_DPLL_MODE is not supported 643 SPRUH73H October 2011 Re...

Page 644: ...R 0h 7 6 5 4 3 2 1 0 Reserved ST_DPLL_CLK R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 120 CM_IDLEST_DPLL_PER Register Field Descriptions Bit Field Type Reset Description 31 9 Reserved R 0h 8 ST_MN_BYPASS R 0h DPLL MN_BYPASS status 0x0 NO_MNBYPASS DPLL is not in MN_Bypass 0x1 MN_BYPASS DPLL is in MN_Bypass 7 1 Reserved R 0h 0 ST_DPLL_CLK R 0h ...

Page 645: ... DELTAMSTEP_INTEGER DELTAMSTEP_FRACTION R 0h R W 0h R W 0h 15 14 13 12 11 10 9 8 DELTAMSTEP_FRACTION R W 0h 7 6 5 4 3 2 1 0 DELTAMSTEP_FRACTION R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 121 CM_SSC_DELTAMSTEP_DPLL_PER Register Field Descriptions Bit Field Type Reset Description 31 20 Reserved R 0h 19 18 DELTAMSTEP_INTEGER R W 0h Integer part fo...

Page 646: ...h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved MODFREQDIV_EXPONENT R 0h R W 0h 7 6 5 4 3 2 1 0 Reserved MODFREQDIV_MANTISSA R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 122 CM_SSC_MODFREQDIV_DPLL_PER Register Field Descriptions Bit Field Type Reset Description 31 11 Reserved R 0h 10 8 MODFREQDIV_EXPONE R W 0h Set the ...

Page 647: ...PLL_PER Register Field Descriptions Bit Field Type Reset Description 31 13 Reserved R 0h 12 DPLL_CLKDCOLDO_PW R W 0h Automatic power down for CLKDCOLDO o p when it is gated DN 0x0 ALWAYS_ACTIVE Keep CLKDCOLDO o p powered on even when it is gated 0x1 AUTO_PWDN Automatically power down CLKDCOLDO o p when it is gated 11 10 Reserved R 0h 9 ST_DPLL_CLKDCOLDO R 0h DPLL CLKDCOLDO status 0x0 CLK_ENABLED T...

Page 648: ...R M4 divider and hence WDN CLKOUT1 output when the o p clock is gated 0x0 ALWAYS_ACTIVE Keep M4 divider powered on even when CLKOUT1 is gated 0x1 AUTO_PWDN Automatically power down M4 divider when CLKOUT1 is gated 11 10 Reserved R 0h 9 ST_HSDIVIDER_CLKOU R 0h HSDIVIDER CLKOUT1 status T1 0x0 CLK_ENABLED The clock output is enabled 0x1 CLK_GATED The clock output is gated 8 HSDIVIDER_CLKOUT1_ R W 0h ...

Page 649: ...R M5 divider and hence WDN CLKOUT2 output when the o p clock is gated 0x0 ALWAYS_ACTIVE Keep M5 divider powered on even when CLKOUT2 is gated 0x1 AUTO_PWDN Automatically power down M5 divider when CLKOUT2 is gated 11 10 Reserved R 0h 9 ST_HSDIVIDER_CLKOU R 0h HSDIVIDER CLKOUT2 status T2 0x0 CLK_ENABLED The clock output is enabled 0x1 CLK_GATED The clock output is gated 8 HSDIVIDER_CLKOUT2_ R W 0h ...

Page 650: ...PREAD When SSC is enabled clock frequency is spread on both sides of the programmed frequency 0x1 LOW_SPREAD When SSC is enabled clock frequency is spread only on the lower side of the programmed frequency 13 DPLL_SSC_ACK R 0h Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature 0x0 Disabled SSC has been turned off on PLL o ps 0x1 Enabled SSC has been turned o...

Page 651: ... before the DPLL s frequency lock indicator is asserted This register is used to enable disable the DPLL ramping feature If enabled it is also used to select the algorithm used for clock ramping 0x0 RAMP_DISABLE CLKOUT No ramping CLKOUTX2 No ramping 0x1 RAMP_ALGO1 CLKOUT Bypass clk Fout 8 Fout 4 Fout 2 Fout CLKOUTX2 Bypass clk Foutx2 8 Foutx2 4 Foutx2 2 Foutx2 0x2 RAMP_ALGO2 CLKOUT Bypass clk Fout...

Page 652: ...h sides of the programmed frequency 0x1 LOW_SPREAD When SSC is enabled clock frequency is spread only on the lower side of the programmed frequency 13 DPLL_SSC_ACK R 0h Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature 0x0 Disabled SSC has been turned off on PLL o ps 0x1 Enabled SSC has been turned on on PLL o ps 12 DPLL_SSC_EN R W 0h Enable or disable Spre...

Page 653: ..._SPREAD When SSC is enabled clock frequency is spread on both sides of the programmed frequency 0x1 LOW_SPREAD When SSC is enabled clock frequency is spread only on the lower side of the programmed frequency 13 DPLL_SSC_ACK R 0h Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature 0x0 Disabled SSC has been turned off on PLL o ps 0x1 Enabled SSC has been turned...

Page 654: ...y before the DPLL s frequency lock indicator is asserted This register is used to enable disable the DPLL ramping feature If enabled it is also used to select the algorithm used for clock ramping 0x0 RAMP_DISABLE CLKOUT No ramping CLKOUTX2 No ramping 0x1 RAMP_ALGO1 CLKOUT Bypass clk Fout 8 Fout 4 Fout 2 Fout CLKOUTX2 Bypass clk Foutx2 8 Foutx2 4 Foutx2 2 Foutx2 0x2 RAMP_ALGO2 CLKOUT Bypass clk Fou...

Page 655: ...PREAD When SSC is enabled clock frequency is spread on both sides of the programmed frequency 0x1 LOW_SPREAD When SSC is enabled clock frequency is spread only on the lower side of the programmed frequency 13 DPLL_SSC_ACK R 0h Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature 0x0 Disabled SSC has been turned off on PLL o ps 0x1 Enabled SSC has been turned o...

Page 656: ... before the DPLL s frequency lock indicator is asserted This register is used to enable disable the DPLL ramping feature If enabled it is also used to select the algorithm used for clock ramping 0x0 RAMP_DISABLE CLKOUT No ramping CLKOUTX2 No ramping 0x1 RAMP_ALGO1 CLKOUT Bypass clk Fout 8 Fout 4 Fout 2 Fout CLKOUTX2 Bypass clk Foutx2 8 Foutx2 4 Foutx2 2 Foutx2 0x2 RAMP_ALGO2 CLKOUT Bypass clk Fout...

Page 657: ..._SPREAD When SSC is enabled clock frequency is spread on both sides of the programmed frequency 0x1 LOW_SPREAD When SSC is enabled clock frequency is spread only on the lower side of the programmed frequency 13 DPLL_SSC_ACK R 0h Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature 0x0 Disabled SSC has been turned off on PLL o ps 0x1 Enabled SSC has been turned...

Page 658: ...y before the DPLL s frequency lock indicator is asserted This register is used to enable disable the DPLL ramping feature If enabled it is also used to select the algorithm used for clock ramping 0x0 RAMP_DISABLE CLKOUT No ramping CLKOUTX2 No ramping 0x1 RAMP_ALGO1 CLKOUT Bypass clk Fout 8 Fout 4 Fout 2 Fout CLKOUTX2 Bypass clk Foutx2 8 Foutx2 4 Foutx2 2 Foutx2 0x2 RAMP_ALGO2 CLKOUT Bypass clk Fou...

Page 659: ...elect 2 255 This factor must be set by s w to ensure optimum jitter performance DPLL_SD_DIV CEILING DPLL_MULT DPLL_DIV 1 CLKINP 250 where CLKINP is the input clock of the DPLL in MHz Must be set with M and N factors and must not be changed once DPLL is locked 0x0 Reserved Reserved 0x1 Reserved1 Reserved 23 Reserved R 0h 22 20 Reserved R 0h 19 8 DPLL_MULT R W 0h DPLL multiplier factor 2 to 4095 Thi...

Page 660: ...2_DPLL_DDR Register Field Descriptions Bit Field Type Reset Description 31 10 Reserved R 0h 9 ST_DPLL_CLKOUT R 0h DPLL CLKOUT status 0x0 CLK_GATED The clock output is gated 0x1 CLK_ENABLED The clock output is enabled 8 DPLL_CLKOUT_GATE_C R W 0h Control gating of DPLL CLKOUT TRL 0x0 CLK_AUTOGATE Automatically gate this clock when there is no dependency for it 0x1 CLK_ENABLE Force this clock to stay...

Page 661: ...M2_DPLL_DISP Register Field Descriptions Bit Field Type Reset Description 31 10 Reserved R 0h 9 ST_DPLL_CLKOUT R 0h DPLL CLKOUT status 0x0 CLK_GATED The clock output is gated 0x1 CLK_ENABLED The clock output is enabled 8 DPLL_CLKOUT_GATE_C R W 0h Control gating of DPLL CLKOUT TRL 0x0 CLK_AUTOGATE Automatically gate this clock when there is no dependency for it 0x1 CLK_ENABLE Force this clock to st...

Page 662: ...2_DPLL_MPU Register Field Descriptions Bit Field Type Reset Description 31 10 Reserved R 0h 9 ST_DPLL_CLKOUT R 0h DPLL CLKOUT status 0x0 CLK_GATED The clock output is gated 0x1 CLK_ENABLED The clock output is enabled 8 DPLL_CLKOUT_GATE_C R W 0h Control gating of DPLL CLKOUT TRL 0x0 CLK_AUTOGATE Automatically gate this clock when there is no dependency for it 0x1 CLK_ENABLE Force this clock to stay...

Page 663: ..._M2_DPLL_PER Register Field Descriptions Bit Field Type Reset Description 31 10 Reserved R 0h 9 ST_DPLL_CLKOUT R 0h DPLL CLKOUT status 0x0 CLK_GATED The clock output is gated 0x1 CLK_ENABLED The clock output is enabled 8 DPLL_CLKOUT_GATE_C R W 0h Control gating of DPLL CLKOUT TRL 0x0 CLK_AUTOGATE Automatically gate this clock when there is no dependency for it 0x1 CLK_ENABLE Force this clock to st...

Page 664: ...0h 7 6 5 4 3 2 1 0 Reserved MODULEMODE R 0h R 2h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 136 CM_WKUP_WKUP_M3_CLKCTRL Register Field Descriptions Bit Field Type Reset Description 31 19 Reserved R 0h 18 STBYST R 0h Module standby status 0x0 Func Module is functional not in standby 0x1 Standby Module is in standby 17 2 Reserved R 0h 1 0 MODULEMODE R 2...

Page 665: ...P 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error ex...

Page 666: ...0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error exce...

Page 667: ... OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error...

Page 668: ...ional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module resu...

Page 669: ...ional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module resu...

Page 670: ...ional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module resu...

Page 671: ...ly W1toCl Write 1 to clear bit n value after reset Table 8 143 CM_L4_WKUP_AON_CLKSTCTRL Register Field Descriptions Bit Field Type Reset Description 31 26 Reserved R 0h 25 14 Reserved R 0h 13 8 Reserved R 0h 7 4 Reserved R 0h 3 Reserved R 0h 2 CLKACTIVITY_L4_WKUP R 1h This field indicates the state of the L4_WKUP clock in the domain _AON_GCLK 0x0 Inact Corresponding clock is gated 0x1 Act Correspo...

Page 672: ... including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 2h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results i...

Page 673: ...ered on even when CLKOUT3 is gated 0x1 AUTO_PWDN Automatically power down M6 divider when CLKOUT3 is gated 11 10 Reserved R 0h 9 ST_HSDIVIDER_CLKOU R 0h HSDIVIDER CLKOUT3 status T3 0x0 CLK_ENABLED The clock output is enabled 0x1 CLK_GATED The clock output is gated 8 HSDIVIDER_CLKOUT3_ R W 0h Control gating of HSDIVIDER CLKOUT3 GATE_CTRL 0x0 CLK_AUTOGATE Automatically gate this clock when there is ...

Page 674: ...IMER6 clock warm Section 8 1 12 3 7 reset insensitive 20h CM_CPTS_RFT_CLKSEL Selects the Mux select line for CPTS RFT clock warm Section 8 1 12 3 8 reset insensitive 28h CLKSEL_TIMER1MS_CLK Selects the Mux select line for TIMER1 clock warm Section 8 1 12 3 9 reset insensitive 2Ch CLKSEL_GFX_FCLK Selects the divider value for GFX clock warm reset Section 8 1 12 3 10 insensitive 30h CLKSEL_PRU_ICSS_...

Page 675: ... 6 5 4 3 2 1 0 Reserved CLKSEL R 0h R W 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 147 CLKSEL_TIMER7_CLK Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 0 CLKSEL R W 1h Selects the Mux select line for TIMER7 clock warm reset insensitive 0x0 SEL1 Select TCLKIN clock 0x1 SEL2 Select CLK_M_OSC clock 0x2 SEL3 Select CL...

Page 676: ... 6 5 4 3 2 1 0 Reserved CLKSEL R 0h R W 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 148 CLKSEL_TIMER2_CLK Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 0 CLKSEL R W 1h Selects the Mux select line for TIMER2 clock warm reset insensitive 0x0 SEL1 Select TCLKIN clock 0x1 SEL2 Select CLK_M_OSC clock 0x2 SEL3 Select CL...

Page 677: ... 6 5 4 3 2 1 0 Reserved CLKSEL R 0h R W 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 149 CLKSEL_TIMER3_CLK Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 0 CLKSEL R W 1h Selects the Mux select line for TIMER3 clock warm reset insensitive 0x0 SEL1 Select TCLKIN clock 0x1 SEL2 Select CLK_M_OSC clock 0x2 SEL3 Select CL...

Page 678: ...7 6 5 4 3 2 1 0 Reserved CLKSEL R 0h R W 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 150 CLKSEL_TIMER4_CLK Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 0 CLKSEL R W 1h Selects the Mux select line for TIMER4 clock warm reset insensitive 0x0 SEL1 Select TCLKIN clock 0x1 SEL2 Select CLK_M_OSC clock 0x2 SEL3 Select C...

Page 679: ... MII_CLK_SEL Reserved R 0h R W 1h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 151 CM_MAC_CLKSEL Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 MII_CLK_SEL R W 1h MII Clock Divider Selection This bit is warm reset insensitive when CPSW RESET_ISO is enabled 0x0 SEL0 Selects 1 2 divider of SYSCLK2 0x1 SEL1 Selects 1...

Page 680: ...7 6 5 4 3 2 1 0 Reserved CLKSEL R 0h R W 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 152 CLKSEL_TIMER5_CLK Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 0 CLKSEL R W 1h Selects the Mux select line for TIMER5 clock warm reset insensitive 0x0 SEL1 Select TCLKIN clock 0x1 SEL2 Select CLK_M_OSC clock 0x2 SEL3 Select C...

Page 681: ...7 6 5 4 3 2 1 0 Reserved CLKSEL R 0h R W 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 153 CLKSEL_TIMER6_CLK Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 0 CLKSEL R W 1h Selects the Mux select line for TIMER6 clock warm reset insensitive 0x0 SEL1 Select TCLKIN clock 0x1 SEL2 Select CLK_M_OSC clock 0x2 SEL3 Select C...

Page 682: ... 4 3 2 1 0 Reserved Reserved Reserved CLKSEL R 0h R 0h R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 154 CM_CPTS_RFT_CLKSEL Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 Reserved R 0h 1 Reserved R 0h 0 CLKSEL R W 0h Selects the Mux select line for cpgmac rft clock warm reset insensitive 0x0 SEL1 Selects COR...

Page 683: ...h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 155 CLKSEL_TIMER1MS_CLK Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 0 CLKSEL R W 0h Selects the Mux select line for DMTIMER_1MS clock warm reset insensitive 0x0 SEL1 Select CLK_M_OSC clock 0x1 SEL2 Select CLK_32KHZ clock 0x2 SEL3 Select TCLKIN clock 0x3 SEL4 Sele...

Page 684: ...ad only W1toCl Write 1 to clear bit n value after reset Table 8 156 CLKSEL_GFX_FCLK Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 CLKSEL_GFX_FCLK R W 0h Selects the clock on gfx fclk warm reset insensitive 0x0 SEL0 SGX FCLK is from CORE PLL same as L3 clock 0x1 SEL1 SGX FCLK is from PER PLL 192 MHz clock 0 CLKDIV_SEL_GFX_FCLK R W 0h Selects the divider value on ...

Page 685: ...1 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved CLKSEL R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 157 CLKSEL_PRU_ICSS_OCP_CLK Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 CLKSEL R W 0h Controls Mux Select of PRU ICSS OCP clock mux 0x0 SEL1 Select L3F clock as OCP Clock of PRU ICSS 0x1 SEL2 Select DISP D...

Page 686: ... Reserved R 0h 7 6 5 4 3 2 1 0 Reserved CLKSEL R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 158 CLKSEL_LCDC_PIXEL_CLK Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 0 CLKSEL R W 0h Controls the Mux Select of LCDC PIXEL clock 0x0 SEL1 Select DISP PLL CLKOUTM2 0x1 SEL2 Select CORE PLL CLKOUTM5 0x2 SEL3 Select...

Page 687: ...erved R 0h 7 6 5 4 3 2 1 0 Reserved CLKSEL R 0h R W 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 159 CLKSEL_WDT1_CLK Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 CLKSEL R W 1h Selects the Mux select line for WDT1 clock warm reset insensitive 0x0 SEL1 Select 32KHZ clock from RC Oscillator 0x1 SEL2 Select 32KHZ from...

Page 688: ...e 0x0 SEL1 Select 32KHZ clock from RC Oscillator 0x1 SEL2 Select 32KHZ from 32K Crystal Oscillator 0x2 SEL3 Select 32KHz from Clock Divider 8 1 12 4 CM_MPU Registers Table 8 161 lists the memory mapped registers for the CM_MPU All register offset addresses not listed in Table 8 161 should be considered as reserved locations and the register contents should not be modified Table 8 161 CM_MPU REGIST...

Page 689: ...Read only W1toCl Write 1 to clear bit n value after reset Table 8 162 CM_MPU_CLKSTCTRL Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 CLKACTIVITY_MPU_CLK R 1h This field indicates the state of the MPU Clock 0x0 Inact Corresponding clock is gated 0x1 Act Corresponding clock is active 1 0 CLKTRCTRL R W 2h Controls the clock state transition of the MPU clock domains...

Page 690: ...ng separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 2h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except if resulting from a module wakeup asynchronous wakeup 0x1 RESERVED_1 Reserved 0x2 ENABLE Module is explicitly enabled Interface clock if not u...

Page 691: ... ti com Power Reset and Clock Management 691 SPRUH73H October 2011 Revised April 2013 Power Reset and Clock Management PRCM Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 692: ...led 0x1 EN SYS_CLKOUT2 is enabled 6 Reserved R 0h 5 3 CLKOUT2DIV R W 0h THis field controls the external clock divison factor 0x0 DIV1 SYS_CLKOUT2 1 0x1 DIV2 SYS_CLKOUT2 2 0x2 DIV3 SYS_CLKOUT2 3 0x3 DIV4 SYS_CLKOUT2 4 0x4 DIV5 SYS_CLKOUT2 5 0x5 DIV6 SYS_CLKOUT2 6 0x6 DIV7 SYS_CLKOUT2 7 0x7 Reserved 2 0 CLKOUT2SOURCE R W 0h This field selects the external output clock source 0x0 SEL0 Select 32KHz O...

Page 693: ...TCTRL This register enables the domain power state transition Section 8 1 12 6 2 It controls the SW supervised clock domain state transition between ON ACTIVE and ON INACTIVE states It also hold one status bit per clock input of the domain 693 SPRUH73H October 2011 Revised April 2013 Power Reset and Clock Management PRCM Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorpora...

Page 694: ...uding OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 2h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an ...

Page 695: ... R 0h 10 Reserved R 0h 9 CLKACTIVITY_RTC_32K R 0h This field indicates the state of the 32K RTC clock in the domain CLK 0x0 Inact 0x1 Act 8 CLKACTIVITY_L4_RTC_ R 1h This field indicates the state of the L4 RTC clock in the domain GCLK 0x0 Inact Corresponding clock is gated 0x1 Act Corresponding clock is active 7 2 Reserved R 0h 1 0 CLKTRCTRL R W 2h Controls the clock state transition of the RTC cl...

Page 696: ...locks Section 8 1 12 7 2 Ch CM_GFX_L4LS_GFX_CLKSTCTR This register enables the domain power state transition Section 8 1 12 7 3 L It controls the SW supervised clock domain state transition between ON ACTIVE and ON INACTIVE states It also hold one status bit per clock input of the domain 10h CM_GFX_MMUCFG_CLKCTRL This register manages the MMU CFG clocks Section 8 1 12 7 4 14h CM_GFX_MMUDATA_CLKCTR...

Page 697: ...d Descriptions Bit Field Type Reset Description 31 26 Reserved R 0h 25 10 Reserved R 0h 9 CLKACTIVITY_GFX_FCL R 0h This field indicates the state of the GFX_GCLK clock in the domain K 0x0 Inact Corresponding clock is gated 0x1 Act Corresponding clock is active 8 CLKACTIVITY_GFX_L3_ R 0h This field indicates the state of the GFX_L3_GCLK clock in the GCLK domain 0x0 Inact Corresponding clock is gate...

Page 698: ... status 0x0 Func Module is fully functional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disab...

Page 699: ...ead Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 172 CM_GFX_L4LS_GFX_CLKSTCTRL Register Field Descriptions Bit Field Type Reset Description 31 9 Reserved R 0h 8 CLKACTIVITY_L4LS_GF R 1h This field indicates the state of the L4_LS clock in the domain X_GCLK 0x0 Inact 0x1 Act 7 2 Reserved R 0h 1 0 CLKTRCTRL R W 2h Controls the clock state transition of the L4LS clock dom...

Page 700: ...CP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error e...

Page 701: ...way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module results in an error except if resulting from a module wakeup asynchronous wakeup 0x1 RESERVED_1 Reserved 0x2 ENABLE Module is explicitly enabled Interface clock if not used for functions may be gated according to the clock domain state Functional clocks are guarantied to stay present As long as in this c...

Page 702: ...ffset Acronym Register Name Section 20h CM_CEFUSE_CEFUSE_CLKCTR This register manages the CEFUSE clocks Section 8 1 12 8 2 L 702 Power Reset and Clock Management PRCM SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 703: ...R 0h This field indicates the state of the Cust_Efuse_SYSCLK clock input USE_SYS_CLK of the domain warm reset insensitive 0x0 Inact Corresponding clock is definitely gated 0x1 Act Corresponding clock is running or gating ungating transition is on going 8 CLKACTIVITY_L4_CEFU R 0h This field indicates the state of the L4_CEFUSE_GCLK clock input of SE_GICLK the domain warm reset insensitive 0x0 Inact...

Page 704: ...ional including OCP 0x1 Trans Module is performing transition wakeup or sleep or sleep abortion 0x2 Idle Module is in Idle mode only OCP part It is functional if using separate functional clock 0x3 Disable Module is disabled and cannot be accessed 15 2 Reserved R 0h 1 0 MODULEMODE R W 0h Control the way mandatory clocks are managed 0x0 DISABLED Module is disable by SW Any OCP access to module resu...

Page 705: ...eration for the event is enabled or not SW is required to clear a set bit by writing a 1 into the bit position to be cleared 8h PRM_IRQENABLE_MPU This register is used to enable and disable events used Section 8 1 13 1 3 to trigger MPU interrupt activation Ch PRM_IRQSTATUS_M3 This register provides status on MPU interrupt events Section 8 1 13 1 4 An event is logged whether interrupt generation fo...

Page 706: ... 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Rev R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 179 REVISION_PRM Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h Reads returns 0 7 0 Rev R 0h IP revision 7 4 Major revision 3 0 Minor revision Examples 0x10 for 1 0 0x21 for 2 1 706 Power Reset and Clock Manageme...

Page 707: ...nterrupt status for usb dpll recaliberation 0 DIS Disables dpll recaliberation 1 EN ENAbles dpll recaliberation 14 dpll_ddr_recal_st R W 0h interrupt status for ddr dpll recaliberation 0 DIS Disables dpll recaliberation 1 EN ENAbles dpll recaliberation 13 dpll_disp_recal_st R W 0h interrupt status for disp dpll recaliberation 0 DIS Disables dpll recaliberation 1 EN ENAbles dpll recaliberation 12 d...

Page 708: ...tion 1 EN ENAbles dpll recaliberation 14 dpll_ddr_recal_en R W 0h Interrupt enable for ddr dpll recaliberation 0 DIS Disables dpll recaliberation 1 EN ENAbles dpll recaliberation 13 dpll_per_recal_en R W 0h Interrupt enable for usb dpll recaliberation 0 DIS Disables dpll recaliberation 1 EN ENAbles dpll recaliberation 12 dpll_core_recal_en R W 0h Interrupt enable for core dpll recaliberation 0 DIS...

Page 709: ...errupt status for usb dpll recaliberation 0 DIS Disables dpll recaliberation 1 EN ENAbles dpll recaliberation 14 dpll_ddr_recal_st R W 0h interrupt status for ddr dpll recaliberation 0 DIS Disables dpll recaliberation 1 EN ENAbles dpll recaliberation 13 dpll_disp_recal_st R W 0h interrupt status for disp dpll recaliberation 0 DIS Disables dpll recaliberation 1 EN ENAbles dpll recaliberation 12 dpl...

Page 710: ...ion 1 EN ENAbles dpll recaliberation 14 dpll_ddr_recal_en R W 0h Interrupt enable for ddr dpll recaliberation 0 DIS Disables dpll recaliberation 1 EN ENAbles dpll recaliberation 13 dpll_per_recal_en R W 0h Interrupt enable for usb dpll recaliberation 0 DIS Disables dpll recaliberation 1 EN ENAbles dpll recaliberation 12 dpll_core_recal_en R W 0h Interrupt enable for core dpll recaliberation 0 DIS ...

Page 711: ... Offset Acronym Register Name Section 0h RM_PER_RSTCTRL This register controls the release of the PER Domain Section 8 1 13 2 1 resets 8h PM_PER_PWRSTST This register provides a status on the current PER power Section 8 1 13 2 2 domain state warm reset insensitive Ch PM_PER_PWRSTCTRL Controls the power state of PER power domain Section 8 1 13 2 3 711 SPRUH73H October 2011 Revised April 2013 Power ...

Page 712: ...eserved PRU_ICSS_LRST Reserved R 0h R 0h R 0h R W 1h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 185 RM_PER_RSTCTRL Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 3 Reserved R 0h 2 Reserved R 0h 1 PRU_ICSS_LRST R W 1h PER domain PRU ICSS local reset control 0x0 CLEAR Reset is cleared for the PRU ICSS 0x1 ASSERT R...

Page 713: ...escription 31 25 Reserved R 0h 24 23 pru_icss_mem_statest R 3h PRU ICSS memory state status 0x0 Mem_off Memory is OFF 0x2 Reserved Reserved 0x3 Mem_on Memory is ON 22 21 ram_mem_statest R 3h OCMC RAM memory state status 0x0 Mem_off Memory is OFF 0x2 Reserved Reserved 0x3 Mem_on Memory is ON 20 InTransition R 0h Domain transition status 0x0 No No on going transition on power domain 0x1 Ongoing Powe...

Page 714: ...ons Bit Field Type Reset Description 31 30 ram_mem_ONState R W 3h OCMC RAM memory on state 0x0 OFF Memory is OFF 0x1 RET Memory is in retention state 0x2 RESERVED 0x3 ON Memory is ON 29 PER_mem_RETState R W 1h Other memories in PER Domain RET state 0x0 OFF 0x1 RET 28 Reserved R 0h 27 ram_mem_RETState R W 1h OCMC RAM memory RET state 0x0 OFF Memory is in off state 0x1 RET Memory is in retention sta...

Page 715: ...trol 0x0 OFF 0x1 RET 0x2 Reserved 0x3 ON 8 1 13 3 PRM_WKUP Registers Table 8 188 lists the memory mapped registers for the PRM_WKUP All register offset addresses not listed in Table 8 188 should be considered as reserved locations and the register contents should not be modified Table 8 188 PRM_WKUP REGISTERS Offset Acronym Register Name Section 0h RM_WKUP_RSTCTRL This register controls the releas...

Page 716: ... 4 3 2 1 0 Reserved Reserved WKUP_M3_LRST Reserved R 0h R 0h R W 1h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 189 RM_WKUP_RSTCTRL Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 4 Reserved R 0h 3 WKUP_M3_LRST R W 1h Assert Reset to WKUP_M3 0x0 CLEAR Reset is cleared for the M3 0x1 ASSERT Reset is asserted for th...

Page 717: ...erved R 0h 29 Reserved R 0h 28 Reserved R 0h 27 Reserved R 0h 26 25 Reserved R 0h 24 5 Reserved R 0h 4 LowPowerStateChange R W 0h Power state change request when domain has already performed a sleep transition Allows going into deeper low power state without waking up the power domain 0x0 DIS Do not request a low power state change 0x1 EN Request a low power state change This bit is automatically ...

Page 718: ...e R Read only W1toCl Write 1 to clear bit n value after reset Table 8 191 PM_WKUP_PWRSTST Register Field Descriptions Bit Field Type Reset Description 31 23 Reserved R 0h 22 21 Reserved R 0h 20 InTransition R 0h Domain transition status 0x0 No No on going transition on power domain 0x1 Ongoing Power domain transition is in progress 19 Reserved R 0h 18 17 Debugss_mem_statest R 3h WKUP domain memory...

Page 719: ...n reset source e g assert reset command initiated by the icepick module 0x0 RESET_NO No reset 0x1 RESET_YES M3 Processor has been reset 5 WKUP_M3_LRST R W 0h M3 Processor has been reset 0x0 RESET_NO No reset 0x1 RESET_YES M3 Processor has been reset 4 0 Reserved R 0h 8 1 13 4 PRM_MPU Registers Table 8 193 lists the memory mapped registers for the PRM_MPU All register offset addresses not listed in...

Page 720: ...er Reset and Clock Management www ti com 720 Power Reset and Clock Management PRCM SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 721: ...n is in retention 22 mpu_l1_RETState R W 1h Default power domain memory L1 retention state when power domain is in retention 21 20 MPU_L2_ONState R 3h Default power domain memory state when domain is ON 19 18 MPU_L1_ONState R 3h Default power domain memory state when domain is ON 17 16 MPU_RAM_ONState R W 3h Default power domain memory state when domain is ON 0x0 Mem_off 0x2 Reserved 0x3 Mem_on Me...

Page 722: ...continued Bit Field Type Reset Description 1 0 PowerState R W 3h Power state control 0x0 OFF OFF State 0x1 RET 0x2 Reserved 0x3 ON ON State 722 Power Reset and Clock Management PRCM SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 723: ...h 20 InTransition R 0h Domain transition status 0x0 No No on going transition on power domain 0x1 Ongoing Power domain transition is in progress 19 10 Reserved R 0h 9 8 MPU_L2_StateSt R 1h MPU L2 memory state status 0x0 Mem_off Memory is OFF 0x2 Reserved Reserved 0x3 Mem_on Memory is ON 7 6 MPU_L1_StateSt R 1h MPU L1 memory state status 0x0 Mem_off Memory is OFF 0x2 Reserved Reserved 0x3 Mem_on Me...

Page 724: ...CRUSHER_MPU_RS R W 0h MPU Processor has been reset due to MPU ICECRUSHER1 reset T event 0x0 RESET_NO No icecrusher reset 0x1 RESET_YES MPU Processor has been reset upon icecursher reset 5 EMULATION_MPU_RST R W 0h MPU Processor has been reset due to emulation reset source e g assert reset command initiated by the icepick module 0x0 RESET_NO No emulation reset 0x1 RESET_YES MPU Processor has been re...

Page 725: ... 13 5 4 10h PRM_LDO_SRAM_CORE_SETUP Section 8 1 13 5 5 14h PRM_LDO_SRAM_CORE_CTRL Section 8 1 13 5 6 18h PRM_LDO_SRAM_MPU_SETUP Section 8 1 13 5 7 1Ch PRM_LDO_SRAM_MPU_CTRL Section 8 1 13 5 8 725 SPRUH73H October 2011 Revised April 2013 Power Reset and Clock Management PRCM Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 726: ...RSTCTRL Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 RST_GLOBAL_COLD_S R W 0h Global COLD software reset control W This bit is reset only upon a global cold source of reset Read returns 0 0x0 0x0 Global COLD software reset is cleared 0x1 0x1 Asserts a global COLD software reset The software must ensure the SDRAM is properly put in sef refresh mode before applyi...

Page 727: ...2 R 0h R W 10h 7 6 5 4 3 2 1 0 RSTTIME1 R W 6h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 199 PRM_RSTTIME Register Field Descriptions Bit Field Type Reset Description 31 13 Reserved R 0h 12 8 RSTTIME2 R W 10h Power domain reset duration 2 number of CLK_M_OSC clock cycles 7 0 RSTTIME1 R W 6h Global reset duration 1 number of CLK_M_OSC clock cycles 727 ...

Page 728: ...K_RST R W 0h IcePick reset event This is a source of global warm reset initiated by the emulation warm reset insensitive 0x0 0x0 No ICEPICK reset 0x1 0x1 IcePick reset has occurred 8 6 Reserved R 0h 5 EXTERNAL_WARM_RST R W 0h External warm reset event warm reset insensitive 0x0 0x0 No global warm reset 0x1 0x1 Global external warm reset has occurred 4 WDT1_RST R W 0h Watchdog1 timer reset event Th...

Page 729: ...it Field Type Reset Description 31 24 StartUp_Count R W 78h Determines the start up duration of SRAM and ABB LDO The duration is computed as 16 x NbCycles of system clock cycles Target is 50us 23 16 SLPCNT_VALUE R W 0h Delay between retention off assertion of last SRAM bank and SRAMALLRET signal to LDO is driven high Counting on system clock Target is 2us 15 8 VSETUPCNT_VALUE R W 0h SRAM LDO rampu...

Page 730: ...ntion is a one step transfer 0x1 Two_step Active to retention is a two steps transfer 6 ENFUNC4 R W 0h ENFUNC4 input of SRAM LDO 0x0 Ext_clock One external clock is supplied 0x1 No_ext_clock No external clock is supplied 5 ENFUNC3_EXPORT R W 0h ENFUNC3 input of SRAM LDO After PowerOn reset and Efuse sensing this bitfield is automatically loaded with an Efuse value from control module Bitfield rema...

Page 731: ...ied by VDDS or VDDAR during active mode After PowerOn reset and Efuse sensing this bitfield is automatically loaded with an Efuse value from control module Bitfield remains writable after this 0x0 SRAMNW_ACT_VDDS SRAMNWA supplied with VDDS 0x1 Read SRAMNW_ACT_VDDASRAMNWA supplied with VDDAR 0 DISABLE_RTA_EXPORT R W 0h Control for HD memory RTA feature After PowerOn reset and Efuse sensing this bit...

Page 732: ...e 8 203 PRM_LDO_SRAM_CORE_CTRL Register Field Descriptions Bit Field Type Reset Description 31 10 Reserved R 0h 9 SRAM_IN_TRANSITION R 0h Status indicating SRAM LDO state machine state 0x0 IDLE SRAM LDO state machine is stable 0x1 IN_TRANSITION SRAM LDO state machine is in transition state 8 SRAMLDO_STATUS R 0h SRAMLDO status 0x0 ACTIVE SRAMLDO is in ACTIVE mode 0x1 RETENTION SRAMLDO is on RETENTI...

Page 733: ...ion is a one step transfer 0x1 Two_step Active to retention is a two steps transfer 6 ENFUNC4 R W 0h ENFUNC4 input of SRAM LDO 0x0 Ext_clock One external clock is supplied 0x1 No_ext_clock No external clock is supplied 5 ENFUNC3_EXPORT R W 0h ENFUNC3 input of SRAM LDO After PowerOn reset and Efuse sensing this bitfield is automatically loaded with an Efuse value from control module Bitfield remain...

Page 734: ...ied by VDDS or VDDAR during active mode After PowerOn reset and Efuse sensing this bitfield is automatically loaded with an Efuse value from control module Bitfield remains writable after this 0x0 SRAMNW_ACT_VDDS SRAMNWA supplied with VDDS 0x1 Read SRAMNW_ACT_VDDASRAMNWA supplied with VDDAR 0 DISABLE_RTA_EXPORT R W 0h Control for HD memory RTA feature After PowerOn reset and Efuse sensing this bit...

Page 735: ...on state 8 SRAMLDO_STATUS R 0h SRAMLDO status 0x0 ACTIVE SRAMLDO is in ACTIVE mode 0x1 RETENTION SRAMLDO is on RETENTION mode 7 1 Reserved R 0h 0 RETMODE_ENABLE R W 0h Control if the SRAM LDO retention mode is used or not 0x0 Disabled SRAM LDO is not allowed to go to RET mode 0x1 Enabled SRAM LDO go to RET mode when all memory of voltage domain are OFF or RET 8 1 13 6 PRM_RTC Registers Table 8 206...

Page 736: ...er Reset and Clock Management www ti com 736 Power Reset and Clock Management PRCM SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 737: ...ription 31 26 Reserved R 0h 25 16 Reserved R 0h 15 5 Reserved R 0h 4 LowPowerStateChange R W 0h Power state change request when domain has already performed a sleep transition Allows going into deeper low power state without waking up the power domain 0x0 DIS Do not request a low power state change 0x1 EN Request a low power state change This bit is automatically cleared when the power state is ef...

Page 738: ...eSt R 1h Logic state status 0x0 OFF Logic in domain is OFF 0x1 ON Logic in domain is ON 1 0 Reserved R 0h 8 1 13 7 PRM_GFX Registers Table 8 209 lists the memory mapped registers for the PRM_GFX All register offset addresses not listed in Table 8 209 should be considered as reserved locations and the register contents should not be modified Table 8 209 PRM_GFX REGISTERS Offset Acronym Register Nam...

Page 739: ... ti com Power Reset and Clock Management 739 SPRUH73H October 2011 Revised April 2013 Power Reset and Clock Management PRCM Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 740: ...R 3h GFX memory state when domain is ON 16 7 Reserved R 0h 6 GFX_MEM_RETState R W 1h 5 Reserved R 0h 4 LowPowerStateChange R W 0h Power state change request when domain has already performed a sleep transition Allows going into deeper low power state without waking up the power domain 0x0 DIS Do not request a low power state change 0x1 EN Request a low power state change This bit is automatically ...

Page 741: ...erved Reserved Reserved GFX_RST R 0h R 0h R 0h R W 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 8 211 RM_GFX_RSTCTRL Register Field Descriptions Bit Field Type Reset Description 31 4 Reserved R 0h 3 2 Reserved R 0h 1 Reserved R 0h 0 GFX_RST R W 1h GFX domain local reset control 0x0 CLEAR Reset is cleared for the GFX Domain SGX530 0x1 ASSERT Reset is as...

Page 742: ...fter reset Table 8 212 PM_GFX_PWRSTST Register Field Descriptions Bit Field Type Reset Description 31 21 Reserved R 0h 20 InTransition R 0h Domain transition status 0x0 No No on going transition on power domain 0x1 Ongoing Power domain transition is in progress 19 6 Reserved R 0h 5 4 GFX_MEM_StateSt R 1h GFX memory state status 0x0 Mem_off Memory is OFF 0x2 Reserved Reserved 0x3 Mem_on Memory is O...

Page 743: ...1 12 Reserved R 0h 11 2 Reserved R 0h 1 Reserved R 0h 0 GFX_RST R W 0h GFX Domain Logic Reset 0x0 RESET_NO No SW reset occured 0x1 RESET_YES GFX Domain Logic has been reset upon SW reset 8 1 13 8 PRM_CEFUSE Registers Table 8 214 lists the memory mapped registers for the PRM_CEFUSE All register offset addresses not listed in Table 8 214 should be considered as reserved locations and the register co...

Page 744: ...able 8 215 PM_CEFUSE_PWRSTCTRL Register Field Descriptions Bit Field Type Reset Description 31 5 Reserved R 0h 4 LowPowerStateChange R W 0h Power state change request when domain has already performed a sleep transition Allows going into deeper low power state without waking up the power domain 0x0 DIS Do not request a low power state change 0x1 EN Request a low power state change This bit is auto...

Page 745: ...eset Description 31 26 Reserved R 0h 25 24 LastPowerStateEntered R W 0h Last low power state entered Set to 0x3 upon write of the same only This register is intended for debug purpose only 0x0 OFF Power domain was previously OFF 0x1 ON Power domain was previously ON ACTIVE 23 21 Reserved R 0h 20 InTransition R 0h Domain transition status 0x0 No No on going transition on power domain 0x1 Ongoing Po...

Page 746: ... describes the control module of the device Topic Page 9 1 Introduction 747 9 2 Functional Description 747 9 3 CONTROL_MODULE Registers 757 746 Control Module SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 747: ...bit field reflects the state of the sys_boot pins captured at POR in the PRCM module 9 2 2 Pad Control Registers The Pad Control Registers are 32 bit registers to control the signal muxing and other aspects of each I O pad After POR software must set the pad functional multiplexing and configuration registers to the desired values according to the requested device configuration The configuration i...

Page 748: ...gured in output mode it is recommended for user software to disable any internal pull resistor tied to it to avoid unnecessary consumption The following table summarizes the various possible combinations of PULLTYPESEL and PULLUDEN fields of PAD control register Table 9 3 Pull Selection PULL TYPE Pin Behavior PULLTYPESEL PULLUDENABLE 0b 0b Pulldown selected and activated 0b 1b Pulldown selected bu...

Page 749: ...ping When this is set TINT0 interrupt event will trigger the channel 24 Please note that once this is set The SDTXEVT0 can no longer be handled by EDMA The user has to allocate the correct DMA event number for crossbar mapped events so that there is no compromise on the channel allocation for the used event numbers 9 2 4 Device Control and Status 9 2 4 1 Control and Boot Status The device configur...

Page 750: ...priority 9 2 4 4 Peripheral Control and Status 9 2 4 4 1 USB Control and Status The USB_CTRLn and USB_STSn registers reflect the Control and Status of the USB instances The USB IO lines can be used as UART TX and RX lines the USB Control register bit field GPIOMODE has settings that configures the USB lines as GPIO lines The other USB PHY control settings for controlling the OTG settings and PHY a...

Page 751: ...ction during normal operation ensure that the PHY and charger are enabled and the automatic detection is turned on Then initiate a charger detection cycle by transitioning CHGDET_RSTRT from 1 to 0 If a Charging Downstream Port or a Dedicated Charging Port is detected the charger enable signal USBx_CE will be driven high and remain high until the charger is disabled by either CHGDET_DIS 1 or CHGDET...

Page 752: ...register RESET_ISO has an ISO_CONTROL field which controls the reset isolation feature If the reset isolation is enabled any warm reset source will be blocked to the EMAC switch If the EMAC reset isolation is NOT active default state then the warm reset sources are allowed to propagate as normal including to the EMAC Switch module both reset inputs to the IP All cold or POR resets will always prop...

Page 753: ...ut from IO signal eCAP1 IO pin eCAP1 For eCAP 2 MUX input from IO signal eCAP2 IO pin eCAP2 1 UART0 UART0INT 2 UART1 UART1INT 3 UART2 UART2INT 4 UART3 UART3INT 5 UART4 UART4INT 6 UART5 UART5INT 7 3PGSW 3PGSWRXTHR0 8 3PGSW 3PGSWRXINT0 9 3PGSW 3PGSWTXINT0 10 3PGSW 3PGSWMISC0 11 McASP0 MCATXINT0 12 McASP0 MCARXINT0 13 McASP1 MCATXINT1 14 McASP1 MCARXINT1 15 Reserved Reserved 16 Reserved Reserved 17 G...

Page 754: ...Functional Description www ti com 754 Control Module SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 755: ...ent This pin is the external hardware trigger to start the ADC channel conversion The ADC_EVT_CAPT register needs to programmed to select the proper source for this conversion Figure 9 3 Timer Events The following table contains the value to be programmed in the selection mux Table 9 6 Selection Mux Values ADC_EVENT_SEL Value ADC External event selected 000 PRU ICSS Host Event 0 001 Timer 4 Event ...

Page 756: ... 1 Drv8 Rext Iout 50 ohms 8 mA 1 0 0 Drv9 0 88 Rext 1 125 Iout 44 ohms 9 mA 1 0 1 Drv10 0 8 Rext 1 250 Iout 40 ohms 10 mA 1 1 0 Drv11 0 73 Rext 1 375 Iout 36 ohms 11 mA 1 1 1 Drv12 0 67 Rext 1 5 Iout 33 ohms 12 mA 1 These values are programmed in the following registers ddr_cmd0_ioctrl ddr_cmd1_ioctrl ddr_cmd2_ioctrl ddr_data0_ioctrl ddr_data1_ioctrl 2 Values for DDR_CMDx_IOCTRL io_config_i_clk sh...

Page 757: ...ivratio_ctrl Section 9 3 8 448h bandgap_ctrl Section 9 3 9 44Ch bandgap_trim Section 9 3 10 458h pll_clkinpulow_ctrl Section 9 3 11 468h mosc_ctrl Section 9 3 12 470h deepsleep_ctrl Section 9 3 13 50Ch dpll_pwr_sw_status Section 9 3 14 600h device_id Section 9 3 15 604h dev_feature Section 9 3 16 608h init_priority_0 Section 9 3 17 60Ch init_priority_1 Section 9 3 18 610h mmu_cfg Section 9 3 19 61...

Page 758: ...on 9 3 51 808h conf_gpmc_ad2 Section 9 3 51 80Ch conf_gpmc_ad3 Section 9 3 51 810h conf_gpmc_ad4 Section 9 3 51 814h conf_gpmc_ad5 Section 9 3 51 818h conf_gpmc_ad6 Section 9 3 51 81Ch conf_gpmc_ad7 Section 9 3 51 820h conf_gpmc_ad8 Section 9 3 51 824h conf_gpmc_ad9 Section 9 3 51 828h conf_gpmc_ad10 Section 9 3 51 82Ch conf_gpmc_ad11 Section 9 3 51 830h conf_gpmc_ad12 Section 9 3 51 834h conf_gpm...

Page 759: ...3 51 8CCh conf_lcd_data11 Section 9 3 51 8D0h conf_lcd_data12 Section 9 3 51 8D4h conf_lcd_data13 Section 9 3 51 8D8h conf_lcd_data14 Section 9 3 51 8DCh conf_lcd_data15 Section 9 3 51 8E0h conf_lcd_vsync Section 9 3 51 8E4h conf_lcd_hsync Section 9 3 51 8E8h conf_lcd_pclk Section 9 3 51 8ECh conf_lcd_ac_bias_en Section 9 3 51 8F0h conf_mmc0_dat3 Section 9 3 51 8F4h conf_mmc0_dat2 Section 9 3 51 8...

Page 760: ... 51 988h conf_i2c0_sda Section 9 3 51 98Ch conf_i2c0_scl Section 9 3 51 990h conf_mcasp0_aclkx Section 9 3 51 994h conf_mcasp0_fsx Section 9 3 51 998h conf_mcasp0_axr0 Section 9 3 51 99Ch conf_mcasp0_ahclkr Section 9 3 51 9A0h conf_mcasp0_aclkr Section 9 3 51 9A4h conf_mcasp0_fsr Section 9 3 51 9A8h conf_mcasp0_axr1 Section 9 3 51 9ACh conf_mcasp0_ahclkx Section 9 3 51 9B0h conf_xdma_event_intr0 S...

Page 761: ...9 3 68 FC4h tpcc_evt_mux_52_55 Section 9 3 69 FC8h tpcc_evt_mux_56_59 Section 9 3 70 FCCh tpcc_evt_mux_60_63 Section 9 3 71 FD0h timer_evt_capt Section 9 3 72 FD4h ecap_evt_capt Section 9 3 73 FD8h adc_evt_capt Section 9 3 74 1000h reset_iso Section 9 3 75 1318h dpll_pwr_sw_ctrl Section 9 3 76 131Ch ddr_cke_ctrl Section 9 3 77 1320h sma2 Section 9 3 78 1324h m3_txev_eoi Section 9 3 79 1328h ipc_ms...

Page 762: ...r Field Descriptions Bit Field Type Reset Description 31 30 ip_rev_scheme R 0h 01 New Scheme 29 28 Reserved R 0h 27 16 ip_rev_func R 0h Function indicates a software compatible module family If there is no level of software compatibility a new Func number and hence REVISION should be assigned 15 11 ip_rev_rtl R 0h RTL Version R 10 8 ip_rev_major R 0h Major Revision X 7 6 ip_rev_custom R 0h Indicat...

Page 763: ...1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ip_hwinfo R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 12 control_hwinfo Register Field Descriptions Bit Field Type Reset Description 31 0 ip_hwinfo R 0h IP Module dependent 763 SPRUH73H October 2011 Revised April 2013 Control Module Submit Documentation Feedback Copyright 2011 2013 Texas Instr...

Page 764: ...nfig Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 4 standby R 0h Configure local initiator state management 00 Force Standby 01 No Standby Mode 10 Smart Standby 11 Smart Standby wakeup capable Reserved in Control Module since it has no local initiator 3 2 idlemode R W 0h Configure local target state management 00 Force Idle 01 No Idle 10 Smart Idle 11 Smart Idl...

Page 765: ...SBOOT Configuration Pins for more information Reset value is from SYSBOOT 13 12 19 18 admux R W 0h GPMC CS0 Default Address Muxing 00 No Addr Data Muxing 01 Addr Addr Data Muxing 10 Addr Data Muxing 11 Reserved Reset value is from SYSBOOT 11 10 17 waiten R W 0h GPMC CS0 Default Wait Enable 0 Ignore WAIT input 1 Use WAIT input See SYSBOOT Configuration Pins for more information Reset value is from ...

Page 766: ...TYPE R W 0h SDRAM Type selection 000 Reserved 001 LPDDR1 010 DDR2 011 DDR3 100 Reserved 101 Reserved 110 Reserved 111 Reserved 28 27 IBANK_POS R W 0h Internal bank position 00 All Bank Address bits assigned from OCP address above column address bits 01 Bank Address bits 1 0 assigned from OCP address above column address bits and bit 2 from OCP address bits above row address bits 10 Bank Address bi...

Page 767: ...r DDR2 Value of 2 4 6 8 10 12 and 14 CAS latency of 5 6 7 8 9 10 and 11 are supported for DDR3 All other values are reserved 9 7 ROWSIZE R W 0h Row Size Defines the number of row address bits of connected SDRAM devices Set to 0 for 9 row bits set to 1 for 10 row bits set to 2 for 11 row bits set to 3 for 12 row bits set to 4 for 13 row bits set to 5 for 14 row bits set to 6 for 15 row bits and set...

Page 768: ... vset R W 0h 15 14 13 12 11 10 9 8 Reserved R W 0h 7 6 5 4 3 2 1 0 Reserved R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 16 core_sldo_ctrl Register Field Descriptions Bit Field Type Reset Description 31 26 Reserved R W 0h 25 16 vset R W 0h Trims VDDAR 15 0 Reserved R W 0h 768 Control Module SPRUH73H October 2011 Revised April 2013 Submit Document...

Page 769: ... vset R W 0h 15 14 13 12 11 10 9 8 Reserved R W 0h 7 6 5 4 3 2 1 0 Reserved R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 17 mpu_sldo_ctrl Register Field Descriptions Bit Field Type Reset Description 31 26 Reserved R W 0h 25 16 vset R W 0h Trims VDDAR 15 0 Reserved R W 0h 769 SPRUH73H October 2011 Revised April 2013 Control Module Submit Documenta...

Page 770: ...6 5 4 3 2 1 0 Reserved clkdivopp50_en R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 18 clk32kdivratio_ctrl Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 clkdivopp50_en R W 0h 0 OPP100 operation use ratio for 24MHz to 32KHz division 1 OPP50 operation use ratio for 12MHz to 32KHz division 770 Control Module S...

Page 771: ...ature data from ADC To be used when end of conversion EOCZ is 0 7 cbiassel R W 0h 0 Select bandgap voltage as reference 1 Select resistor divider as reference 6 bgroff R W 0h 0 Normal operation 1 Bandgap is OFF OFF Mode 5 tmpsoff R W 0h 0 Normal operation 1 Temperature sensor is off and thermal shutdown in OFF mode 4 soc R W 0h ADC start of conversion Transition to high starts a new ADC conversion...

Page 772: ...c R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 20 bandgap_trim Register Field Descriptions Bit Field Type Reset Description 31 24 dtrbgapc R W 0h trim the output voltage of bandgap 23 16 dtrbgapv R W 0h trim the output voltage of bandgap 15 8 dtrtemps R W 0h trim the temperature sensor 7 0 dtrtempsc R W 0h trim the temperature sensor 772 Control ...

Page 773: ...Read only W1toCl Write 1 to clear bit n value after reset Table 9 21 pll_clkinpulow_ctrl Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 ddr_pll_clkinpulow_sel R W 0h 0 Select CORE_CLKOUT_M6 clock as CLKINPULOW 1 Select PER_CLKOUT_M2 clock as CLKINPULOW 1 disp_pll_clkinpulow_sel R W 0h 0 Select CORE_CLKOUT_M6 clock as CLKINPULOW 1 Select PER_CLKOUT_M2 clock as CLK...

Page 774: ...ead only W1toCl Write 1 to clear bit n value after reset Table 9 22 mosc_ctrl Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 resselect R W 0h For oscillation with a crystal while RESSELECT is 1 an external resistor must be connected between padxi and padxo to provide bias 0 1 MHz ohm resistor is connected between padxi and padxo for oscillator bias 1 Internal res...

Page 775: ... W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 23 deepsleep_ctrl Register Field Descriptions Bit Field Type Reset Description 31 18 Reserved R 0h 17 dsenable R W 0h Deep sleep enable 0 Normal operation 1 Master oscillator output is gated 16 Reserved R 0h 15 0 dscount R W 0h Programmable count of how many CLK_M_OSC clocks needs to be seen before exit...

Page 776: ...us Register Field Descriptions Bit Field Type Reset Description 31 26 Reserved R 0h 25 pgoodout_ddr R 0h Power Good status for DDR DPLL 0 Power Fault 1 Power Good 24 ponout_ddr R 0h Power Enable status for DDR DPLL 0 Disabled 1 Enabled 23 18 Reserved R 0h 17 pgoodout_disp R 0h Power Good status for DISP DPLL 0 Power Fault 1 Power Good 16 ponout_disp R 0h Power Enable status for DISP DPLL 0 Disable...

Page 777: ...te 1 to clear bit n value after reset Table 9 25 device_id Register Field Descriptions Bit Field Type Reset Description 31 28 devrev R 0h Device revision 0000b Silicon Revision 1 0 0001b Silicon Revision 2 0 0010b Silicon Revision 2 1 See device errata for detailed information on functionality in each device revision Reset value is revision dependent 27 12 partnum R B944h Device part number unique...

Page 778: ...ed 1 SGX enabled Reset value is device dependent 28 24 Reserved R 0h 23 18 Reserved R 0h 17 pru_icss_fea 1 R 0h 0 TX_AUTO_SEQUENCE disabled 1 TX_AUTO_SEQUENCE enabled Reset value is device dependent 16 pru_icss_fea 0 R 0h 0 EtherCAT functionality disabled ODD_NIBBLE disabled 1 EtherCAT functionality enabled ODD_NIBBLE enabled Reset value is device dependent 15 10 Reserved R 0h 9 Reserved R 0h 8 Re...

Page 779: ...ield Descriptions Bit Field Type Reset Description 31 28 Reserved R 0h 27 26 tcwr2 R W 0h TPTC 2 Write Port initiator priority 25 24 tcrd2 R W 0h TPTC 2 Read Port initiator priority 23 22 tcwr1 R W 0h TPTC 1 Write Port initiator priority 21 20 tcrd1 R W 0h TPTC 1 Read Port initiator priority 19 18 tcwr0 R W 0h TPTC 0 Write Port initiator priority 17 16 tcrd0 R W 0h TPTC 0 Read Port initiator prior...

Page 780: ...nly W1toCl Write 1 to clear bit n value after reset Table 9 28 init_priority_1 Register Field Descriptions Bit Field Type Reset Description 31 26 Reserved R 0h 25 24 debug R W 0h Debug Subsystem initiator priority 23 22 lcd R W 0h LCD initiator priority 21 20 sgx R W 0h SGX initiator priority 19 18 Reserved R 0h 17 16 Reserved R 0h 15 8 Reserved R 0h 7 6 usb_qmgr R W 0h USB Queue Manager initiator...

Page 781: ...Descriptions Bit Field Type Reset Description 31 16 Reserved R 0h 15 mmu_abort R W 0h MMU abort operation This bit causes the MMU to abort the current operation in case of lockup 14 8 Reserved R 0h 7 mmu_disable R W 0h MMU Disable Setting this bit disables MMU table lookup and causes accesses to use the non translated address This bit defaults to enabled but an identical bit within an MMU configur...

Page 782: ...d Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 30 tptc_cfg Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 4 tc2dbs R W 0h TPTC2 Default Burst Size 00 16 byte 01 32 byte 10 64 byte 11 128 byte 3 2 tc1dbs R W 0h TPTC1 Default Burst Size 00 16 byte 01 32 byte 10 64 byte 11 128 byte 1 0 tc0dbs R W 0h TPTC0 Default Burst Size 00 16 byte 01...

Page 783: ...3C 23 datapolarity_inv R W 0h Data Polarity Invert 0 DP DM normal polarity matching port definition 1 DM DP inverted polarity of port definition 22 Reserved R 0h 21 Reserved R 0h 20 otgsessenden R W 0h Session End Detect Enable 0 Disable Session End Comparator 1 Turns on Session End Comparator 19 otgvdet_en R W 0h VBUS Detect Enable 0 Disable VBUS Detect Enable 1 Turns on all comparators except Se...

Page 784: ...sinkondp R W 0h Sink on DP 0 Sink on DM 1 Sink on DP 4 srcondm R W 0h Source on DM 0 Source on DP 1 Source on DM 3 chgdet_rstrt R W 0h Restart Charger Detect 2 chgdet_dis R W 0h Charger Detect Disable 0 Enable 1 Disable 1 otg_pwrdn R W 0h Power down the USB OTG PHY 0 PHY in normal mode 1 PHY Powered down 0 cm_pwrdn R W 0h Power down the USB CM PHY 0 PHY in normal mode 1 PHY Powered down 784 Contro...

Page 785: ... 000 Wait State When a D WPU and D 15K are connected it enters into this state and will remain in this state unless it enters into other state 001 No Contact 010 PS 2 011 Unknown error 100 Dedicated charger valid if CE is HIGH 101 HOST charger valid if CE is HIGH 110 PC 111 Interrupt if any of the pullup is enabled charger detect routine gets interrupted and will restart from the beginning if the ...

Page 786: ...to 0x3C 23 datapolarity_inv R W 0h Data Polarity Invert 0 DP DM normal polarity matching port definition 1 DM DP inverted polarity of port definition 22 Reserved R 0h 21 Reserved R 0h 20 otgsessenden R W 0h Session End Detect Enable 0 Disable Session End Comparator 1 Turns on Session End Comparator 19 otgvdet_en R W 0h VBUS Detect Enable 0 Disable VBUS Detect Enable 1 Turns on all comparators exce...

Page 787: ...sinkondp R W 0h Sink on DP 0 Sink on DM 1 Sink on DP 4 srcondm R W 0h Source on DM 0 Source on DP 1 Source on DM 3 chgdet_rstrt R W 0h Restart Charger Detect 2 chgdet_dis R W 0h Charger Detect Disable 0 Enable 1 Disable 1 otg_pwrdn R W 0h Power down the USB OTG PHY 0 PHY in normal mode 1 PHY Powered down 0 cm_pwrdn R W 0h Power down the USB CM PHY 1 PHY Powered down 0 PHY in normal mode 787 SPRUH7...

Page 788: ... 000 Wait State When a D WPU and D 15K are connected it enters into this state and will remain in this state unless it enters into other state 001 No Contact 010 PS 2 011 Unknown error 100 Dedicated charger valid if CE is HIGH 101 HOST charger valid if CE is HIGH 110 PC 111 Interrupt if any of the pullup is enabled charger detect routine gets interrupted and will restart from the beginning if the ...

Page 789: ...4 3 2 1 0 macaddr_15_8 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 35 mac_id0_lo Register Field Descriptions Bit Field Type Reset Description 31 16 Reserved R 0h 15 8 macaddr_7_0 R 0h MAC0 Address Byte 0 Reset value is device dependent 7 0 macaddr_15_8 R 0h MAC0 Address Byte 1 Reset value is device dependent 789 SPRUH73H October 2011 Revised April...

Page 790: ...W1toCl Write 1 to clear bit n value after reset Table 9 36 mac_id0_hi Register Field Descriptions Bit Field Type Reset Description 31 24 macaddr_23_16 R 0h MAC0 Address Byte 2 Reset value is device dependent 23 16 macaddr_31_24 R 0h MAC0 Address Byte 3 Reset value is device dependent 15 8 macaddr_39_32 R 0h MAC0 Address Byte 4 Reset value is device dependent 7 0 macaddr_47_40 R 0h MAC0 Address Byt...

Page 791: ...4 3 2 1 0 macaddr_15_8 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 37 mac_id1_lo Register Field Descriptions Bit Field Type Reset Description 31 16 Reserved R 0h 15 8 macaddr_7_0 R 0h MAC1 Address Byte 0 Reset value is device dependent 7 0 macaddr_15_8 R 0h MAC1 Address Byte 1 Reset value is device dependent 791 SPRUH73H October 2011 Revised April...

Page 792: ...W1toCl Write 1 to clear bit n value after reset Table 9 38 mac_id1_hi Register Field Descriptions Bit Field Type Reset Description 31 24 macaddr_23_16 R 0h MAC1 Address Byte 2 Reset value is device dependent 23 16 macaddr_31_24 R 0h MAC1 Address Byte 3 Reset value is device dependent 15 8 macaddr_39_32 R 0h MAC1 Address Byte 4 Reset value is device dependent 7 0 macaddr_47_40 R 0h MAC1 Address Byt...

Page 793: ... n value after reset Table 9 39 dcan_raminit Register Field Descriptions Bit Field Type Reset Description 31 10 Reserved R 0h 9 dcan1_raminit_done R W1toClr 0h 0 DCAN1 RAM Initialization NOT complete 1 DCAN1 RAM Initialization complete 8 dcan0_raminit_done R W1toClr 0h 0 DCAN0 RAM Initialization NOT complete 1 DCAN0 RAM Initialization complete 7 2 Reserved R 0h 1 dcan1_raminit_start R W 0h A trans...

Page 794: ... 0 Reserved phy0_wuen R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 40 usb_wkup_ctrl Register Field Descriptions Bit Field Type Reset Description 31 9 Reserved R 0h 8 phy1_wuen R W 0h PHY1 Wakeup Enable Write to 1 enables WKUP from USB PHY1 7 1 Reserved R 0h 0 phy0_wuen R W 0h PHY0 Wakeup Enable Write to 1 enables WKUP from USB PHY0 794 Contr...

Page 795: ... based on AM335x silicon revision 6 rmii1_io_clk_en R W 1h 0 RMII Reference Clock Output mode Enable RMII clock to be sourced from PLL 1 RMII Reference Clock Input mode Enable RMII clock to be sourced from chip pin See Silicon Revision Functional Differences and Enhancements for differences in operation based on AM335x silicon revision 5 rgmii2_idmode R W 1h RGMII2 Internal Delay Mode 0 Reserved 1...

Page 796: ...clken pwmss0_tbclken R 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 42 pwmss_ctrl Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 pwmss2_tbclken R W 0h Timebase clock enable for PWMSS2 1 pwmss1_tbclken R W 0h Timebase clock enable for PWMSS1 0 pwmss0_tbclken R W 0h Timebase clock enable for PWMSS...

Page 797: ... Descriptions Bit Field Type Reset Description 31 Reserved R 0h 30 28 sgx R W 0h MReqPriority for SGX Initiator OCP Interface 27 Reserved R 0h 26 24 usb1 R W 0h MReqPriority for USB1 Initiator OCP Interface 23 Reserved R 0h 22 20 usb0 R W 0h MReqPriority for USB0 Initiator OCP Interface 19 Reserved R 0h 18 16 cpsw R W 0h MReqPriority for CPSW Initiator OCP Interface 15 Reserved R 0h 14 12 Reserved...

Page 798: ... 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved exp R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 44 mreqprio_1 Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 0 exp R W 0h MReqPriority for Expansion Initiator OCP Interface 798 Control Module SPRUH73H October 2011 Revised April 2013 Submit Documentati...

Page 799: ...W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 45 hw_event_sel_grp1 Register Field Descriptions Bit Field Type Reset Description 31 24 event4 R W 0h Select 4th trace event from group 1 23 16 event3 R W 0h Select 3rd trace event from group 1 15 8 event2 R W 0h Select 2nd trace event from group 1 7 0 event1 R W 0h Select 1st trace event from group 1 79...

Page 800: ...W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 46 hw_event_sel_grp2 Register Field Descriptions Bit Field Type Reset Description 31 24 event8 R W 0h Select 8th trace event from group 2 23 16 event7 R W 0h Select 7th trace event from group 2 15 8 event6 R W 0h Select 6th trace event from group 2 7 0 event5 R W 0h Select 5th trace event from group 2 80...

Page 801: ... 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 47 hw_event_sel_grp3 Register Field Descriptions Bit Field Type Reset Description 31 24 event12 R W 0h Select 12th trace event from group 3 23 16 event11 R W 0h Select 11th trace event from group 3 15 8 event10 R W 0h Select 10th trace event from group 3 7 0 event9 R W 0h Select 9th trace event from group...

Page 802: ...0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 48 hw_event_sel_grp4 Register Field Descriptions Bit Field Type Reset Description 31 24 event16 R W 0h Select 16th trace event from group 4 23 16 event15 R W 0h Select 15th trace event from group 4 15 8 event14 R W 0h Select 14th trace event from group 4 7 0 event13 R W 0h Select 13th trace event from grou...

Page 803: ...0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 49 smrt_ctrl Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 sr1_sleep R W 0h 0 Disable sensor SRSLEEP on sensor driven to 1 1 Enable sensor SRSLEEP on sensor driven to 0 0 sr0_sleep R W 0h 0 Disable sensor SRSLEEP on sensor driven to 1 1 Enable sensor SRSLEEP on sensor dr...

Page 804: ...ebug_sel Register Field Descriptions Bit Field Type Reset Description 31 10 Reserved R 0h 9 hw_dbg_gate_en R W 0h To save power input to MPUSS_HW_DBG_INFO is gated off to all zeros when HW_DBG_GATE_EN bit is low 0 Debug info gated off 1 Debug info not gated off 8 Reserved R 0h 7 4 Reserved R 0h 3 0 hw_dbg_sel R W 0h Selects which Group of signals are sent out to the MODENA_HW_DBG_INFO register Ple...

Page 805: ... 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 hw_dbg_info R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 51 mpuss_hw_dbg_info Register Field Descriptions Bit Field Type Reset Description 31 0 hw_dbg_info R 0h Hardware Debug Info from MPU 805 SPRUH73H October 2011 Revised April 2013 Control Module Submit Documentation Feedback Copyright 2011 2...

Page 806: ... 12 11 10 9 8 ntarget R 0h 7 6 5 4 3 2 1 0 ntarget R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 52 vdd_mpu_opp_050 Register Field Descriptions Bit Field Type Reset Description 31 24 Reserved R 0h 23 0 ntarget R 0h Ntarget value for MPU Voltage domain OPP50 Reset value is device dependent 806 Control Module SPRUH73H October 2011 Revised April 2013 S...

Page 807: ...12 11 10 9 8 ntarget R 0h 7 6 5 4 3 2 1 0 ntarget R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 53 vdd_mpu_opp_100 Register Field Descriptions Bit Field Type Reset Description 31 24 Reserved R 0h 23 0 ntarget R 0h Ntarget value for MPU Voltage domain OPP100 Reset value is device dependent 807 SPRUH73H October 2011 Revised April 2013 Control Module S...

Page 808: ...12 11 10 9 8 ntarget R 0h 7 6 5 4 3 2 1 0 ntarget R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 54 vdd_mpu_opp_120 Register Field Descriptions Bit Field Type Reset Description 31 24 Reserved R 0h 23 0 ntarget R 0h Ntarget value for MPU Voltage domain OPP120 Reset value is device dependent 808 Control Module SPRUH73H October 2011 Revised April 2013 S...

Page 809: ... 12 11 10 9 8 ntarget R 0h 7 6 5 4 3 2 1 0 ntarget R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 55 vdd_mpu_opp_turbo Register Field Descriptions Bit Field Type Reset Description 31 24 Reserved R 0h 23 0 ntarget R 0h Ntarget value for MPU Voltage domain OPPTURBO Reset value is device dependent 809 SPRUH73H October 2011 Revised April 2013 Control Mod...

Page 810: ... 12 11 10 9 8 ntarget R 0h 7 6 5 4 3 2 1 0 ntarget R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 56 vdd_core_opp_050 Register Field Descriptions Bit Field Type Reset Description 31 24 Reserved R 0h 23 0 ntarget R 0h Ntarget value for CORE Voltage domain OPP50 Reset value is device dependent 810 Control Module SPRUH73H October 2011 Revised April 2013...

Page 811: ... 12 11 10 9 8 ntarget R 0h 7 6 5 4 3 2 1 0 ntarget R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 57 vdd_core_opp_100 Register Field Descriptions Bit Field Type Reset Description 31 24 Reserved R 0h 23 0 ntarget R 0h Ntarget value for CORE Voltage domain OPP100 Reset value is device dependent 811 SPRUH73H October 2011 Revised April 2013 Control Modul...

Page 812: ...R 0h R 0h 7 6 5 4 3 2 1 0 Reserved bbias R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 58 bb_scale Register Field Descriptions Bit Field Type Reset Description 31 12 Reserved R 0h 11 8 scale R 0h Dynamic core voltage scaling for class 0 7 2 Reserved R 0h 1 0 bbias R 0h BBIAS value from Efuse 812 Control Module SPRUH73H October 2011 Revised Apri...

Page 813: ...d R 451h 15 14 13 12 11 10 9 8 usb_pid R 6141h 7 6 5 4 3 2 1 0 usb_pid R 6141h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 59 usb_vid_pid Register Field Descriptions Bit Field Type Reset Description 31 16 usb_vid R 0x451 USB Vendor ID 15 0 usb_pid R 0x6141 USB Product ID 813 SPRUH73H October 2011 Revised April 2013 Control Module Submit Documentation F...

Page 814: ...evice to device 17 16 package_type R Package Designates the Package type of the device PG2 x only dependent 00b Undefined 01b ZCZ Package 10b ZCE Package 11b Reserved 15 13 Reserved R These bits are undefined and contents can vary from device to device 12 0 arm_mpu_max_freq R Device Designates the ARM MPU Maximum Frequency supported by the dependent device PG2 x only There are also voltage require...

Page 815: ...R W 1h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 61 conf_ module _ pin Register Field Descriptions Bit Field Type Reset Description 31 20 Reserved R 0h 19 7 Reserved R 0h 6 conf_ module _ pin _sle R W X Select between faster or slower slew rate wctrl 0 Fast 1 Slow Reset value is pad dependent 5 conf_ module _ pin _rx R W 1h Input...

Page 816: ...t Field Type Reset Description 31 22 Reserved R 0h 21 Reserved R 0h 20 Reserved R 0h 19 Reserved R 0h 18 Reserved R 0h 17 Reserved R 0h 16 Reserved R 0h 15 14 Reserved R 0h 13 cqerr_general R 0h CQDetect Mode Error Status 12 cqerr_gemac_b R 0h CQDetect Mode Error Status 11 cqerr_gemac_a R 0h CQDetect Mode Error Status 10 cqerr_mmcsd_b R 0h CQDetect Mode Error Status 9 cqerr_mmcsd_a R 0h CQDetect M...

Page 817: ... to clear bit n value after reset Table 9 63 ddr_io_ctrl Register Field Descriptions Bit Field Type Reset Description 31 ddr3_rst_def_val R W 0h DDR3 reset default value 30 ddr_wuclk_disable R W 0h Disables the slow clock to WUCLKIN and ISOCLKIN of DDR emif SS and IOs required for proper initialization after which clock could be shut off 0 free running SLOW 32k clock 1 clock is synchronously gated...

Page 818: ...evision Functional Differences and Enhancements for differences in operation based on AM335x silicon revision 7 Reserved R 0h 6 enable R W 0h 0 VTP macro in bypass mode P and N are driven from PCIN and NCIN 1 Dynamic VTP compensation mode 5 ready R 0h 0 Training sequence is not complete 1 Training sequence is complete 4 lock R W 0h 0 Normal operation dynamic update 1 freeze dynamic update pwrdn co...

Page 819: ...vref_ccap R W 0h select for coupling cap for DDR 00 No capacitor connected 01 Capacitor between BIAS2 and VSS 10 Capacitor between BIAS2 and VDDS 11 Capacitor between BIAS2 and VSS andamp Capacitor between BIAS2 and VDDS 2 1 ddr_vref_tap R W 0h select for int ref for DDR 00 Pad Bias2 connected to internal reference VDDS 2 for 2uA current load 01 Pad Bias2 connected to internal reference VDDS 2 for...

Page 820: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 66 tpcc_evt_mux_0_3 Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 24 evt_mux_3 R W 0h Selects 1 of 64 inputs for DMA event 3 23 22 Reserved R 0h 21 16 evt_mux_2 R W 0h Selects 1 of 64 inputs for DMA event 2 15 14 Reserved R 0h 13 8 evt_mux_1 R W 0h Selects 1 of 64 inputs for DMA event...

Page 821: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 67 tpcc_evt_mux_4_7 Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 24 evt_mux_7 R W 0h Selects 1 of 64 inputs for DMA event 7 23 22 Reserved R 0h 21 16 evt_mux_6 R W 0h Selects 1 of 64 inputs for DMA event 6 15 14 Reserved R 0h 13 8 evt_mux_5 R W 0h Selects 1 of 64 inputs for DMA event...

Page 822: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 68 tpcc_evt_mux_8_11 Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 24 evt_mux_11 R W 0h Selects 1 of 64 inputs for DMA event 11 23 22 Reserved R 0h 21 16 evt_mux_10 R W 0h Selects 1 of 64 inputs for DMA event 10 15 14 Reserved R 0h 13 8 evt_mux_9 R W 0h Selects 1 of 64 inputs for DMA ...

Page 823: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 69 tpcc_evt_mux_12_15 Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 24 evt_mux_15 R W 0h Selects 1 of 64 inputs for DMA event 15 23 22 Reserved R 0h 21 16 evt_mux_14 R W 0h Selects 1 of 64 inputs for DMA event 14 15 14 Reserved R 0h 13 8 evt_mux_13 R W 0h Selects 1 of 64 inputs for DM...

Page 824: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 70 tpcc_evt_mux_16_19 Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 24 evt_mux_19 R W 0h Selects 1 of 64 inputs for DMA event 19 23 22 Reserved R 0h 21 16 evt_mux_18 R W 0h Selects 1 of 64 inputs for DMA event 18 15 14 Reserved R 0h 13 8 evt_mux_17 R W 0h Selects 1 of 64 inputs for DM...

Page 825: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 71 tpcc_evt_mux_20_23 Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 24 evt_mux_23 R W 0h Selects 1 of 64 inputs for DMA event 23 23 22 Reserved R 0h 21 16 evt_mux_22 R W 0h Selects 1 of 64 inputs for DMA event 22 15 14 Reserved R 0h 13 8 evt_mux_21 R W 0h Selects 1 of 64 inputs for DM...

Page 826: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 72 tpcc_evt_mux_24_27 Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 24 evt_mux_27 R W 0h Selects 1 of 64 inputs for DMA event 27 23 22 Reserved R 0h 21 16 evt_mux_26 R W 0h Selects 1 of 64 inputs for DMA event 26 15 14 Reserved R 0h 13 8 evt_mux_25 R W 0h Selects 1 of 64 inputs for DM...

Page 827: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 73 tpcc_evt_mux_28_31 Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 24 evt_mux_31 R W 0h Selects 1 of 64 inputs for DMA event 31 23 22 Reserved R 0h 21 16 evt_mux_30 R W 0h Selects 1 of 64 inputs for DMA event 30 15 14 Reserved R 0h 13 8 evt_mux_29 R W 0h Selects 1 of 64 inputs for DM...

Page 828: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 74 tpcc_evt_mux_32_35 Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 24 evt_mux_35 R W 0h Selects 1 of 64 inputs for DMA event 35 23 22 Reserved R 0h 21 16 evt_mux_34 R W 0h Selects 1 of 64 inputs for DMA event 34 15 14 Reserved R 0h 13 8 evt_mux_33 R W 0h Selects 1 of 64 inputs for DM...

Page 829: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 75 tpcc_evt_mux_36_39 Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 24 evt_mux_39 R W 0h Selects 1 of 64 inputs for DMA event 39 23 22 Reserved R 0h 21 16 evt_mux_38 R W 0h Selects 1 of 64 inputs for DMA event 38 15 14 Reserved R 0h 13 8 evt_mux_37 R W 0h Selects 1 of 64 inputs for DM...

Page 830: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 76 tpcc_evt_mux_40_43 Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 24 evt_mux_43 R W 0h Selects 1 of 64 inputs for DMA event 43 23 22 Reserved R 0h 21 16 evt_mux_42 R W 0h Selects 1 of 64 inputs for DMA event 42 15 14 Reserved R 0h 13 8 evt_mux_41 R W 0h Selects 1 of 64 inputs for DM...

Page 831: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 77 tpcc_evt_mux_44_47 Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 24 evt_mux_47 R W 0h Selects 1 of 64 inputs for DMA event 47 23 22 Reserved R 0h 21 16 evt_mux_46 R W 0h Selects 1 of 64 inputs for DMA event 46 15 14 Reserved R 0h 13 8 evt_mux_45 R W 0h Selects 1 of 64 inputs for DM...

Page 832: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 78 tpcc_evt_mux_48_51 Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 24 evt_mux_51 R W 0h Selects 1 of 64 inputs for DMA event 51 23 22 Reserved R 0h 21 16 evt_mux_50 R W 0h Selects 1 of 64 inputs for DMA event 50 15 14 Reserved R 0h 13 8 evt_mux_49 R W 0h Selects 1 of 64 inputs for DM...

Page 833: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 79 tpcc_evt_mux_52_55 Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 24 evt_mux_55 R W 0h Selects 1 of 64 inputs for DMA event 55 23 22 Reserved R 0h 21 16 evt_mux_54 R W 0h Selects 1 of 64 inputs for DMA event 54 15 14 Reserved R 0h 13 8 evt_mux_53 R W 0h Selects 1 of 64 inputs for DM...

Page 834: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 80 tpcc_evt_mux_56_59 Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 24 evt_mux_59 R W 0h Selects 1 of 64 inputs for DMA event 59 23 22 Reserved R 0h 21 16 evt_mux_58 R W 0h Selects 1 of 64 inputs for DMA event 58 15 14 Reserved R 0h 13 8 evt_mux_57 R W 0h Selects 1 of 64 inputs for DM...

Page 835: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 81 tpcc_evt_mux_60_63 Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 24 evt_mux_63 R W 0h Selects 1 of 64 inputs for DMA event 63 23 22 Reserved R 0h 21 16 evt_mux_62 R W 0h Selects 1 of 64 inputs for DMA event 62 15 14 Reserved R 0h 13 8 evt_mux_61 R W 0h Selects 1 of 64 inputs for DM...

Page 836: ... Reserved timer5_evtcapt R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 82 timer_evt_capt Register Field Descriptions Bit Field Type Reset Description 31 21 Reserved R 0h 20 16 timer7_evtcapt R W 0h Timer 7 event capture mux 15 13 Reserved R 0h 12 8 timer6_evtcapt R W 0h Timer 6 event capture mux 7 5 Reserved R 0h 4 0 timer5_evtcapt R W 0h Tim...

Page 837: ...1 0 Reserved ecap0_evtcapt R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 83 ecap_evt_capt Register Field Descriptions Bit Field Type Reset Description 31 21 Reserved R 0h 20 16 ecap2_evtcapt R W 0h ECAP2 event capture mux 15 13 Reserved R 0h 12 8 ecap1_evtcapt R W 0h ECAP1 event capture mux 7 5 Reserved R 0h 4 0 ecap0_evtcapt R W 0h ECAP0 eve...

Page 838: ...h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved adc_evtcapt R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 84 adc_evt_capt Register Field Descriptions Bit Field Type Reset Description 31 4 Reserved R 0h 3 0 adc_evtcapt R W 0h ECAP0 event capture mux 838 Control Module SPRUH73H October 2011 Revised April 2013 Submit Documentation...

Page 839: ... 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved iso_control R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 85 reset_iso Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 iso_control R W 0h 0 Ethernet Switch is not isolated 1 Ethernet Switch is isolated 839 SPRUH73H October 2011 Revised April 2013 Control Module Submit...

Page 840: ...sp R 0h R 0h R 0h R 0h R 0h R 0h R 1h R 1h 15 14 13 12 11 10 9 8 sw_ctrl_per_dpll Reserved isoscan_per ret_per reset_per iso_per pgoodin_per ponin_per R 0h R 0h R 0h R 0h R 0h R 0h R 1h R 1h 7 6 5 4 3 2 1 0 Reserved R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 86 dpll_pwr_sw_ctrl Register Field Descriptions Bit Field Type Reset Description 31 sw_ct...

Page 841: ...gs 0 PRCM controls the DPLL reset RET 0 ISO 0 PGOODIN 1 PONIN 1 1 Controlled by corresponding bits in this register 14 Reserved R 0h 13 isoscan_per R W 0h Drives ISOSCAN of PER PLL 12 ret_per R W 0h Drives RET of PER DPLL 11 reset_per R W 0h Drives RESET signal of PER DPLL 10 iso_per R W 0h Drives ISO signal of PER DPLL 9 pgoodin_per R W 1h Drives PGOODIN signal of PER DPLL 8 ponin_per R W 1h Driv...

Page 842: ...D R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 87 ddr_cke_ctrl Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 ddr_cke_ctrl R W 0h CKE from EMIF DDRPHY is ANDed with this bit 0 CKE to memories gated off to zero External DRAM memories will not able to register DDR commands from device 1 Normal operation CKE is now controlled by...

Page 843: ...3 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved vsldo_core_auto_ram rmii2_crs_dv_mode_s p_en el R 0h R W0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 88 sma2 Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 vsldo_core_auto_ramp_en R W 0h 0 PRCM controls VSLDO 1 A...

Page 844: ... Field Type Reset Description 31 1 Reserved R 0h 0 m3_txev_eoi R W 0h TXEV Event from M3 processor is a pulse signal connected as intertupt to MPU IRQ 78 Since MPU expects level signals The TXEV pulse from M3 is converted to a level in glue logic The logic works as follows On a 0 1 transition on TXEV the IRQ 78 is set For clearing the interrupt S W must do the following S W must clear the IRQ 78 b...

Page 845: ...ers are used to communicate with the Cortex M3 firmware Figure 9 83 ipc_msg_reg0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ipc_msg_reg0 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 90 ipc_msg_reg0 Register Field Descriptions Bit Field Type Reset Description 31 0 ipc_msg_reg0 R W 0h Inter Proces...

Page 846: ...ers are used to communicate with the Cortex M3 firmware Figure 9 84 ipc_msg_reg1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ipc_msg_reg1 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 91 ipc_msg_reg1 Register Field Descriptions Bit Field Type Reset Description 31 0 ipc_msg_reg1 R W 0h Inter Proces...

Page 847: ...ers are used to communicate with the Cortex M3 firmware Figure 9 85 ipc_msg_reg2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ipc_msg_reg2 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 92 ipc_msg_reg2 Register Field Descriptions Bit Field Type Reset Description 31 0 ipc_msg_reg2 R W 0h Inter Proces...

Page 848: ...ers are used to communicate with the Cortex M3 firmware Figure 9 86 ipc_msg_reg3 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ipc_msg_reg3 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 93 ipc_msg_reg3 Register Field Descriptions Bit Field Type Reset Description 31 0 ipc_msg_reg3 R W 0h Inter Proces...

Page 849: ...ers are used to communicate with the Cortex M3 firmware Figure 9 87 ipc_msg_reg4 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ipc_msg_reg4 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 94 ipc_msg_reg4 Register Field Descriptions Bit Field Type Reset Description 31 0 ipc_msg_reg4 R W 0h Inter Proces...

Page 850: ...ers are used to communicate with the Cortex M3 firmware Figure 9 88 ipc_msg_reg5 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ipc_msg_reg5 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 95 ipc_msg_reg5 Register Field Descriptions Bit Field Type Reset Description 31 0 ipc_msg_reg5 R W 0h Inter Proces...

Page 851: ...ers are used to communicate with the Cortex M3 firmware Figure 9 89 ipc_msg_reg6 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ipc_msg_reg6 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 96 ipc_msg_reg6 Register Field Descriptions Bit Field Type Reset Description 31 0 ipc_msg_reg6 R W 0h Inter Proces...

Page 852: ...ers are used to communicate with the Cortex M3 firmware Figure 9 90 ipc_msg_reg7 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ipc_msg_reg7 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 9 97 ipc_msg_reg7 Register Field Descriptions Bit Field Type Reset Description 31 0 ipc_msg_reg7 R W 0h Inter Proces...

Page 853: ...io_config_gp_wd0 For example macro pin 0 WD1 is bit 21 WD0 is bit 10 macro pin 1 WD1 is bit 22 WD0 is bit 11 macro pin 10 WD1 is bit 31 WD0 is bit 20 See the DDR PHY to IO Pin Mapping table in the Control Module Functional Description section for a mapping of macro bits to I Os WD1 WD0 00 Pullup Pulldown disabled 01 Weak pullup enabled 10 Weak pulldown enabled 11 Weak keeper enabled 9 8 io_config_...

Page 854: ... input to program addr cmd IO output impedance These connect as I2 I1 I0 to the corresponding DDR IO buffer See the DDR Impedance Control Settings table in the Control Module Functional Description section for a definition of these bits 854 Control Module SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 855: ...io_config_gp_wd0 For example macro pin 0 WD1 is bit 21 WD0 is bit 10 macro pin 1 WD1 is bit 22 WD0 is bit 11 macro pin 10 WD1 is bit 31 WD0 is bit 20 See the DDR PHY to IO Pin Mapping table in the Control Module Functional Description section for a mapping of macro bits to I Os WD1 WD0 00 Pullup Pulldown disabled 01 Weak pullup enabled 10 Weak pulldown enabled 11 Weak keeper enabled 9 8 io_config_...

Page 856: ... input to program addr cmd IO output impedance These connect as I2 I1 I0 to the corresponding DDR IO buffer See the DDR Impedance Control Settings table in the Control Module Functional Description section for a definition of these bits 856 Control Module SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 857: ... io_config_gp_wd0 For example macro pin 0 WD1 is bit 21 WD0 is bit 10 macro pin 1 WD1 is bit 22 WD0 is bit 11 macro pin 10 WD1 is bit 31 WD0 is bit 20 See the DDR PHY to IO Pin Mapping table in the Control Module Functional Description section for a mapping of macro bits to I Os WD1 WD0 00 Pullup Pulldown disabled 01 Weak pullup enabled 10 Weak pulldown enabled 11 Weak keeper enabled 9 8 io_config...

Page 858: ...n input to program addr cmd IO output impedance These connect as I2 I1 I0 to the corresponding DDR IO buffer See the DDR Impedance Control Settings table in the Control Module Functional Description section for a definition of these bits 858 Control Module SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 859: ...0b Pullup Pulldown disabled for both DDR_DQS0 and DDR_DQSn0 01b Enable weak pullup for DDR_DQS0 and weak pulldown for DDR_DQSn0 10b Enable weak pulldown for DDR_DQS0 and weak pullup for DDR_DQSn0 11b Weak keeper enabled for both DDR_DQS0 and DDR_DQSn0 28 io_config_wd1_dm R W 0h Input that selects pullup or pulldown for DM Used with io_config_wd0_dm to define pullup pulldown according to the follow...

Page 860: ...tion for a mapping of macro bits to I Os WD1 WD0 00 Pullup Pulldown disabled 01 Weak pullup enabled 10 Weak pulldown enabled 11 Weak keeper enabled 9 8 io_config_sr_clk R W 0h 2 bit to program clock IO Pads DDR_DQS DDR_DQSn output slew rate These connect as SR1 SR0 of the corresponding IO buffer See the DDR Slew Rate Control Settings table in the Control Module Functional Description section for a...

Page 861: ...0b Pullup Pulldown disabled for both DDR_DQS1 and DDR_DQSn1 01b Enable weak pullup for DDR_DQS1 and weak pulldown for DDR_DQSn1 10b Enable weak pulldown for DDR_DQS1 and weak pullup for DDR_DQSn1 11b Weak keeper enabled for both DDR_DQS1 and DDR_DQSn1 28 io_config_wd1_dm R W 0h Input that selects pullup or pulldown for DM Used with io_config_wd0_dm to define pullup pulldown according to the follow...

Page 862: ...tion for a mapping of macro bits to I Os WD1 WD0 00 Pullup Pulldown disabled 01 Weak pullup enabled 10 Weak pulldown enabled 11 Weak keeper enabled 9 8 io_config_sr_clk R W 0h 2 bit to program clock IO Pads DDR_DQS DDR_DQSn output slew rate These connect as SR1 SR0 of the corresponding IO buffer See the DDR Slew Rate Control Settings table in the Control Module Functional Description section for a...

Page 863: ... 2013 Interconnects This chapter describes the interconnects of the device Topic Page 10 1 Introduction 864 863 SPRUH73H October 2011 Revised April 2013 Interconnects Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 864: ...e enables etc Signal behavior is defined by the protocol semantics Sideband Signal Any signal whose behavior is not associated to a precise transaction or data flow Command Slot A command slot is a subset of the command list It is the memory buffer for a single command A total of 32 command slots exist Out of band Error Any signal whose behavior is associated to a device error reporting scheme as ...

Page 865: ...readed with tags used to enable pipelined transactions The interconnect includes Initiator Ports L3F Cortex A8 MPUSS 128 bit initiator port0 and 64 bit initiator port1 SGX530 128 bit initiator port 3 TPTC 128 bit read initiator ports 3 TPTC 128 bit write initiator ports LCDC 32 bit initiator port 2 PRU ICSS1 32 bit initiator ports 2 port Gigabit Ethernet Switch 2PGSW 32 bit initiator port Debug Su...

Page 866: ...4_PER Port1 Expansion Slot L4_PER Port 2 L4_PER Port 3 NOC Registers 0x00 MPUSS M1 128 bit R 0x00 MPUSS M2 64 bit R R R R R R R R R R R R R R R R 0x18 TPTC0 RD R R R R R R R R R R R 0x19 TPTC0 WR R R R R R R R R R R R R 0x1A TPTC1 RD R R R R R R R R R R R 0x1B TPTC1 WR R R R R R R R R R R R 0x1C TPTC2 RD R R R R R R R R R R R 0x1D TPTC2 WR R R R R R R R R R R R 0x24 LCD Controller R R R 0x0E PRU I...

Page 867: ...TPTC2 Read 0x1C 0 TPTC2 Write 0x1D 0 SGX530 0x20 0 OCP WP Traffic Probe 0x21 1 HW Direct connect to DebugSS OCP WP DMA Profiling 0x22 1 HW Direct connect to DebugSS OCP WP Event Trace 0x23 1 HW Direct connect to DebugSS LCD Ctrl 0x24 0 GEMAC 0x30 0 USB DMA 0x34 0 USB QMGR 0x35 0 Stat Collector 0 0x3C HW Stat Collector 1 0x3D HW Stat Collector 2 0x3E HW Stat Collector 3 0x3F HW 1 These MConnIDs are...

Page 868: ...0 1 3 L4 Interconnect The L4 interconnect is a non blocking peripheral interconnect that provides low latency access to a large number of low bandwidth physically dispersed target cores The L4 can handle incoming traffic from up to four initiators and can distribute those communication requests to and collect related responses from up to 63 targets This device provides three interfaces with L3 int...

Page 869: ...e EDMA of the device Topic Page 11 1 Introduction 870 11 2 Integration 873 11 3 Functional Description 876 11 4 EDMA3 Registers 939 11 5 Appendix A 1018 869 SPRUH73H October 2011 Revised April 2013 Enhanced Direct Memory Access EDMA Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 870: ...controller serves as the user interface for the EDMA3 controller The EDMA3CC includes parameter RAM PaRAM channel control registers and interrupt control registers The EDMA3CC serves to prioritize incoming software requests or events from peripherals and submits transfer requests TRs to the transfer controller The EDMA3 transfer controllers are slaves to the EDMA3 channel controller that is respon...

Page 871: ...mable assignment of Priority to TC channel Proxied Memory Protection for TR submission Parameterizable support for Active Memory Protection for accesses to PaRAM and registers Queue Watermarking Missed Event Detection Error and status recording to facilitate debug Single Clock domain for all interfaces Parameterizable number of Write Completion interfaces up to 8 set to number of TC Channels AET E...

Page 872: ...port Single clock domain for all interfaces 11 1 3 2 Unsupported TPTC Features There are no unsupported TPTC features on this device 872 Enhanced Direct Memory Access EDMA SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 873: ...ty Attributes Attributes Type Power domain Peripheral Domain Clock domain PD_PER_L3_GCLK Reset signals PER_DOM_RST_N Idle Wakeup signals Smart Idle Interrupt request 4 Regional Completion Interrupts int_pend_po0 EDMACOMPINT to MPU Subsystem int_pend_po1 tpcc_int_pend_po1 to PRU ICSS Int_pend_po 3 2 unused Error Interrupt errint_po EDMAERRINT to MPU Subsystem Memory Protection Error Interrupt mpint...

Page 874: ...Connectivity Attributes The general connectivity attributes for the TPTCs are shown in Table 11 3 Table 11 3 TPTC Connectivity Attributes Attributes Type Power domain Peripheral Domain Clock domain PD_PER_L3_GCLK Reset signals PER_DOM_RST_N Idle Wakeup signals Standby Smart Idle Interrupt request Error interrupt per instance erint_pend_po TCERRINTx to MPU Subsystem and PRU ICSS tptc_erint_pend_po ...

Page 875: ...PTC Pin List The TPTC module does not include any external interface pins 875 SPRUH73H October 2011 Revised April 2013 Enhanced Direct Memory Access EDMA Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 876: ...ansfers or to assert interrupts Event queues Event queues form the interface between the event detection logic and the transfer request submission logic Memory protection registers Memory protection registers define the accesses privilege level and requestor s that are allowed to access the DMA channel shadow region view s and regions of PaRAM Other functions include the following Region registers...

Page 877: ...n external event manual write to the event set register or chained event for DMA channels QDMA channels auto trigger when a write to the trigger word that you program occurs on the associated PaRAM set All such trigger events are logged into appropriate registers upon recognition Once a trigger event is recognized the appropriate event gets queued in the EDMA3CC event queue The assignment of each ...

Page 878: ...generation logic is responsible for generating EDMA3CC completion interrupts to the CPU For more information refer to Section 11 3 5 Additionally the EDMA3CC also has an error detection logic that causes an error interrupt generation on various error conditions like missed events exceeding event queue thresholds etc For more information on error interrupts refer to Section 11 3 9 4 11 3 1 2 EDMA3 ...

Page 879: ...pending on the number of entries the read controller can process up to two or four transfer requests ahead of the destination subject to the amount of free data FIFO 11 3 2 Types of EDMA3 Transfers An EDMA3 transfer is always defined in terms of three dimensions Figure 11 6 shows the three dimensions used by EDMA3 transfers These three dimensions are defined as 1st Dimension or Array A The 1st dim...

Page 880: ... in Figure 11 7 where the start address of Array N is equal to the start address of Array N 1 plus source SRC or destination DST BIDX Frames are always separated by SRCCIDX and DSTCIDX For A synchronized transfers after the frame is exhausted the address is updated by adding SRCCIDX DSTCIDX to the beginning address of the last array in the frame As in Figure 11 7 SRCCIDX DSTCIDX is the difference ...

Page 881: ...ynchronized transfer of 3 CCNT frames of 4 BCNT arrays of n ACNT bytes In this example a total of 3 sync events CCNT exhaust a PaRAM set that is a total of 3 transfers of 4 arrays each completes the transfer Figure 11 8 AB Synchronized Transfers ACNT n BCNT 4 CCNT 3 NOTE ABC synchronized transfers are not directly supported But can be logically achieved by chaining between multiple AB synchronized...

Page 882: ...e PaRAM set 6 Address 40DFh 7 EDMA Base Address 40E0h to EDMA Base PaRAM set 7 Address 40FFh 8 EDMA Base Address 4100h to EDMA Base PaRAM set 8 Address 411Fh 9 EDMA Base Address 4120h to EDMA Base PaRAM set 9 Address 413Fh 63 EDMA Base Address 47E0h to EDMA Base PaRAM set 63 Address 47FFh 64 EDMA Base Address 4800h to EDMA Base PaRAM set 64 Address 481Fh 65 EDMA Base Address 4820h to EDMA Base PaR...

Page 883: ...MA Base Address 5FC0 EDMA Base Address 5FE0 0 1 2 3 254 255 DSTBIDX BCNTRLD Rsvd DSTCIDX CCNT SRCCIDX LINK SRCBIDX DST BCNT ACNT SRC OPT PaRAM PaRAM set 0h 4h 8h Ch Byte address offset 1Ch 18h 14h 10h www ti com Functional Description Figure 11 9 PaRAM Set 883 SPRUH73H October 2011 Revised April 2013 Enhanced Direct Memory Access EDMA Submit Documentation Feedback Copyright 2011 2013 Texas Instrum...

Page 884: ...1 SRCCIDX Source CCNT Index Signed value specifying the byte address offset between frames within a block 3rd dimension Valid values range from 32 768 and 32 767 A synchronized transfers The byte address offset from the beginning of the last source array in a frame to the beginning of the first source array in the next frame AB synchronized transfers The byte address offset from the beginning of t...

Page 885: ...ry intermediate TR in the PaRAM set except the final TR in the PaRAM set The bit position set in CER or CERH is the TCC value specified 22 TCCHEN Transfer complete chaining enable 0 Transfer complete chaining is disabled 1 Transfer complete chaining is enabled When enabled the chained event register CER CERH bit is set on final chained transfer completion upon completion of the final TR in the PaR...

Page 886: ...s 2 SYNCDIM Transfer synchronization dimension 0 A synchronized Each event triggers the transfer of a single array of ACNT bytes 1 AB synchronized Each event triggers the transfer of BCNT arrays of ACNT bytes 1 DAM Destination address mode 0 Increment INCR mode Destination addressing within an array increments Destination is not a FIFO 1 Constant addressing CONST mode Destination addressing within...

Page 887: ...the BCNT field once the last array in the 2nd dimension is transferred This field is only used for A synchronized transfers In this case the EDMA3CC decrements the BCNT value by 1 on each TR submission When BCNT reaches 0 the EDMA3CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value For AB synchronized transfers the EDMA3CC submits the BCNT in the TR and the EDMA3TC decreme...

Page 888: ...e LINK field should be cleared to 0 The EDMA3CC ignores the upper 2 bits of the LINK entry allowing the programmer the flexibility of programming the link address as either an absolute literal byte address or use the PaRAM base relative offset address Therefore if you make use of the literal address with a range from 4000h to 7FFFh it will be treated as a PaRAM base relative value of 0000h to 3FFF...

Page 889: ...QDMA channel and its corresponding PaRAM set the EDMA3CC is responsible for updating the PaRAM set in anticipation of the next trigger event For events that are not final this includes address and count updates for final events this includes the link update The specific PaRAM set entries that are updated depend on the channel s synchronization type A synchronized or B synchronized and the current ...

Page 890: ...CNT 1 BCNT 1 Condition BCNT 1 CCNT 1 CCNT 1 N A CCNT 1 CCNT 1 SRC SRCBIDX SRCCIDX Link SRC in EDMA3TC SRCCIDX Link SRC DST DSTBIDX DSTCIDX Link DST in EDMA3TC DSTCIDX Link DST ACNT None None Link ACNT None None Link ACNT BCNT 1 BCNTRLD Link BCNT in EDMA3TC N A Link BCNT CCNT None 1 Link CCNT in EDMA3TC 1 Link CCNT SRCBIDX None None Link SRCBIDX in EDMA3TC None Link SRCBIDX DSTBIDX None None Link D...

Page 891: ... see Section 11 3 6 should only be used for linking if the corresponding events are disabled If a PaRAM set location is defined as a QDMA channel PaRAM set by QCHMAPn then copying the link PaRAM set into the current QDMA channel PaRAM set is recognized as a trigger event It is latched in QER because a write to the trigger word was performed You can use this feature to create a linked list of trans...

Page 892: ...nk FFFFh 0h 0h 0h 0h 0h 0h 0h 0h 0h PaRAM set 3 Null PaRAM set 0h EDMA Base Address 5FE0h 255 Parameter set 255 c After completion of PaRAM set 51 1 link to null set OPT Y SRC Y BCNT Y ACNT Y DST Y SRCBIDX Y DSTBIDX Y Link Y FFFFh BCNTRLD Y CCNT Y SRCCIDX Y DSTCIDX Y Rsvd OPT Y SRC Y BCNT Y ACNT Y DST Y SRCBIDX Y DSTBIDX Y Link Y FFFFh BCNTRLD Y CCNT Y SRCCIDX Y DSTCIDX Y Rsvd PaRAM set 255 OPT Y ...

Page 893: ... X SRCCIDX X Link 5FE0h SRCBIDX X ACNT X DSTCIDX X Rsvd BCNTRLD X DSTBIDX X BCNT X DST X SRC X PaRAM set 3 OPT X EDMA Base Address 5FE0h 255 Parameter set 255 c After completion of PaRAM set 127 link to self OPT X SRC X BCNT X ACNT X DST X SRCBIDX X DSTBIDX X Link 5FE0h BCNTRLD X CCNT X SRCCIDX X DSTCIDX X Rsvd OPT X SRC X BCNT X ACNT X DST X SRCBIDX X DSTBIDX Y Link 5FE0h BCNTRLD X CCNT X SRCCIDX...

Page 894: ... the TR is processed submitted after which the ER En bit is cleared If an event is being processed prioritized or is in the event queue and another sync event is received for the same channel prior to the original being cleared ER En 0 then the second event is registered as a missed event in the corresponding bit of the event missed register EMR En 1 See Section 9 2 3 EDMA Event Multiplexing for a...

Page 895: ...sources event triggered manually triggered or chain triggered 11 3 4 2 QDMA Channels 11 3 4 2 1 Auto triggered and Link Triggered Transfer Request QDMA based transfer requests are issued when a QDMA event gets latched in the QDMA event register QER En 1 A bit corresponding to a QDMA channel is set in the QDMA event register QER when the following occurs A CPU or any EDMA3 programmer write occurs t...

Page 896: ... Number of Transfers for Non Null Transfer Sync Mode Counts at time 0 Total Transfers Counts prior to final TR A synchronized ACNT BCNT CCNT TRs of ACNT bytes each BCNT 1 CCNT 1 BCNT CCNT AB synchronized ACNT CCNT TRs for ACNT BCNT bytes each CCNT 1 BCNT CCNT You must program the PaRAM OPT field with a specific transfer completion code TCC along with the other OPT fields TCCHEN TCINTEN ITCCHEN and...

Page 897: ...ll has the OPT field programmed to return completion code intermediate final interrupt chaining completion then it will set the appropriate bits in the interrupt pending registers IPR IPRH or chained event register CER CERH The internal early completion path is used by the channel controller to return the completion codes internally that is EDMA3CC generates the completion code 11 3 6 Event Channe...

Page 898: ...PaRAM Mapping The mapping between the QDMA channels and the PaRAM sets is programmable The QDMA channel mapping register QCHMAP in the EDMA3CC allows you to map the QDMA channels to any of the PaRAM sets in the PaRAM memory map Figure 11 14 illustrates the use of QCHMAP Additionally QCHMAP allows you to program the trigger word in the PaRAM set for the QDMA channel A trigger word is one of the eig...

Page 899: ...f the assigned resources Memory protection is described in Section 11 3 10 11 3 7 1 Region Overview The EDMA3 channel controller memory mapped registers are divided in three main categories 1 Global registers 2 Global region channel registers 3 Shadow region channel registers The global registers are located at a single fixed location in the EDMA3CC memory map These registers control EDMA3 resourc...

Page 900: ...Registers DRAEm DRAEHm QRAEn ER ERH QER ECR ECRH QEER ESR ESRH QEECR CER CERH QEESR EER EERH EECR EECRH EESR EESRH SER SERH SECR SECRH IER IERH IECR IECRH IESR IESRH IPR IPRH ICR ICRH Register not affected by DRAE DRAEH IEVAL Figure 11 15 Shadow Region Registers 11 3 7 2 Channel Controller Regions There are eight EDMA3 shadow regions and associated memory maps Associated with each shadow region ar...

Page 901: ...ds to be allocated 16 DMA channels 16 32 and the remaining 7 QDMA channels 1 7 and TCC codes 16 47 DRAE should be equal to the OR of the bits that are required for the DMA channels and the TCC codes Region 0 DRAEH DRAE 0xFFFF0000 0x0000FFFF QRAE 0x0000001 Region 1 DRAEH DRAE 0x0000FFFF 0xFFFF0000 QRAE 0x00000FE 11 3 7 3 Region Interrupts In addition to the EDMA3CC global completion interrupt there...

Page 902: ...pts Name Description EDMA3CC_INT0 EDMA3CC Transfer Completion Interrupt Shadow Region 0 EDMA3CC_INT1 EDMA3CC Transfer Completion Interrupt Shadow Region 1 EDMA3CC_INT2 EDMA3CC Transfer Completion Interrupt Shadow Region 2 EDMA3CC_INT3 EDMA3CC Transfer Completion Interrupt Shadow Region 3 EDMA3CC_INT4 EDMA3CC Transfer Completion Interrupt Shadow Region 4 EDMA3CC_INT5 EDMA3CC Transfer Completion Int...

Page 903: ... channels If the channel is used in the context of a shadow region and you intend for the shadow region interrupt to be asserted then ensure that the bit corresponding to the TCC code is enabled in IER IERH and in the corresponding shadow region s DMA region access registers DRAE DRAEH You can enable Interrupt generation at either final transfer completion or intermediate transfer completion or bo...

Page 904: ...cal registers that are in the global region The EDMA3 channel controller has a hierarchical completion interrupt scheme that uses a single set of interrupt pending registers IPR IPRH and single set of interrupt enable registers IER IERH The programmable DMA region access enable registers DRAE DRAEH provides a second level of interrupt masking The global region interrupt output is gated based on th...

Page 905: ...o a state where at least one enabled interrupt is set 11 3 9 2 EDMA3 Interrupt Servicing Upon completion of a transfer early or normal completion the EDMA3 channel controller sets the appropriate bit in the interrupt pending registers IPR IPRH as the transfer completion codes specify If the completion interrupts are appropriately enabled then the CPU enters the interrupt service routine ISR when t...

Page 906: ...ew interrupt triggers if any enabled interrupts are still pending 11 3 9 3 Interrupt Evaluation Operations The EDMA3CC has interrupt evaluate registers IEVAL that exist in the global region and in each shadow region The registers in the shadow region are the only registers in the DMA channel shadow region memory map that are not affected by the settings for the DMA region access enable registers D...

Page 907: ...egister CCERR Figure 11 17 illustrates the EDMA3CC error interrupt generation operation If any of the bits are set in the error registers due to any error condition the EDMA3CC_ERRINT is always asserted as there are no enables for masking these error events Similar to transfer completion interrupts EDMA3CC_INT the error interrupt also only pulses when the error interrupt condition transitions from...

Page 908: ...s that are allowed or not allowed to the MPPAG and MPPAn The active memory protection uses the PRIV and PRIVID attributes of the EDMA programmer The PRIV is the privilege level i e user vs supervisor The PRIVID refers to a privilege ID with a number that is associated with an EDMA3 programmer See the device specific data manual for the PRIVIDs that are associated with potential EDMA3 programmers T...

Page 909: ... a privilege level of User and Privilege ID of 0 MPPA 7 0x0000 04B0 Memory Protection Filter AID0 1 UW 0 UR 0 SW 1 SR 1 offset 0x082C X Access Denied EER 0x0000 0000 Final value of EER offset 0x1020 Example Access Allowed Write access to shadow region 7 s event enable set register EESR 1 The original value of the event enable register EER at address offset 0x1020 is 0x0 2 The MPPA 7 is set to allo...

Page 910: ...the write transactions to the destination endpoints The PRIV bit and PRIVID bit in the channel options parameter OPT is set with the EDMA3 programmer s PRIV value and PRIVID values respectively when any part of the PaRAM set is written The PRIV is the privilege level i e user vs supervisor The PRIVID refers to a privilege ID with a number that is associated with an EDMA3 programmer See the data ma...

Page 911: ...RIVID information travels along with the read and write requests that are issued to the source and destination memories For example if the access attributes that are associated with the L2 page with the source buffer only allow supervisor read write accesses SR SW the user level read request above is refused Similarly if the access attributes that are associated with the L1D page with the destinat...

Page 912: ...ng transfer controller is ready to receive another TR the event is de queued and the PaRAM set corresponding to the de queued event is processed and submitted as a transfer request packet TRP to the associated EDMA3 transfer controller Queue0 has highest priority and Queue3 has the lowest priority if Queue0 and Queue1 both have at least one event entry and if both TC0 and TC1 can accept transfer r...

Page 913: ...RTPTR are indicative of events still queued in the respective queue The remaining entry may be read to determine what s already de queued and submitted to the associated transfer controller 11 3 11 3 Queue Resource Tracking The EDMA3CC event queue includes watermarking threshold logic that allows you to keep track of maximum usage of all event queues This is useful for debugging real time deadline...

Page 914: ...S sized commands to the source destination addresses Each BCNT number of arrays are then serviced in succession For BCNT arrays of ACNT bytes that is a 2D transfer if the ACNT value is less than or equal to the DBS value then the TR may be optimized into a 1D transfer in order to maximize efficiency The optimization takes place if the EDMA3TC recognizes that the 2D transfer is organized as a singl...

Page 915: ...r high priority transfers and to a higher value if the transfer controller is targeted for low priority transfers In contrast the Write Interface does not have any performance turning knobs because writes always have an interval between commands as write commands are submitted along with the associated write data 11 3 12 2 Memory Protection The transfer controller plays an important role in handli...

Page 916: ... two important status details in TCSTAT that may be used during advanced debugging if necessary The DFSTRTPTR is a start pointer that is the index to the head of the destination FIFO register The DSTACTV is a counter for the number of valid occupied entries These registers may be used to get a brief history of transfers Examples of some register field values and their interpretation DFSTRTPTR 0 an...

Page 917: ...3CC programs the associated EDMA3TCn s Program Register Set with the TR 7 The TR is then passed to the Source Active set and the DST FIFO Register Set if both the register sets are available 8 The Read Controller processes the TR by issuing read commands to the source slave endpoint The Read Data lands in the Data FIFO of the EDMA3TCn 9 As soon as sufficient data is available the Write Controller ...

Page 918: ...or all masters including the priority of the transfer controllers with respect to each other 11 3 15 EDMA3 Operating Frequency Clock Control The EDMA3 channel controller and transfer controller are clocked from PLL_L3 SYSCLK4 The EDMA3 system runs at the L3 clock frequency 11 3 16 Reset Considerations A hardware reset resets the EDMA3 EDMA3CC and EDMA3TC and the EDMA3 configuration registers The P...

Page 919: ...TC0 TC3 L3 System priority Channel priority Trigger source priority Dequeue priority Early completion www ti com Functional Description Since EDMA3 is involved in servicing multiple master and slave peripherals it is not feasible to have an independent behavior of the EDMA3 for emulation halts EDMA3 functionality would be coupled with the peripherals it is servicing which might have different beha...

Page 920: ...gure 11 23 holds true with the synchronization type set to A synchronized and indexes cleared to 0 If the amount of data is greater than 64K bytes BCNT and the B indexes need to be set appropriately with the synchronization type set to AB synchronized The STATIC bit in OPT is set to prevent linking This transfer example may also be set up using QDMA For successive transfer submissions of a similar...

Page 921: ... transfer the EDMA3 retrieves a portion of data for the CPU to process In this example a 640 480 pixel frame of video data is stored in external memory Each pixel is represented by a 16 bit halfword The CPU extracts a 16 12 pixel subframe of the image for processing To facilitate more efficient processing time by the CPU the EDMA3 places the subframe in internal L2 SRAM Figure 11 24 shows the tran...

Page 922: ...rray occupying a portion of contiguous memory spaces For these instances the EDMA3 can reorganize the data into the desired format Figure 11 26 shows the data sorting To determine the parameter set values the following need to be considered ACNT Program this to be the size in bytes of an element BCNT Program this to be the number of elements in a frame CCNT Program this to be the number of frames ...

Page 923: ...A3 channel to service a peripheral it is necessary to know how data is to be presented to the processor Data is always provided with some kind of synchronization event as either one element per event non bursting or multiple elements per event bursting 11 3 19 4 1 Non bursting Peripherals Non bursting peripherals include the on chip multichannel audio serial port McASP and many external devices su...

Page 924: ...ension ACNT Channel Destination Address DST Channel Destination Address DST 0001h 0000h Destination BCNT Index DSTBIDX Source BCNT Index SRCBIDX 0000h FFFFh BCNT Reload BCNTRLD Link Address LINK 0000h 0000h Destination CCNT Index DSTCIDX Source CCNT Index SRCCIDX 0000h 0004h Reserved Count for 3rd Dimension CCNT b Channel Options Parameter OPT Content 31 30 28 27 24 23 22 21 20 19 18 17 16 0 000 0...

Page 925: ...to an external buffer one array at a time based on EVTn channel n must be configured Due to the nature of the data a video frame made up of arrays of pixels the destination is essentially a 2D entity Figure 11 31 shows the parameters to service the incoming data with a 1D to 2D transfer using AB synchronization The source address is set to the location of the video framer peripheral and the destin...

Page 926: ...ce BCNT Index SRCBIDX 0000h FFFFh BCNT Reload BCNTRLD Link Address LINK 0500h 0000h Destination CCNT Index DSTCIDX Source CCNT Index SRCCIDX 0000h 01E0h Reserved Count for 3rd Dimension CCNT b Channel Options Parameter OPT Content 31 30 28 27 24 23 22 21 20 19 18 17 16 0 000 0000 0 0 0 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0000 0 000 00...

Page 927: ...t be setup for 1D to 1D transfers with A synchronization Figure 11 33 shows the parameter entries for the channel for these transfers To service the McASP continuously the channels must be linked to a duplicate PaRAM set in the PaRAM After all frames have been transferred the EDMA3 channels reload and continue Figure 11 34 shows the reload parameters for the channel 11 3 19 4 3 1 Receive Channel E...

Page 928: ...1 0 0000 0 000 0000 0 0 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM c EDMA Parameters for Transmit Channel PaRAM Set 12 being Linked to PaRAM Set 65 Parameter Contents Parameter 0010 1000h Channel Options Parameter OPT Channel Source Address SRC Channel Source Address SRC 0080h 0001h Count for 2nd Dimension BCNT Count for 1st Dimension ACNT McASP TX Register Channel Destination Address DST...

Page 929: ... 2 1 0 0000 0 000 0000 0 0 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM c EDMA Reload Parameters PaRAM Set 65 for Transmit Channel Parameter Contents Parameter 0010 1000h Channel Options Parameter OPT Channel Source Address SRC Channel Source Address SRC 0080h 0001h Count for 2nd Dimension BCNT Count for 1st Dimension ACNT McASP TX Register Channel Destination Address DST 0000h 0001h Destin...

Page 930: ...her and the data transfers continue Figure 11 36 shows the EDMA3 channel configuration required Each channel has two parameter sets ping and pong The EDMA3 channel is initially loaded with the ping parameters Figure 11 36 The link address for the ping set is set to the PaRAM offset of the pong parameter set Figure 11 37 The link address for the pong set is set to the PaRAM offset of the ping param...

Page 931: ...mple Figure 11 36 Ping Pong Buffering for McASP Example PaRAM Configuration a EDMA Parameters for Channel 15 Using PaRAM Set 15 Linked to Pong Set 64 Parameter Contents Parameter 0010 D000h Channel Options Parameter OPT McASP RX Register Channel Source Address SRC 0080h 0001h Count for 2nd Dimension BCNT Count for 1st Dimension ACNT Channel Destination Address DST Channel Destination Address DST 0...

Page 932: ... to Set 65 Parameter Contents Parameter 0010 D000h Channel Options Parameter OPT McASP RX Register Channel Source Address SRC 0080h 0001h Count for 2nd Dimension BCNT Count for 1st Dimension ACNT Channel Destination Address DST Channel Destination Address DST 0001h 0000h Destination BCNT Index DSTBIDX Source BCNT Index SRCBIDX 0080h 4820h BCNT Reload BCNTRLD Link Address LINK 0000h 0000h Destinati...

Page 933: ...serviced at the same rate One FIFO buffers data input and the other buffers data output The EDMA3 channels that service these FIFOs can be set up for AB synchronized transfers While each FIFO is serviced with a different set of parameters both can be signaled from a single event For example an external interrupt pin can be tied to the status flags of one of the FIFOs When this event arrives the ED...

Page 934: ...l 48 parameters for chaining for chaining Channel 8 parameters Enable channel 48 EER E48 1 Event enable register EER Functional Description www ti com Figure 11 39 Intermediate Transfer Completion Chaining Example 11 3 19 4 5 2 Breaking Up Large Transfers with Intermediate Chaining Another feature of intermediate transfer chaining ITCCHEN is for breaking up large transfers A large transfer may loc...

Page 935: ... byte elements The TCC field in the channel options parameter OPT is set to the same value as the channel number and ITCCHEN are set In this example EDMA3 channel 25 is used and TCC is also set to 25 The TCINTEN may also be set to trigger interrupt 25 when the last 1 Kbyte array is transferred The CPU starts the EDMA3 transfer by writing to the appropriate bit of the event set register ESR E25 The...

Page 936: ...EVT1 McSPI0 20 Open Open 21 Open Open 22 GPIOEVT0 GPIO0 23 GPIOEVT1 GPIO1 24 SDTXEVT0 MMCHS0 25 SDRXEVT0 MMCHS0 26 UTXEVT0 UART0 27 URXEVT0 UART0 28 UTXEVT1 UART1 29 URXEVT1 UART1 30 UTXEVT2 UART2 31 URXEVT2 UART2 32 Open Open 33 Open Open 34 Open Open 35 Open Open 36 Open Open 37 Open Open 38 eCAPEVT0 eCAP 0 39 eCAPEVT1 eCAP 1 40 CAN_IF1DMA DCAN 0 41 CAN_IF2DMA DCAN 0 42 SPIXEVT0 McSPI1 43 SPIREV...

Page 937: ...HRPWMEVT2 eHRPWM 2 Table 11 24 Crossbar Mapped Event Number Event Name Source Module 1 SDTXEVT2 MMCHS2 2 SDRXEVT2 MMCHS2 3 I2CTXEVT2 I2C2 4 I2CRXEVT2 I2C2 5 Open Open 6 Open Open 7 UTXEVT3 UART3 8 URXEVT3 UART3 9 UTXEVT4 UART4 10 URXEVT4 UART4 11 UTXEVT5 UART5 12 URXEVT5 UART5 13 CAN_IF1DMA DCAN 1 14 CAN_IF2DMA DCAN 1 15 CAN_IF3DMA DCAN 1 16 Open Open 17 Open Open 18 Open Open 19 Open Open 20 Open...

Page 938: ...ernal pin XDMA_EVENT_INTR2 31 eQEPEVT2 eQEP 2 32 GPIOEVT2 GPIO2 33 Open 34 Open 35 Open 36 Open 37 Open 38 Open 39 Open 40 Open 41 Open 42 Open 43 Open 44 Open 45 Open 46 Open 47 Open 48 Open 49 Open 50 Open 51 Open 52 Open 53 Open 54 Open 55 Open 56 Open 57 Open 58 Open 59 Open 60 Open 61 Open 62 Open 63 Open 938 Enhanced Direct Memory Access EDMA SPRUH73H October 2011 Revised April 2013 Submit D...

Page 939: ...tion 11 4 1 1 6 0258h DMAQNUM6 DMA Queue Number Register 6 Section 11 4 1 1 6 025Ch DMAQNUM7 DMA Queue Number Register 7 Section 11 4 1 1 6 0260h QDMAQNUM QDMA Queue Number Register Section 11 4 1 1 7 0284h QUEPRI Queue Priority Register Section 11 4 1 1 8 0300h EMR Event Missed Register Section 11 4 1 2 1 0304h EMRH Event Missed Register High Section 11 4 1 2 1 0308h EMCR Event Missed Clear Regis...

Page 940: ... 6 2 1010h ESR Event Set Register Section 11 4 1 6 3 1014h ESRH Event Set Register High Section 11 4 1 6 3 1018h CER Chained Event Register Section 11 4 1 6 4 101Ch CERH Chained Event Register High Section 11 4 1 6 4 1020h EER Event Enable Register Section 11 4 1 6 5 1024h EERH Event Enable Register High Section 11 4 1 6 5 1028h EECR Event Enable Clear Register Section 11 4 1 6 6 102Ch EECRH Event...

Page 941: ...h SERH Secondary Event Register High 2040h SECR Secondary Event Clear Register 2044h SECRH Secondary Event Clear Register High 2050h IER Interrupt Enable Register 2054h IERH Interrupt Enable Register High 2058h IECR Interrupt Enable Clear Register 205Ch IECRH Interrupt Enable Clear Register High 2060h IESR Interrupt Enable Set Register 2064h IESRH Interrupt Enable Set Register High 2068h IPR Inter...

Page 942: ...ure 11 42 Peripheral ID Register PID 31 16 15 0 PID PID R 4001h R 4C00h LEGEND R W Read Write R Read only n value after reset Table 11 26 Peripheral ID Register PID Field Descriptions Bit Field Value Description 31 0 PID 40014C00h Peripheral identifier uniquely identifies the EDMA3CC and the specific revision of the EDMA3CC 942 Enhanced Direct Memory Access EDMA SPRUH73H October 2011 Revised April...

Page 943: ... reset Table 11 27 EDMA3CC Configuration Register CCCFG Field Descriptions Bit Field Value Description 31 26 Reserved 0 Reserved 25 MP_EXIST Memory protection existence 0 Reserved 1 Memory protection logic included 24 CHMAP_EXIST Channel mapping existence 0 Reserved 1 Channel mapping logic included 23 22 Reserved 0 Reserved 21 20 NUM_REGN 0 3h Number of MP and shadow regions 0 1h Reserved 2h 4 reg...

Page 944: ...t channels 5h 7h Reserved 7 Reserved 0 Reserved 6 4 NUM_QDMACH 0 7h Number of QDMA channels 0 3h Reserved 4h 8 QDMA channels 5h 7h Reserved 3 Reserved 0 Reserved 2 0 NUM_DMACH 0 7h Number of DMA channels 0 4h Reserved 5h 64 DMA channels 6h 7h Reserved 944 Enhanced Direct Memory Access EDMA SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments ...

Page 945: ...of the local target state management mode By definition target can handle read write transaction as long as it is out of IDLE state 0x0 Force idle mode local target s idle state follows acknowledges the system s idle requests unconditionally i e regardless of the IP module s internal requirements Backup mode for debug only 0x1 No idle mode local target never enters idle state Backup mode for debug...

Page 946: ... PAENTRY Reserved R 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 11 29 DMA Channel Map n Registers DCHMAPn Field Descriptions Bit Field Value Description 31 14 Reserved 0 Reserved 13 5 PAENTRY 0 1FFh Points to the PaRAM set number for DMA channel n 4 0 Reserved 0 Reserved 946 Enhanced Direct Memory Access EDMA SPRUH73H October 2011 Revised April 2013 Submit Documentation...

Page 947: ...ved R 0 15 14 13 5 4 2 1 0 Reserved PAENTRY TRWORD Reserved R 0 R W 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 11 30 QDMA Channel Map n Registers QCHMAPn Field Descriptions Bit Field Value Description 31 14 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior 13 5 PAENTRY 0 1FFh ...

Page 948: ... reset Table 11 31 DMA Channel Queue n Number Registers DMAQNUMn Field Descriptions Bit Field Value Description 31 0 En 0 7h DMA queue number Contains the event queue number to be used for the corresponding DMA channel Programming DMAQNUMn for an event queue number to a value more then the number of queues available in the EDMA3CC results in undefined behavior 0 Event n is queued on Q0 1h Event n ...

Page 949: ...DMAQNUM Field Descriptions Bit Field Value Description 31 15 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior 14 0 En 0 7h QDMA queue number Contains the event queue number to be used for the corresponding QDMA channel 0 Event n is queued on Q0 1h Event n is queued on Q1 2h Event n is queued on Q2 3h Eve...

Page 950: ...riority level used by TC3 relative to other masters in the device A value of 0 means highest priority and a value of 7 means lowest priority 11 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior 10 8 PRIQ2 0 7h Priority level for queue 2 Dictates the priority level used by TC2 relative to other masters in ...

Page 951: ...2 21 20 19 18 17 16 E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 11 35 Event Missed Register EMR Field Descriptions ...

Page 952: ...d Descriptions Bit Field Value Description 31 0 En Event missed 0 31 clear All error bits must be cleared before additional error interrupts will be asserted by the EDMA3CC 0 No effect 1 Corresponding missed event bit in the event missed register EMR is cleared En 0 Figure 11 53 Event Missed Clear Register High EMCRH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E63 E62 E61 E60 E59 E58 E57 E56 E...

Page 953: ...QEMR is shown in Figure 11 54 and described in Table 11 39 Figure 11 54 QDMA Event Missed Register QEMR 31 16 Reserved R 0 15 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 11 39 QDMA Event Missed Register QEMR Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved Always write 0 to this bit writes ...

Page 954: ... 0 11 4 1 2 5 EDMA3CC Error Register CCERR The EDMA3CC error register CCERR indicates whether or not at any instant of time the number of events queued up in any of the event queues exceeds or equals the threshold watermark value that is set in the queue watermark threshold register QWMTHRA Additionally CCERR also indicates if when the number of outstanding TRs that have been programmed to return ...

Page 955: ...shold has not been exceeded 1 Watermark threshold has been exceeded 0 QTHRXCD0 Queue threshold error for queue 0 QTHRXCD0 is cleared by writing a 1 to the corresponding bit in the EDMA3CC error clear register CCERRCLR 0 Watermark threshold has not been exceeded 1 Watermark threshold has been exceeded 11 4 1 2 6 EDMA3CC Error Clear Register CCERRCLR The EDMA3CC error clear register CCERRCLR is used...

Page 956: ...rror clear for queue 2 0 No effect 1 Clears the QTHRXCD2 bit in the EDMA3CC error register CCERR and the WM and THRXCD bits in the queue status register 2 QSTAT2 1 QTHRXCD1 Queue threshold error clear for queue 1 0 No effect 1 Clears the QTHRXCD1 bit in the EDMA3CC error register CCERR and the WM and THRXCD bits in the queue status register 1 QSTAT1 0 QTHRXCD0 Queue threshold error clear for queue...

Page 957: ... 58 Error Evaluation Register EEVAL 31 16 Reserved R 0 15 2 1 0 Reserved Rsvd EVAL R 0 R W 0 W 0 LEGEND R W Read Write R Read only W Write only n value after reset Table 11 43 Error Evaluation Register EEVAL Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may result in undefined behav...

Page 958: ... value after reset Figure 11 60 DMA Region Access Enable High Register for Region m DRAEHm 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E63 E62 E61 E60 E59 E58 E57 E56 E55 E54 E53 E52 E51 E50 E49 E48 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E47 E46 E45 E44 E43 E42 E41 E40 E39 E38 E37 E36 E35 E34 E33 E32 RW 0 RW 0 RW 0 ...

Page 959: ... 1 to this bit are not supported and attempts to do so may result in undefined behavior 7 0 En QDMA region access enable for bit n QDMA channel n in region m 0 Accesses via region m address space to bit n in any QDMA channel register are not allowed Reads return 0 on bit n and writes do not modify the state of bit n 1 Accesses via region m address space to bit n in any QDMA channel register are al...

Page 960: ...riggered event on DMA channel 15 The QxEy is shown in Figure 11 62 and described in Table 11 46 Figure 11 62 Event Queue Entry Registers QxEy 31 16 Reserved R 0 15 8 7 6 5 0 Reserved ETYPE ENUM R 0 R x R x LEGEND R Read only n value after reset x value is indeterminate after reset Table 11 46 Event Queue Entry Registers QxEy Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved A...

Page 961: ...t are not supported and attempts to do so may result in undefined behavior 20 16 WM 0 10h Watermark for maximum queue usage Watermark tracks the most entries that have been in queue n since reset or since the last time that the watermark WM bit was cleared WM is cleared by writing a 1 to the corresponding QTHRXCDn bit in the EDMA3CC error clear register CCERRCLR 0 10h Legal values are 0 empty to 1...

Page 962: ...RR and the THRXCD bit in the queue status register 2 QSTAT2 are set when the number of events in queue 2 at an instant in time visible via the NUMVAL bit in QSTAT2 equals or exceeds the value specified by Q2 0 10h The default is 16 maximum allowed 11h Disables the threshold errors 12h 1Fh Reserved 15 13 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and at...

Page 963: ...R is queued in queue 1 16 QUEACTV0 Queue 0 active 0 No events are queued in queue 0 1 At least one TR is queued in queue 0 15 14 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior 13 8 COMPACTV 0 3Fh Completion request active The COMPACTV field reflects the count for the number of completion requests submi...

Page 964: ... undefined behavior 2 TRACTV Transfer request active 0 Transfer request processing submission logic is inactive 1 Transfer request processing submission logic is active 1 QEVTACTV QDMA event active 0 No enabled QDMA events are active within the EDMA3CC 1 At least one enabled QDMA event QER is active within the EDMA3CC 0 EVTACTV DMA event active 0 No enabled DMA events are active within the EDMA3CC...

Page 965: ...on Fault Address Register MPFAR 31 16 FADDR R 0 15 0 FADDR R 0 LEGEND R Read only n value after reset Table 11 50 Memory Protection Fault Address Register MPFAR Field Descriptions Bit Field Value Description 31 0 FADDR 0 FFFF FFFFh Fault address This 32 bit read only status register contains the fault address when a memory protection violation is detected This register can only be cleared via the ...

Page 966: ...s been detected The FID field contains the privilege ID for the specific request requestor that resulted in an MP error 8 6 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior 5 SRE Supervisor read error 0 No error detected 1 Supervisor level task attempted to read from a MP page without SR permissions 4 SW...

Page 967: ...R Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior 0 MPFCLR Fault clear register 0 CPU write of 0 has no effect 1 CPU write of 1 to the MPFCLR bit causes any error conditions stored in the memory protection fault address register MPFAR and the memory pr...

Page 968: ...uests with Privilege ID 6 are permitted if access type is allowed as defined by permission settings UW UR SW SR 8 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior 7 6 Reserved 1 Reserved Always write 1 to this bit 5 SR Supervisor read permission 0 Supervisor read accesses are not allowed from region M 1 ...

Page 969: ...H The events are latched even when the events are not enabled If the event bit corresponding to the latched event is enabled EER En EERH En 1 then the event is evaluated by the EDMA3CC logic for an associated transfer request submission to the transfer controllers The event register bits are automatically cleared ER En ERH En 0 once the corresponding events are prioritized and serviced If ER En ER...

Page 970: ... prioritized versus other pending DMA QDMA events for submission to the EDMA3TC Figure 11 71 Event Register High ERH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E63 E62 E61 E60 E59 E58 E57 E56 E55 E54 E53 E52 E51 E50 E49 E48 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E47 E46 E45 E44 E43 E42 E41 E40 E39 E38 E37 E36 E35 E34 E33 E32 R 0 R...

Page 971: ...15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND W Write only n value after reset Table 11 56 Event Clear Register ECR Field Descriptions Bit Field Value Description 31 0 En Event clear for event 0 31 Any of the event bits in ECR is set to clear the event En in the event register ER A write of 0 has no effect 0 No effect 1 ...

Page 972: ... event was previously clear then the event remains set and is prioritized for submission to the event queues Manually triggered transfers via writes to ESR ESRH allow the CPU to submit DMA requests in the system these are relevant for memory to memory transfer scenarios If the ESR En ESRH En bit is already set and another CPU write of 1 is attempted to the same bit then the corresponding event is ...

Page 973: ...E36 E35 E34 E33 E32 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 LEGEND R W Read Write n value after reset Table 11 59 Event Set Register High ESRH Field Descriptions Bit Field Value Description 31 0 En Event set for event 32 63 0 No effect 1 Corresponding DMA event is prioritized versus other pending DMA QDMA events for submission to the EDMA3TC 973 SPRUH73H Oct...

Page 974: ...ion wins If the event was previously set then EMR EMRH would be set because an event is lost If the event was previously clear then the event remains set and is prioritized for submission to the event queues The CER is shown in Figure 11 76 and described in Table 11 60 The CERH is shown in Figure 11 77 and described in Table 11 61 Figure 11 76 Chained Event Register CER 31 30 29 28 27 26 25 24 23 ...

Page 975: ...1 0 En Chained event set for event 32 63 0 No effect 1 Corresponding DMA event is prioritized versus other pending DMA QDMA events for submission to the EDMA3TC 975 SPRUH73H October 2011 Revised April 2013 Enhanced Direct Memory Access EDMA Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 976: ... 12 11 10 9 8 7 6 5 4 3 2 1 0 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 11 62 Event Enable Register EER Field Descriptions Bit Field Value Description 31 0 En Event enable for events 0 31 0 Event is not enabled An external event latched in the event register ER is not evaluated ...

Page 977: ... W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND W Write only n value after reset Table 11 64 Event Enable Clear Register EECR Field Descriptions Bit Field Value Description 31 0 En Event enable clear for events 0 31 0 No effect 1 Event is disabled Corresponding bit in the event enable register EER is cleared En 0 Figure 11 81 Event Enable Clear Register High EECRH 31 30 29 28 27 26 25 24 23 22 21 20 19 18...

Page 978: ...W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND W Write only n value after reset Table 11 66 Event Enable Set Register EESR Field Descriptions Bit Field Value Description 31 0 En Event enable set for events 0 31 0 No effect 1 Event is enabled Corresponding bit in the event enable register EER is set En 1 Figure 11 83 Event Enable Set Register High EESRH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E63 E...

Page 979: ...E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 11 68 Secondary Event Register SER Field Descriptions Bit Field Value Description 31 0 En Secondary event register The secondary event register is used along with the event register ER to provide information on the state of an event 0 Event ...

Page 980: ... Secondary Event Clear Register SECR Field Descriptions Bit Field Value Description 31 0 En Secondary event clear register 0 No effect 1 Corresponding bit in the secondary event register SER is cleared En 0 Figure 11 87 Secondary Event Clear Register High SECRH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E63 E62 E61 E60 E59 E58 E57 E56 E55 E54 E53 E52 E51 E50 E49 E48 W 0 W 0 W 0 W 0 W 0 W 0 W ...

Page 981: ...R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 11 72 Interrupt Enable Register IER Field Descriptions Bit Field Value Description 31 0 En Interrupt enable for channels 0 31 0 Interrupt is not enabled 1 Inte...

Page 982: ...No effect 1 Corresponding bit in the interrupt enable register IER is cleared In 0 Figure 11 91 Interrupt Enable Clear Register High IECRH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 I63 I62 I61 I60 I59 I58 I57 I56 I55 I54 I53 I52 I51 I50 I49 I48 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I47 I46 I45 I44 I43 I42 I41 I40 I39 I38 I37 I36...

Page 983: ...le 11 76 Interrupt Enable Set Register IESR Field Descriptions Bit Field Value Description 31 0 En Interrupt enable set for channels 0 31 0 No effect 1 Corresponding bit in the interrupt enable register IER is set In 1 Figure 11 93 Interrupt Enable Set Register High IESRH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 I63 I62 I61 I60 I59 I58 I57 I56 I55 I54 I53 I52 I51 I50 I49 I48 W 0 W 0 W 0 W 0...

Page 984: ...R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 11 78 Interrupt Pending Register IPR Field Descriptions Bit Field Value Description 31 0 In Interrupt pending for TCC 0 31 0 Interrupt transfer completion code is not detected or was cleared 1 Interrupt transfer completion code is detected In 1 n EDMA3TC 5 0 Figure 11 95 Interrupt Pending Regis...

Page 985: ... effect 1 Corresponding bit in the interrupt pending register IPR is cleared In 0 Figure 11 97 Interrupt Clear Register High ICRH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 I63 I62 I61 I60 I59 I58 I57 I56 I55 I54 I53 I52 I51 I50 I49 I48 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I47 I46 I45 I44 I43 I42 I41 I40 I39 I38 I37 I36 I35 I34 ...

Page 986: ...AL Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior 1 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior 0 EVAL Interrupt evaluate 0 No effect 1 Causes EDMA3CC ...

Page 987: ...itional conditions that can lead to the setting of QER bits see EDMA Overview The setting of an event is a higher priority relative to clear operations via hardware If set and clear conditions occur concurrently the set condition wins If the event was previously set then the QDMA event missed register QEMR would be set because an event is lost If the event was previously clear then the event remai...

Page 988: ...Figure 11 100 QDMA Event Enable Register QEER 31 16 Reserved R 0 15 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 11 84 QDMA Event Enable Register QEER Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so m...

Page 989: ...e Clear Register QEECR 31 16 Reserved R 0 15 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND R Read only W Write only n value after reset Table 11 85 QDMA Event Enable Clear Register QEECR Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may ...

Page 990: ...ble Set Register QEESR 31 16 Reserved R 0 15 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND R Read only W Write only n value after reset Table 11 86 QDMA Event Enable Set Register QEESR Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may re...

Page 991: ... QDMA transfer might be different For additional conditions that can cause the secondary event registers QSER SER to be set see EDMA Overview The QSER is shown in Figure 11 103 and described in Table 11 87 Figure 11 103 QDMA Secondary Event Register QSER 31 16 Reserved R 0 15 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset...

Page 992: ... 104 and described in Table 11 88 Figure 11 104 QDMA Secondary Event Clear Register QSECR 31 16 Reserved R 0 15 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND R Read only W Write only n value after reset Table 11 88 QDMA Secondary Event Clear Register QSECR Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 En QDMA secondary eve...

Page 993: ...O Set Destination Address B Reference Register Section 11 4 2 7 18 0300h DFOPT0 Destination FIFO Options Register 0 Section 11 4 2 7 10 0304h DFSRC0 Destination FIFO Source Address Register 0 Section 11 4 2 7 11 0308h DFCNT0 Destination FIFO Count Register 0 Section 11 4 2 7 12 030Ch DFDST0 Destination FIFO Destination Address Register 0 Section 11 4 2 7 13 0310h DFBIDX0 Destination FIFO BIDX Regi...

Page 994: ...tant register that uniquely identifies the EDMA3TC and specific revision of the EDMA3TC The PID is shown in Figure 11 105 and described in Table 11 90 Figure 11 105 Peripheral ID Register PID 31 16 15 0 PID PID R 4000h R 7C00h LEGEND R W Read Write R Read only n value after reset Table 11 90 Peripheral ID Register PID Field Descriptions Bit Field Value Description 31 0 PID 40007C00 Peripheral iden...

Page 995: ...MA3TC Configuration Register TCCFG Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 8 DREGDEPTH 0 3h Destination register FIFO depth parameterization 0 Reserved 1h Reserved 2h 4 entry for TC0 TC1 TC2 and TC3 3h Reserved 7 6 Reserved 0 Reserved 5 4 BUSWIDTH 0 3h Bus width parameterization 0 1h Reserved 2h 128 bit 3h Reserved 3 Reserved 0 Reserved 2 0 FIFOSIZE 0 7h FIFO siz...

Page 996: ...f standby state Backup mode for debug only 0x2 Smart standby mode local initiator standby status depends on local conditions i e the module s functional requirement from the initiator IP module should not generate initiator related wakeup events 0x3 Reserved 3 2 IDLEMODE 2h Configuration of the local target state management mode By definition target can handle read write transaction as long as it ...

Page 997: ...al values are constrained by the destination register FIFO depth parameterization DSTREGDEPTH parameter 0 Destination FIFO is empty 1h Destination FIFO contains 1 TR 2h Destination FIFO contains 2 TRs 3h Destination FIFO contains 3 TRs 4h Destination FIFO contains 4 TRs Full if DSTREGDEPTH 4 If the destination register FIFO is empty then any TR written to Prog Set immediately transitions to the de...

Page 998: ...it Field Value Description 0 PROGBUSY Program register set busy 0 Program set idle and is available for programming by the EDMA3CC 1 Program set busy 998 Enhanced Direct Memory Access EDMA SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 999: ...error 0 Condition is not detected 1 User attempted to read or write to an invalid address in configuration memory map 2 TRERR Transfer request TR error event 0 Condition is not detected 1 TR detected that violates constant addressing mode transfer SAM or DAM is set alignment rules or has ACNT or BCNT 0 1 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and a...

Page 1000: ... and attempts to do so may result in undefined behavior 3 MMRAERR Interrupt enable for MMR address error MMRAERR 0 MMRAERR is disabled 1 MMRAERR is enabled and contributes to the state of EDMA3TC error interrupt generation 2 TRERR Interrupt enable for transfer request error TRERR 0 TRERR is disabled 1 TRERR is enabled and contributes to the state of EDMA3TC error interrupt generation 1 Reserved 0 ...

Page 1001: ... MMRAERR bit in the error status register ERRSTAT 0 No effect 1 Clears the MMRAERR bit in ERRSTAT but does not clear the error details register ERRDET 2 TRERR Interrupt enable clear for the TRERR bit in the error status register ERRSTAT 0 No effect 1 Clears the TRERR bit in ERRSTAT but does not clear the error details register ERRDET 1 Reserved 0 Reserved Always write 0 to this bit writes of 1 to ...

Page 1002: ... parameter OPT programmed by the channel controller for the read or write transaction that resulted in an error 15 14 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior 13 8 TCC 0 3Fh Transfer complete code Contains the TCC value in the channel options parameter OPT programmed by the channel controller for...

Page 1003: ...it Field Value Description 31 2 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior 1 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior 0 EVAL Error evaluate 0 No effect 1 EDMA3TC error line is pulsed if any of the...

Page 1004: ... NOTE It is expected that the RDRATE value for a transfer controller is static as it is decided based on the application requirement It is not recommended to change this setting on the fly Figure 11 114 Read Rate Register RDRATE 31 16 Reserved R 0 15 3 2 0 Reserved RDRATE R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 11 99 Read Rate Register RDRATE Field Descriptions Bit Fi...

Page 1005: ...23 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior 22 TCCHEN Transfer complete chaining enable 0 Transfer complete chaining is disabled 1 Transfer complete chaining is enabled 21 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may result in ...

Page 1006: ...o may result in undefined behavior 1 DAM Destination address mode within an array 0 Increment INCR mode Destination addressing within an array increments 1 Constant addressing CONST mode Destination addressing within an array wraps around upon reaching FIFO width 0 SAM Source address mode within an array 0 Increment INCR mode Source addressing within an array increments 1 Constant addressing CONST...

Page 1007: ...cribed in Table 11 102 Figure 11 117 Source Active Count Register SACNT 31 16 BCNT R 0 15 0 ACNT R 0 LEGEND R Read only n value after reset Table 11 102 Source Active Count Register SACNT Field Descriptions Bit Field Value Description 31 16 BCNT 0 FFFFh B dimension count Number of arrays to be transferred where each array is ACNT in length It is decremented after each read command appropriately Re...

Page 1008: ...on index register SABIDX is shown in Figure 11 119 and described in Table 11 104 Figure 11 119 Source Active Source B Dimension Index Register SABIDX 31 16 DBIDX R 0 15 0 SBIDX R 0 LEGEND R Read only n value after reset Table 11 104 Source Active Source B Dimension Index Register SABIDX Field Descriptions Bit Field Value Description 31 16 DBIDX 0 B Index offset between destination arrays Represent...

Page 1009: ... is submitted to the EDMA3TC The privilege ID is used while issuing read and write command to the target endpoints so that the target endpoints can perform memory protection checks based on the PRIV of the host that set up the DMA transaction 0 User level privilege 1 Supervisor level privilege 7 4 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts...

Page 1010: ...ginally programmed value of ACNT The reload value is used to reinitialize ACNT after each array is serviced 11 4 2 7 8 Source Active Source Address B Reference Register SASRCBREF The source active source address B reference register SASRCBREF is shown in Figure 11 122 and described in Table 11 107 Figure 11 122 Source Active Source Address B Reference Register SASRCBREF 31 16 SADDRBREF R 0 15 0 SA...

Page 1011: ... Destination Address B Reference Register SADSTBREF 31 16 Reserved R 0 15 0 Reserved R 0 LEGEND R Read only n value after reset Table 11 108 Source Active Destination Address B Reference Register SADSTBREF Field Descriptions Bit Field Value Description 31 0 Reserved 0 Reserved Always reads as 0 1011 SPRUH73H October 2011 Revised April 2013 Enhanced Direct Memory Access EDMA Submit Documentation Fe...

Page 1012: ...nable 0 Transfer complete interrupt is disabled 1 Transfer complete interrupt is enabled 19 18 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempts to do so may result in undefined behavior 17 12 TCC 0 3Fh Transfer complete code This 6 bit code is used to set the relevant bit in CER or IPR of the EDMA3PCC module 11 Reserved 0 Reserved Always write 0...

Page 1013: ...dressing CONST mode Destination addressing within an array wraps around upon reaching FIFO width 0 SAM Source address mode within an array 0 Increment INCR mode Source addressing within an array increments 1 Constant addressing CONST mode Source addressing within an array wraps around upon reaching FIFO width 1013 SPRUH73H October 2011 Revised April 2013 Enhanced Direct Memory Access EDMA Submit D...

Page 1014: ...scribed in Table 11 111 NOTE The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC Figure 11 126 Destination FIFO Count Register DFCNTn 31 16 BCNT R 0 15 0 ACNT R 0 LEGEND R Read only n value after reset Table 11 111 Destination FIFO Count Register DFCNTn Field Descriptions Bit Field Value Description 31 16 BCNT 0 FFFFh B dimension count Number of arrays to be transferred where each a...

Page 1015: ...alue should be the address of the last write command issued 11 4 2 7 14 Destination FIFO B Index Register DFBIDXn The destination FIFO B index register DFBIDXn is shown in Figure 11 128 and described in Table 11 113 NOTE The value for n varies from 0 to DSTREGDEPTH for the given EDMA3TC Figure 11 128 Destination FIFO B Index Register DFBIDXn 31 16 DBIDX R 0 15 0 SBIDX R 0 LEGEND R Read only n valu...

Page 1016: ...he associated TR is submitted to the EDMA3TC The privilege ID is used while issuing read and write command to the target endpoints so that the target endpoints can perform memory protection checks based on the PRIV of the host that set up the DMA transaction 0 User level privilege 1 Supervisor level privilege 7 4 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not suppor...

Page 1017: ...t reload value Represents the originally programmed value of ACNT The reload value is used to reinitialize ACNT after each array is serviced 11 4 2 7 17 Destination FIFO Source Address B Reference Register DFSRCBREFn The destination FIFO source address B reference register DFSRCBREFn is shown in Figure 11 131 and described in Table 11 116 Figure 11 131 Destination FIFO Source Address B Reference R...

Page 1018: ...is possible that a trigger event was received when the parameter set associated with set not allowing additional transfers to the channel event was a NULL set for a previous transfer on the channel This is occur on a channel typical in two cases 1 QDMA channels Typically if the parameter set is non static and expected to be terminated by a NULL set i e OPT STATIC 0 LINK 0xFFFF the parameter set is...

Page 1019: ...2 Writes to the shadow region memory maps are governed by region access registers DRAE DRAEH QRAE If the appropriate channels are not enabled in these registers read write access to the shadow region memory map is not enabled 3 When working with shadow region completion interrupts ensure that the DMA Region Access Registers DRAE DRAEH for every region are set in a mutually exclusive way unless it ...

Page 1020: ...el is used set up the QDMAQNUM to map the channel to the respective event queue ii If a DMA channel is used set up the DMAQNUM to map the event to the respective event queue Step 2 Parameter set setup a Program the PaRAM set number associated with the channel Note that if it is a QDMA channel the PaRAM entry that is configured as trigger word is written to last Alternatively enable the QDMA channe...

Page 1021: ...letion a If the interrupts are enabled as mentioned in step 3 above then the EDMA3CC will generate a completion interrupt to the CPU whenever transfer completion results in setting the corresponding bits in the interrupt pending register IPR IPRH The set bits must be cleared in the IPR IPRH by writing to corresponding bit in ICR ICRH b If polling for completion interrupts not enabled in the device...

Page 1022: ...r of the device Topic Page 12 1 Introduction 1023 12 2 Integration 1024 12 3 Functional Description 1026 12 4 Operational Modes 1029 12 5 Touchscreen Controller Registers 1033 1022 Touchscreen Controller SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1023: ...ns Sequence through all input channels based on a mask Programmable OpenDelay before sampling each channel Programmable sampling delay for each channel Programmable averaging of input samples 16 8 4 2 1 Differential or singled ended mode setting for each channel Store data in either of two FIFO groups Option to encode channel number with data Support for servicing FIFOs via DMA or CPU Programmable...

Page 1024: ...ADC Integration pr1_host_intr 0 7 corresponds to Host 2 to Host 9 of the PRU ICSS interrupt controller 12 2 1 TSC_ADC Connectivity Attributes The general connectivity attributes for the TSC_ADC module are summarized in Table 12 1 Table 12 1 TSC_ADC Connectivity Attributes Attributes Type Power domain Wakeup Domain Clock domain PD_WKUP_L4_WKUP_GCLK OCP PD_WKUP_ADC_FCLK Func Reset signals WKUP_DOM_R...

Page 1025: ..._wkup_gclk OCP Functional clock From PRCM adc_clk 24 MHz CLK_M_OSC pd_wkup_adc_fclk ADC clock typ From PRCM 12 2 3 TSC_ADC Pin List The TSC_ADC external interface signals are shown in Table 12 3 Table 12 3 TSC_ADC Pin List Pin Type Description AN 7 0 I Analog Input VREFN Power Analog Reference Input Negative Terminal VREFP Power Analog Reference Input Positive Terminal 1025 SPRUH73H October 2011 R...

Page 1026: ...ediately sampled again up to 16 times and final averaged sample data is stored in the FIFO Each channel input can be independently configured via the Step Configuration registers 12 3 4 One Shot Single or Continuous Mode When the sequencer finishes cycling through all the enabled steps the user can decide if the sequencer should stop one shot or loop back and schedule a the step again continuous I...

Page 1027: ...the TSC_ADC_SS Before user can turn the module back on he must first check if the ADC FSM is in IDLE state by reading from the ADC_STATUS_REG register 12 3 6 DMA Requests Each FIFO group can be serviced by either a DMA or by the CPU To generate DMA requests the user must set the enable bit in the DMAENABLE_SET Register Also the user can program the desired number of words to generate a DMA request...

Page 1028: ...Control PENIRQ 1 0 PENCTR 1 0 4 SEL_RFP 2 0 SEL_INP 3 0 YPPSW XNPSW XPPSW Functional Description www ti com Figure 12 2 Functional Block Diagram 1 In AM335x ARM Cortex A8 Microprocessors MPUs literature number SPRS717 VDDA_ADC and VSSA_ADC are referred to as Internal References VREFP and VREFN are referred to as External References 2 In AM438x ARM Cortex A9 Microprocessors MPUs literature number S...

Page 1029: ...a HW pen down event occurred and then begin the HW step conversions The touchscreen Charge step occurs after the last HW step before going back to the Idle state the TS Charge step is needed to charge touch screen capacitance which allows the controller to detect subsequent Pen touch events Assuming a mixed mode application touchscreen and general purpose channels the user can configure the steps ...

Page 1030: ...control The HW Pen events will be temporarily ignored during the Charge step HW will mask any potential glitches that may occur If the sequencer is not using the HW synchronized approach all the steps are configured as software enabled then it is the software programmer s responsibility to correctly turn on and off the AFE_Pen_Ctrl bits to receive the correct measurements from the touchscreen The ...

Page 1031: ...No Set preempt flag 1 Save N Yes HW event can either be Pen touch or input HW event but not both Set N 0 Set pen down flag 1 Set pen override mask 1 Ignore Pen IRQs Incr N Update Shadow StepEnable Reg Yes No Ifpreempt flag is 1 restore N elseset N to first SW Stepconfig www ti com Operational Modes Figure 12 3 Sequencer FSM The previous diagram does not actually represent clock cycles but instead ...

Page 1032: ...nd assuming at least one StepEnable N is active the FSM will transition from the Idle state and apply the first active StepConfig N and StepDelay N register settings It is possible for the OpenDelay N value to be 0 and therefore the FSM will immediately skip to the SampleDelay N state which is minimum 1 clock cycle The ADC will begin the sampling on the falling edge of the SOC signal After the ADC...

Page 1033: ...ection 12 5 1 15 58h IDLECONFIG Section 12 5 1 16 5Ch TS_CHARGE_STEPCONFIG Section 12 5 1 17 60h TS_CHARGE_DELAY Section 12 5 1 18 64h STEPCONFIG1 Section 12 5 1 19 68h STEPDELAY1 Section 12 5 1 20 6Ch STEPCONFIG2 Section 12 5 1 21 70h STEPDELAY2 Section 12 5 1 22 74h STEPCONFIG3 Section 12 5 1 23 78h STEPDELAY3 Section 12 5 1 24 7Ch STEPCONFIG4 Section 12 5 1 25 80h STEPDELAY4 Section 12 5 1 26 8...

Page 1034: ...5 1 47 D8h STEPDELAY15 Section 12 5 1 48 DCh STEPCONFIG16 Section 12 5 1 49 E0h STEPDELAY16 Section 12 5 1 50 E4h FIFO0COUNT Section 12 5 1 51 E8h FIFO0THRESHOLD Section 12 5 1 52 ECh DMA0REQ Section 12 5 1 53 F0h FIFO1COUNT Section 12 5 1 54 F4h FIFO1THRESHOLD Section 12 5 1 55 F8h DMA1REQ Section 12 5 1 56 100h FIFO0DATA Section 12 5 1 57 200h FIFO1DATA Section 12 5 1 58 1034 Touchscreen Control...

Page 1035: ...GEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 12 5 REVISION Register Field Descriptions Bit Field Type Reset Description 31 30 SCHEME R 1h HL 0 8 scheme 29 28 Reserved R 0h Always read as 0 Writes have no affect 27 16 FUNC R 730h Functional Number 15 11 R_RTL R 0h RTL revision Will vary depending on release 10 8 X_MAJOR R 0h Major revision 7 6 CUSTOM R 0h Cu...

Page 1036: ...0 Reserved IdleMode Reserved R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 12 6 SYSCONFIG Register Field Descriptions Bit Field Type Reset Description 31 4 Reserved R W 0h 3 2 IdleMode R W 0h 00 Force Idle always acknowledges 01 No Idle Mode never acknowledges 10 Smart Idle Mode 11 Smart Idle with Wakeup 1 0 Reserved R W 0h 1036 Touchs...

Page 1037: ...ized R W 0h Write 0 No action Write 1 Set event debug Read 0 No event pending Read 1 Event pending 9 Pen_Up_Event R W 0h Write 0 No action Write 1 Set event debug Read 0 No event pending Read 1 Event pending 8 Out_of_Range R W 0h Write 0 No action Write 1 Set event debug Read 0 No event pending Read 1 Event pending 7 FIFO1_Underflow R W 0h Write 0 No action Write 1 Set event debug Read 0 No event ...

Page 1038: ...event pending Read 1 Event pending 1 End_of_Sequence R W 0h Write 0 No action Write 1 Set event debug Read 0 No event pending Read 1 Event pending 0 HW_Pen_Event_asynchro R W 0h Write 0 No action nous Write 1 Set event debug Read 0 No event pending Read 1 Event pending 1038 Touchscreen Controller SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instr...

Page 1039: ...No enabled event pending Read 1 Event pending Write 1 Clear raw event 9 Pen_Up_event R W 0h Write 0 No action Read 0 No enabled event pending Read 1 Event pending Write 1 Clear raw event 8 Out_of_Range R W 0h Write 0 No action Read 0 No enabled event pending Read 1 Event pending Write 1 Clear raw event 7 FIFO1_Underflow R W 0h Write 0 No action Read 0 No enabled event pending Read 1 Event pending ...

Page 1040: ...ding Write 1 Clear raw event 1 End_of_Sequence R W 0h Write 0 No action Read 0 No enabled event pending Read 1 Event pending Write 1 Clear raw event 0 HW_Pen_Event_asynchro R W 0h Write 0 No action nous Read 0 No enabled event pending Read 1 Event pending Write 1 Clear raw event 1040 Touchscreen Controller SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 T...

Page 1041: ...led masked Read 1 Interrupt enabled Write 1 Enable interrupt 9 Pen_Up_event R W 0h Write 0 No action Read 0 Interrupt disabled masked Read 1 Interrupt enabled Write 1 Enable interrupt 8 Out_of_Range R W 0h Write 0 No action Read 0 Interrupt disabled masked Read 1 Interrupt enabled Write 1 Enable interrupt 7 FIFO1_Underflow R W 0h Write 0 No action Read 0 Interrupt disabled masked Read 1 Interrupt ...

Page 1042: ...ed Write 1 Enable interrupt 1 End_of_Sequence R W 0h Write 0 No action Read 0 Interrupt disabled masked Read 1 Interrupt enabled Write 1 Enable interrupt 0 HW_Pen_Event_asynchro R W 0h Write 0 No action nous Read 0 Interrupt disabled masked Read 1 Interrupt enabled Write 1 Enable interrupt 1042 Touchscreen Controller SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright ...

Page 1043: ...ed masked Read 1 Interrupt enabled Write 1 Disable interrupt 9 Pen_Up_Event R W 0h Write 0 No action Read 0 Interrupt disabled masked Read 1 Interrupt enabled Write 1 Disable interrupt 8 Out_of_Range R W 0h Write 0 No action Read 0 Interrupt disabled masked Read 1 Interrupt enabled Write 1 Disable interrupt 7 FIFO1_Underflow R W 0h Write 0 No action Read 0 Interrupt disabled masked Read 1 Interrup...

Page 1044: ...d Write 1 Disable interrupt 1 End_of_Sequence R W 0h Write 0 No action Read 0 Interrupt disabled masked Read 1 Interrupt enabled Write 1 Disable interrupt 0 HW_Pen_Event_asynchro R W 0h Write 0 No action nous Read 0 Interrupt disabled masked Read 1 Interrupt enabled Write 1 Disable interrupt 1044 Touchscreen Controller SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyrigh...

Page 1045: ...2 11 10 9 8 Reserved R W 0h 7 6 5 4 3 2 1 0 Reserved WAKEEN0 R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 12 11 IRQWAKEUP Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R W 0h 0 WAKEEN0 R W 0h Wakeup generation for HW Pen event 0 Wakeup disabled 1 Wakeup enabled 1045 SPRUH73H October 2011 Revised April 2013 Touchs...

Page 1046: ...ND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 12 12 DMAENABLE_SET Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R W 0h 1 Enable_1 R W 0h Enable DMA request FIFO 1 Write 0 No action Read 0 DMA line disabled Read 1 DMA line enabled Write 1 Enable DMA line 0 Enable_0 R W 0h Enable DMA request FIFO 0 Write 0 No action Read 0 DMA line d...

Page 1047: ... R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 12 13 DMAENABLE_CLR Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R W 0h 1 Enable_1 R W 0h Disable DMA request FIFO 1 Write 0 No action Read 0 DMA line disabled Read 1 DMA line enabled Write 1 Disable DMA line 0 Enable_0 R W 0h Disable DMA request FIFO 0 Write 0 No action Read 0 DMA line ...

Page 1048: ..._Ctrl R W 0h These two bits are sent directly to the AFE Pen Ctrl inputs Bit 6 controls the Wiper touch 5 wire modes Bit 5 controls the X touch 4 wire modes User also needs to make sure the ground path is connected properly for pen interrupt to occur using the StepConfig registers Refer to section 4 interrupts for more information 4 Power_Down R W 0h ADC Power Down control 0 AFE is powered up defa...

Page 1049: ... clear bit n value after reset Table 12 15 ADCSTAT Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 PEN_IRQ1 R 0h PEN_IRQ 1 status 6 PEN_IRQ0 R 0h PEN_IRQ 0 status 5 FSM_BUSY R 0h Status of OCP FSM and ADC FSM 0 Idle 1 Busy 4 0 STEP_ID R 10h Encoded values 10000 Idle 10001 Charge 00000 Step 1 00001 Step 2 00010 Step 3 00011 Step 4 00100 Step 5 00101 Step 6 00110 St...

Page 1050: ...EGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 12 16 ADCRANGE Register Field Descriptions Bit Field Type Reset Description 31 28 Reserved R 0h 27 16 High_Range_Data R W 0h Sampled ADC data is compared to this value If the sampled data is greater than the value then an interrupt is generated 15 12 Reserved R 0h Reserved 11 0 Low_Range_Data R W 0h Sampled ADC ...

Page 1051: ...15 14 13 12 11 10 9 8 ADC_ClkDiv R W 0h 7 6 5 4 3 2 1 0 ADC_ClkDiv R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 12 17 ADC_CLKDIV Register Field Descriptions Bit Field Type Reset Description 31 16 Reserved R 0h 15 0 ADC_ClkDiv R W 0h The input ADC clock will be divided by this value and sent to the AFE Program to the value minus 1 1051 SPRUH73H Octo...

Page 1052: ...pare_Output AFE_Spare_Input R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 12 18 ADC_MISC Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h RESERVED 7 4 AFE_Spare_Output R 0h Connected to AFE Spare Output pins Reserved in normal operation 3 0 AFE_Spare_Input R W 0h Connected to AFE Spare Input pins Reserved in norma...

Page 1053: ...it n value after reset Table 12 19 STEPENABLE Register Field Descriptions Bit Field Type Reset Description 31 17 Reserved R 0h RESERVED 16 STEP16 R W 0h Enable step 16 15 STEP15 R W 0h Enable step 15 14 STEP14 R W 0h Enable step 14 13 STEP13 R W 0h Enable step 13 12 STEP12 R W 0h Enable step 12 11 STEP11 R W 0h Enable step 11 10 STEP10 R W 0h Enable step 10 9 STEP9 R W 0h Enable step 9 8 STEP8 R W...

Page 1054: ...1 26 Reserved R W 0h 25 Diff_CNTRL R W 0h Differential Control Pin 0 Single Ended 1 Differential Pair Enable 24 23 SEL_RFM__SWC_1_0 R W 0h SEL_RFM pins SW configuration 00 VSSA_ADC 01 XNUR 10 YNLR 11 VREFN 22 19 SEL_INP_SWC_3_0 R W 0h SEL_INP pins SW configuration 0000 Channel 1 0111 Channel 8 1xxx VREFN 18 15 SEL_INM_SWM3_0 R W 0h SEL_INM pins for neg differential 0000 Channel 1 0111 Channel 8 1x...

Page 1055: ...Field Type Reset Description 31 26 Reserved R W 0h 25 Diff_CNTRL R W 0h Differential Control Pin 0 Single Ended 1 Differential Pair Enable 24 23 SEL_RFM__SWC_1_0 R W 0h SEL_RFM pins SW configuration 00 VSSA 01 XNUR 10 YNLR 11 VREFN 22 19 SEL_INP_SWC_3_0 R W 0h SEL_INP pins SW configuration 0000 Channel 1 0111 Channel 8 1xxx VREFN 18 15 SEL_INM_SWM3_0 R W 0h SEL_INM pins for neg differential 0000 C...

Page 1056: ...12 11 10 9 8 OpenDelay R W 1h 7 6 5 4 3 2 1 0 OpenDelay R W 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 12 22 TS_CHARGE_DELAY Register Field Descriptions Bit Field Type Reset Description 31 18 Reserved R W 0h 17 0 OpenDelay R W 1h Program the of ADC clock cycles to wait between applying the step configuration registers and going back to the IDLE state...

Page 1057: ...check register 26 FIFO_select R W 0h Sampled data will be stored in FIFO 0 FIFO 1 FIFO 1 25 Diff_CNTRL R W 0h Differential Control Pin 24 23 SEL_RFM_SWC_1_0 R W 0h SEL_RFM pins SW configuration 22 19 SEL_INP_SWC_3_0 R W 0h SEL_INP pins SW configuration 18 15 SEL_INM_SWC_3_0 R W 0h SEL_INM pins for negative differential 14 12 SEL_RFP_SWC_2_0 R W 0h SEL_RFP pins SW configuration 11 WPNSW_SWC R W 0h ...

Page 1058: ...clear bit n value after reset Table 12 24 STEPDELAY1 Register Field Descriptions Bit Field Type Reset Description 31 24 SampleDelay R W 0h This register will control the number of ADC clock cycles to sample hold SOC high Any value programmed here will be added to the minimum requirement of 1 clock cycle 23 18 Reserved R W 0h 17 0 OpenDelay R W 0h Program the number of ADC clock cycles to wait afte...

Page 1059: ...e check register 26 FIFO_select R W 0h Sampled data will be stored in FIFO 0 FIFO 1 FIFO1 25 Diff_CNTRL R W 0h Differential Control Pin 24 23 SEL_RFM_SWC_1_0 R W 0h SEL_RFM pins SW configuration 22 19 SEL_INP_SWC_3_0 R W 0h SEL_INP pins SW configuration 18 15 SEL_INM_SWC_3_0 R W 0h SEL_INM pins for negative differential 14 12 SEL_RFP_SWC_2_0 R W 0h SEL_RFP pins SW configuration 11 WPNSW_SWC R W 0h...

Page 1060: ...clear bit n value after reset Table 12 26 STEPDELAY2 Register Field Descriptions Bit Field Type Reset Description 31 24 SampleDelay R W 0h This register will control the number of ADC clock cycles to sample hold SOC high Any value programmed here will be added to the minimum requirement of 1 clock cycle 23 18 Reserved R W 0h 17 0 OpenDelay R W 0h Program the number of ADC clock cycles to wait afte...

Page 1061: ...e check register 26 FIFO_select R W 0h Sampled data will be stored in FIFO 0 FIFO 1 FIFO1 25 Diff_CNTRL R W 0h Differential Control Pin 24 23 SEL_RFM_SWC_1_0 R W 0h SEL_RFM pins SW configuration 22 19 SEL_INP_SWC_3_0 R W 0h SEL_INP pins SW configuration 18 15 SEL_INM_SWC_3_0 R W 0h SEL_INM pins for negative differential 14 12 SEL_RFP_SWC_2_0 R W 0h SEL_RFP pins SW configuration 11 WPNSW_SWC R W 0h...

Page 1062: ...clear bit n value after reset Table 12 28 STEPDELAY3 Register Field Descriptions Bit Field Type Reset Description 31 24 SampleDelay R W 0h This register will control the number of ADC clock cycles to sample hold SOC high Any value programmed here will be added to the minimum requirement of 1 clock cycle 23 18 Reserved R W 0h 17 0 OpenDelay R W 0h Program the number of ADC clock cycles to wait afte...

Page 1063: ...e check register 26 FIFO_select R W 0h Sampled data will be stored in FIFO 0 FIFO 1 FIFO1 25 Diff_CNTRL R W 0h Differential Control Pin 24 23 SEL_RFM_SWC_1_0 R W 0h SEL_RFM pins SW configuration 22 19 SEL_INP_SWC_3_0 R W 0h SEL_INP pins SW configuration 18 15 SEL_INM_SWC_3_0 R W 0h SEL_INM pins for negative differential 14 12 SEL_RFP_SWC_2_0 R W 0h SEL_RFP pins SW configuration 11 WPNSW_SWC R W 0h...

Page 1064: ...clear bit n value after reset Table 12 30 STEPDELAY4 Register Field Descriptions Bit Field Type Reset Description 31 24 SampleDelay R W 0h This register will control the number of ADC clock cycles to sample hold SOC high Any value programmed here will be added to the minimum requirement of 1 clock cycle 23 18 Reserved R W 0h 17 0 OpenDelay R W 0h Program the number of ADC clock cycles to wait afte...

Page 1065: ...e check register 26 FIFO_select R W 0h Sampled data will be stored in FIFO 0 FIFO 1 FIFO1 25 Diff_CNTRL R W 0h Differential Control Pin 24 23 SEL_RFM_SWC_1_0 R W 0h SEL_RFM pins SW configuration 22 19 SEL_INP_SWC_3_0 R W 0h SEL_INP pins SW configuration 18 15 SEL_INM_SWC_3_0 R W 0h SEL_INM pins for negative differential 14 12 SEL_RFP_SWC_2_0 R W 0h SEL_RFP pins SW configuration 11 WPNSW_SWC R W 0h...

Page 1066: ...clear bit n value after reset Table 12 32 STEPDELAY5 Register Field Descriptions Bit Field Type Reset Description 31 24 SampleDelay R W 0h This register will control the number of ADC clock cycles to sample hold SOC high Any value programmed here will be added to the minimum requirement of 1 clock cycle 23 18 Reserved R W 0h 17 0 OpenDelay R W 0h Program the number of ADC clock cycles to wait afte...

Page 1067: ...e check register 26 FIFO_select R W 0h Sampled data will be stored in FIFO 0 FIFO 1 FIFO1 25 Diff_CNTRL R W 0h Differential Control Pin 24 23 SEL_RFM_SWC_1_0 R W 0h SEL_RFM pins SW configuration 22 19 SEL_INP_SWC_3_0 R W 0h SEL_INP pins SW configuration 18 15 SEL_INM_SWC_3_0 R W 0h SEL_INM pins for negative differential 14 12 SEL_RFP_SWC_2_0 R W 0h SEL_RFP pins SW configuration 11 WPNSW_SWC R W 0h...

Page 1068: ...clear bit n value after reset Table 12 34 STEPDELAY6 Register Field Descriptions Bit Field Type Reset Description 31 24 SampleDelay R W 0h This register will control the number of ADC clock cycles to sample hold SOC high Any value programmed here will be added to the minimum requirement of 1 clock cycle 23 18 Reserved R W 0h 17 0 OpenDelay R W 0h Program the number of ADC clock cycles to wait afte...

Page 1069: ...e check register 26 FIFO_select R W 0h Sampled data will be stored in FIFO 0 FIFO 1 FIFO1 25 Diff_CNTRL R W 0h Differential Control Pin 24 23 SEL_RFM_SWC_1_0 R W 0h SEL_RFM pins SW configuration 22 19 SEL_INP_SWC_3_0 R W 0h SEL_INP pins SW configuration 18 15 SEL_INM_SWC_3_0 R W 0h SEL_INM pins for negative differential 14 12 SEL_RFP_SWC_2_0 R W 0h SEL_RFP pins SW configuration 11 WPNSW_SWC R W 0h...

Page 1070: ...clear bit n value after reset Table 12 36 STEPDELAY7 Register Field Descriptions Bit Field Type Reset Description 31 24 SampleDelay R W 0h This register will control the number of ADC clock cycles to sample hold SOC high Any value programmed here will be added to the minimum requirement of 1 clock cycle 23 18 Reserved R W 0h 17 0 OpenDelay R W 0h Program the number of ADC clock cycles to wait afte...

Page 1071: ...e check register 26 FIFO_select R W 0h Sampled data will be stored in FIFO 0 FIFO 1 FIFO1 25 Diff_CNTRL R W 0h Differential Control Pin 24 23 SEL_RFM_SWC_1_0 R W 0h SEL_RFM pins SW configuration 22 19 SEL_INP_SWC_3_0 R W 0h SEL_INP pins SW configuration 18 15 SEL_INM_SWC_3_0 R W 0h SEL_INM pins for negative differential 14 12 SEL_RFP_SWC_2_0 R W 0h SEL_RFP pins SW configuration 11 WPNSW_SWC R W 0h...

Page 1072: ...clear bit n value after reset Table 12 38 STEPDELAY8 Register Field Descriptions Bit Field Type Reset Description 31 24 SampleDelay R W 0h This register will control the number of ADC clock cycles to sample hold SOC high Any value programmed here will be added to the minimum requirement of 1 clock cycle 23 18 Reserved R W 0h 17 0 OpenDelay R W 0h Program the number of ADC clock cycles to wait afte...

Page 1073: ...e check register 26 FIFO_select R W 0h Sampled data will be stored in FIFO 0 FIFO 1 FIFO1 25 Diff_CNTRL R W 0h Differential Control Pin 24 23 SEL_RFM_SWC_1_0 R W 0h SEL_RFM pins SW configuration 22 19 SEL_INP_SWC_3_0 R W 0h SEL_INP pins SW configuration 18 15 SEL_INM_SWC_3_0 R W 0h SEL_INM pins for negative differential 14 12 SEL_RFP_SWC_2_0 R W 0h SEL_RFP pins SW configuration 11 WPNSW_SWC R W 0h...

Page 1074: ...clear bit n value after reset Table 12 40 STEPDELAY9 Register Field Descriptions Bit Field Type Reset Description 31 24 SampleDelay R W 0h This register will control the number of ADC clock cycles to sample hold SOC high Any value programmed here will be added to the minimum requirement of 1 clock cycle 23 18 Reserved R W 0h 17 0 OpenDelay R W 0h Program the number of ADC clock cycles to wait afte...

Page 1075: ...nge check register 26 FIFO_select R W 0h Sampled data will be stored in FIFO 0 FIFO 1 FIFO1 25 Diff_CNTRL R W 0h Differential Control Pin 24 23 SEL_RFM_SWC_1_0 R W 0h SEL_RFM pins SW configuration 22 19 SEL_INP_SWC_3_0 R W 0h SEL_INP pins SW configuration 18 15 SEL_INM_SWC_3_0 R W 0h SEL_INM pins for negative differential 14 12 SEL_RFP_SWC_2_0 R W 0h SEL_RFP pins SW configuration 11 WPNSW_SWC R W ...

Page 1076: ... clear bit n value after reset Table 12 42 STEPDELAY10 Register Field Descriptions Bit Field Type Reset Description 31 24 SampleDelay R W 0h This register will control the number of ADC clock cycles to sample hold SOC high Any value programmed here will be added to the minimum requirement of 1 clock cycle 23 18 Reserved R W 0h 17 0 OpenDelay R W 0h Program the number of ADC clock cycles to wait af...

Page 1077: ...nge check register 26 FIFO_select R W 0h Sampled data will be stored in FIFO 0 FIFO 1 FIFO1 25 Diff_CNTRL R W 0h Differential Control Pin 24 23 SEL_RFM_SWC_1_0 R W 0h SEL_RFM pins SW configuration 22 19 SEL_INP_SWC_3_0 R W 0h SEL_INP pins SW configuration 18 15 SEL_INM_SWC_3_0 R W 0h SEL_INM pins for negative differential 14 12 SEL_RFP_SWC_2_0 R W 0h SEL_RFP pins SW configuration 11 WPNSW_SWC R W ...

Page 1078: ... clear bit n value after reset Table 12 44 STEPDELAY11 Register Field Descriptions Bit Field Type Reset Description 31 24 SampleDelay R W 0h This register will control the number of ADC clock cycles to sample hold SOC high Any value programmed here will be added to the minimum requirement of 1 clock cycle 23 18 Reserved R W 0h 17 0 OpenDelay R W 0h Program the number of ADC clock cycles to wait af...

Page 1079: ...nge check register 26 FIFO_select R W 0h Sampled data will be stored in FIFO 0 FIFO 1 FIFO1 25 Diff_CNTRL R W 0h Differential Control Pin 24 23 SEL_RFM_SWC_1_0 R W 0h SEL_RFM pins SW configuration 22 19 SEL_INP_SWC_3_0 R W 0h SEL_INP pins SW configuration 18 15 SEL_INM_SWC_3_0 R W 0h SEL_INM pins for negative differential 14 12 SEL_RFP_SWC_2_0 R W 0h SEL_RFP pins SW configuration 11 WPNSW_SWC R W ...

Page 1080: ... clear bit n value after reset Table 12 46 STEPDELAY12 Register Field Descriptions Bit Field Type Reset Description 31 24 SampleDelay R W 0h This register will control the number of ADC clock cycles to sample hold SOC high Any value programmed here will be added to the minimum requirement of 1 clock cycle 23 18 Reserved R W 0h 17 0 OpenDelay R W 0h Program the number of ADC clock cycles to wait af...

Page 1081: ...nge check register 26 FIFO_select R W 0h Sampled data will be stored in FIFO 0 FIFO 1 FIFO1 25 Diff_CNTRL R W 0h Differential Control Pin 24 23 SEL_RFM_SWC_1_0 R W 0h SEL_RFM pins SW configuration 22 19 SEL_INP_SWC_3_0 R W 0h SEL_INP pins SW configuration 18 15 SEL_INM_SWC_3_0 R W 0h SEL_INM pins for negative differential 14 12 SEL_RFP_SWC_2_0 R W 0h SEL_RFP pins SW configuration 11 WPNSW_SWC R W ...

Page 1082: ... clear bit n value after reset Table 12 48 STEPDELAY13 Register Field Descriptions Bit Field Type Reset Description 31 24 SampleDelay R W 0h This register will control the number of ADC clock cycles to sample hold SOC high Any value programmed here will be added to the minimum requirement of 1 clock cycle 23 18 Reserved R W 0h 17 0 OpenDelay R W 0h Program the number of ADC clock cycles to wait af...

Page 1083: ...nge check register 26 FIFO_select R W 0h Sampled data will be stored in FIFO 0 FIFO 1 FIFO1 25 Diff_CNTRL R W 0h Differential Control Pin 24 23 SEL_RFM_SWC_1_0 R W 0h SEL_RFM pins SW configuration 22 19 SEL_INP_SWC_3_0 R W 0h SEL_INP pins SW configuration 18 15 SEL_INM_SWC_3_0 R W 0h SEL_INM pins for negative differential 14 12 SEL_RFP_SWC_2_0 R W 0h SEL_RFP pins SW configuration 11 WPNSW_SWC R W ...

Page 1084: ... clear bit n value after reset Table 12 50 STEPDELAY14 Register Field Descriptions Bit Field Type Reset Description 31 24 SampleDelay R W 0h This register will control the number of ADC clock cycles to sample hold SOC high Any value programmed here will be added to the minimum requirement of 1 clock cycle 23 18 Reserved R W 0h 17 0 OpenDelay R W 0h Program the number of ADC clock cycles to wait af...

Page 1085: ...nge check register 26 FIFO_select R W 0h Sampled data will be stored in FIFO 0 FIFO 1 FIFO1 25 Diff_CNTRL R W 0h Differential Control Pin 24 23 SEL_RFM_SWC_1_0 R W 0h SEL_RFM pins SW configuration 22 19 SEL_INP_SWC_3_0 R W 0h SEL_INP pins SW configuration 18 15 SEL_INM_SWC_3_0 R W 0h SEL_INM pins for negative differential 14 12 SEL_RFP_SWC_2_0 R W 0h SEL_RFP pins SW configuration 11 WPNSW_SWC R W ...

Page 1086: ... clear bit n value after reset Table 12 52 STEPDELAY15 Register Field Descriptions Bit Field Type Reset Description 31 24 SampleDelay R W 0h This register will control the number of ADC clock cycles to sample hold SOC high Any value programmed here will be added to the minimum requirement of 1 clock cycle 23 18 Reserved R W 0h 17 0 OpenDelay R W 0h Program the number of ADC clock cycles to wait af...

Page 1087: ...nge check register 26 FIFO_select R W 0h Sampled data will be stored in FIFO 0 FIFO 1 FIFO1 25 Diff_CNTRL R W 0h Differential Control Pin 24 23 SEL_RFM_SWC_1_0 R W 0h SEL_RFM pins SW configuration 22 19 SEL_INP_SWC_3_0 R W 0h SEL_INP pins SW configuration 18 15 SEL_INM_SWC_3_0 R W 0h SEL_INM pins for negative differential 14 12 SEL_RFP_SWC_2_0 R W 0h SEL_RFP pins SW configuration 11 WPNSW_SWC R W ...

Page 1088: ... clear bit n value after reset Table 12 54 STEPDELAY16 Register Field Descriptions Bit Field Type Reset Description 31 24 SampleDelay R W 0h This register will control the number of ADC clock cycles to sample hold SOC high Any value programmed here will be added to the minimum requirement of 1 clock cycle 23 18 Reserved R W 0h 17 0 OpenDelay R W 0h Program the number of ADC clock cycles to wait af...

Page 1089: ...6 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved Words_in_FIFO0 R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 12 55 FIFO0COUNT Register Field Descriptions Bit Field Type Reset Description 31 7 Reserved R 0h RESERVED 6 0 Words_in_FIFO0 R 0h Number of words currently in the FIFO0 1089 SPRUH73H October 2011 Revised April ...

Page 1090: ...0 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved FIFO0_threshold_Level R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 12 56 FIFO0THRESHOLD Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 0 FIFO0_threshold_Level R W 0h Program the desired FIFO0 data sample level to reach before generating interrupt to CPU program to ...

Page 1091: ...2 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved DMA_Request_Level R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 12 57 DMA0REQ Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h RESERVED 5 0 DMA_Request_Level R W 0h Number of words in FIFO0 before generating a DMA request program to value minus 1 1091 SPRUH73H Oct...

Page 1092: ...6 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved Words_in_FIFO0 R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 12 58 FIFO1COUNT Register Field Descriptions Bit Field Type Reset Description 31 7 Reserved R 0h RESERVED 6 0 Words_in_FIFO0 R 0h Number of words currently in the FIFO0 1092 Touchscreen Controller SPRUH73H Octo...

Page 1093: ...0 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved FIFO0_threshold_Level R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 12 59 FIFO1THRESHOLD Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 0 FIFO0_threshold_Level R W 0h Program the desired FIFO0 data sample level to reach before generating interrupt to CPU program to ...

Page 1094: ...2 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved DMA_Request_Level R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 12 60 DMA1REQ Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h RESERVED 5 0 DMA_Request_Level R W 0h Number of words in FIFO0 before generating a DMA request program to value minus 1 1094 Touchscreen ...

Page 1095: ...7 6 5 4 3 2 1 0 ADCDATA R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 12 61 FIFO0DATA Register Field Descriptions Bit Field Type Reset Description 31 20 Reserved R 0h RESERVED 19 16 ADCCHNLID R 0h Optional ID tag of channel that captured the data If tag option is disabled these bits will be 0 15 12 Reserved R 0h 11 0 ADCDATA R 0h 12 bit sampled ADC co...

Page 1096: ...4 3 2 1 0 ADCDATA R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 12 62 FIFO1DATA Register Field Descriptions Bit Field Type Reset Description 31 20 Reserved R 0h RESERVED 19 16 ADCCHNLID R 0h Optional ID tag of channel that captured the data If tag option is disabled these bits will be 0 15 12 Reserved R 0h RESERVED 11 0 ADCDATA R 0h 12 bit sampled ADC...

Page 1097: ...roller of the device Topic Page 13 1 Introduction 1098 13 2 Integration 1100 13 3 Functional Description 1102 13 4 Programming Model 1122 13 5 LCD Registers 1128 1097 SPRUH73H October 2011 Revised April 2013 LCD Controller Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1098: ...phics data is processed and stored in frame buffers A frame buffer is a contiguous memory block in the system A built in DMA engine supplies the graphics data to the Raster engine which in turn outputs to the external LCD device The LIDD Controller supports the asynchronous LCD interface It provides full timing programmability of control signals CS WE OE ALE and output data Figure 13 1 shows the L...

Page 1099: ...bus timing parameters when in asynchronous Hitachi Motorola and Intel modes Supports 1 Character Panel CS0 with programmable bus timing parameters when in synchronous Motorola and Intel modes Can be used as a generic 16 bit address data interleaved MPU bus master with no external stall Passive Matrix LCD Panels Panel types including STN DSTN and C DSTN AC Bias Control Active Matrix LCD Panels Pane...

Page 1100: ...gration is shown in Figure 13 2 Figure 13 2 LCD Controller Integration 13 2 1 LCD Controller Connectivity Attributes The general connectivity attributes for the LCDC subsystems are shown in Table 13 1 Table 13 1 LCD Controller Connectivity Attributes Attributes Type Power Domain Peripheral Domain Clock Domain PD_PER_LCD_L3_GCLK OCP Master Clock PD_PER_LCD_L3_GCLK OCP Slave Clock PD_PER_LCD_GCLK Fu...

Page 1101: ...LCDC From PRCM lcd_clk 200 MHz Display PLL CLKOUT pd_per_lcd_gclk Functional Clock From PRCM 13 2 3 LCD Controller Pin List The LCD Controller external interface signals are shown in Table 13 3 Table 13 3 LCD Controller Pin List Pin Type Description lcd_cp O Pixel Clock in Raster model Read Strobe or Read Write Strobe in LIDD mode lcd_pixel_i 15 0 I LCD Data Bus input for LIDD mode only lcd_pixel_...

Page 1102: ...the reference clock to this LCD module see Figure 13 3 The pixel clock is used by the LCD display to clock the pixel data into the line shift register where CLKDIV is a field in the LCD_CTRL register and should not be 0 or 1 Passive STN mode LCD_PCLK only transitions when valid data is available for output It does not transition when the horizontal clock HSYNC is asserted or during wait state inse...

Page 1103: ...e clock cycles has elapsed both at the beginning and end of each frame The RASTER_TIMING_1 register fully defines the behavior of this signal LCD_VSYNC can be programmed to be synchronized with the rising or falling edge of LCD_PCLK The configuration field is bits 24 and 25 in the RASTER_TIMING_2 register Passive STN mode The vertical or frame clock toggles during the first line of the screen Acti...

Page 1104: ...n output enable to signal when data is available on the LCD pin LIDD character not used LIDD graphics 6800 mode enable strobe 8080 mode not read strobe LCD_AC_BIAS_EN OUT Raster controller ac bias used to signal the LCD to switch the polarity of the power supplies to the row and column axis of the screen to counteract DC offset Used in TFT mode as the output enable to signal when data is latched f...

Page 1105: ...r or the LCDEN bit in the RASTER_CTRL register should be written with 1 13 3 3 1 Interrupts Interrupts in this LCD module are related to DMA engine operation Four registers are used to control and monitor the interrupts The IRQENABLE_SET register allows the user to enable any of the interrupt sources The IRQENABLE_CLEAR register allows the user to disable interrupts sources The IRQSTATUS_RAW regis...

Page 1106: ...ister reflects the interrupt signal regardless of the interrupt enable bits settings 13 3 3 1 3 Interrupt Handling See Chapter 6 Interrupts for information about LCD interrupt number to CPU The interrupt service routine needs to determine the interrupt source by examining the IRQSTATUS_RAW register and clearing the interrupt properly 13 3 4 LIDD Controller The LIDD Controller is designed to suppor...

Page 1107: ...k LCD_HSYNC R W Read Write LCD_VSYNC A0 Address Data Select LCD_AC_BIAS_EN CS or CS0 Chip Select first display LCD_MCLK CS1 Chip Select second display optional 000 LCD_MCLK None Synchronous Clock optional Micro Interface 8080 Up to 011 LCD_DATA 15 0 DATA 7 0 Data Bus 16 bits always Graphic Display Family 16 available LCD_PCLK RD Read Strobe LCD_HSYNC WR Write Strobe LCD_VSYNC A0 Address Data Selec...

Page 1108: ...BIAS_EN AC Bias LCD_MCLK Not used Passive STN Mono 8 101 LCD_DATA 7 0 Data bus 8 bit LCD_PCLK Pixel clock LCD_HSYNC Horizontal clock Line Clock LCD_VSYNC Vertical clock Frame Clock LCD_AC_BIAS_EN AC Bias LCD_MCLK Not used Passive STN Color 8 100 LCD_DATA 7 0 Data bus LCD_PCLK Pixel clock LCD_HSYNC Horizontal clock Line Clock LCD_VSYNC Vertical clock Frame Clock LCD_AC_BIAS_EN AC Bias LCD_MCLK Not ...

Page 1109: ...odes The palette is bypassed in both 12 and 16 BPP modes Figure 13 4 Logical Data Path for Raster Controller In summary The display image is stored in frame buffers The built in DMA engine constantly transfers the data stored in the frame buffers to the Input FIFO The Raster Controller relays data to the external pins according to the specified format The remainder of this section describes the fu...

Page 1110: ... color entries while the other palettes have up to 16 color entries 4 BPP mode uses up the all the 16 entries in a palette 1 BPP mode uses the first 2 entries in a palette while 2 BPP mode uses the first 4 entries The remaining entries are not used and must be filled with 0 In 12 and 16 BPP modes pixel data is RGB data For all the other modes pixel data is actually an index of the palette entry Ta...

Page 1111: ...nal Description The equations shown in Table 13 9 are used to calculate the total frame buffer size in bytes based on varying pixel size encoding and screen sizes Figure 13 6 and Figure 13 7 show more detail of the palette entry organization Table 13 9 Frame Buffer Size According to BPP BPP Frame Buffer Size 1 32 Lines Columns 8 2 32 Lines Columns 4 4 32 Lines Columns 2 8 512 Lines Columns 12 16 3...

Page 1112: ...Ch Base FEh Unused BPP A Functional Description www ti com Figure 13 7 256 Entry Palette Buffer Format 8 BPP Bits 12 13 and 14 of the first palette entry select the number of bits per pixel to be used in the following frame and thus the number of palette RAM entries The palette entry is used by the Raster Controller to correctly unpack pixel data Figure 13 8 through Figure 13 13 show the memory or...

Page 1113: ... 11 12 13 14 12 bits pixel Bit Pixel 0 Pixel 1 Bit 15 0 Base 2 Unused www ti com Functional Description Figure 13 9 12 BPP Data Memory Organization Little Endian Unused 15 12 bits are filled with zeroes in TFT mode Figure 13 10 8 BPP Data Memory Organization Figure 13 11 4 BPP Data Memory Organization 1113 SPRUH73H October 2011 Revised April 2013 LCD Controller Submit Documentation Feedback Copyri...

Page 1114: ...ed by the DMA engine at the very beginning which is followed by the loading of pixel data If PLM is 10b data only mode the palette is not loaded Instead the DMA engine loads the pixel data immediately 13 3 5 4 Gray Scaler Serializer 13 3 5 4 1 Passive STN Mode Once a palette entry is selected from the look up palette by the pixel data its content is sent to the gray scaler serializer If it is mono...

Page 1115: ...ries to select within 15 grayscales 3375 possible colors 4096 possible colors 2 4 palette entries to select within 4 palette entries to select within 4 palette entries to select within 15 grayscales 3375 possible colors 4096 possible colors 4 16 palette entries to select within 16 palette entries to select within 16 palette entries to select within 15 grayscales 3375 possible colors 4096 possible ...

Page 1116: ...nctional Description www ti com 13 3 5 5 Output Format 13 3 5 5 1 Passive STN Mode As shown in Figure 13 4 the pixel data stored in frame buffers go through palette if applicable and gray scaler serializer before reaching the Output FIFO As a result it is likely that the data fed to the Output FIFO is numerically different from the data in the frame buffers However they represent the same color or...

Page 1117: ... lines of data instead of 100 Figure 13 15 Example of Subpicture The subpicture feature is enabled when the spen MMR control bit is set to 1 The hols bit when set to 0 puts the Default Pixel Data lines at the top of the screen and the active video lines at the bottom of the screen When the hols bit is set to 1 Active video lines are at the top of the screen and Default Pixel Data lines are at the ...

Page 1118: ... from 1 to P 1 L 2 2 L 1 3 L 2 L 1 L 1 1 L P L 2 P 1 L 1 P 2 L P 1 L P L 1 P L Functional Description www ti com Figure 13 17 Raster Mode Display Format 1118 LCD Controller SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1119: ...ion of the interrupt vector Likewise Hardware Interrupt 1 is referenced by bit 1 of the interrupt vector and so on The Host CPU can see all the interrupts that have been set regardless of the interrupt mask by reading Reg22 the Raw Status Register If the Host CPU writes a 1 to a bit position in Reg 22 it will do a software set for the interrupt associated with that bit position 13 3 6 1 3 Masked S...

Page 1120: ...sitions has been seen the AC Bias Count interrupt is triggered The module will not post any further interrupts or keep counting AC Bias transitions until the interrupt has been cleared 13 3 6 2 1 5 Sync Lost Interrupt When the DMA module reads a frame buffer and stores it in the FIFO it sets a start frame and an end frame indicator embedded with the data On retrieving the data from the FIFO in the...

Page 1121: ...wer Compiler clock gates are automatically instantiated within datapaths to minimize active power Items 1 and 2 are accomplished using the standard IDLE for L4 and STANDBY for L3 IPGeneric modules When these modules are instructed to disable clocks for the internal L3 or L4 MMR clock domains the internal clock networks will be shut down This shutdown applies to the external clock pins l3_clk and l...

Page 1122: ... individually available for CS0 and CS1 such that the bus transactions can be customized for each of the two supported LCD character displays 13 4 1 1 2 Defining Panel Commands and Panel Data In the Hitachi interface mode used for the example panel whether the Character Panel understands a data transfer as Command or Data depends on the state of the REGSEL input pin Writing to the cfg_adr_indx reg...

Page 1123: ...MA module sends the sequence of data to the LIDD module by acting as another CPU The DMA can only perform write bus transactions It cannot read from the external character panel a series of data elements and store them in the DRAM When the LIDD module is controlled by the DMA module by setting cfg_lidd_dma_en 1 CPU reads or writes to cfg_adr_index and cfg_data are not allowed The fb0_base and fb0_...

Page 1124: ...actions or for the DMA module to start again 13 4 1 4 Passive Matrix 13 4 1 4 1 Monochrome Bitrate Awareness In a mostly testbench related note care must be taken when configuring the module for Passive Matrix cfg_lcdtft 0 monochrome cfg_lcdbw 1 modes In passive matrix mode the Blue component of the Grayscaler output is used as the quantized value for each scan order pixel When cfg_mono8b 1 eight ...

Page 1125: ... 12 bit Palette RAM Lookup can be used For Active Matrix cfg_lcdtft 1 palette lookup is enabled when cfg_tft24 0 and the bpp field in the Palette RAM is set to 000 001 010 or 011 1 2 4 or 8 bpp Palette lookup cannot used when the bpp field is set to 100 12 16 bpp For Passive Matrix cfg_lcdtft 0 palette lookup is enabled when the bpp field in the Palette RAM is set to 000 001 010 or 011 1 2 4 or 8 ...

Page 1126: ... a 32 bit word The Palette Lookup logic uses the lower halfword first followed by the upper halfword The cfg_rdorder and cfg_nibmode registers determine the raster read ordering of the frame buffer data to be sent to the palette lookup table There are precedence rules for the hardware as it parses each 16 bit word from the frame buffer 1 If cfg_rdorder 0 the data halfword is parsed from the least ...

Page 1127: ...5 8 2 Else if cfg_nibmode 1 scan order is 7 0 15 8 3 Otherwise scan order is 15 8 7 0 13 4 5 Test Logic 13 4 6 Disable and Software Reset Sequence In Raster Modes the module must be disabled before applying a software reset When cfg_lcden is set to 0 to disable the module the output continues to the end of the current frame The Done interrupt will trigger once the frame is complete The software re...

Page 1128: ... Table 13 13 should be considered as reserved locations and the register contents should not be modified Table 13 13 LCD REGISTERS Offset Acronym Register Name Section 0h PID Section 13 5 1 4h CTRL Section 13 5 2 Ch LIDD_CTRL Section 13 5 3 10h LIDD_CS0_CONF Section 13 5 4 14h LIDD_CS0_ADDR Section 13 5 5 18h LIDD_CS0_DATA Section 13 5 6 1Ch LIDD_CS1_CONF Section 13 5 7 20h LIDD_CS1_ADDR Section 1...

Page 1129: ...20 54h SYSCONFIG Section 13 5 21 58h IRQSTATUS_RAW Section 13 5 22 5Ch IRQSTATUS Section 13 5 23 60h IRQENABLE_SET Section 13 5 24 64h IRQENABLE_CLEAR Section 13 5 25 6Ch CLKC_ENABLE Section 13 5 26 70h CLKC_RESET Section 13 5 27 1129 SPRUH73H October 2011 Revised April 2013 LCD Controller Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1130: ... Write 1 to clear bit n value after reset Table 13 14 PID Register Field Descriptions Bit Field Type Reset Description 31 30 scheme R 0h The scheme of the register used This field indicates the 3 5 Method 29 28 Reserved R 0h 27 16 func R 0h The function of the module being used 15 11 rtl R 0h The Release number for this IP 10 8 major R 0h Major Release Number 7 6 custom R 0h Custom IP 5 0 minor R ...

Page 1131: ...6 Reserved R 0h 15 8 clkdiv R W 0h Clock divisor Raster mode Values of 2 through 255 are permitted and resulting pixel clock is lcd_clk 2 through lcd_clk 255 LIDD mode Values of 0 through 255 are permitted with resulting MCLK of lcd_clk 1 through lcd_clk 255 where both 0 and 1 result in lcd_clk 1 7 2 Reserved R W 0h 1 auto_uflow_restart R W 0h 0 On an underflow the software has to restart the modu...

Page 1132: ... panel directly in this mode 7 cs1_e1_pol R W 0h Chip Select 1 Enable 1 Secondary Polarity Control 0 Do Not Invert Chip Select 1 Enable 1 Chip Select 1 is active low by default Enable 1 is active high by default 1 Invert Chip Select 1 Enable 1 6 cs0_e0_pol R W 0h Chip Select 0 Enable 0 Secondary Polarity Control 0 Do Not Invert Chip Select 0 Enable 0 Chip Select 0 is active low by default Enable 0...

Page 1133: ...es the number of memclk cycles for which Data Bus Pas Output Enable ALE the Direction bit and Chip Select 0 are held after the Write Strobe is de asserted when performing write access The minimum value is 0x1 16 12 r_su R W 0h Read Strobe Set Up cycles When performing a read access this field defines the number of memclk cycles that Data Bus Pad Output Enable the Direction bit and Chip Select 0 ha...

Page 1134: ...s a shared Address Data output bus A write to this register would initiate a bus write transaction A read from this register would initiate a bus read transaction CPU reads and writes to this register are not permitted if the LIDD module is in DMA mode cfg_lidd_dma_en 1 If the LIDD is being used as a generic bus interface writing to this register can store adr_indx to an external transparent latch...

Page 1135: ...ared Address Data output bus A write to this register would initiate a bus write transaction A read from this register would initiate a bus read transaction CPU reads and writes to this register are not permitted if the LIDD module is in DMA mode cfg_lidd_dma_en 1 If the LIDD is being used as a generic bus interface writing to this register can store adr_indx to an external transparent latch holdi...

Page 1136: ... of memclk cycles for which Data Bus Pad Output Enable ALE the Direction bit and Chip Select 1 are held after the Write Strobe is deasserted when performing a write access The minimum value is 0x1 16 12 r_su R W 0h Read Strobe Set Up cycles When performing a read access this field defines the number of memclk cycles that Data Bus Pad Output Enable the Direction bit and Chip Select 1 have to be rea...

Page 1137: ...s a shared Address Data output bus A write to this register would initiate a bus write transaction A read from this register would initiate a bus read transaction CPU reads and writes to this register are not permitted if the LIDD module is in DMA mode cfg_lidd_dma_en 1 If the LIDD is being used as a generic bus interface writing to this register can store adr_indx to an external transparent latch...

Page 1138: ...ared Address Data output bus A write to this register would initiate a bus write transaction A read from this register would initiate a bus read transaction CPU reads and writes to this register are not permitted if the LIDD module is in DMA mode cfg_lidd_dma_en 1 If the LIDD is being used as a generic bus interface writing to this register can store adr_indx to an external transparent latch holdi...

Page 1139: ...a depends on cfg_tft24unpacked 24 stn565 R W 0h Passive Matrix Mode only cfg_lcdtft 0 and 16 bpp raw data framebuffers bpp 00 If the bpp field in the framebuffer palette header is 00 12 16 24 bpp source then the DDR contains raw data and the palette lookup is bypassed Only for this case this bit selects whether the framebuffer format is 16 bpp 565 or 12 bpp The Grayscaler can only take 12 bits per...

Page 1140: ...f system clock cycles that should be paused between bursts of 16 word reads from the Async FIFO while loading the Palette SRAM Programming reqdly 00h disables this pause when loading the palette table 11 10 Reserved R W 0h 9 nono8b R W 0h Mono 8 bit 0 lcd_pixel_o 3 0 is used to output four pixel values to the panel each pixel clock transition 1 lcd_pixel_o 7 0 is used to output eight pixel values ...

Page 1141: ...he number of pixel clock periods to add to the end of a line transmission before line clock is asserted programmed value plus 1 Note that pixel clock is held in its inactive state during the end of line wait period in passive display mode and is permitted to transition in active display mode 15 10 hsw R W 0h Horizontal Sync Pulse Width Lowbits Bits 5 0 of the horizontal sync pulse width field Enco...

Page 1142: ...ring the insertion of the extra line clock periods 15 10 vsw R W 0h Vertical Sync Width Pulse In active mode lcdtft 1 encoded value from 1 64 used to specify the number of line clock periods to set the lcd_fp pin active at the end of each frame after the vfp period elapses The number of clock cycles is programmed value plus one The frame clock is used as the VSYNC signal in active mode In passive ...

Page 1143: ...e set to 1 23 ieo R W 0h Invert Output Enable 0 lcd_ac pin is active high in active display mode 1 lcd_ac pin is active low in active display mode Active display mode data driven out of the LCD s data lines on programmed pixel clock edge where AC bias is active Note that ieo is ignored in passive display mode 22 ipc R W 0h Invert Pixel Clock 0 Data is driven on the LCD s data lines on the rising e...

Page 1144: ...when acbi b 0000 15 8 acb R W 0h AC Bias Pin Frequency Value from 0 255 used to specify the number of line clocks to count before transitioning the AC Bias pin This pin is used to periodically invert the polarity of the power supply to prevent DC charge build up within the display acb Number of line clocks toggle of the lcd_ac pin 7 6 Reserved R 0h 5 4 hbp_highbits R W 0h Bits 9 8 of the horizonta...

Page 1145: ...value 0 Default Pixel Data lines are at the top of the screen and the active video lines are at the bottom of the screen 1 Active video lines are at the top of the screen and Default Pixel Data lines are at the bottom of the screen 28 26 Reserved R W 0h 25 16 lppt R W 0h Line Per Panel Threshold Encoded value programmed value range of 0 2047 represents an actual range of 1 2048 used to specify the...

Page 1146: ...1toCl Write 1 to clear bit n value after reset Table 13 28 RASTER_SUBPANEL2 Register Field Descriptions Bit Field Type Reset Description 31 9 Reserved R 0h 8 lppt_b10 R W 0h Lines Per Panel Threshold Bit 10 This register is Bit 10 of the lppt field in RASTER_SUBPANEL 7 0 dpdmsb R W 0h Default Pixel Data MSB 23 16 DPD defines the default value of the pixel data sent to the panel for the lines until...

Page 1147: ...ransfers all DMA transfers are 32 bits wide 000 burst size of 1 001 burst size of 2 010 burst size of 4 011 burst size of 8 100 burst size of 16 101 N A 110 N A 111 N A burst_size cannot be changed once the DMA is enabled in LIDD or Raster modes In this case the DMA must be disabled and the Done Interrupt must occur before the value in this register can be changed 3 byte_swap R W 0h This bit contr...

Page 1148: ... 14 13 12 11 10 9 8 fb0_base R W 0h 7 6 5 4 3 2 1 0 fb0_base Reserved R W 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 13 30 LCDDMA_FB0_BASE Register Field Descriptions Bit Field Type Reset Description 31 2 fb0_base R W 0h Frame Buffer 0 Base Address pointer 1 0 Reserved R 0h 1148 LCD Controller SPRUH73H October 2011 Revised April 2013 Submit Docu...

Page 1149: ...15 14 13 12 11 10 9 8 fb0_ceil R W 0h 7 6 5 4 3 2 1 0 fb0_ceil Reserved R W 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 13 31 LCDDMA_FB0_CEILING Register Field Descriptions Bit Field Type Reset Description 31 2 fb0_ceil R W 0h Frame Buffer 0 Ceiling Address pointer 1 0 Reserved R 0h 1149 SPRUH73H October 2011 Revised April 2013 LCD Controller Sub...

Page 1150: ... 14 13 12 11 10 9 8 fb1_base R W 0h 7 6 5 4 3 2 1 0 fb1_base Reserved R W 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 13 32 LCDDMA_FB1_BASE Register Field Descriptions Bit Field Type Reset Description 31 2 fb1_base R W 0h Frame Buffer 1 Base Address pointer 1 0 Reserved R 0h 1150 LCD Controller SPRUH73H October 2011 Revised April 2013 Submit Docu...

Page 1151: ...15 14 13 12 11 10 9 8 fb1_ceil R W 0h 7 6 5 4 3 2 1 0 fb1_ceil Reserved R W 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 13 33 LCDDMA_FB1_CEILING Register Field Descriptions Bit Field Type Reset Description 31 2 fb1_ceil R W 0h Frame Buffer 1 Ceiling Address pointer 1 0 Reserved R 0h 1151 SPRUH73H October 2011 Revised April 2013 LCD Controller Sub...

Page 1152: ... out of standby state Backup mode for debug only 2 Smart standby mode local initiator standby status depends on local conditions i e the module s functional requirement from the initiator IP module shall not generate initiator related wakeup events 3 Reserved 3 2 idlemode R W 0h Configuration of the local target state management mode By definition target can handle read write transaction as long a...

Page 1153: ...0 inactive 1 active Writing 1 will set status Writing 0 has no effect 5 fuf_raw_set R W 0h DMA FIFO Underflow Raw Interrupt Status and Set LCD dithering logic not supplying data to FIFO at a sufficient rate FIFO has completely emptied and data pin driver logic has attempted to take added data from FIFO Read indicates raw status 0 Inactive 1 Active Writing 1 will set status Writing 0 has no effect ...

Page 1154: ...Raster or LIDD Frame Done shared depends on whether Raster or LIDD mode enabled Raw Interrupt Status and Set Read indicates raw status 0 inactive 1 active Writing 1 will set status Writing 0 has no effect 1154 LCD Controller SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1155: ...nabled Interrupt and Clear Read indicates enabled masked status 0 inactive 1 active Writing 1 will clear interrupt enable Writing 0 has no effect 5 fuf_en_clr R W 0h DMA FIFO Underflow Enabled Interrupt and Clear LCD dithering logic not supplying data to FIFO at a sufficient rate FIFO has completely emptied and data pin driver logic has attempted to take added data from FIFO Read indicates enabled...

Page 1156: ...ing 1 will clear interrupt enable Writing 0 has no effect 0 done_en_clr R W 0h Raster or LIDD Frame Done shared depends on whether Raster or LIDD mode enabled Enabled Interrupt and Clear Read indicates enabled status 0 inactive 1 active Writing 1 will clear interrupt enable Writing 0 has no effect 1156 LCD Controller SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright ...

Page 1157: ...alette Loaded Interrupt Enable Set Read indicates enabled mask status 0 disabled 1 enabled Writing 1 will set interrupt enable Writing 0 has no effect 5 fuf_en_set R W 0h DMA FIFO Underflow Interrupt Enable Set LCD dithering logic not supplying data to FIFO at a sufficient rate FIFO has completely emptied and data pin driver logic has attempted to take added data from FIFO Read indicates enabled m...

Page 1158: ...isabled 1 Enabled Writing 1 will set interrupt enable Writing 0 has no effect 0 done_en_set R W 0h Raster or LIDD Frame Done shared depends on whether Raster or LIDD mode enabled Interrupt Enable Set Read indicates enabled mask status 0 disabled 1 enabled Writing 1 will set interrupt enable 1158 LCD Controller SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 20...

Page 1159: ...DMA Palette Loaded Interrupt Enable Clear Read indicates enabled status 0 disabled 1 enabled Writing 1 will clear interrupt enable Writing 0 has no effect 5 fuf_en_clr R W 0h DMA FIFO Underflow Interrupt Enable Clear LCD dithering logic not supplying data to FIFO at a sufficient rate FIFO has completely emptied and data pin driver logic has attempted to take added data from FIFO Read indicates ena...

Page 1160: ...bled Writing 1 will clear interrupt enable Writing 0 has no effect 0 done_en_clr R W 0h Raster or LIDD Frame Done shared depends on whether Raster or LIDD mode enabled Interrupt Enable Clear Read indicates enabled status 0 disabled 1 enabled Writing 1 will clear interrupt enable Writing 0 has no effect 1160 LCD Controller SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyr...

Page 1161: ... 39 CLKC_ENABLE Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 dma_clk_en R W 0h Software Clock Enable for the DMA submodule The DMA submodule runs on the L3 Clock domain 1 lidd_clk_en R W 0h Software Clock Enable for the LIDD submodule character displays The LIDD submodule runs on the System Clock lcd_clk domain 0 core_clk_en R W 0h Software Clock Enable for the...

Page 1162: ...ble 13 40 CLKC_RESET Register Field Descriptions Bit Field Type Reset Description 31 4 Reserved R W 0h 3 main_rst R W 0h Software Reset for the entire LCD module 1 Reset Enable 0 Reset Disable 2 dma_rst R W 0h Software Reset for the DMA submodule 1 Reset Enable 0 Reset Disable 1 lidd_rst R W 0h Software Reset for the LIDD submodule character displays 1 Reset Enable 0 Reset Disable 0 core_rst R W 0...

Page 1163: ... of the device Topic Page 14 1 Introduction 1164 14 2 Integration 1166 14 3 Functional Description 1176 14 4 Software Operation 1235 14 5 Ethernet Subsystem Registers 1240 1163 SPRUH73H October 2011 Revised April 2013 Ethernet Subsystem Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1164: ... stamping logic inside the SS Device Level Ring DLR Support Address Lookup Engine 1024 addresses plus VLANs Wire rate lookup VLAN support Host controlled time based aging Spanning tree support L2 address lock and L2 filtering support MAC authentication 802 1x Receive or destination based Multicast and Broadcast limits MAC address blocking Source port locking OUI host accept deny feature Flow Contr...

Page 1165: ...core split processing Core 1 and Core 2 interrupts not connected GMII Only 4 Rx Tx data pins are pinned out for each port The device supports MII on GMII interface RGMII and RMII interfaces only Phy link status The MLINK inputs are not pinned out Phy link status outputs can be connected to device GPIOs Internal Delay mode for RGMII RGMII Internal Delay mode is not supported RMII reference clock ou...

Page 1166: ...n main_arst_n hw1_ts_push hw2_ts_push hw3_ts_push hw4_ts_push DMTIMER4 DMTIMER5 DMTIMER6 DMTIMER7 0 1 2 2 5 10 CORE_CLKOUTM5 250 MHz POTIMERPWM POTIMERPWM POTIMERPWM POTIMERPWM RMII2_CRS_DV RMII1_CRS_DV rmii2_txen_o rmii2_txd_o 1 0 rmii2_rxer_I rmii2_rxd_i 1 0 rmii2_crs_dv_I rmii1_txen_o rmii1_txd_o 1 0 rmii1_rxer_I rmii1_rxd_i 1 0 rmii1_crs_dv_I rgmii2_mii_mcol_I rgmii2_mii_mcrs_I rgmii2_mii_mrxe...

Page 1167: ...T_N Idle Wakeup Signals Idle Standby Interrupt Requests 4 Interrupts RX_THRESH 3PGSWRXTHR0 Receive Threshold interrupt nonpaced RX 3PGSWRXINT0 Receive interrupt paced TX 3PGSWTXINT0 Transmit interrupt paced Misc 3PGSWMISC0 Other interrupts All Ethernet Switch interrupts go to MPU Subsystem and PRU ICSS The Subsystem contains 3 sets of interrupts C0 C1 and C2 to allow for split core processing of p...

Page 1168: ..._cpsw_5mhz_gclk 10 mbpsRGMII Reference from PRCM clock cpts_rft_clk 250 MHz CORE_CLKOUTM4 pd_per_cpsw_cpts_rft_clk IEEE 1588v2 clock CORE_CLKOUTM5 from PRCM gmii1_mr_clk 25 MHz External Pin gmii1_rxclk_in GMII Port 1 Receive clock from GMII1_RCLK pad gmii2_mr_clk 25 MHz External Pin gmii2_rxclk_in GMII Port 2 Receive clock from GMII2_RCLK pad gmii1_mt_clk 25 MHz External Pin gmii1_txclk_in GMII Po...

Page 1169: ...MII Receive data RGMIIx_TCLK O RGMII Transmit clock RGMIIx_TCTL O RGMII Transmit control RGMIIx_TD 3 0 O RGMII Transmit data RMIIx_RXD 1 0 I RMII Receiver data RMIIx_RXER I RMII Receiver error RMIIx_CRS_DV I RMII Carrier sense Data valid RMIIx_TXEN O RMII Transmit enable RMIIx_REFCLK I O RMII Reference clock RMIIx_TXD 1 0 O RMII Transmit data MDIO_MCLK O MDIO Serial clock MDIO_MDIO I O MDIO Serial...

Page 1170: ...itch RMII Clock Detail 14 2 5 GMII Interface Signal Connections and Descriptions GMII Interface can operate in GIG MII Modes In GIG 1000Mbps Mode 3PSW operates only in Full duplex Mode In MII Mode 100 10 Mbps 3PSW operates in Full duplex and Half Duplex The pin connections of the GMII Interace are shown in Figure 14 3 1170 Ethernet Subsystem SPRUH73H October 2011 Revised April 2013 Submit Document...

Page 1171: ... that provides the timing reference for GMTCLK O transmit operations The clock is generated by the CPSW and is 125 MHz at 1000 Mbps operation The transmit clock is a continuous free running clock and is generated by the MtCLK I PHY The transmit data pins are a collection of 8 data signals comprising 8 bits of data Mtxd O MTXD0 is the least significant bit LSB The signals are synchronized by GMTCLK...

Page 1172: ...tions The MTXD and MTXEN signals are tied to this clock The MtCLK I clock is generated by the PHY and is 2 5 MHz at 10 Mbps operation and 25 MHz at 100 Mbps operation MTXD 7 4 pins of MTXD data are not used The transmit data pins are a collection of 4 data signals MTXD 3 0 comprising 4 bits of data MTXD0 is the Mtxd O least significant bit LSB The signals are synchronized by MTCLK and valid only w...

Page 1173: ...ividual CPSW and MDIO signals for the RMII interface are summarized in Table 14 7 For more information see either the IEEE 802 3 standard or ISO IEC 8802 3 2000 E Figure 14 4 RMII Interface Connections Table 14 7 RMII Interface Signal Descriptions Signal Type Description Transmit data The transmit data pins are a collection of 2 bits of data RMII_TXD 1 0 O RMII_TXD0 is the least significant bit LS...

Page 1174: ...rations done on the MDIO pin MDIO DATA MDIO data pin drives PHY management data into and out of the PHY by way of an access frame consisting of start of frame read write MDIO_DATA I O indication PHY address register address and data bit cycles The MDIO_DATA signal acts as an output for all but the data bit cycles at which time it is an input for read operations 14 2 7 RGMII Signal Connections and ...

Page 1175: ... are nibble RGMII_RCTL I data for use by the 3PSW The receive clock is a continuous clock that provides the timing reference for receive operations The clock is generated by the PHY and is 2 5 MHz at 10 RGMII_RCLK I Mbps operation and 25 MHz at 100 Mbps operation 125 MHz at 1000Mbps of operation Management data clock The MDIO data clock is sourced by the MDIO module MDIO_CLK O on the system It is ...

Page 1176: ...e value should be written with the number of VBUSP_CLK periods in 4us The pacing timer determines the interval during which interrupts are blocked and decrements every 4us It is reloaded each time a zero count is reached The value loaded into the pacing timer is calculated by hardware every 1ms according to the following algorithm if intr_count 2 intr_max pace_timer 255 else if intr_count 1 5 intr...

Page 1177: ... of control module is 1 Upon any device reset source other than POR pin or ICEPICK cold so this includes SW global cold any watchdog reset warm RESETn pin ICEPICK warm SW global warm the following should be true The CPSW_3GSS_R is put into isolate mode and non switch related portions of the IP are reset The 50 MHz and 125 MHz reference clocks to the 3PSW Ethernet Subsystem remains active throughou...

Page 1178: ... The data written by the host buffer descriptor address of the last processed buffer is compared to the data in the register written by the subsystem address of last buffer descriptor used by the subsystem If the two values are not equal which means that the 3PSW has received more packets than the CPU has processed the receive packet completion interrupt signal remains asserted If the two values a...

Page 1179: ...an immediate non paced pulse interrupt selected from the CPSW_3G RX_THRESH_PEND 7 0 interrupts The receive DMA controller has eight channels with each channel having a corresponding threshold pulse interrupt RX_THRESH_PEND 7 0 To enable the receive threshold pulse Interrupt Enable the required channel interrupts of the DMA engine by setting 1 to the appropriate bit in the RX_INTMASK_SET register T...

Page 1180: ...y setting to one the appropriate bit in the INTMASK_SET register in the CPDMA submodule The statistics interrupt is disabled by writing one to the appropriate bit in the INTMASK_CLEAR register The raw and masked statistics interrupt status may be read by reading the TX_IntStat_Raw and TX_IntStat_Masked registers respectively 14 3 1 3 4 3 Host Error Interrupt The host error interrupt HOST_PEND will...

Page 1181: ...rupt is enabled by setting to 1 the STAT_INT_MASK bit in the DMA_INTMASK_SET register The HOST_PEND is enabled by setting to 1 the HOST_ERR_INT_MASK in the DMA_INTMASK_SET register Upon receiving of an interrupt software should perform the following Read the Cn_MISC_STAT register to determine the source of the interrupt Process the interrupt Write the value 3h to the CPDMA_EOI_VECTOR register 14 3...

Page 1182: ...with a handle pX_ts_rx_mii_hndl 3 0 to the CPTS controller for each packet that is received The record signal is a single clock pulse indicating that a receive packet has been detected at the associated port MII interface The handle value is incremented with each packet and rolls over to zero after 15 There are 16 possible handle values so there can be a maximum of 16 packets in flight from the TS...

Page 1183: ...nd pX_vlan_ltype1_en is set and the second packet ltype matches vlan_ltype2 and pX_vlan_ltype2_en is set and the third packet ltype matches ts_ltype1 and pX_ts_ltype1_en is set vlan_ltype1 and pX_vlan_ltype1_en is set and the second packet ltype matches vlan_ltype2 and pX_vlan_ltype2_en is set and the third packet ltype matches ts_ltype2 and pX_ts_ltype2_en is set 3 The PTP message begins in the b...

Page 1184: ...c_evnt pX_ts_tx_dec_hndl 3 0 pX_ts_tx_dec_msg_type pX_ts_tx_dec_seq_id The event signal is a single clock pulse indicating that the packet matched the time sync event packet criteria and that the associated packet handle message type and sequence ID are valid The 16 bit sequence ID is found in the time sync event packet at the sequence ID offset into the message header pX_ts_seq_id_offset No indic...

Page 1185: ...X_ts_ttl_nonzero bit in the switch Px_Control register is zero or byte 22 contains any value if pX_ts_ttl_nonzero is set Byte 22 is the time to live field 5 Byte 23 contains 0x11 UDP Fixed 6 Byte 30 contains decimal 224 0xe0 7 Byte 31 contains 0x00 8 Byte 32 contains 0x01 9 Byte 33 contains one of the following Decimal 129 and the pX_ts_129 bit in the switch Px_Control register is set Decimal 130 ...

Page 1186: ...nicast packets Packets are determined to be DLR packets as shown 1 DLR is enabled dlr_en is set in the switch CPSW_Control register 2 One of the following sequences is true The first packet ltype matches vlan_ltype1 and pX_vlan_ltype1_en is set and the second packet ltype matches dlr_ltype The first packet ltype matches vlan_ltype2 and pX_vlan_ltype2_en is set and the second packet ltype matches d...

Page 1187: ...6 SOP EOP Owner EOQ Teardown_Com Pass Reserved To_Po Reserved To_Port_En ship plete CRC rt_En 15 11 10 0 Reserved packet_length 14 3 2 4 1 1 1 CPPI Tx Data Word 0 Next Descriptor Pointer The next descriptor pointer points to the 32 bit word aligned memory address of the next buffer descriptor in the transmit queue This pointer is used to create a linked list of buffer descriptors If the value of t...

Page 1188: ...acket buffer that is last for a given packet In the case of a single fragment packet both the start of packet SOP and EOP flags are set Otherwise the descriptor pointing to the last packet buffer for the packet sets the EOP flag This bit is set by the software application and is not altered by the EMAC 0 Not end of packet buffer 1 End of packet buffer Ownership When set this flag indicates that al...

Page 1189: ...e part of the valid packet data Note that this flag is valid on SOP descriptors only 0 The CRC is not included with the packet data and packet length 1 The CRC is included with the packet data and packet length to_port To Port Port number to send the directed packet to This field is set by the host This field is valid on SOP Directed packets go to the directed port but an ALE lookup is performed t...

Page 1190: ...icates that there are no unused bytes at the start of the buffer and that valid data begins on the first byte of the buffer A value of 0x000F decimal 15 indicates that the first 15 bytes of the buffer are to be ignored by the port and that valid buffer data starts on byte 16 of the buffer The port writes the buffer_offset with the value from the rx_buffer_offset register value The host initializes...

Page 1191: ...the corresponding receiver channel has halted This flag is initially cleared by the software application prior to adding the descriptor to the receive queue This bit is set by the EMAC when the EMAC identifies that a descriptor is the last for a given packet received also sets the EOP flag and there are no more descriptors in the receive list next descriptor pointer is NULL The software applicatio...

Page 1192: ...ption 14 3 2 4 2 1 Receive DMA Host Configuration To configure the Rx DMA for operation the host must perform the following Initialize the receive addresses Initialize the Rx_HDP Registers to zero Enable the desired receive interrupts in the IntMask register Write the rx_buffer_offset register value Setup the receive channel s buffer descriptors in host memory as required by CPPI 3 0 Enable the RX...

Page 1193: ...fer descriptor if there is one The channel head descriptor pointer will be set to zero An interrupt will be issued to inform the host of the channel teardown The host should acknowledge a teardown interrupt with a 0xfffffffc acknowledge value Channel teardown may be commanded on any channel at any time The host is informed of the teardown completion by the set teardown complete buffer descriptor b...

Page 1194: ...is changed depending on the packet type pkt_type packet priority pkt_pri and VLAN information as shown in the below tables Figure 14 9 VLAN Header Encapsulation Word 31 29 28 27 16 HDR_PKT_Priority HDR_PKT_CFI HDR_PKT_Vid 15 10 9 8 7 6 5 4 3 2 1 0 Reserved PKT_Type Reserved Table 14 9 VLAN Header Encapsulation Word Field Descriptions Field Description HDR_PKT_Priority Header Packet VLAN priority H...

Page 1195: ... the table with the super bit set Unicast packets will be dropped unless the unicast address is in the table with block and secure both set supervisory unicast packet Multicast supervisory packets are designated by the super bit in the table entry Unicast supervisory packets are indicated when block and secure are both set Supervisory packets are not dropped due to rate limiting OUI or VLAN proces...

Page 1196: ...okup in order for the multicast packet to be forwarded to the transmit port s A transmit port must be in the Forwarding state in order to forward the packet If the transmit port_mask has multiple set bits then each forward decision is independent of the other transmit port s forward decision 00 Forwarding 01 Blocking Forwarding Learning 10 Forwarding Learning 11 Forwarding The forward state test r...

Page 1197: ...ss bit 40 VLAN ID VLAN_ID The unique identifier for VLAN identification This is the 12 bit VLAN ID Packet Address MULTICAST_ADDRESS This is the 48 bit packet MAC address For an OUI address only the upper 24 bits of the address are used in the source or destination address lookup Otherwise all 48 bits are used in the lookup 14 3 2 7 1 4 Unicast Address Table Entry Table 14 14 Unicast Address Table ...

Page 1198: ..._TYPE Unicast Type This field indicates the type of unicast address the table entry contains 00 Unicast address that is not ageable 01 Ageable unicast address that has not been touched 10 OUI address lower 24 bits are don t cares not ageable 11 Ageable unicast address that has been touched Table Entry Type ENTRY_TYPE Address entry Unicast or multicast determined by address bit 40 01 Address entry ...

Page 1199: ...y super packet and they determine the unicast forward state test criteria If both bits are set then the packet is forwarded if the receive port is in the Forwarding Blocking Learning state If both bits are not set then the packet is forwarded if the receive port is in the Forwarding state Secure SECURE Secure This bit indicates that a packet with a matching source address should be dropped if the ...

Page 1200: ...sses are described in the following sections In the packet ingress process receive packet process there is a forward state test for unicast destination addresses and a forward state test for multicast addresses The multicast forward state test indicates the port states required for the receiving port in order for the multicast packet to be forwarded to the transmit port s A transmit port must be i...

Page 1201: ... found then discard the packet if not forward state test valid and destination address found then discard the packet to any port not meeting the requirements Unicast destination addresses use the unicast forward state test and multicast destination addresses use the multicast forward state test if destination address not found and not transmit port forwarding or not receive port forwarding then di...

Page 1202: ...acket destination address not found then portmask is the logical AND of unreg_mcast_flood_mask and vlan_member_list then goto Egress process if Broadcast packet then use found vlan_member_list and goto Egress process 14 3 2 7 2 3 VLAN_Unaware Lookup Process if unicast packet and destination address found with or without VLAN and dlr_unicast then portmask is the vlan_member_list less the host port ...

Page 1203: ...without error in order to learn update touch an address 14 3 2 7 3 1 Learning Process If not Learning or Forwarding or enable_auth_mode or packet error or no_learn then do not learn address if Non tagged packet and drop_untagged then do not learn address if vlan_aware and VLAN not found and unknown_vlan_member_list 000 then do not learn address if vid_ingress_check and Rx port is not VLAN member a...

Page 1204: ...ket priority if the VLAN information is to be sent on egress 14 3 2 9 FIFO Memory Control Each of the three CPSW_3G ports has an identical associated FIFO Each FIFO contains a single logical receive ingress queue and four logical transmit queues priority 0 through 3 Each FIFO memory contains 20 480 bytes 20k total organized as 2560 by 64 bit words contained in a single memory instance The FIFO mem...

Page 1205: ...he packet destination The CPSW_3G vlan aware bit may be set or not as required must be set if VLAN s are to exit the switch Configure the Port 1 to Port 0 VLAN Add a VLAN Table Entry with ports 0 and 1 as members clear the flood masks Add a VLAN Unicast Address Table Entry with the Port1 0 VLAN and a port number of 0 Packets received on port 1 with this unicast address will be sent only to port 0 ...

Page 1206: ...priority If shaping is required on two queues then it must be on priorities 2 and 3 priorities 1 and 0 are strict priority If shaping is required on three queues then it must be priorities 3 2 and 1 priority 0 would then get the leftovers Priority shaping follows the requirements in the IEEE P802 1Qav D6 0 specification Priority shaping is not compatible with priority escalation escalation must be...

Page 1207: ...In either case receive flow control prevents frame reception by issuing the flow control appropriate for the current mode of operation Receive flow control is enabled by the rx_flow_en bit in the MacControl register Receive flow control is triggered when enabled when the RX_FLOW_TRIGGER input is asserted The CPGMAC_SL is configured for collision or IEEE 802 3X flow control via the fullduplex bit i...

Page 1208: ...py MAC Frames bit in the MacControl register is set The tx_flow_en and fullduplex bits effect whether or not MAC control frames are acted upon but they have no effect upon whether or not MAC control frames are transferred to memory or filtered Pause frames are a subset of MAC Control Frames with an opcode field 0x0001 Incoming pause frames will only be acted upon by the port if tx_flow_en is set i...

Page 1209: ...ped the external logic must assert the drop signal by no later than the second clock after the end of packet or abort indication from the CPGMAC_SL The drop signal should remain asserted until the second clock after the end of packet or abort indication If the packet is not to be dropped then the drop signal should remain deasserted The CPGMAC_SL section contains more information on the receive FI...

Page 1210: ...ial frame in the tx cell fifo will be transmitted For receive frames that are detected by the CPDMA after the suspend state is entered are ignored No statistics will be kept for ignored frames Emulation control is implemented for compatibility with other peripherals The following table shows the operations of the emulation control input and register bits Table 14 18 Operations of Emulation Control...

Page 1211: ... The statistics values are cleared to zero 38 clocks after the rising edge of VBUSP_RST_N When one or more port enable bits stat_port_en 2 0 are set all statistics registers are write to decrement The value written will be subtracted from the register value with the result being stored in the register If a value greater than the statistics value is written then zero will be written to the register...

Page 1212: ...r code error Pause frames had been enabled on the port tx_flow_en 1 The port could have been in either half or full duplex mode See the Rx Align Code Errors and Rx CRC errors statistic descriptions for definitions of alignment code and CRC errors Overruns have no effect upon this statistic 14 3 2 20 1 5 Rx CRC Errors Offset 10h The total number of frames received on the port that experienced a CRC...

Page 1213: ... Code Errors and Rx CRC errors statistic descriptions for definitions of alignment code and CRC errors Overruns have no effect upon this statistic 14 3 2 20 1 9 Undersize Short Rx Frames Offset 20h The total number of undersized frames received on the port An undersized frame is defined to be Was any data frame which matched a unicast broadcast or multicast address or matched due to promiscuous mo...

Page 1214: ...tatistic 14 3 2 20 1 14 Rx Octets Offset 30h The total number of bytes in all good frames received on the port A good frame is defined to be Any data or MAC control frame which matched a unicast broadcast or multicast address or matched due to promiscuous mode Of length 64 to rx_maxlen bytes inclusive Had no CRC error alignment error or code error See the Rx Align Code Errors and Rx CRC errors sta...

Page 1215: ...stic indicates the number of IEEE 802 3X pause frames transmitted by the port Pause frames cannot underrun or contain a CRC error because they are created in the transmitting MAC so these error conditions have no effect upon the statistic Pause frames sent by software will not be included in this count Since pause frames are only transmitted in full duplex carrier loss and collisions have no effec...

Page 1216: ...doning all attempts at transmitting the frame None of the collisions were late CRC errors have no effect upon this statistic 14 3 2 20 2 9 Late Collisions Offset 58h The total number of frames on the port for which transmission was abandoned because they experienced a late collision Such a frame Was any data or MAC control frame destined for any unicast broadcast or multicast address Was any size ...

Page 1217: ...ned for any unicast broadcast or multicast address Did not experience late collisions excessive collisions or carrier sense error Was exactly 64 bytes long If the frame was being transmitted and experienced carrier loss that resulted in a frame of this size being transmitted then the frame will be recorded in this statistic CRC errors code align errors and overruns do not affect the recording of f...

Page 1218: ...any unicast broadcast or multicast address Did not experience late collisions excessive collisions or carrier sense error Was 512 to 1023 bytes long CRC errors code align errors underruns and overruns do not affect the recording of frames in this statistic 14 3 2 20 3 6 Rx Tx 1024_Up Octet Frames Offset 7Ch The total number of frames of size 1024 to rx_maxlen bytes for receive or 1024 up for trans...

Page 1219: ... n Oversized Rx Frames F Rx y y y y y n n n n n n n y n n n Rx Jabbers F Rx y y y y y n n n n n n n y y y n Undersized Rx Frames F Rx n n y y y y n n n n n n n n n n Rx Fragments F Rx n n y y y y n n n n n n n y y Rx Overruns F Rx y y y y y y y y y y y y y y n Rx T 64octet Frames F y y y y y n y n n n n n n n x Rx T 65 127octet Frames F y y y y y n n y n n n n n n x Rx T 128 255octet Frames F y y ...

Page 1220: ...sion will be forced during the first 8 bytes so should not show in frame fragments Some of the s in this column might in reality be n s 9 The rx_overruns stat show above is for rx_mof_overruns and rx_sof_overruns added together Table 14 20 Tx Statistics Summary Frame Type Frame Size bytes Event MAC control Data Collision Type Tx Frame 1024 No Und Paus Tx Statistic Rx 65 128 256 512 CRC Que Defe An...

Page 1221: ...Rx F y y y y y n n y n n n n n n n Frames Tx 256 511octet Rx F y y y y y n n n y n n n n n n Frames Tx 512 1023octet Rx F y y y y y n n n n y n n n n n Frames Tx 1024 UPoctet Rx F y y y y y n n n n n y y n n n Frames Tx Tx Octets O Tx y y y y y y y y y y y y n n n n Rx Net Octets O y y y y y y y y y y y y Tx 1221 SPRUH73H October 2011 Revised April 2013 Ethernet Subsystem Submit Documentation Feed...

Page 1222: ...ted 6 indicates collisions which are summed i e every collision is counted in the Collisions statistic Jam sequences used for halfduplex flow control are also counted 7 Every byte written on the wire during each retry attempt is also counted in addition to frames which experience no collisions or carrier loss 8 The flow collision type is for half duplex collisions forced by the MAC to achieve flow...

Page 1223: ...ic redundancy checking CRC and statistics control signal generation 14 3 3 1 1 2 Receive Inter Frame Interval The 802 3 required inter packet gap IPG is 24 GMII clocks 96 bit times for 10 100 Mbit modes and 12 GMII clocks 96 bit times for 1000 Mbit mode However the MAC can tolerate a reduced IPG 2 GMII clocks in 10 100 mode and 5 GMII clocks in 1000 mode with a correct preamble and start frame del...

Page 1224: ...nly if the pacing counter is zero If the pacing counter is non zero the frame is delayed by the pacing delay a delay of approximately four inter packet gap delays APO only affects the IPG preceding the first attempt at transmitting a frame It does not affect the back off algorithm for retransmitted frames 14 3 3 1 2 5 Inter Packet Gap Enforcement The measurement reference for the IPG of 96 bit tim...

Page 1225: ...t the next frame boundary Any frame currently in reception or transmission will be completed normally without suspension Received frames that are detected after the suspend state is entered are ignored Commanded idle is similar in operation to emulation control and clock stop 14 3 5 RMII Interface The CPRMII peripheral shall be compliant to the RMII specification document Features Source Synchrono...

Page 1226: ...RGMII specification The link speed is indicated as shown in the following table RGMII _SPEED 1 0 Link Speed 00 10 Mbs mode 01 100 Mbs mode 10 1000 Mbs mode 11 reserved 14 3 6 3 Forced Mode of Operation The CPRGMII is operating in the forced mode of operation when the RGMII_RX_INBAND input is deasserted by setting MACCONTROL EXT_EN to 0 In the forced mode of operation the in band data is ignored if...

Page 1227: ...he GMII_SEL register should only be set to 1 for no internal delay The device does not support internal delay mode for RGMII 1227 SPRUH73H October 2011 Revised April 2013 Ethernet Subsystem Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1228: ...value when the packet was transmitted or received In addition both hardware HWx_TS_PUSH and software TS_PUSH can be used to read the current time stamp value though the Event FIFO The reference clock used for the time stamp RCLK is sourced from one of the two sources as shown in Figure 14 10 The source can be selected by configuring the CM_CPTS_RFT_CLKSEL register in the Control Module For more de...

Page 1229: ... timely manner to prevent FIFO overrun 14 3 7 2 4 Time Sync Events Time Sync events are 64 bit values that are pushed onto the event FIFO and read in two 32 bit reads CPTS_EVENT_LOW and CPTS_EVENT_HIGH are defined in Section 14 5 3 10 and Section 14 5 3 11 respectively There are six types of sync events Time stamp push event Hardware time stamp push event Time stamp counter rollover event Time sta...

Page 1230: ...er the packet time stamp has been taken but before the packet has been determined to be a valid time sync packet Figure 14 11 Event FIFO Misalignment Condition Host software must detect and correct for misaligned event conditions For every event after a rollover and before a half rollover software must examine the time stamp most significant bit If bit 31 of the time stamp value is low 0x0000_0000...

Page 1231: ... associated port The Px_TS_RX_MII interface issues a record signal pX_ts_rx_mii_rec along with a handle pX_ts_rx_mii_hndl for each packet every packet that is received on the associated ethernet port The record signal is a single clock pulse indicating that a receive packet has been detected at the associated port MII interface The handle value is incremented with each packet and rolls over to zer...

Page 1232: ... Px_TS_TX_MII interface issues a single clock record signal pX_ts_tx_mii_rec at the beginning of each transmitted packet If the packet is a time sync event packet then a single clock event signal pX_ts_tx_mii_evnt along with a handle pX_ts_rx_mii_hndl will be issued before the next record signal for the next transmitted packet The event signal will not be issued for packets that were not indicated...

Page 1233: ...22 MDIO Read Frame Format Operatio Preamble Start Delimiter PHY Address Register Address Turnaround Data n Code 0xFFFFF DDDD DDDD DDD 01 10 AAAAA RRRRR Z0 FFF D DDDD Table 14 23 MDIO Write Frame Format Operatio Preamble Start Delimiter PHY Address Register Address Turnaround Data n Code 0xFFFFF DDDD DDDD DDD 01 00 AAAAA RRRRR 10 FFF D DDDD The default or idle state of the two wire serial interface...

Page 1234: ...gister is updated by the MII Management I F module if the PHY acknowledged the read of the generic status register In addition any PHY register read transactions initiated by the host also cause the MDIOAlive register to be updated At any time the host can define a transaction for the MII Management interface module to undertake using the data phyadr regadr and write fields in a MDIOUserAccess reg...

Page 1235: ...ess of the last buffer descriptor processed by the port The port issues a maskable level interrupt which may then be routed through external interrupt control logic to the host On interrupt from the port the host processes the buffer queue detecting transmitted packets by the status of the Ownership bit in the SOP buffer descriptor If the Ownership bit is cleared to zero then the packet has been t...

Page 1236: ...tate head descriptor pointer The host software should always check for and reinitiate transmission for misqueued packets during queue processing on interrupt from the port In order to preclude software underrun the host should avoid adding buffers to an active queue for any Tx packet that is not complete and ready for transmission The port determines that a packet is the last packet in the queue b...

Page 1237: ...zero value to the channel s head descriptor pointer in the channel s Rx DMA state When packet reception begins on a given channel the port fills each Rx buffer with data in order starting with the first buffer and proceeding through the Rx queue If the Buffer Offset in the Rx DMA State is nonzero then the port will begin writing data after the offset number of bytes in the SOP buffer The port perf...

Page 1238: ... for the host to determine the condition and reinitiate the transaction but the packet is not actually lost In the receive case receive overrun condition may occur in the misqueued buffer case If a new packet reception is begun during the time that the port has determined the end of queue condition then the received packet will overrun start of packet overrun If the misqueued buffer occurs during ...

Page 1239: ...omplete interrupt register MDIOUSERINTRAW corresponding to USERACCESSn used If interrupts have been enabled on this bit using the MDIO user command complete interrupt mask set register MDIOUSERINTMASKSET then the bit is also set in the MDIO user command complete interrupt register MDIOUSERINTMASKED and an interrupt is triggered on the CPU 14 4 6 Initialization and Configuration of CPSW To configur...

Page 1240: ... ADDRESS LOOKUP ENGINE TABLE CONTROL Section 14 5 1 5 34h TBLW2 ADDRESS LOOKUP ENGINE TABLE WORD 2 Section 14 5 1 6 REGISTER 38h TBLW1 ADDRESS LOOKUP ENGINE TABLE WORD 1 Section 14 5 1 7 REGISTER 3Ch TBLW0 ADDRESS LOOKUP ENGINE TABLE WORD 0 Section 14 5 1 8 REGISTER 40h PORTCTL0 ADDRESS LOOKUP ENGINE PORT 0 CONTROL Section 14 5 1 9 REGISTER 44h PORTCTL1 ADDRESS LOOKUP ENGINE PORT 1 CONTROL Section...

Page 1241: ...13 12 11 10 9 8 MAJ_VER R 0 7 6 5 4 3 2 1 0 MINOR_VER R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 25 IDVER Register Field Descriptions Bit Field Type Reset Description 31 16 IDENT R 0 0 ALE Identification Value 15 8 MAJ_VER R 0 0 ALE Major Version Value 7 0 MINOR_VER R 0 0 ALE Minor Version Value 1241 SPRUH73H October 2011 Revised April 2013 Ether...

Page 1242: ... as one because the read is blocked until the clear table is completed at which time this bit is cleared to zero 29 AGE_OUT_NOW R W 0 0 Age Out Address Table Now Setting this bit causes the ALE hardware to remove free up any ageable table entry that does not have a set touch bit This bit is cleared when the age out process has completed This bit may be read The age out process takes 4096 clocks be...

Page 1243: ...authorization mode requires that all table entries be made by the host software There are no learned address in authorization mode and the packet will be dropped if the source address is not found and the destination address is not a multicast address with the super table entry bit set 0 The ALE is not in MAC authorization mode 1 The ALE is in MAC authorization mode 0 ENABLE_RATE_LIMIT R W 0 0 Ena...

Page 1244: ... W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 27 PRESCALE Register Field Descriptions Bit Field Type Reset Description 19 0 PRESCALE R W 0 0 ALE Prescale Register The input clock is divided by this value for use in the multicast broadcast rate limiters The minimum operating value is 0x10 The prescaler is off when the value is zero 1244 Ethernet Sub...

Page 1245: ...served UNKNOWN_VLAN_MEMBER_LIST R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 28 UNKNOWN_VLAN Register Field Descriptions Bit Field Type Reset Description 29 24 UNKNOWN_FORCE_UN R W 0 0 Unknown VLAN Force Untagged Egress TAGGED_EGRESS 21 16 UNKNOWN_REG_MCAS R W 0 0 Unknown VLAN Registered Multicast Flood Mask T_FLOOD_MASK 13 8 UNKNOWN_MCAST_FLO R ...

Page 1246: ...Z R W 0 0 Write Bit This bit is always read as zero Writing a 1 to this bit causes the three table word register values to be written to the entry_pointer location in the address table Writing a 0 to this bit causes the three table word register values to be loaded from the entry_pointer location in the address table so that they may be subsequently read A read of any ALE address location will be ...

Page 1247: ... 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ENTRY71 64 R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 30 TBLW2 Register Field Descriptions Bit Field Type Reset Description 7 0 ENTRY71 64 R W 0 0 Table entry bits 71 64 1247 SPRUH73H October 2011 Revised April 2013 Ethernet Subsystem Submit Documentation Feedback Copyright...

Page 1248: ...5 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENTRY63_32 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 31 TBLW1 Register Field Descriptions Bit Field Type Reset Description 31 0 ENTRY63_32 R W 0h Table entry bits 63 32 1248 Ethernet Subsystem SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 201...

Page 1249: ...25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENTRY31_0 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 32 TBLW0 Register Field Descriptions Bit Field Type Reset Description 31 0 ENTRY31_0 R W 0h Table entry bits 31 0 1249 SPRUH73H October 2011 Revised April 2013 Ethernet Subsystem Submit Documentation Feedback Copyright 2011 ...

Page 1250: ...scale pulse Broadcast rate limiting is enabled by a non zero value in this field 23 16 MCAST_LIMIT R W 0 0 Multicast Packet Rate Limit Each prescale pulse loads this field into the port multicast rate limit counter The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive If the counters decrement to zero then further packets ar...

Page 1251: ...scale pulse Broadcast rate limiting is enabled by a non zero value in this field 23 16 MCAST_LIMIT R W 0 0 Multicast Packet Rate Limit Each prescale pulse loads this field into the port multicast rate limit counter The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive If the counters decrement to zero then further packets ar...

Page 1252: ...scale pulse Broadcast rate limiting is enabled by a non zero value in this field 23 16 MCAST_LIMIT R W 0 0 Multicast Packet Rate Limit Each prescale pulse loads this field into the port multicast rate limit counter The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive If the counters decrement to zero then further packets ar...

Page 1253: ...scale pulse Broadcast rate limiting is enabled by a non zero value in this field 23 16 MCAST_LIMIT R W 0 0 Multicast Packet Rate Limit Each prescale pulse loads this field into the port multicast rate limit counter The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive If the counters decrement to zero then further packets ar...

Page 1254: ...scale pulse Broadcast rate limiting is enabled by a non zero value in this field 23 16 MCAST_LIMIT R W 0 0 Multicast Packet Rate Limit Each prescale pulse loads this field into the port multicast rate limit counter The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive If the counters decrement to zero then further packets ar...

Page 1255: ...t Packet Rate Limit Each prescale pulse loads this field into the port multicast rate limit counter The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive If the counters decrement to zero then further packets are rate limited until the next prescale pulse Multicast rate limiting is enabled by a non zero value in this field 5...

Page 1256: ...E CPDMA_REGS TRANSMIT INGRESS PRIORITY 6 Section 14 5 2 18 RATE 4Ch TX_PRI7_RATE CPDMA_REGS TRANSMIT INGRESS PRIORITY 7 Section 14 5 2 19 RATE 80h TX_INTSTAT_RAW CPDMA_INT TX INTERRUPT STATUS REGISTER Section 14 5 2 20 RAW VALUE 84h TX_INTSTAT_MASKED CPDMA_INT TX INTERRUPT STATUS REGISTER Section 14 5 2 21 MASKED VALUE 88h TX_INTMASK_SET CPDMA_INT TX INTERRUPT MASK SET REGISTER Section 14 5 2 22 8...

Page 1257: ...NT RECEIVE THRESHOLD PENDING Section 14 5 2 41 REGISTER CHANNEL 7 E0h RX0_FREEBUFFER CPDMA_INT RECEIVE FREE BUFFER REGISTER Section 14 5 2 42 CHANNEL 0 E4h RX1_FREEBUFFER CPDMA_INT RECEIVE FREE BUFFER REGISTER Section 14 5 2 43 CHANNEL 1 E8h RX2_FREEBUFFER CPDMA_INT RECEIVE FREE BUFFER REGISTER Section 14 5 2 44 CHANNEL 2 ECh RX3_FREEBUFFER CPDMA_INT RECEIVE FREE BUFFER REGISTER Section 14 5 2 45 ...

Page 1258: ... 4 3 2 1 0 TX_MINOR_VER R 8h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 40 TX_IDVER Register Field Descriptions Bit Field Type Reset Description 31 16 TX_IDENT R 18h TX Identification Value 15 8 TX_MAJOR_VER R 1h TX Major Version Value The value read is the major version number 7 0 TX_MINOR_VER R 8h TX Minor Version Value The value read is the minor ...

Page 1259: ...17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TX_EN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 41 TX_CONTROL Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 TX_EN R W 0h TX Enable 0 Disabled 1 Enabled 1259 SPRUH73H October 2011 Revised April 2013 Ethernet Subsystem Submi...

Page 1260: ...oCl Write 1 to clear bit n value after reset Table 14 42 TX_TEARDOWN Register Field Descriptions Bit Field Type Reset Description 31 TX_TDN_RDY R 0h Tx Teardown Ready read as zero but is always assumed to be one unused 30 3 Reserved R 0h 2 0 TX_TDN_CH R W 0h Tx Teardown Channel Transmit channel teardown is commanded by writing the encoded value of the transmit channel to be torn down The teardown ...

Page 1261: ...14 13 12 11 10 9 8 RX_MAJOR_VER R 1h 7 6 5 4 3 2 1 0 RX_MINOR_VER R 7h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 43 RX_IDVER Register Field Descriptions Bit Field Type Reset Description 31 16 RX_IDENT R Ch RX Identification Value 15 8 RX_MAJOR_VER R 1h RX Major Version Value 7 0 RX_MINOR_VER R 7h RX Minor Version Value 1261 SPRUH73H October 2011 Rev...

Page 1262: ... 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved RX_EN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 44 RX_CONTROL Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 RX_EN R W 0h RX DMA Enable 0 Disabled 1 Enabled 1262 Ethernet Subsystem SPRUH73H October 2011 Revised April 2013 Sub...

Page 1263: ... W1toCl Write 1 to clear bit n value after reset Table 14 45 RX_TEARDOWN Register Field Descriptions Bit Field Type Reset Description 31 RX_TDN_RDY R 0h Teardown Ready read as zero but is always assumed to be one unused 30 3 Reserved R 0h 2 0 RX_TDN_CH R W 0h Rx Teardown Channel Receive channel teardown is commanded by writing the encoded value of the receive channel to be torn down The teardown r...

Page 1264: ...n value after reset Table 14 46 CPDMA_SOFT_RESET Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 SOFT_RESET R W 0h Software reset Writing a one to this bit causes the CPDMA logic to be reset Software reset occurs when the RX and TX DMA Controllers are in an idle state to avoid locking up the VBUSP bus After writing a one to this bit it may be polled to determine i...

Page 1265: ...ted all others invalid this bus must be set msb towards lsb tx_ptype must be set if any tx_rlim bit is set for fixed priority 7 5 Reserved R 0h 4 RX_CEF R W 0h RX Copy Error Frames Enable Enables DMA overrun frames to be transferred to memory up to the point of overrun The overrun error bit will be set in the frame EOP buffer descriptor Overrun frame data will be filtered when rx_cef is not set Fr...

Page 1266: ...packet processing Users who do not use the ownership mechanism can use this mode to preclude the necessity of software having to set this bit each time the buffer descriptor is used 0 TX_PTYPE R W 0h Transmit Queue Priority Type 0 The queue uses a round robin scheme to select the next channel for transmission 1 The queue uses a fixed channel 7 highest priority priority scheme to select the next ch...

Page 1267: ... packet length is an error but it is not detected 0000 No error 0001 SOP error 0010 Ownership bit not set in SOP buffer 0011 Zero Next Buffer Descriptor Pointer Without EOP 0100 Zero Buffer Pointer 0101 Zero Buffer Length 0110 Packet Length Error sum of buffers is less than packet length 0111 reserved 1111 reserved 19 Reserved R 0h 18 16 TX_ERR_CH R 0h TX Host Error Channel This field indicates wh...

Page 1268: ...t Error Channel This field indicates which RX channel the host error occurred on This field is cleared to zero on a host read 000 The host error occurred on RX channel 0 111 The host error occurred on RX channel 7 7 0 Reserved R 0h 1268 Ethernet Subsystem SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1269: ...t Description 31 16 Reserved R 0h 15 0 RX_BUFFER_OFFSET R W 0h Receive Buffer Offset Value The rx_buffer_offset will be written by the port into each frame SOP buffer descriptor buffer_offset field The frame data will begin after the rx_buffer_offset value of bytes A value of 0x0000 indicates that there are no unused bytes at the beginning of the data and that valid data begins on the first byte o...

Page 1270: ...0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved SOFT FREE R 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 50 EMCONTROL Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 SOFT R W 0h Emulation Soft Bit 0 FREE R W 0h Emulation Free Bit 1270 Ethernet Subsystem SPRUH73H October 2011 Revised Apr...

Page 1271: ... 14 13 12 11 10 9 8 Reserved PRIN_SEND_CNT R 0h R W 0h 7 6 5 4 3 2 1 0 PRIN_SEND_CNT R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 51 TX_PRI0_RATE Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 16 PRIN_IDLE_CNT R W 0h Priority 7 0 idle count 15 14 Reserved R 0h 13 0 PRIN_SEND_CNT R W 0h Priority 7 0 send count...

Page 1272: ... 14 13 12 11 10 9 8 Reserved PRIN_SEND_CNT R 0h R W 0h 7 6 5 4 3 2 1 0 PRIN_SEND_CNT R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 52 TX_PRI1_RATE Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 16 PRIN_IDLE_CNT R W 0h Priority 7 0 idle count 15 14 Reserved R 0h 13 0 PRIN_SEND_CNT R W 0h Priority 7 0 send count...

Page 1273: ... 14 13 12 11 10 9 8 Reserved PRIN_SEND_CNT R 0h R W 0h 7 6 5 4 3 2 1 0 PRIN_SEND_CNT R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 53 TX_PRI2_RATE Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 16 PRIN_IDLE_CNT R W 0h Priority 7 0 idle count 15 14 Reserved R 0h 13 0 PRIN_SEND_CNT R W 0h Priority 7 0 send count...

Page 1274: ... 14 13 12 11 10 9 8 Reserved PRIN_SEND_CNT R 0h R W 0h 7 6 5 4 3 2 1 0 PRIN_SEND_CNT R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 54 TX_PRI3_RATE Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 16 PRIN_IDLE_CNT R W 0h Priority 7 0 idle count 15 14 Reserved R 0h 13 0 PRIN_SEND_CNT R W 0h Priority 7 0 send count...

Page 1275: ... 14 13 12 11 10 9 8 Reserved PRIN_SEND_CNT R 0h R W 0h 7 6 5 4 3 2 1 0 PRIN_SEND_CNT R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 55 TX_PRI4_RATE Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 16 PRIN_IDLE_CNT R W 0h Priority 7 0 idle count 15 14 Reserved R 0h 13 0 PRIN_SEND_CNT R W 0h Priority 7 0 send count...

Page 1276: ... 14 13 12 11 10 9 8 Reserved PRIN_SEND_CNT R 0h R W 0h 7 6 5 4 3 2 1 0 PRIN_SEND_CNT R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 56 TX_PRI5_RATE Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 16 PRIN_IDLE_CNT R W 0h Priority 7 0 idle count 15 14 Reserved R 0h 13 0 PRIN_SEND_CNT R W 0h Priority 7 0 send count...

Page 1277: ... 14 13 12 11 10 9 8 Reserved PRIN_SEND_CNT R 0h R W 0h 7 6 5 4 3 2 1 0 PRIN_SEND_CNT R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 57 TX_PRI6_RATE Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 16 PRIN_IDLE_CNT R W 0h Priority 7 0 idle count 15 14 Reserved R 0h 13 0 PRIN_SEND_CNT R W 0h Priority 7 0 send count...

Page 1278: ... 14 13 12 11 10 9 8 Reserved PRIN_SEND_CNT R 0h R W 0h 7 6 5 4 3 2 1 0 PRIN_SEND_CNT R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 58 TX_PRI7_RATE Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 16 PRIN_IDLE_CNT R W 0h Priority 7 0 idle count 15 14 Reserved R 0h 13 0 PRIN_SEND_CNT R W 0h Priority 7 0 send count...

Page 1279: ...R Read only W1toCl Write 1 to clear bit n value after reset Table 14 59 TX_INTSTAT_RAW Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 TX7_PEND R 0h TX7_PEND raw int read before mask 6 TX6_PEND R 0h TX6_PEND raw int read before mask 5 TX5_PEND R 0h TX5_PEND raw int read before mask 4 TX4_PEND R 0h TX4_PEND raw int read before mask 3 TX3_PEND R 0h TX3_PEND raw int ...

Page 1280: ...D R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 60 TX_INTSTAT_MASKED Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 TX7_PEND R 0h TX7_PEND masked interrupt read 6 TX6_PEND R 0h TX6_PEND masked interrupt read 5 TX5_PEND R 0h TX5_PEND masked interrupt read 4 TX4_PEND R 0h TX4_PEND masked interrupt read 3 TX3_PEND R 0h TX3_PEND ...

Page 1281: ...Table 14 61 TX_INTMASK_SET Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 TX7_MASK R W 0h TX Channel 7 Mask Write one to enable interrupt 6 TX6_MASK R W 0h TX Channel 6 Mask Write one to enable interrupt 5 TX5_MASK R W 0h TX Channel 5 Mask Write one to enable interrupt 4 TX4_MASK R W 0h TX Channel 4 Mask Write one to enable interrupt 3 TX3_MASK R W 0h TX Channel ...

Page 1282: ...able 14 62 TX_INTMASK_CLEAR Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 TX7_MASK R W 0h TX Channel 7 Mask Write one to disable interrupt 6 TX6_MASK R W 0h TX Channel 6 Mask Write one to disable interrupt 5 TX5_MASK R W 0h TX Channel 5 Mask Write one to disable interrupt 4 TX4_MASK R W 0h TX Channel 4 Mask Write one to disable interrupt 3 TX3_MASK R W 0h TX Cha...

Page 1283: ...e R Read only W1toCl Write 1 to clear bit n value after reset Table 14 63 CPDMA_IN_VECTOR Register Field Descriptions Bit Field Type Reset Description 31 0 DMA_IN_VECTOR R 0h DMA Input Vector The value of DMA_In_Vector is reset to zero but will change to the IN_VECTOR bus value one clock after reset is deasserted Thereafter this value will change to a new IN_VECTOR value one clock after the IN_VEC...

Page 1284: ...d Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 64 CPDMA_EOI_VECTOR Register Field Descriptions Bit Field Type Reset Description 31 5 Reserved R 0h 4 0 DMA_EOI_VECTOR R W 0h DMA End of Interrupt Vector The EOI_VECTOR 4 0 pins reflect the value written to this location one CLK cycle after a write to this location The EOI_WR signal is asserted for a single clock cycle af...

Page 1285: ...PEND R 0h RX7_THRESH_PEND raw int read before mask 14 RX6_THRESH_PEND R 0h RX6_THRESH_PEND raw int read before mask 13 RX5_THRESH_PEND R 0h RX5_THRESH_PEND raw int read before mask 12 RX4_THRESH_PEND R 0h RX4_THRESH_PEND raw int read before mask 11 RX3_THRESH_PEND R 0h RX3_THRESH_PEND raw int read before mask 10 RX2_THRESH_PEND R 0h RX2_THRESH_PEND raw int read before mask 9 RX1_THRESH_PEND R 0h R...

Page 1286: ...escriptions Bit Field Type Reset Description 31 16 Reserved R 0h 15 RX7_THRESH_PEND R 0h RX7_THRESH_PEND masked int read 14 RX6_THRESH_PEND R 0h RX6_THRESH_PEND masked int read 13 RX5_THRESH_PEND R 0h RX5_THRESH_PEND masked int read 12 RX4_THRESH_PEND R 0h RX4_THRESH_PEND masked int read 11 RX3_THRESH_PEND R 0h RX3_THRESH_PEND masked int read 10 RX2_THRESH_PEND R 0h RX2_THRESH_PEND masked int read...

Page 1287: ...t 13 RX5_THRESH_PEND_M R W 0h RX Channel 5 Threshold Pending Int ASK Mask Write one to enable Int 12 RX4_THRESH_PEND_M R W 0h RX Channel 4 Threshold Pending Int ASK Mask Write one to enable Int 11 RX3_THRESH_PEND_M R W 0h RX Channel 3 Threshold Pending Int ASK Mask Write one to enable Int 10 RX2_THRESH_PEND_M R W 0h RX Channel 2 Threshold Pending Int ASK Mask Write one to enable Int 9 RX1_THRESH_P...

Page 1288: ... 13 RX5_THRESH_PEND_M R W 0h RX Channel 5 Threshold Pending Int ASK Mask Write one to disable Int 12 RX4_THRESH_PEND_M R W 0h RX Channel 4 Threshold Pending Int ASK Mask Write one to disable Int 11 RX3_THRESH_PEND_M R W 0h RX Channel 3 Threshold Pending Int ASK Mask Write one to disable Int 10 RX2_THRESH_PEND_M R W 0h RX Channel 2 Threshold Pending Int ASK Mask Write one to disable Int 9 RX1_THRES...

Page 1289: ...9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved HOST_PEND STAT_PEND R 0h R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 69 DMA_INTSTAT_RAW Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 HOST_PEND R 0h Host Pending Interrupt raw int read before mask 0 STAT_PEND R 0h Statistics Pending Interrupt raw int read before m...

Page 1290: ... 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved HOST_PEND STAT_PEND R 0h R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 70 DMA_INTSTAT_MASKED Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 HOST_PEND R 0h Host Pending Interrupt masked interrupt read 0 STAT_PEND R 0h Statistics Pending Interrupt masked interru...

Page 1291: ...3 2 1 0 Reserved HOST_ERR_INT_MA STAT_INT_MASK SK R 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 71 DMA_INTMASK_SET Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 HOST_ERR_INT_MASK R W 0h Host Error Interrupt Mask Write one to enable interrupt 0 STAT_INT_MASK R W 0h Statistics Interrupt Mask Write one...

Page 1292: ...4 3 2 1 0 Reserved HOST_ERR_INT_MA STAT_INT_MASK SK R 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 72 DMA_INTMASK_CLEAR Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 HOST_ERR_INT_MASK R W 0h Host Error Interrupt Mask Write one to disable interrupt 0 STAT_INT_MASK R W 0h Statistics Interrupt Mask Writ...

Page 1293: ...2 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 RX_PENDTHRESH R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 73 RX0_PENDTHRESH Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 RX_PENDTHRESH R W 0h Rx Flow Threshold This field contains the threshold value for issuing receive threshold pending interrupts when enabled 129...

Page 1294: ...2 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 RX_PENDTHRESH R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 74 RX1_PENDTHRESH Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 RX_PENDTHRESH R W 0h Rx Flow Threshold This field contains the threshold value for issuing receive threshold pending interrupts when enabled 129...

Page 1295: ...2 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 RX_PENDTHRESH R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 75 RX2_PENDTHRESH Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 RX_PENDTHRESH R W 0h Rx Flow Threshold This field contains the threshold value for issuing receive threshold pending interrupts when enabled 129...

Page 1296: ...2 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 RX_PENDTHRESH R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 76 RX3_PENDTHRESH Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 RX_PENDTHRESH R W 0h Rx Flow Threshold This field contains the threshold value for issuing receive threshold pending interrupts when enabled 129...

Page 1297: ...2 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 RX_PENDTHRESH R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 77 RX4_PENDTHRESH Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 RX_PENDTHRESH R W 0h Rx Flow Threshold This field contains the threshold value for issuing receive threshold pending interrupts when enabled 129...

Page 1298: ...2 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 RX_PENDTHRESH R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 78 RX5_PENDTHRESH Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 RX_PENDTHRESH R W 0h Rx Flow Threshold This field contains the threshold value for issuing receive threshold pending interrupts when enabled 129...

Page 1299: ...2 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 RX_PENDTHRESH R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 79 RX6_PENDTHRESH Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 RX_PENDTHRESH R W 0h Rx Flow Threshold This field contains the threshold value for issuing receive threshold pending interrupts when enabled 129...

Page 1300: ...2 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 RX_PENDTHRESH R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 80 RX7_PENDTHRESH Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 RX_PENDTHRESH R W 0h Rx Flow Threshold This field contains the threshold value for issuing receive threshold pending interrupts when enabled 130...

Page 1301: ...er Count This field contains the count of free buffers available The rx_pendthresh value is compared with this field to determine if the receive threshold pending interrupt should be asseted if enabled This is a write to increment field This field rolls over to zero on overflow If receive threshold pending interrupts are used the host must initialize this field to the number of available buffers o...

Page 1302: ...er Count This field contains the count of free buffers available The rx_pendthresh value is compared with this field to determine if the receive threshold pending interrupt should be asseted if enabled This is a write to increment field This field rolls over to zero on overflow If receive threshold pending interrupts are used the host must initialize this field to the number of available buffers o...

Page 1303: ...er Count This field contains the count of free buffers available The rx_pendthresh value is compared with this field to determine if the receive threshold pending interrupt should be asseted if enabled This is a write to increment field This field rolls over to zero on overflow If receive threshold pending interrupts are used the host must initialize this field to the number of available buffers o...

Page 1304: ...er Count This field contains the count of free buffers available The rx_pendthresh value is compared with this field to determine if the receive threshold pending interrupt should be asseted if enabled This is a write to increment field This field rolls over to zero on overflow If receive threshold pending interrupts are used the host must initialize this field to the number of available buffers o...

Page 1305: ...er Count This field contains the count of free buffers available The rx_pendthresh value is compared with this field to determine if the receive threshold pending interrupt should be asseted if enabled This is a write to increment field This field rolls over to zero on overflow If receive threshold pending interrupts are used the host must initialize this field to the number of available buffers o...

Page 1306: ...er Count This field contains the count of free buffers available The rx_pendthresh value is compared with this field to determine if the receive threshold pending interrupt should be asseted if enabled This is a write to increment field This field rolls over to zero on overflow If receive threshold pending interrupts are used the host must initialize this field to the number of available buffers o...

Page 1307: ...er Count This field contains the count of free buffers available The rx_pendthresh value is compared with this field to determine if the receive threshold pending interrupt should be asseted if enabled This is a write to increment field This field rolls over to zero on overflow If receive threshold pending interrupts are used the host must initialize this field to the number of available buffers o...

Page 1308: ...rements by the number of buffers in the received frame the associated channel register for each received frame This is a write to increment field The host must write this field with the number of buffers that have been freed due to host processing 14 5 3 CPSW_CPTS Registers Table 14 89 lists the memory mapped registers for the CPSW_CPTS All register offset addresses not listed in Table 14 89 shoul...

Page 1309: ...POP EVENT INTERRUPT POP REGISTER Section 14 5 3 9 34h CPTS_EVENT_LOW LOWER 32 BITS OF THE EVENT VALUE Section 14 5 3 10 38h CPTS_EVENT_HIGH UPPER 32 BITS OF THE EVENT VALUE Section 14 5 3 11 1309 SPRUH73H October 2011 Revised April 2013 Ethernet Subsystem Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1310: ...ER R 9D140h R 4E8A01h 7 6 5 4 3 2 1 0 MINOR_VER R 4E8A0101h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 90 CPTS_IDVER Register Field Descriptions Bit Field Type Reset Description 31 16 TX_IDENT R 4E8Ah TX Identification Value 15 11 RTL_VER R 9D140h RTL Version Value 10 8 MAJOR_VER R 4E8A01h Major Version Value 7 0 MINOR_VER R 4E8A0101h Minor Version V...

Page 1311: ...bit n value after reset Table 14 91 CPTS_CONTROL Register Field Descriptions Bit Field Type Reset Description 31 12 Reserved R 0h 11 HW4_TS_PUSH_EN R W 0h Hardware push 4 enable 10 HW3_TS_PUSH_EN R W 0h Hardware push 3 enable 9 HW2_TS_PUSH_EN R W 0h Hardware push 2 enable 8 HW1_TS_PUSH_EN R W 0h Hardware push 1 enable 7 2 Reserved R 0h 1 INT_TEST R W 0h Interrupt Test When set this bit allows the ...

Page 1312: ... Description 31 1 Reserved R 0h 0 TS_PUSH W 0h Time stamp event push When a logic high is written to this bit a time stamp event is pushed onto the event FIFO The time stamp value is the time of the write of this register not the time of the event read The time stamp value can then be read on interrupt via the event registers Software should not push a second time stamp event onto the event FIFO u...

Page 1313: ...fter reset Table 14 93 CPTS_TS_LOAD_VAL Register Field Descriptions Bit Field Type Reset Description 31 0 TS_LOAD_VAL R W 0h Time Stamp Load Value Writing the ts_load_en bit causes the value contained in this register to be written into the time stamp The time stamp value is read by initiating a time stamp push event not by reading this register When reading this register the value read is not the...

Page 1314: ...served TS_LOAD_EN R 0h W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 94 CPTS_TS_LOAD_EN Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 TS_LOAD_EN W 0h Time Stamp Load Writing a one to this bit enables the time stamp value to be written via the ts_load_val 31 0 register This feature is included for test purposes Th...

Page 1315: ...d R 0h 7 6 5 4 3 2 1 0 Reserved TS_PEND_RAW R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 95 CPTS_INTSTAT_RAW Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 TS_PEND_RAW R W 0h TS_PEND_RAW int read before enable Writable when int_test 1 A one in this bit indicates that there is one or more events in the even...

Page 1316: ...20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TS_PEND R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 96 CPTS_INTSTAT_MASKED Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 TS_PEND R 0h TS_PEND masked interrupt read after enable 1316 Ethernet Subsystem SPRUH73H October...

Page 1317: ...8 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TS_PEND_EN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 97 CPTS_INT_ENABLE Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 TS_PEND_EN R W 0h TS_PEND masked interrupt enable 1317 SPRUH73H October 2011 Revised April 2013 Ethern...

Page 1318: ...alue after reset Table 14 98 CPTS_EVENT_POP Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 EVENT_POP W 0h Event Pop When a logic high is written to this bit an event is popped off the event FIFO The event FIFO pop occurs as part of the interrupt process after the event has been read in the Event_Low and Event_High registers Popping an event discards the event and...

Page 1319: ...4 3 2 1 0 TIME_STAMP R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 99 CPTS_EVENT_LOW Register Field Descriptions Bit Field Type Reset Description 31 0 TIME_STAMP R 0h Time Stamp The timestamp is valid for transmit receive and time stamp push event types The timestamp value is not valid for counter roll event types 1319 SPRUH73H October 2011 Revised...

Page 1320: ...tes the port number of an ethernet event or the hardware push pin number 1 to 4 23 20 EVENT_TYPE R 0h Time Sync Event Type 0000 Time Stamp Push Event 0001 Time Stamp Rollover Event 0010 Time Stamp Half Rollover Event 0011 Hardware Time Stamp Push Event 0100 Ethernet Receive Event 0101 Ethernet Transmit Event 19 16 MESSAGE_TYPE R 0h Message type The message type value that was contained in an ether...

Page 1321: ... Tx Frames Section 14 3 2 20 2 7 54h Excessive Collisions Section 14 3 2 20 2 8 58h Late Collisions Section 14 3 2 20 2 9 5Ch Tx Underrun Section 14 3 2 20 2 10 60h Carrier Sense Errors Section 14 3 2 20 2 12 64h Tx Octets Section 14 3 2 20 2 13 68h Rx Tx 64 Octet Frames Section 14 3 2 20 3 1 6Ch Rx Tx 65 127 Octet Frames Section 14 3 2 20 3 2 70h Rx Tx 128 255 Octet Frames Section 14 3 2 20 3 3 7...

Page 1322: ...EAD DESC Section 14 5 5 15 POINTER 3Ch RX7_HDP CPDMA_STATERAM RX 7 CHANNEL 7 HEAD DESC Section 14 5 5 16 POINTER 40h TX0_CP CPDMA_STATERAM TX CHANNEL 0 COMPLETION Section 14 5 5 17 POINTER REGISTER 44h TX1_CP CPDMA_STATERAM TX CHANNEL 1 COMPLETION Section 14 5 5 18 POINTER REGISTER 48h TX2_CP CPDMA_STATERAM TX CHANNEL 2 COMPLETION Section 14 5 5 19 POINTER REGISTER 4Ch TX3_CP CPDMA_STATERAM TX CHA...

Page 1323: ...5 COMPLETION Section 14 5 5 30 POINTER REGISTER 78h RX6_CP CPDMA_STATERAM RX CHANNEL 6 COMPLETION Section 14 5 5 31 POINTER REGISTER 7Ch RX7_CP CPDMA_STATERAM RX CHANNEL 7 COMPLETION Section 14 5 5 32 POINTER REGISTER 1323 SPRUH73H October 2011 Revised April 2013 Ethernet Subsystem Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1324: ...t n value after reset Table 14 103 TX0_HDP Register Field Descriptions Bit Field Type Reset Description 31 0 TX_HDP R W 0h TX Channel 0 7 DMA Head Descriptor Pointer Writing a TX DMA Buffer Descriptor address to a head pointer location initiates TX DMA operations in the queue for the selected channel Writing to these locations when they are non zero is an error except at reset Host software must i...

Page 1325: ...t n value after reset Table 14 104 TX1_HDP Register Field Descriptions Bit Field Type Reset Description 31 0 TX_HDP R W 0h TX Channel 0 7 DMA Head Descriptor Pointer Writing a TX DMA Buffer Descriptor address to a head pointer location initiates TX DMA operations in the queue for the selected channel Writing to these locations when they are non zero is an error except at reset Host software must i...

Page 1326: ...t n value after reset Table 14 105 TX2_HDP Register Field Descriptions Bit Field Type Reset Description 31 0 TX_HDP R W 0h TX Channel 0 7 DMA Head Descriptor Pointer Writing a TX DMA Buffer Descriptor address to a head pointer location initiates TX DMA operations in the queue for the selected channel Writing to these locations when they are non zero is an error except at reset Host software must i...

Page 1327: ...t n value after reset Table 14 106 TX3_HDP Register Field Descriptions Bit Field Type Reset Description 31 0 TX_HDP R W 0h TX Channel 0 7 DMA Head Descriptor Pointer Writing a TX DMA Buffer Descriptor address to a head pointer location initiates TX DMA operations in the queue for the selected channel Writing to these locations when they are non zero is an error except at reset Host software must i...

Page 1328: ...t n value after reset Table 14 107 TX4_HDP Register Field Descriptions Bit Field Type Reset Description 31 0 TX_HDP R W 0h TX Channel 0 7 DMA Head Descriptor Pointer Writing a TX DMA Buffer Descriptor address to a head pointer location initiates TX DMA operations in the queue for the selected channel Writing to these locations when they are non zero is an error except at reset Host software must i...

Page 1329: ...t n value after reset Table 14 108 TX5_HDP Register Field Descriptions Bit Field Type Reset Description 31 0 TX_HDP R W 0h TX Channel 0 7 DMA Head Descriptor Pointer Writing a TX DMA Buffer Descriptor address to a head pointer location initiates TX DMA operations in the queue for the selected channel Writing to these locations when they are non zero is an error except at reset Host software must i...

Page 1330: ...t n value after reset Table 14 109 TX6_HDP Register Field Descriptions Bit Field Type Reset Description 31 0 TX_HDP R W 0h TX Channel 0 7 DMA Head Descriptor Pointer Writing a TX DMA Buffer Descriptor address to a head pointer location initiates TX DMA operations in the queue for the selected channel Writing to these locations when they are non zero is an error except at reset Host software must i...

Page 1331: ...t n value after reset Table 14 110 TX7_HDP Register Field Descriptions Bit Field Type Reset Description 31 0 TX_HDP R W 0h TX Channel 0 7 DMA Head Descriptor Pointer Writing a TX DMA Buffer Descriptor address to a head pointer location initiates TX DMA operations in the queue for the selected channel Writing to these locations when they are non zero is an error except at reset Host software must i...

Page 1332: ... bit n value after reset Table 14 111 RX0_HDP Register Field Descriptions Bit Field Type Reset Description 31 0 RX_HDP R W 0h RX DMA Head Descriptor Pointer Writing an RX DMA Buffer Descriptor address to this location allows RX DMA operations in the selected channel when a channel frame is received Writing to these locations when they are non zero is an error except at reset Host software must ini...

Page 1333: ...r bit n value after reset Table 14 112 RX1_HDP Register Field Descriptions Bit Field Type Reset Description 31 0 RX_HDP R W 0h RX DMA Head Descriptor Pointer Writing an RX DMA Buffer Descriptor address to this location allows RX DMA operations in the selected channel when a channel frame is received Writing to these locations when they are non zero is an error except at reset Host software must in...

Page 1334: ...r bit n value after reset Table 14 113 RX2_HDP Register Field Descriptions Bit Field Type Reset Description 31 0 RX_HDP R W 0h RX DMA Head Descriptor Pointer Writing an RX DMA Buffer Descriptor address to this location allows RX DMA operations in the selected channel when a channel frame is received Writing to these locations when they are non zero is an error except at reset Host software must in...

Page 1335: ...ar bit n value after reset Table 14 114 RX3_HDP Register Field Descriptions Bit Field Type Reset Description 31 0 RX_HDP R W 0h RX DMA Head Descriptor Pointer Writing an RX DMA Buffer Descriptor address to this location allows RX DMA operations in the selected channel when a channel frame is received Writing to these locations when they are non zero is an error except at reset Host software must i...

Page 1336: ...ar bit n value after reset Table 14 115 RX4_HDP Register Field Descriptions Bit Field Type Reset Description 31 0 RX_HDP R W 0h RX DMA Head Descriptor Pointer Writing an RX DMA Buffer Descriptor address to this location allows RX DMA operations in the selected channel when a channel frame is received Writing to these locations when they are non zero is an error except at reset Host software must i...

Page 1337: ...ar bit n value after reset Table 14 116 RX5_HDP Register Field Descriptions Bit Field Type Reset Description 31 0 RX_HDP R W 0h RX DMA Head Descriptor Pointer Writing an RX DMA Buffer Descriptor address to this location allows RX DMA operations in the selected channel when a channel frame is received Writing to these locations when they are non zero is an error except at reset Host software must i...

Page 1338: ...ar bit n value after reset Table 14 117 RX6_HDP Register Field Descriptions Bit Field Type Reset Description 31 0 RX_HDP R W 0h RX DMA Head Descriptor Pointer Writing an RX DMA Buffer Descriptor address to this location allows RX DMA operations in the selected channel when a channel frame is received Writing to these locations when they are non zero is an error except at reset Host software must i...

Page 1339: ...ar bit n value after reset Table 14 118 RX7_HDP Register Field Descriptions Bit Field Type Reset Description 31 0 RX_HDP R W 0h RX DMA Head Descriptor Pointer Writing an RX DMA Buffer Descriptor address to this location allows RX DMA operations in the selected channel when a channel frame is received Writing to these locations when they are non zero is an error except at reset Host software must i...

Page 1340: ... Read only W1toCl Write 1 to clear bit n value after reset Table 14 119 TX0_CP Register Field Descriptions Bit Field Type Reset Description 31 0 TX_CP R W 0h Tx Completion Pointer Register This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The port uses the value written to determine if the interrupt should ...

Page 1341: ... Read only W1toCl Write 1 to clear bit n value after reset Table 14 120 TX1_CP Register Field Descriptions Bit Field Type Reset Description 31 0 TX_CP R W 0h Tx Completion Pointer Register This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The port uses the value written to determine if the interrupt should ...

Page 1342: ... Read only W1toCl Write 1 to clear bit n value after reset Table 14 121 TX2_CP Register Field Descriptions Bit Field Type Reset Description 31 0 TX_CP R W 0h Tx Completion Pointer Register This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The port uses the value written to determine if the interrupt should ...

Page 1343: ... Read only W1toCl Write 1 to clear bit n value after reset Table 14 122 TX3_CP Register Field Descriptions Bit Field Type Reset Description 31 0 TX_CP R W 0h Tx Completion Pointer Register This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The port uses the value written to determine if the interrupt should ...

Page 1344: ... Read only W1toCl Write 1 to clear bit n value after reset Table 14 123 TX4_CP Register Field Descriptions Bit Field Type Reset Description 31 0 TX_CP R W 0h Tx Completion Pointer Register This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The port uses the value written to determine if the interrupt should ...

Page 1345: ... Read only W1toCl Write 1 to clear bit n value after reset Table 14 124 TX5_CP Register Field Descriptions Bit Field Type Reset Description 31 0 TX_CP R W 0h Tx Completion Pointer Register This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The port uses the value written to determine if the interrupt should ...

Page 1346: ... Read only W1toCl Write 1 to clear bit n value after reset Table 14 125 TX6_CP Register Field Descriptions Bit Field Type Reset Description 31 0 TX_CP R W 0h Tx Completion Pointer Register This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The port uses the value written to determine if the interrupt should ...

Page 1347: ... Read only W1toCl Write 1 to clear bit n value after reset Table 14 126 TX7_CP Register Field Descriptions Bit Field Type Reset Description 31 0 TX_CP R W 0h Tx Completion Pointer Register This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The port uses the value written to determine if the interrupt should ...

Page 1348: ...s register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The port uses the value written to determine if the interrupt should be deasserted Note The value read is the completion pointer interrupt acknowledge value that was written by the CPDMA DMA controller port The value written to this register by the host is comp...

Page 1349: ...s register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The port uses the value written to determine if the interrupt should be deasserted Note The value read is the completion pointer interrupt acknowledge value that was written by the CPDMA DMA controller port The value written to this register by the host is comp...

Page 1350: ...s register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The port uses the value written to determine if the interrupt should be deasserted Note The value read is the completion pointer interrupt acknowledge value that was written by the CPDMA DMA controller port The value written to this register by the host is comp...

Page 1351: ...s register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The port uses the value written to determine if the interrupt should be deasserted Note The value read is the completion pointer interrupt acknowledge value that was written by the CPDMA DMA controller port The value written to this register by the host is comp...

Page 1352: ...s register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The port uses the value written to determine if the interrupt should be deasserted Note The value read is the completion pointer interrupt acknowledge value that was written by the CPDMA DMA controller port The value written to this register by the host is comp...

Page 1353: ...s register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The port uses the value written to determine if the interrupt should be deasserted Note The value read is the completion pointer interrupt acknowledge value that was written by the CPDMA DMA controller port The value written to this register by the host is comp...

Page 1354: ...s register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing The port uses the value written to determine if the interrupt should be deasserted Note The value read is the completion pointer interrupt acknowledge value that was written by the CPDMA DMA controller port The value written to this register by the host is comp...

Page 1355: ...ed in the location The interrupt is deasserted if the two values are equal 14 5 6 CPSW_PORT Registers Table 14 135 lists the memory mapped registers for the CPSW_PORT All register offset addresses not listed in Table 14 135 should be considered as reserved locations and the register contents should not be modified Table 14 135 CPSW_PORT REGISTERS Offset Acronym Register Name Section 0h P0_CONTROL ...

Page 1356: ... Section 14 5 6 34 200h P2_CONTROL Section 14 5 6 35 208h P2_MAX_BLKS Section 14 5 6 36 20Ch P2_BLK_CNT Section 14 5 6 37 210h P2_TX_IN_CTL Section 14 5 6 38 214h P2_PORT_VLAN Section 14 5 6 39 218h P2_TX_PRI_MAP Section 14 5 6 40 21Ch P2_TS_SEQ_MTYPE Section 14 5 6 41 220h P2_SA_LO Section 14 5 6 42 224h P2_SA_HI Section 14 5 6 43 228h P2_SEND_PERCENT Section 14 5 6 44 230h P2_RX_DSCP_PRI_MAP0 Se...

Page 1357: ...CPDMA_CH R W 0h Port 0 DLR CPDMA Channel This field indicates the CPDMA channel that DLR packets will be received on 24 P0_PASS_PRI_TAGGED R W 0h Port 0 Pass Priority Tagged 0 Priority tagged packets have the zero VID replaced with the input port P0_PORT_VLAN 11 0 1 Priority tagged packets are processed unchanged 21 P0_VLAN_LTYPE2_EN R W 0h Port 0 VLAN LTYPE 2 enable 0 disabled 1 enabled 20 P0_VLA...

Page 1358: ...ions Bit Field Type Reset Description 8 4 P0_TX_MAX_BLKS R W 10h Transmit FIFO Maximum Blocks This value is the maximum number of 1k memory blocks that may be allocated to the FIFO s logical transmit priority queues 0x10 is the recommended value of p0_tx_max_blks Port 0 should remain in flow control mode 0xe is the minimum value tx max blks 3 0 P0_RX_MAX_BLKS R W 4h Receive FIFO Maximum Blocks Thi...

Page 1359: ...R 4h R 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 138 P0_BLK_CNT Register Field Descriptions Bit Field Type Reset Description 8 4 P0_TX_BLK_CNT R 4h Port 0 Transmit Block Count Usage This value is the number of blocks allocated to the FIFO logical transmit queues 3 0 P0_RX_BLK_CNT R 1h Port 0 Receive Block Count Usage This value is the number of b...

Page 1360: ...alue after reset Table 14 139 P0_TX_IN_CTL Register Field Descriptions Bit Field Type Reset Description 23 20 TX_RATE_EN R W 0h Transmit FIFO Input Rate Enable 17 16 TX_IN_SEL R W 0h Transmit FIFO Input Queue Type Select 00 Normal priority mode 01 Dual MAC mode 10 Rate Limit mode 11 reserved Note that Dual MAC mode is not compatible with escalation or shaping because dual mac mode forces round rob...

Page 1361: ...RI PORT_CFI PORT_VID R W 0h R W 0h R W 0h 7 6 5 4 3 2 1 0 PORT_VID R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 140 P0_PORT_VLAN Register Field Descriptions Bit Field Type Reset Description 15 13 PORT_PRI R W 0h Port VLAN Priority 7 is highest priority 12 PORT_CFI R W 0h Port CFI bit 11 0 PORT_VID R W 0h Port VLAN ID 1361 SPRUH73H October 2011 R...

Page 1362: ...iption 29 28 PRI7 R W 3h Priority 7 A packet header priority of 0x7 is given this switch queue pri 25 24 PRI6 R W 3h Priority 6 A packet header priority of 0x6 is given this switch queue pri 21 20 PRI5 R W 2h Priority 5 A packet header priority of 0x5 is given this switch queue pri 17 16 PRI4 R W 2h Priority 4 A packet header priority of 0x4 is given this switch queue pri 13 12 PRI3 R W 1h Priorit...

Page 1363: ...t Description 30 28 PRI7 R W 7h Priority 7 A packet pri of 0x7 is mapped changed to this header packet pri 26 24 PRI6 R W 6h Priority 6 A packet pri of 0x6 is mapped changed to this header packet pri 22 20 PRI5 R W 5h Priority 5 A packet pri of 0x5 is mapped changed to this header packet pri 18 16 PRI4 R W 4h Priority 4 A packet pri of 0x4 is mapped changed to this header packet pri 14 12 PRI3 R W...

Page 1364: ...able 14 143 P0_CPDMA_RX_CH_MAP Register Field Descriptions Bit Field Type Reset Description 30 28 P2_PRI3 R W 0h Port 2 Priority 3 packets go to this CPDMA Rx Channel 26 24 P2_PRI2 R W 0h Port 2 Priority 2 packets go to this CPDMA Rx Channel 22 20 P2_PRI1 R W 0h Port 2 Priority 1 packets go to this CPDMA Rx Channel 18 16 P2_PRI0 R W 0h Port 2 Priority 0 packets go to this CPDMA Rx Channel 14 12 P1...

Page 1365: ...t Description 30 28 PRI7 R W 0h Priority 7 A packet TOS of 0d7 is mapped to this received packet priority 26 24 PRI6 R W 0h Priority 6 A packet TOS of 0d6 is mapped to this received packet priority 22 20 PRI5 R W 0h Priority 5 A packet TOS of 0d5 is mapped to this received packet priority 18 16 PRI4 R W 0h Priority 4 A packet TOS of 0d4 is mapped to this received packet priority 14 12 PRI3 R W 0h ...

Page 1366: ...cription 30 28 PRI15 R W 0h Priority 15 A packet TOS of 0d15 is mapped to this received packet priority 26 24 PRI14 R W 0h Priority 14 A packet TOS of 0d14 is mapped to this received packet priority 22 20 PRI13 R W 0h Priority 13 A packet TOS of 0d13 is mapped to this received packet priority 18 16 PRI12 R W 0h Priority 12 A packet TOS of 0d12 is mapped to this received packet priority 14 12 PRI11...

Page 1367: ...iption 30 28 PRI23 R W 0h Priority 23 A packet TOS of 0d23 is mapped to this received packet priority 26 24 PRI22 R W 0h Priority 22 A packet TOS of 0d22 is mapped to this received packet priority 22 20 PRI21 R W 0h Priority 21 A packet TOS of 0d21 is mapped to this received packet priority 18 16 PRI20 R W 0h Priority 20 A packet TOS of 0d20 is mapped to this received packet priority 14 12 PRI19 R...

Page 1368: ...iption 30 28 PRI31 R W 0h Priority 31 A packet TOS of 0d31 is mapped to this received packet priority 26 24 PRI30 R W 0h Priority 30 A packet TOS of 0d30 is mapped to this received packet priority 22 20 PRI29 R W 0h Priority 29 A packet TOS of 0d39 is mapped to this received packet priority 18 16 PRI28 R W 0h Priority 28 A packet TOS of 0d28 is mapped to this received packet priority 14 12 PRI27 R...

Page 1369: ...iption 30 28 PRI39 R W 0h Priority 39 A packet TOS of 0d39 is mapped to this received packet priority 26 24 PRI38 R W 0h Priority 38 A packet TOS of 0d38 is mapped to this received packet priority 22 20 PRI37 R W 0h Priority 37 A packet TOS of 0d37 is mapped to this received packet priority 18 16 PRI36 R W 0h Priority 36 A packet TOS of 0d36 is mapped to this received packet priority 14 12 PRI35 R...

Page 1370: ...iption 30 28 PRI47 R W 0h Priority 47 A packet TOS of 0d47 is mapped to this received packet priority 26 24 PRI46 R W 0h Priority 46 A packet TOS of 0d46 is mapped to this received packet priority 22 20 PRI45 R W 0h Priority 45 A packet TOS of 0d45 is mapped to this received packet priority 18 16 PRI44 R W 0h Priority 44 A packet TOS of 0d44 is mapped to this received packet priority 14 12 PRI43 R...

Page 1371: ...iption 30 28 PRI55 R W 0h Priority 55 A packet TOS of 0d55 is mapped to this received packet priority 26 24 PRI54 R W 0h Priority 54 A packet TOS of 0d54 is mapped to this received packet priority 22 20 PRI53 R W 0h Priority 53 A packet TOS of 0d53 is mapped to this received packet priority 18 16 PRI52 R W 0h Priority 52 A packet TOS of 0d52 is mapped to this received packet priority 14 12 PRI51 R...

Page 1372: ...iption 30 28 PRI63 R W 0h Priority 63 A packet TOS of 0d63 is mapped to this received packet priority 26 24 PRI62 R W 0h Priority 62 A packet TOS of 0d62 is mapped to this received packet priority 22 20 PRI61 R W 0h Priority 61 A packet TOS of 0d61 is mapped to this received packet priority 18 16 PRI60 R W 0h Priority 60 A packet TOS of 0d60 is mapped to this received packet priority 14 12 PRI59 R...

Page 1373: ... R W 0h Port 1 VLAN LTYPE 2 enable 0 disabled 1 VLAN LTYPE2 enabled on transmit and receive 20 P1_VLAN_LTYPE1_EN R W 0h Port 1 VLAN LTYPE 1 enable 0 disabled 1 VLAN LTYPE1 enabled on transmit and receive 16 P1_DSCP_PRI_EN R W 0h Port 1 DSCP Priority Enable 0 DSCP priority disabled 1 DSCP priority enabled All non tagged IPV4 packets have their received packet priority determined by mapping the 6 TO...

Page 1374: ...ZERO R W 0h Port 1 Time Sync Time To Live Non zero enable 0 TTL must be zero 1 TTL may be any value 4 P1_TS_ANNEX_D_EN R W 0h Port 1 Time Sync Annex D enable 0 Annex D disabled 1 Annex D enabled 3 P1_TS_LTYPE2_EN R 0h Port 1 Time Sync LTYPE 2 enable 0 disabled 1 enabled 2 P1_TS_LTYPE1_EN R W 0h Port 1 Time Sync LTYPE 1 enable 0 disabled 1 enabled 1 P1_TS_TX_EN R W 0h Port 1 Time Sync Transmit Enab...

Page 1375: ...queues 0x11 is the recommended value of p1_tx_max_blks unless the port is in fullduplex flow control mode In flow control mode the p1_rx_max_blks will need to increase in order to accept the required run out in fullduplex mode This value will need to decrease by the amount of increase in p1_rx_max_blks 0xe is the minimum value tx max blks 3 0 P1_RX_MAX_BLKS R W 3h Receive FIFO Maximum Blocks This ...

Page 1376: ...T R 4h R 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 154 P1_BLK_CNT Register Field Descriptions Bit Field Type Reset Description 8 4 P1_TX_BLK_CNT R 4h Port 1 Transmit Block Count Usage This value is the number of blocks allocated to the FIFO logical transmit queues 3 0 P1_RX_BLK_CNT R 1h Port 1 Receive Block Count Usage This value is the number of...

Page 1377: ... 155 P1_TX_IN_CTL Register Field Descriptions Bit Field Type Reset Description 27 24 HOST_BLKS_REM R W 8h Transmit FIFO Blocks that must be free before a non rate limited CPDMA channel can begin sending a packet to the FIFO 23 20 TX_RATE_EN R W 0h Transmit FIFO Input Rate Enable 17 16 TX_IN_SEL R W 0h Transmit FIFO Input Queue Type Select 00 Normal priority mode 01 reserved 10 Rate Limit mode 11 r...

Page 1378: ...PRI PORT_CFI PORT_VID R W 0h R W 0h R W 0h 7 6 5 4 3 2 1 0 PORT_VID R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 156 P1_PORT_VLAN Register Field Descriptions Bit Field Type Reset Description 15 13 PORT_PRI R W 0h Port VLAN Priority 7 is highest priority 12 PORT_CFI R W 0h Port CFI bit 11 0 PORT_VID R W 0h Port VLAN ID 1378 Ethernet Subsystem SPR...

Page 1379: ...scription 29 28 PRI7 R W 3h Priority 7 A packet header priority of 0x7 is given this switch queue pri 25 24 PRI6 R W 3h Priority 6 A packet header priority of 0x6 is given this switch queue pri 21 20 PRI5 R W 2h Priority 5 A packet header priority of 0x5 is given this switch queue pri 17 16 PRI4 R W 2h Priority 4 A packet header priority of 0x4 is given this switch queue pri 13 12 PRI3 R W 1h Prio...

Page 1380: ...W1toCl Write 1 to clear bit n value after reset Table 14 158 P1_TS_SEQ_MTYPE Register Field Descriptions Bit Field Type Reset Description 21 16 P1_TS_SEQ_ID_OFFSET R W 1Eh Port 1 Time Sync Sequence ID Offset This is the number of octets that the sequence ID is offset in the tx and rx time sync message header The minimum value is 6 15 0 P1_TS_MSG_TYPE_EN R W 0h Port 1 Time Sync Message Type Enable ...

Page 1381: ... 12 11 10 9 8 MACSRCADDR_7_0 R W 0h 7 6 5 4 3 2 1 0 MACSRCADDR_15_8 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 159 P1_SA_LO Register Field Descriptions Bit Field Type Reset Description 15 8 MACSRCADDR_7_0 R W 0h Source Address Lower 8 bits byte 0 7 0 MACSRCADDR_15_8 R W 0h Source Address bits 15 8 byte 1 1381 SPRUH73H October 2011 Revised Apri...

Page 1382: ...1 0 MACSRCADDR_47_40 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 160 P1_SA_HI Register Field Descriptions Bit Field Type Reset Description 31 24 MACSRCADDR_23_16 R W 0h Source Address bits 23 16 byte 2 23 16 MACSRCADDR_31_24 R W 0h Source Address bits 31 24 byte 3 15 8 MACSRCADDR_39_32 R W 0h Source Address bits 39 32 byte 4 7 0 MACSRCADDR_47_4...

Page 1383: ... includes interpacket gap and preamble bytes If shaping is enabled on this queue then this value must be between zero and 0d100 not inclusive 14 8 PRI2_SEND_PERCENT R W 0h Priority 2 Transmit Percentage This percentage value is sent from FIFO priority 2 maximum when the p1_pri2_shape_en is set queue shaping enabled This is the percentage of the wire that packets from priority 2 receive which inclu...

Page 1384: ...et Description 30 28 PRI7 R W 0h Priority 7 A packet TOS of 0d7 is mapped to this received packet priority 26 24 PRI6 R W 0h Priority 6 A packet TOS of 0d6 is mapped to this received packet priority 22 20 PRI5 R W 0h Priority 5 A packet TOS of 0d5 is mapped to this received packet priority 18 16 PRI4 R W 0h Priority 4 A packet TOS of 0d4 is mapped to this received packet priority 14 12 PRI3 R W 0h...

Page 1385: ...cription 30 28 PRI15 R W 0h Priority 15 A packet TOS of 0d15 is mapped to this received packet priority 26 24 PRI14 R W 0h Priority 14 A packet TOS of 0d14 is mapped to this received packet priority 22 20 PRI13 R W 0h Priority 13 A packet TOS of 0d13 is mapped to this received packet priority 18 16 PRI12 R W 0h Priority 12 A packet TOS of 0d12 is mapped to this received packet priority 14 12 PRI11...

Page 1386: ...iption 30 28 PRI23 R W 0h Priority 23 A packet TOS of 0d23 is mapped to this received packet priority 26 24 PRI22 R W 0h Priority 22 A packet TOS of 0d22 is mapped to this received packet priority 22 20 PRI21 R W 0h Priority 21 A packet TOS of 0d21 is mapped to this received packet priority 18 16 PRI20 R W 0h Priority 20 A packet TOS of 0d20 is mapped to this received packet priority 14 12 PRI19 R...

Page 1387: ...iption 30 28 PRI31 R W 0h Priority 31 A packet TOS of 0d31 is mapped to this received packet priority 26 24 PRI30 R W 0h Priority 30 A packet TOS of 0d30 is mapped to this received packet priority 22 20 PRI29 R W 0h Priority 29 A packet TOS of 0d39 is mapped to this received packet priority 18 16 PRI28 R W 0h Priority 28 A packet TOS of 0d28 is mapped to this received packet priority 14 12 PRI27 R...

Page 1388: ...iption 30 28 PRI39 R W 0h Priority 39 A packet TOS of 0d39 is mapped to this received packet priority 26 24 PRI38 R W 0h Priority 38 A packet TOS of 0d38 is mapped to this received packet priority 22 20 PRI37 R W 0h Priority 37 A packet TOS of 0d37 is mapped to this received packet priority 18 16 PRI36 R W 0h Priority 36 A packet TOS of 0d36 is mapped to this received packet priority 14 12 PRI35 R...

Page 1389: ...iption 30 28 PRI47 R W 0h Priority 47 A packet TOS of 0d47 is mapped to this received packet priority 26 24 PRI46 R W 0h Priority 46 A packet TOS of 0d46 is mapped to this received packet priority 22 20 PRI45 R W 0h Priority 45 A packet TOS of 0d45 is mapped to this received packet priority 18 16 PRI44 R W 0h Priority 44 A packet TOS of 0d44 is mapped to this received packet priority 14 12 PRI43 R...

Page 1390: ...iption 30 28 PRI55 R W 0h Priority 55 A packet TOS of 0d55 is mapped to this received packet priority 26 24 PRI54 R W 0h Priority 54 A packet TOS of 0d54 is mapped to this received packet priority 22 20 PRI53 R W 0h Priority 53 A packet TOS of 0d53 is mapped to this received packet priority 18 16 PRI52 R W 0h Priority 52 A packet TOS of 0d52 is mapped to this received packet priority 14 12 PRI51 R...

Page 1391: ...iption 30 28 PRI63 R W 0h Priority 63 A packet TOS of 0d63 is mapped to this received packet priority 26 24 PRI62 R W 0h Priority 62 A packet TOS of 0d62 is mapped to this received packet priority 22 20 PRI61 R W 0h Priority 61 A packet TOS of 0d61 is mapped to this received packet priority 18 16 PRI60 R W 0h Priority 60 A packet TOS of 0d60 is mapped to this received packet priority 14 12 PRI59 R...

Page 1392: ...EN R W 0h Port 2 VLAN LTYPE 2 enable 0 disabled 1 VLAN LTYPE2 enabled on transmit and receive 20 P2_VLAN_LTYPE1_EN R W 0h Port 2 VLAN LTYPE 1 enable 0 disabled 1 VLAN LTYPE1 enabled on transmit and receive 16 P2_DSCP_PRI_EN R W 0h Port 0 DSCP Priority Enable 0 DSCP priority disabled 1 DSCP priority enabled All non tagged IPV4 packets have their received packet priority determined by mapping the 6 ...

Page 1393: ...ZERO R W 0h Port 2 Time Sync Time To Live Non zero enable 0 TTL must be zero 1 TTL may be any value 4 P2_TS_ANNEX_D_EN R W 0h Port 2 Time Sync Annex D enable 0 Annex D disabled 1 Annex D enabled 3 P2_TS_LTYPE2_EN R 0h Port 2 Time Sync LTYPE 2 enable 0 disabled 1 enabled 2 P2_TS_LTYPE1_EN R W 0h Port 2 Time Sync LTYPE 1 enable 0 disabled 1 enabled 1 P2_TS_TX_EN R W 0h Port 2 Time Sync Transmit Enab...

Page 1394: ...queues 0x11 is the recommended value of p2_tx_max_blks unless the port is in fullduplex flow control mode In flow control mode the p2_rx_max_blks will need to increase in order to accept the required run out in fullduplex mode This value will need to decrease by the amount of increase in p2_rx_max_blks 0xe is the minimum value tx max blks 3 0 P2_RX_MAX_BLKS R W 3h Receive FIFO Maximum Blocks This ...

Page 1395: ...T R 4h R 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 172 P2_BLK_CNT Register Field Descriptions Bit Field Type Reset Description 8 4 P2_TX_BLK_CNT R 4h Port 2 Transmit Block Count Usage This value is the number of blocks allocated to the FIFO logical transmit queues 3 0 P2_RX_BLK_CNT R 1h Port 2 Receive Block Count Usage This value is the number of...

Page 1396: ... 173 P2_TX_IN_CTL Register Field Descriptions Bit Field Type Reset Description 27 24 HOST_BLKS_REM R W 8h Transmit FIFO Blocks that must be free before a non rate limited CPDMA channel can begin sending a packet to the FIFO 23 20 TX_RATE_EN R W 0h Transmit FIFO Input Rate Enable 17 16 TX_IN_SEL R W 0h Transmit FIFO Input Queue Type Select 00 Normal priority mode 01 reserved 10 Rate Limit mode 11 r...

Page 1397: ...PRI PORT_CFI PORT_VID R W 0h R W 0h R W 0h 7 6 5 4 3 2 1 0 PORT_VID R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 174 P2_PORT_VLAN Register Field Descriptions Bit Field Type Reset Description 15 13 PORT_PRI R W 0h Port VLAN Priority 7 is highest priority 12 PORT_CFI R W 0h Port CFI bit 11 0 PORT_VID R W 0h Port VLAN ID 1397 SPRUH73H October 2011 ...

Page 1398: ...scription 29 28 PRI7 R W 3h Priority 7 A packet header priority of 0x7 is given this switch queue pri 25 24 PRI6 R W 3h Priority 6 A packet header priority of 0x6 is given this switch queue pri 21 20 PRI5 R W 2h Priority 5 A packet header priority of 0x5 is given this switch queue pri 17 16 PRI4 R W 2h Priority 4 A packet header priority of 0x4 is given this switch queue pri 13 12 PRI3 R W 1h Prio...

Page 1399: ...y W1toCl Write 1 to clear bit n value after reset Table 14 176 P2_TS_SEQ_MTYPE Register Field Descriptions Bit Field Type Reset Description 21 16 P2_TS_SEQ_ID_OFFSET R W 1Eh Port 2 Time Sync Sequence ID Offset This is the number of octets that the sequence ID is offset in the tx and rx time sync message header The minimum value is 6 15 0 P2_TS_MSG_TYPE_EN R W 0h Port 2 Time Sync Message Type Enabl...

Page 1400: ... 12 11 10 9 8 MACSRCADDR_7_0 R W 0h 7 6 5 4 3 2 1 0 MACSRCADDR_15_8 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 177 P2_SA_LO Register Field Descriptions Bit Field Type Reset Description 15 8 MACSRCADDR_7_0 R W 0h Source Address Lower 8 bits byte 0 7 0 MACSRCADDR_15_8 R W 0h Source Address bits 15 8 byte 1 1400 Ethernet Subsystem SPRUH73H Octobe...

Page 1401: ...1 0 MACSRCADDR_47_40 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 178 P2_SA_HI Register Field Descriptions Bit Field Type Reset Description 31 24 MACSRCADDR_23_16 R W 0h Source Address bits 23 16 byte 2 23 16 MACSRCADDR_31_23 R W 0h Source Address bits 31 23 byte 3 15 8 MACSRCADDR_39_32 R W 0h Source Address bits 39 32 byte 4 7 0 MACSRCADDR_47_4...

Page 1402: ... includes interpacket gap and preamble bytes If shaping is enabled on this queue then this value must be between zero and 0d100 not inclusive 14 8 PRI2_SEND_PERCENT R W 0h Priority 2 Transmit Percentage This percentage value is sent from FIFO priority 2 maximum when the p1_pri2_shape_en is set queue shaping enabled This is the percentage of the wire that packets from priority 2 receive which inclu...

Page 1403: ...et Description 30 28 PRI7 R W 0h Priority 7 A packet TOS of 0d7 is mapped to this received packet priority 26 24 PRI6 R W 0h Priority 6 A packet TOS of 0d6 is mapped to this received packet priority 22 20 PRI5 R W 0h Priority 5 A packet TOS of 0d5 is mapped to this received packet priority 18 16 PRI4 R W 0h Priority 4 A packet TOS of 0d4 is mapped to this received packet priority 14 12 PRI3 R W 0h...

Page 1404: ...cription 30 28 PRI15 R W 0h Priority 15 A packet TOS of 0d15 is mapped to this received packet priority 26 24 PRI14 R W 0h Priority 14 A packet TOS of 0d14 is mapped to this received packet priority 22 20 PRI13 R W 0h Priority 13 A packet TOS of 0d13 is mapped to this received packet priority 18 16 PRI12 R W 0h Priority 12 A packet TOS of 0d12 is mapped to this received packet priority 14 12 PRI11...

Page 1405: ...iption 30 28 PRI23 R W 0h Priority 23 A packet TOS of 0d23 is mapped to this received packet priority 26 24 PRI22 R W 0h Priority 22 A packet TOS of 0d22 is mapped to this received packet priority 22 20 PRI21 R W 0h Priority 21 A packet TOS of 0d21 is mapped to this received packet priority 18 16 PRI20 R W 0h Priority 20 A packet TOS of 0d20 is mapped to this received packet priority 14 12 PRI19 R...

Page 1406: ...iption 30 28 PRI31 R W 0h Priority 31 A packet TOS of 0d31 is mapped to this received packet priority 26 24 PRI30 R W 0h Priority 30 A packet TOS of 0d30 is mapped to this received packet priority 22 20 PRI29 R W 0h Priority 29 A packet TOS of 0d39 is mapped to this received packet priority 18 16 PRI28 R W 0h Priority 28 A packet TOS of 0d28 is mapped to this received packet priority 14 12 PRI27 R...

Page 1407: ...iption 30 28 PRI39 R W 0h Priority 39 A packet TOS of 0d39 is mapped to this received packet priority 26 24 PRI38 R W 0h Priority 38 A packet TOS of 0d38 is mapped to this received packet priority 22 20 PRI37 R W 0h Priority 37 A packet TOS of 0d37 is mapped to this received packet priority 18 16 PRI36 R W 0h Priority 36 A packet TOS of 0d36 is mapped to this received packet priority 14 12 PRI35 R...

Page 1408: ...iption 30 28 PRI47 R W 0h Priority 47 A packet TOS of 0d47 is mapped to this received packet priority 26 24 PRI46 R W 0h Priority 46 A packet TOS of 0d46 is mapped to this received packet priority 22 20 PRI45 R W 0h Priority 45 A packet TOS of 0d45 is mapped to this received packet priority 18 16 PRI44 R W 0h Priority 44 A packet TOS of 0d44 is mapped to this received packet priority 14 12 PRI43 R...

Page 1409: ...iption 30 28 PRI55 R W 0h Priority 55 A packet TOS of 0d55 is mapped to this received packet priority 26 24 PRI54 R W 0h Priority 54 A packet TOS of 0d54 is mapped to this received packet priority 22 20 PRI53 R W 0h Priority 53 A packet TOS of 0d53 is mapped to this received packet priority 18 16 PRI52 R W 0h Priority 52 A packet TOS of 0d52 is mapped to this received packet priority 14 12 PRI51 R...

Page 1410: ...0h Priority 62 A packet TOS of 0d62 is mapped to this received packet priority 22 20 PRI61 R W 0h Priority 61 A packet TOS of 0d61 is mapped to this received packet priority 18 16 PRI60 R W 0h Priority 60 A packet TOS of 0d60 is mapped to this received packet priority 14 12 PRI59 R W 0h Priority 59 A packet TOS of 0d59 is mapped to this received packet priority 10 8 PRI58 R W 0h Priority 58 A pack...

Page 1411: ...STER Section 14 5 7 5 14h BOFFTEST CPGMAC_SL BACKOFF TEST REGISTER Section 14 5 7 6 18h RX_PAUSE CPGMAC_SL RECEIVE PAUSE TIMER REGISTER Section 14 5 7 7 1Ch TX_PAUSE CPGMAC_SL TRANSMIT PAUSE TIMER REGISTER Section 14 5 7 8 20h EMCONTROL CPGMAC_SL EMULATION CONTROL REGISTER Section 14 5 7 9 24h RX_PRI_MAP CPGMAC_SL RX PKT PRIORITY TO HEADER Section 14 5 7 10 PRIORITY MAPPING REGISTER 28h TX_GAP TRA...

Page 1412: ...0 9 8 Z X R 2E0h R 1701h 7 6 5 4 3 2 1 0 Y R 170112h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 189 IDVER Register Field Descriptions Bit Field Type Reset Description 31 16 IDENT R 17h Rx Identification Value 15 11 Z R 2E0h Rx Z value X Y Z 10 8 X R 1701h Rx X value major 7 0 Y R 170112h Rx Y value minor 1412 Ethernet Subsystem SPRUH73H October 2011 ...

Page 1413: ...ltered but acted upon if enabled 1 MAC control frames are transferred to memory 23 RX_CSF_EN R W 0h RX Copy Short Frames Enable Enables frames or fragments shorter than 64 bytes to be copied to memory Frames transferred to memory due to rx_csf_en will have the fragment or undersized bit set in their receive footer Fragments are short frames that contain CRC align code errors and undersized are sho...

Page 1414: ...GMII RX and TX released from reset 4 TX_FLOW_EN R W 0h Transmit Flow Control Enable Determines if incoming pause frames are acted upon in full duplex mode Incoming pause frames are not acted upon in half duplex mode regardless of this bit setting The RX_MBP_Enable bits determine whether or not received pause frames are transferred to memory 0 Transmit Flow Control Disabled Full duplex mode Incomin...

Page 1415: ...0h Full Duplex mode Gigabit mode forces fullduplex mode regardless of whether the fullduplex bit is set or not The FULLDUPLEX_OUT output is the value of this register bit 0 half duplex mode 1 full duplex mode 1415 SPRUH73H October 2011 Revised April 2013 Ethernet Subsystem Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1416: ...ter an idle command 0 The CPGMAC_SL is not in the idle state 1 The CPGMAC_SL is in the idle state 30 5 Reserved R 0h 4 EXT_GIG R 0h External GIG This is the value of the EXT_GIG input bit 3 EXT_FULLDUPLEX R 0h External Fullduplex This is the value of the EXT_FULLDUPLEX input bit 2 Reserved R 0h 1 RX_FLOW_ACT R 0h Receive Flow Control Active When asserted indicates that receive flow control is enab...

Page 1417: ...d Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 192 SOFT_RESET Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 SOFT_RESET R W 0h Software reset Writing a one to this bit causes the CPGMAC_SL logic to be reset After writing a one to this bit it may be polled to determine if the reset has occurred If a one is read the reset has not yet o...

Page 1418: ...Cl Write 1 to clear bit n value after reset Table 14 193 RX_MAXLEN Register Field Descriptions Bit Field Type Reset Description 31 14 Reserved R 0h 13 0 RX_MAXLEN R W 5EEh RX Maximum Frame Length This field determines the maximum length of a received frame The reset value is 1518 dec Frames with byte counts greater than rx_maxlen are long frames Long frames with no errors are oversized frames Long...

Page 1419: ...val is nonzero the transmitter delays 4 IPGs between new frame transmissions after each successfully transmitted frame that had no deferrals or collisions Transmit pacing helps reduce capture effects improving overall network bandwidth 25 16 RNDNUM R W 0h Backoff Random Number Generator This field allows the Backoff Random Number Generator to be read or written in test mode only This field can be ...

Page 1420: ...er Field Descriptions Bit Field Type Reset Description 31 16 rx_pausetimer R 0h RX Pause Timer Value This field allows the contents of the receive pause timer to be observed and written in test mode The receive pause timer is loaded with 0xFF00 when the CPGMAC_SL sends an outgoing pause frame with pause time of 0xFFFF The receive pause timer is decremented at slot time intervals If the receive pau...

Page 1421: ... Write 1 to clear bit n value after reset Table 14 196 TX_PAUSE Register Field Descriptions Bit Field Type Reset Description 31 16 tx_pausetimer R 0h TX Pause Timer Value This field allows the contents of the transmit pause timer to be observed and written in test mode The transmit pause timer is loaded by a received incoming pause frame and then decremented at slottime intervals down to zero at w...

Page 1422: ...ed R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved SOFT FREE R 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 197 EMCONTROL Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 SOFT R W 0h Emulation Soft Bit 0 FREE R W 0h Emulation Free Bit 1422 Ethernet Subsystem SPRUH73H October 2011 Revis...

Page 1423: ...28 PRI7 R W 7h Priority 7 A packet priority of 0x7 is mapped changed to this value 27 Reserved R Eh 26 24 PRI6 R W 76h Priority 6 A packet priority of 0x6 is mapped changed to this value 23 Reserved R ECh 22 20 PRI5 R W 765h Priority 5 A packet priority of 0x5 is mapped changed to this value 19 Reserved R ECAh 18 16 PRI4 R W 7654h Priority 4 A packet priority of 0x4 is mapped changed to this value...

Page 1424: ...tions and the register contents should not be modified Table 14 200 CPSW_SS REGISTERS Offset Acronym Register Name Section 0h ID_VER ID VERSION REGISTER Section 14 5 8 1 4h CONTROL SWITCH CONTROL REGISTER Section 14 5 8 2 8h SOFT_RESET SOFT RESET REGISTER Section 14 5 8 3 Ch STAT_PORT_EN STATISTICS PORT ENABLE REGISTER Section 14 5 8 4 10h PTYPE TRANSMIT PRIORITY TYPE REGISTER Section 14 5 8 5 14h...

Page 1425: ...0 7 6 5 4 3 2 1 0 CPSW_3G_MINOR_VER R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 201 ID_VER Register Field Descriptions Bit Field Type Reset Description 31 16 CPSW_3G_IDENT R 0 0 3G Identification Value 15 11 CPSW_3G_RTL_VER R 0 0 3G RTL Version Value 10 8 CPSW_3G_MAJ_VER R 0 0 3G Major Version Value 7 0 CPSW_3G_MINOR_VER R 0 0 3G Minor Version Val...

Page 1426: ..._cpdma_ch 1 DLR is disabled DLR packets be moved to destination port transmit queue priority 3 and will be separated out onto dlr_cpdma_ch when packet is to egress on port 0 2 RX_VLAN_ENCAP R W 0 0 Port 0 VLAN Encapsulation egress 0 Port 2 receive packets from 3G are not VLAN encapsulated 1 Port 2 receive packets from 3G are VLAN encapsulated 1 VLAN_AWARE R W 0 0 VLAN Aware Mode 0 3G is in the VLA...

Page 1427: ...only W1toCl Write 1 to clear bit n value after reset Table 14 203 SOFT_RESET Register Field Descriptions Bit Field Type Reset Description 0 SOFT_RESET R W 0 0 Software reset Writing a one to this bit causes the 3G logic to be reset After writing a one to this bit it may be polled to determine if the reset has occurred If a one is read the reset has not yet occurred If a zero is read then reset has...

Page 1428: ...04 STAT_PORT_EN Register Field Descriptions Bit Field Type Reset Description 2 P2_STAT_EN R W 0 0 Port 2 GMII2 and Port 2 FIFO Statistics Enable 0 Port 2 statistics are not enabled 1 Port 2 statistics are enabled 1 P1_STAT_EN R W 0 0 Port 1 GMII1 and Port 1 FIFO Statistics Enable 0 Port 1 statistics are not enabled 1 Port 1 statistics are enabled 0 P0_STAT_EN R W 0 0 Port 0 Statistics Enable 0 Por...

Page 1429: ...EN R W 0 0 Port 1 Queue Priority 3 Transmit Shape Enable If there is only one shaping queue then it must be priority 3 17 P1_PRI2_SHAPE_EN R W 0 0 Port 1 Queue Priority 2 Transmit Shape Enable If there are two shaping queues then they must be priorities 3 and 2 16 P1_PRI1_SHAPE_EN R W 0 0 Port 1 Queue Priority 1 Transmit Shape Enable If there are three shaping queues all three bits should be set 1...

Page 1430: ...4 3 2 1 0 Reserved SOF T_ID LE R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 206 SOFT_IDLE Register Field Descriptions Bit Field Type Reset Description 0 SOFT_IDLE R W 0 0 Software Idle Setting this bit causes the switch fabric to stop forwarding packets at the next start of packet 1430 Ethernet Subsystem SPRUH73H October 2011 Revised April 2013 S...

Page 1431: ... 207 THRU_RATE Register Field Descriptions Bit Field Type Reset Description 15 12 SL_RX_THRU_RATE R W 0 0 CPGMAC_SL Switch FIFO receive through rate This register value is the maximum throughput of the ethernet ports to the crossbar SCR The default is one 8 byte word for every 3 CLK periods maximum 3 0 CPDMA_THRU_RATE R W 0 0 CPDMA Switch FIFO receive through rate This register value is the maximu...

Page 1432: ...5 4 3 2 1 0 Reserved GAP_THRESH R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 208 GAP_THRESH Register Field Descriptions Bit Field Type Reset Description 4 0 GAP_THRESH R W 0 0 CPGMAC_SL Short Gap Threshold This is the CPGMAC_SL associated FIFO transmit block usage value for triggering TX_SHORT_GAP 1432 Ethernet Subsystem SPRUH73H October 2011 Rev...

Page 1433: ... bit n value after reset Table 14 209 TX_START_WDS Register Field Descriptions Bit Field Type Reset Description 10 0 TX_START_WDS R W 0 0 FIFO Packet Transmit egress Start Words This value is the number of required packet words in the transmit FIFO before the packet egress will begin This value is non zero to preclude underrun Decimal 32 is the recommended value It should not be increased unnecess...

Page 1434: ...P2_FLOW_EN P1_FLOW_EN P0_FLOW_EN R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 210 FLOW_CONTROL Register Field Descriptions Bit Field Type Reset Description 2 P2_FLOW_EN R W 0 0 Port 2 Receive flow control enable 1 P1_FLOW_EN R W 0 0 Port 1 Receive flow control enable 0 P0_FLOW_EN R W 0 0 Port 0 Receive flow control enable 1434 Etherne...

Page 1435: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 211 VLAN_LTYPE Register Field Descriptions Bit Field Type Reset Description 31 16 VLAN_LTYPE2 R W 0 0 Time Sync VLAN LTYPE2 This VLAN LTYPE value is used for tx and rx This is the inner VLAN if both are present 15 0 VLAN_LTYPE1 R W 0 0 Time Sync VLAN LTYPE1 This VLAN LTYPE value is used for tx and rx This ...

Page 1436: ...3 2 1 0 TS_LTYPE1 R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 212 TS_LTYPE Register Field Descriptions Bit Field Type Reset Description 21 16 TS_LTYPE2 R W 0 0 Time Sync LTYPE2 This is an Ethertype value to match for tx and rx time sync packets 15 0 TS_LTYPE1 R W 0 0 Time Sync LTYPE1 This is an ethertype value to match for tx and rx time sync pa...

Page 1437: ...4h SOFT_RESET Section 14 5 9 2 8h CONTROL Section 14 5 9 3 Ch INT_CONTROL Section 14 5 9 4 10h C0_RX_THRESH_EN Section 14 5 9 5 14h C0_RX_EN Section 14 5 9 6 18h C0_TX_EN Section 14 5 9 7 1Ch C0_MISC_EN Section 14 5 9 8 20h C1_RX_THRESH_EN Section 14 5 9 9 24h C1_RX_EN Section 14 5 9 10 28h C1_TX_EN Section 14 5 9 11 2Ch C1_MISC_EN Section 14 5 9 12 30h C2_RX_THRESH_EN Section 14 5 9 13 34h C2_RX_...

Page 1438: ...9 29 74h C0_TX_IMAX Section 14 5 9 30 78h C1_RX_IMAX Section 14 5 9 31 7Ch C1_TX_IMAX Section 14 5 9 32 80h C2_RX_IMAX Section 14 5 9 33 84h C2_TX_IMAX Section 14 5 9 34 88h RGMII_CTL Section 14 5 9 35 1438 Ethernet Subsystem SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1439: ...R 1h 7 6 5 4 3 2 1 0 CUSTOM MINOR R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 215 IDVER Register Field Descriptions Bit Field Type Reset Description 31 30 SCHEME R 1h Scheme value 29 28 Reserved R 0h 27 16 FUNCTION R EDBh function value 15 11 RTL R 0h rtl version 10 8 MAJOR R 1h major version 7 6 CUSTOM R 0h custom version 5 0 MINOR R 0h min...

Page 1440: ... Reserved SOFT_RESET R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 216 SOFT_RESET Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 SOFT_RESET R W 0h Software reset Writing a one to this bit causes the CPGMACSS_R logic to be reset INT REGS CPPI Software reset occurs on the clock following the register bit writ...

Page 1441: ...management mode By definition initiator may generate read write transaction as long as it is out of STANDBY state 0x0 Force standby mode Local initiator is unconditionally placed in standbystate 0x1 No standby mode Local initiator is unconditionally placed out of standby state 0x2 Reserved Reserved 0x3 Reserved Reserved 1 0 MMR_IDLEMODE R W 0h Configuration of the local initiator state management ...

Page 1442: ...t Description 31 INT_TEST R W 0h Interrupt Test Test bit to the interrupt pacing blocks 30 22 Reserved R 0h 21 16 INT_PACE_EN R W 0h Interrupt Pacing Enable Bus int_pace_en 0 Enables C0_Rx_Pulse Pacing 0 is pacing bypass int_pace_en 1 Enables C0_Tx_Pulse Pacing 0 is pacing bypass int_pace_en 2 Enables C1_Rx_Pulse Pacing 0 is pacing bypass int_pace_en 3 Enables C1_Tx_Pulse Pacing 0 is pacing bypass...

Page 1443: ...5 4 3 2 1 0 C0_RX_THRESH_EN R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 219 C0_RX_THRESH_EN Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 C0_RX_THRESH_EN R W 0h Core 0 Receive Threshold Enable Each bit in this register corresponds to the bit in the receive threshold interrupt that is enabled to generate an ...

Page 1444: ...rved R 0h 7 6 5 4 3 2 1 0 C0_RX_EN R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 220 C0_RX_EN Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 C0_RX_EN R W 0h Core 0 Receive Enable Each bit in this register corresponds to the bit in the rx interrupt that is enabled to generate an interrupt on C0_RX_PULSE 1444 Et...

Page 1445: ...rved R 0h 7 6 5 4 3 2 1 0 C0_TX_EN R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 221 C0_TX_EN Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 C0_TX_EN R W 0h Core 0 Transmit Enable Each bit in this register corresponds to the bit in the tx interrupt that is enabled to generate an interrupt on C0_TX_PULSE 1445 S...

Page 1446: ... R Read only W1toCl Write 1 to clear bit n value after reset Table 14 222 C0_MISC_EN Register Field Descriptions Bit Field Type Reset Description 31 5 Reserved R 0h 4 0 C0_MISC_EN R W 0h Core 0 Misc Enable Each bit in this register corresponds to the miscellaneous interrupt evnt_pend stat_pend host_pend mdio_linkint mdio_userint that is enabled to generate an interrupt on C0_Misc_PULSE Bit 4 evnt_...

Page 1447: ...5 4 3 2 1 0 C1_RX_THRESH_EN R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 223 C1_RX_THRESH_EN Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 C1_RX_THRESH_EN R W 0h Core 1 Receive Threshold Enable Each bit in this register corresponds to the bit in the receive threshold interrupt that is enabled to generate an ...

Page 1448: ...erved R 0h 7 6 5 4 3 2 1 0 C1_RX_EN R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 224 C1_RX_EN Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 C1_RX_EN R W 0h Core 1 Receive Enable Each bit in this register corresponds to the bit in the rx interrupt that is enabled to generate an interrupt on C1_RX_PULSE 1448 E...

Page 1449: ...erved R 0h 7 6 5 4 3 2 1 0 C1_TX_EN R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 225 C1_TX_EN Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 C1_TX_EN R W 0h Core 1 Transmit Enable Each bit in this register corresponds to the bit in the tx interrupt that is enabled to generate an interrupt on C1_TX_PULSE 1449 ...

Page 1450: ...e R Read only W1toCl Write 1 to clear bit n value after reset Table 14 226 C1_MISC_EN Register Field Descriptions Bit Field Type Reset Description 31 5 Reserved R 0h 4 0 C1_MISC_EN R W 0h Core 1 Misc Enable Each bit in this register corresponds to the miscellaneous interrupt evnt_pend stat_pend host_pend mdio_linkint mdio_userint that is enabled to generate an interrupt on C1_Misc_PULSE Bit 4 evnt...

Page 1451: ... 5 4 3 2 1 0 C2_RX_THRESH_EN R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 227 C2_RX_THRESH_EN Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 C2_RX_THRESH_EN R W 0h Core 2 Receive Threshold Enable Each bit in this register corresponds to the bit in the receive threshold interrupt that is enabled to generate an...

Page 1452: ...erved R 0h 7 6 5 4 3 2 1 0 C2_RX_EN R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 228 C2_RX_EN Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 C2_RX_EN R W 0h Core 2 Receive Enable Each bit in this register corresponds to the bit in the rx interrupt that is enabled to generate an interrupt on C2_RX_PULSE 1452 E...

Page 1453: ...erved R 0h 7 6 5 4 3 2 1 0 C2_TX_EN R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 229 C2_TX_EN Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 C2_TX_EN R W 0h Core 2 Transmit Enable Each bit in this register corresponds to the bit in the tx interrupt that is enabled to generate an interrupt on C2_TX_PULSE 1453 ...

Page 1454: ...e R Read only W1toCl Write 1 to clear bit n value after reset Table 14 230 C2_MISC_EN Register Field Descriptions Bit Field Type Reset Description 31 5 Reserved R 0h 4 0 C2_MISC_EN R W 0h Core 2 Misc Enable Each bit in this register corresponds to the miscellaneous interrupt evnt_pend stat_pend host_pend mdio_linkint mdio_userint that is enabled to generate an interrupt on C2_Misc_PULSE Bit 4 evnt...

Page 1455: ... C0_RX_THRESH_STAT R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 231 C0_RX_THRESH_STAT Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 C0_RX_THRESH_STAT R 0h Core 0 Receive Threshold Masked Interrupt Status Each bit in this read only register corresponds to the bit in the receive threshold interrupt that is enabl...

Page 1456: ... 7 6 5 4 3 2 1 0 C0_RX_STAT R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 232 C0_RX_STAT Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 C0_RX_STAT R 0h Core 0 Receive Masked Interrupt Status Each bit in this read only register corresponds to the bit in the Rx interrupt that is enabled and generating an interrupt...

Page 1457: ...7 6 5 4 3 2 1 0 C0_TX_STAT R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 233 C0_TX_STAT Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 C0_TX_STAT R 0h Core 0 Transmit Masked Interrupt Status Each bit in this read only register corresponds to the bit in the Tx interrupt that is enabled and generating an interrupt...

Page 1458: ... Read only W1toCl Write 1 to clear bit n value after reset Table 14 234 C0_MISC_STAT Register Field Descriptions Bit Field Type Reset Description 31 5 Reserved R 0h 4 0 C0_MISC_STAT R 0h Core 0 Misc Masked Interrupt Status Each bit in this register corresponds to the miscellaneous interrupt evnt_pend stat_pend host_pend mdio_linkint mdio_userint that is enabled and generating an interrupt on C0_MI...

Page 1459: ...2 1 0 C1_RX_THRESH_STAT R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 235 C1_RX_THRESH_STAT Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 C1_RX_THRESH_STAT R 0h Core 1 Receive Threshold Masked Interrupt Status Each bit in this register corresponds to the bit in the receive threshold interrupt that is enabled an...

Page 1460: ... R 0h 7 6 5 4 3 2 1 0 C1_RX_STAT R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 236 C1_RX_STAT Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 C1_RX_STAT R 0h Core 1 Receive Masked Interrupt Status Each bit in this register corresponds to the bit in the Rx interrupt that is enabled and generating an interrupt on C...

Page 1461: ... R 0h 7 6 5 4 3 2 1 0 C1_TX_STAT R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 237 C1_TX_STAT Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 C1_TX_STAT R 0h Core 1 Transmit Masked Interrupt Status Each bit in this register corresponds to the bit in the Tx interrupt that is enabled and generating an interrupt on ...

Page 1462: ...ead only W1toCl Write 1 to clear bit n value after reset Table 14 238 C1_MISC_STAT Register Field Descriptions Bit Field Type Reset Description 31 5 Reserved R 0h 4 0 C1_MISC_STAT R 0h Core 1 Misc Masked Interrupt Status Each bit in this register corresponds to the miscellaneous interrupt evnt_pend stat_pend host_pend mdio_linkint mdio_userint that is enabled and generating an interrupt on C1_MISC...

Page 1463: ...2 1 0 C2_RX_THRESH_STAT R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 239 C2_RX_THRESH_STAT Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 C2_RX_THRESH_STAT R 0h Core 2 Receive Threshold Masked Interrupt Status Each bit in this register corresponds to the bit in the receive threshold interrupt that is enabled an...

Page 1464: ... R 0h 7 6 5 4 3 2 1 0 C2_RX_STAT R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 240 C2_RX_STAT Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 C2_RX_STAT R 0h Core 2 Receive Masked Interrupt Status Each bit in this register corresponds to the bit in the Rx interrupt that is enabled and generating an interrupt on C...

Page 1465: ... R 0h 7 6 5 4 3 2 1 0 C2_TX_STAT R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 241 C2_TX_STAT Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 C2_TX_STAT R 0h Core 2 Transmit Masked Interrupt Status Each bit in this register corresponds to the bit in the Tx interrupt that is enabled and generating an interrupt on ...

Page 1466: ...ead only W1toCl Write 1 to clear bit n value after reset Table 14 242 C2_MISC_STAT Register Field Descriptions Bit Field Type Reset Description 31 5 Reserved R 0h 4 0 C2_MISC_STAT R 0h Core 2 Misc Masked Interrupt Status Each bit in this register corresponds to the miscellaneous interrupt evnt_pend stat_pend host_pend mdio_linkint mdio_userint that is enabled and generating an interrupt on C2_MISC...

Page 1467: ...7 6 5 4 3 2 1 0 Reserved C0_RX_IMAX R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 243 C0_RX_IMAX Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 0 C0_RX_IMAX R W 0h Core 0 Receive Interrupts per Millisecond The maximum number of interrupts per millisecond generated on C0_RX_PULSE if pacing is enabled for thi...

Page 1468: ...7 6 5 4 3 2 1 0 Reserved C0_TX_IMAX R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 244 C0_TX_IMAX Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 0 C0_TX_IMAX R W 0h Core 0 Transmit Interrupts per Millisecond The maximum number of interrupts per millisecond generated on C0_TX_PULSE if pacing is enabled for th...

Page 1469: ...7 6 5 4 3 2 1 0 Reserved C1_RX_IMAX R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 245 C1_RX_IMAX Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 0 C1_RX_IMAX R W 0h Core 1 Receive Interrupts per Millisecond The maximum number of interrupts per millisecond generated on C1_RX_PULSE if pacing is enabled for thi...

Page 1470: ...7 6 5 4 3 2 1 0 Reserved C1_TX_IMAX R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 246 C1_TX_IMAX Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 0 C1_TX_IMAX R W 0h Core 1 Transmit Interrupts per Millisecond The maximum number of interrupts per millisecond generated on C1_TX_PULSE if pacing is enabled for th...

Page 1471: ...7 6 5 4 3 2 1 0 Reserved C2_RX_IMAX R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 247 C2_RX_IMAX Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 0 C2_RX_IMAX R W 0h Core 2 Receive Interrupts per Millisecond The maximum number of interrupts per millisecond generated on C2_RX_PULSE if pacing is enabled for thi...

Page 1472: ...7 6 5 4 3 2 1 0 Reserved C2_TX_IMAX R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 14 248 C2_TX_IMAX Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 0 C2_TX_IMAX R W 0h Core 2 Transmit Interrupts per Millisecond The maximum number of interrupts per millisecond generated on C2_TX_PULSE if pacing is enabled for th...

Page 1473: ...Half duplex mode 1 Fullduplex mode 6 5 RGMII2_SPEED R 0h RGMII2 Speed This is the CPRGMI speed output signal 00 10Mbps mode 01 100Mbps mode 10 1000Mbps gig mode 11 reserved 4 RGMII2_LINK R 0h RGMII2 Link Indicator This is the CPRGMII link output signal 0 RGMII2 link is down 1 RGMII2 link is up 3 RGMII1_FULLDUPLEX R 0h RGMII1 Fullduplex This is the CPRGMII fullduplex output signal 0 Half duplex mod...

Page 1474: ...SERINTMASKCLR MDIO User Interrupt Mask Clear Register Section 14 5 10 10 80h MDIOUSERACCESS0 MDIO User Access Register 0 Section 14 5 10 11 84h MDIOUSERPHYSEL0 MDIO User PHY Select Register 0 Section 14 5 10 12 88h MDIOUSERACCESS1 MDIO User Access Register 1 Section 14 5 10 13 8Ch MDIOUSERPHYSEL1 MDIO User PHY Select Register 1 Section 14 5 10 14 14 5 10 1 MDIO Version Register MDIOVER The MDIO ve...

Page 1475: ...his implies that the MDIOUSERACCESS1 register is the highest available user access channel 23 21 Reserved 0 Reserved 20 PREAMBLE Preamble disable 0 Standard MDIO preamble is used 1 Disables this device from sending MDIO frame preambles 19 FAULT Fault indicator This bit is set to 1 if the MDIO pins fail to read back what the device is driving onto them This indicates a physical layer fault and the ...

Page 1476: ...ister MDIOLINK The PHY link status register MDIOLINK is shown in Figure 14 235 and described in Table 14 254 Figure 14 235 PHY Link Status Register MDIOLINK 31 0 LINK R 0x0 LEGEND R Read only n value after reset Table 14 254 PHY Link Status Register MDIOLINK Field Descriptions Bit Field Value Description 31 0 LINK 0 FFFF FFFFh MDIO link state This register is updated after a read of the Generic St...

Page 1477: ...nk Status Change Interrupt Register Masked Value MDIOLINKINTMASKED The MDIO link status change interrupt register Masked Value MDIOLINKINTMASKED is shown in Figure 14 237 and described in Table 14 256 Figure 14 237 MDIO Link Status Change Interrupt Register Masked Value MDIOLINKINTMASKED 31 16 Reserved R 0x0 15 2 1 0 Reserved LINKINTMASKED R 0x0 RWC 0x0 LEGEND RWC Read Write Clear R Read only n va...

Page 1478: ...14 5 10 8 MDIO User Command Complete Interrupt Register Masked Value MDIOUSERINTMASKED The MDIO user command complete interrupt register Masked Value MDIOUSERINTMASKED is shown in Figure 14 239 and described in Table 14 258 Figure 14 239 MDIO User Command Complete Interrupt Register Masked Value MDIOUSERINTMASKED 31 16 Reserved R 0x0 15 2 1 0 Reserved USERINTMASKED R 0x0 RWC 0x0 LEGEND RWC Read Wr...

Page 1479: ... after reset Table 14 259 MDIO User Command Complete Interrupt Mask Set Register MDIOUSERINTMASKSET Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 USERINTMASKSET 0 3h MDIO user interrupt mask set for USERINTMASKED respectively Writing a bit to 1 will enable MDIO user command complete interrupts for that particular MDIOUSERACCESSn register MDIO user interrupt for a part...

Page 1480: ...ead Write Clear R Read only n value after reset Table 14 260 MDIO User Command Complete Interrupt Mask Clear Register MDIOUSERINTMASKCLR Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 USERINTMASKCLEAR 0 3h MDIO user command complete interrupt mask clear for USERINTMASKED respectively Writing a bit to 1 will disable further user command complete interrupts for that part...

Page 1481: ...ffect This bit is write able only if the MDIO state machine is enabled This bit will self clear when the requested access has been completed Any writes to the MDIOUSERACCESS0 register are blocked when the GO bit is 1 If byte access is being used the GO bit should be written last 30 WRITE 0 1 Write enable Setting this bit to a 1 causes the MDIO transaction to be a register write otherwise it is a r...

Page 1482: ...ed 0 Reserved 7 LINKSEL 0 1 Link status determination select Set to 1 to determine link status using the MLINK pin Default value is 0 which implies that the link status is determined by the MDIO state machine 6 LINKINTENB Link change interrupt enable Set to 1 to enable link change status interrupts for PHY address specified in PHYADDRMON Link change interrupts are disabled if this bit is set to 0 ...

Page 1483: ...fect This bit is write able only if the MDIO state machine is enabled This bit will self clear when the requested access has been completed Any writes to the MDIOUSERACCESS0 register are blocked when the GO bit is 1 If byte access is being used the GO bit should be written last 30 WRITE 0 1 Write enable Setting this bit to a 1 causes the MDIO transaction to be a register write otherwise it is a re...

Page 1484: ... 0 Reserved 7 LINKSEL 0 1 Link status determination select Set to 1 to determine link status using the MLINK pin Default value is 0 which implies that the link status is determined by the MDIO state machine 6 LINKINTENB Link change interrupt enable Set to 1 to enable link change status interrupts for PHY address specified in PHYADDRMON Link change interrupts are disabled if this bit is cleared to ...

Page 1485: ...ge 15 1 Pulse Width Modulation Subsystem PWMSS 1486 15 2 Enhanced PWM ePWM Module 1494 15 3 Enhanced Capture eCAP Module 1607 15 4 Enhanced Quadrature Encoder Pulse eQEP Module 1650 1485 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsystem PWMSS Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1486: ...n a per PWM period basis Can be inserted either on the rising edge or falling edge of the PWM pulse or both or not at all eCAP Dedicated input Capture pin 32 bit Time Base counter 4 x 32 bit Time stamp Capture registers CAP1 CAP4 4 stage sequencer Mod4 counter which is synchronized to external events ECAPx pin edges Independent Edge polarity Rising Falling edge selection for all 4 events Input Cap...

Page 1487: ...atures Feature Reason ePWM inputs Not pinned out ePWM tripzone 1 5 inputs Only Tripzone0 is pinned out ePWM digital comparators Inputs not connected eQEP quadrature outputs Only input signals are connected 1487 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsystem PWMSS Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1488: ... 15 2 Table 15 2 PWMSS Connectivity Attributes Attributes Type Power Domain Peripheral Domain Clock Domain PD_PER_L4LS_GCLK Reset Signals PER_DOM_RST_N Idle Wakeup Signals Smart Idle Interrupt Requests 2 ePWM interrupts per instance epwm_intr_intr Event interrupt ePWMxINT for ARM subsystem epwm_intr_intr_pend for PRU ICSS epwm_tz_intr Tripzone interrupt ePWMx_TZINT for ARM subsystem pwm_trip_zone ...

Page 1489: ...ture input PWM output EQEP_A I O eQEP Quadrature input output EQEP_B I O eQEP Quadrature input output EQEP_INDEX I O eQEP Index input output EQEP_STROBE I O eQEP Strobe input output 15 1 3 PWMSS Registers Table 15 5 lists the memory mapped registers for the PWMSS All register offset addresses not listed in Table 15 5 should be considered as reserved locations and the register contents should not b...

Page 1490: ...2 1 0 CUSTOM Y_MINOR R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 15 6 IDVER Register Field Descriptions Bit Field Type Reset Description 31 30 SCHEME R 1h Used to distinguish between the old scheme and current 29 28 Reserved R 0h 27 16 FUNC R 0h FUNC 15 11 R_RTL R 0h RTL version R maintained by IP design owner 10 8 X_MAJOR R 0h Major revision X...

Page 1491: ...arget can handle read write transaction as long as it is out of IDLE state 0x0 Force idle mode local target s idle state follows acknowledges the system s idle requests unconditionally i e regardless of the IP module s internal requirements Backup mode for debug only 0x1 No idle mode local target never enters idle state Backup mode for debug only 0x2 Smart idle mode local target s idle state event...

Page 1492: ...ite 1 to clear bit n value after reset Table 15 8 CLKCONFIG Register Field Descriptions Bit Field Type Reset Description 31 10 Reserved R 0h 9 ePWMCLKSTOP_REQ R W 0h This bit controls the clkstop_req input to the ePWM module 8 ePWMCLK_EN R W 1h This bit controls the clk_en input to the ePWM module 7 6 Reserved R 0h 5 eQEPCLKSTOP_REQ R W 0h This bit controls the clkstop_req input to the eQEP module...

Page 1493: ... bit n value after reset Table 15 9 CLKSTATUS Register Field Descriptions Bit Field Type Reset Description 31 10 Reserved R 0h 9 ePWM_CLKSTOP_ACK R 0h This bit is the clkstop_req_ack status output of the ePWM module 8 ePWM_CLK_EN_ACK R 0h This bit is the clk_en status output of the ePWM module 7 6 Reserved R 0h 5 eQEP_CLKSTOP_ACK R 0h This bit is the clkstop_req_ack status output of the eQEP modul...

Page 1494: ...ePWMx indicates any instance The ePWM modules are chained together via a clock synchronization scheme that allows them to operate as a single system when required Additionally this synchronization scheme can be extended to the capture peripheral modules eCAP The number of modules is device dependent and based on target application needs Modules can also operate stand alone Each ePWM module support...

Page 1495: ... EPWM2A EPWM2B EPWM1A EPWM1B EPWM1INT EPWM2INT EPWMxINT To eCAP1 TZ1 TZn to TZ1 TZn to Interrupt Controller www ti com Enhanced PWM ePWM Module Figure 15 6 Multiple ePWM Modules 1495 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsystem PWMSS Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1496: ...ignore any of the trip zone signals The trip zone signal can be configured as an asynchronous input through the GPIO peripheral See Section 15 1 2 to determine how many trip zone pins are available in the device Time base synchronization input EPWMxSYNCI and output EPWMxSYNCO signals The synchronization signals daisy chain the ePWM modules together Each module can be configured to either use or ig...

Page 1497: ...8 16 Counter compare CC CMPB active 16 CTR CMPB CMPB shadow 16 CMPAHR 8 EPWMA EPWMB Dead band DB PC chopper PWM zone TZ Trip CTR 0 EPWMxA EPWMxB EPWMxTZINT TZ1 to TZn HiRes PWM HRPWM CTR PRD CTR 0 CTR CMPB CTR CMPA CTR_Dir Event trigger and interrupt ET EPWMxINT CTR 0 www ti com Enhanced PWM ePWM Module Figure 15 8 ePWM Submodules and Critical Internal Signal Interconnects 1497 SPRUH73H October 20...

Page 1498: ...device is halted by an emulator Specify the source for the synchronization output of the ePWM module Synchronization input signal Time base counter equal to zero Time base counter equal to counter compare B CMPB No output synchronization signal generated Counter compare CC Specify the PWM duty cycle for output EPWMxA and or output EPWMxB Specify the time at which switching events occur on the EPWM...

Page 1499: ...figure finer time granularity control or edge positioning Code examples are provided in the remainder of this chapter that show how to implement various ePWM module configurations These examples use the constant definitions shown in Example 15 1 Example 15 1 Constant Definitions Used in the Code Examples TBCTL Time Base Control TBCNT MODE bits define TB_COUNT_UP 0x0 define TB_COUNT_DOWN 0x1 define...

Page 1500: ...ne CHP_DIV1 0x0 define CHP_DIV2 0x1 define CHP_DIV3 0x2 define CHP_DIV4 0x3 define CHP_DIV5 0x4 define CHP_DIV6 0x5 define CHP_DIV7 0x6 define CHP_DIV8 0x7 CHPDUTY bits define CHP1_8TH 0x0 define CHP2_8TH 0x1 define CHP3_8TH 0x2 define CHP4_8TH 0x3 define CHP5_8TH 0x4 define CHP6_8TH 0x5 define CHP7_8TH 0x6 TZSEL Trip zone Select CBCn and OSHTn bits define TZ_ENABLE 0x0 define TZ_DISABLE 0x1 TZCTL...

Page 1501: ...be possible that interrupt flags may be set due to spurious events due to the ePWM registers not being properly initialized The proper procedure for initializing the ePWM peripheral is 1 Disable global interrupts CPU INTM flag 2 Disable ePWM interrupts 3 Initialize peripheral registers 4 Clear any spurious ePWM flags 5 Enable ePWM interrupts 6 Enable global interrupts 15 2 2 3 Time Base TB Submodu...

Page 1502: ...the time base counter to count up count down or count up and down mode Generate the following events CTR PRD Time base counter equal to the specified period TBCNT TBPRD CTR 0 Time base counter equal to zero TBCNT 0000h Configure the rate of the time base clock a prescaled version of the CPU system clock SYSCLKOUT This allows the time base counter to increment decrement at a slower rate 1502 Pulse ...

Page 1503: ...ase Control Register 0h No TBSTS Time Base Status Register 2h No TBPHSHR HRPWM extension Phase Register 1 4h No TBPHS Time Base Phase Register 6h No TBCNT Time Base Counter Register 8h No TBPRD Time Base Period Register Ah Yes 1 This register is available only on ePWM instances that include the high resolution extension HRPWM On ePWM modules that do not include the HRPWM this location is reserved ...

Page 1504: ...when it is decreasing CTR_max Time base counter equal max value TBCNT FFFFh Generated event when the TBCNT value reaches its maximum value This signal is only used only as a status bit TBCLK Time base clock This is a prescaled version of the system clock SYSCLKOUT and is used by all submodules within the ePWM This clock determines the rate at which time base counter increments or decrements 15 2 2...

Page 1505: ...nt in time the shadow register s content is transferred to the active register This prevents corruption or spurious operation due to the register being asynchronously modified by software The memory address of the shadow period register is the same as the active register Which register is written to or read from is determined by the TBCTL PRDLD bit This bit enables and disables the TBPRD shadow re...

Page 1506: ...ePWM module has a synchronization input EPWMxSYNCI and a synchronization output EPWMxSYNCO The input synchronization for the first instance ePWM1 comes from an external pin The possible synchronization connections for the remaining ePWM modules is shown in Figure 15 12 Figure 15 12 Time Base Counter Synchronization Scheme 1 1506 Pulse Width Modulation Subsystem PWMSS SPRUH73H October 2011 Revised ...

Page 1507: ...he EPWMxSYNCO and be used to synchronize other ePWM modules In this way you can set up a master time base for example ePWM1 and downstream modules ePWM2 ePWMx may elect to run in synchronization with the master 15 2 2 3 4 Phase Locking the Time Base Clocks of Multiple ePWM Modules The TBCLKEN bit in the PWMSS_CTRL register in the Control Module can be used to globally synchronize the time base clo...

Page 1508: ...value TBPRD value Enhanced PWM ePWM Module www ti com Figure 15 13 Time Base Up Count Mode Waveforms 1508 Pulse Width Modulation Subsystem PWMSS SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1509: ... CTR 0 CNT_max CTR PRD www ti com Enhanced PWM ePWM Module Figure 15 14 Time Base Down Count Mode Waveforms Figure 15 15 Time Base Up Down Count Waveforms TBCTL PHSDIR 0 Count Down on Synchronization Event 1509 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsystem PWMSS Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1510: ...R PRD Enhanced PWM ePWM Module www ti com Figure 15 16 Time Base Up Down Count Waveforms TBCTL PHSDIR 1 Count Up on Synchronization Event 1510 Pulse Width Modulation Subsystem PWMSS SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1511: ...PB CTR 0 EPWMxINT EPWMxA EPWMxB TZ1 to TZn CTR CMPA Time Base TB CTR PRD CTR 0 CTR_Dir EPWMxSYNCI EPWMxSYNCO EPWMxTZINT PWM chopper PC Event Trigger and Interrupt ET Trip Zone TZ GPIO MUX Interrupt controller Interrupt controller www ti com Enhanced PWM ePWM Module 15 2 2 4 Counter Compare CC Submodule Figure 15 17 illustrates the counter compare submodule within the ePWM Figure 15 18 shows the ba...

Page 1512: ...er compare submodule Table 15 13 Counter Compare Submodule Registers Acronym Register Description Address Offset Shadowed CMPCTL Counter Compare Control Register Eh No CMPAHR HRPWM Counter Compare A Extension Register 1 10h Yes CMPA Counter Compare A Register 12h Yes CMPB Counter Compare B Register 14h Yes 1 This register is available only on ePWM modules with the high resolution extension HRPWM O...

Page 1513: ... shadow register respectively The behavior of the two load modes is described below Shadow Mode The shadow mode for the CMPA is enabled by clearing the CMPCTL SHDWAMODE bit and the shadow register for CMPB is enabled by clearing the CMPCTL SHDWBMODE bit Shadow mode is enabled by default for both CMPA and CMPB If the shadow register is enabled then the content of the shadow register is transferred ...

Page 1514: ...s in Up Count Mode NOTE An EPWMxSYNCI external synchronization event can cause a discontinuity in the TBCNT count sequence This can lead to a compare event being skipped This skipping is considered normal operation and must be taken into account Figure 15 20 Counter Compare Events in Down Count Mode 1514 Pulse Width Modulation Subsystem PWMSS SPRUH73H October 2011 Revised April 2013 Submit Documen...

Page 1515: ...nced PWM ePWM Module Figure 15 21 Counter Compare Events in Up Down Count Mode TBCTL PHSDIR 0 Count Down on Synchronization Event Figure 15 22 Counter Compare Events in Up Down Count Mode TBCTL PHSDIR 1 Count Up on Synchronization Event 1515 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsystem PWMSS Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporat...

Page 1516: ...set clear toggle based on the following events CTR PRD Time base counter equal to the period TBCNT TBPRD CTR 0 Time base counter equal to zero TBCNT 0000h CTR CMPA Time base counter equal to the counter compare A register TBCNT CMPA CTR CMPB Time base counter equal to the counter compare B register TBCNT CMPB Managing priority when these events occur concurrently Providing independent control of e...

Page 1517: ...ced event Asynchronous event initiated by software The software forced action is a useful asynchronous event This control is handled by registers AQSFRC and AQCSFRC The action qualifier submodule controls how the two outputs EPWMxA and EPWMxB behave when a particular event occurs The event inputs to the action qualifier submodule are further qualified by the counter direction up or down This allow...

Page 1518: ...his section For clarity the drawings in this chapter use a set of symbolic actions These symbols are summarized in Figure 15 25 Each symbol represents an action as a marker in time Some actions are fixed in time zero and period while the CMPA and CMPB actions are moveable and their time positions are programmed via the counter compare A and B registers respectively To turn off or disable an action...

Page 1519: ...on down count CAD 1 Counter equals CMPA on up count CBU 1 1 To maintain symmetry for up down count mode both up events CAU CBU and down events CAD CBD can be generated for TBPRD Otherwise up events can occur only when the counter is incrementing and down events can occur only when the counter is decrementing Table 15 18 shows the action qualifier priority for up count mode In this case the counter...

Page 1520: ... user specifies when the update will take place either when the time base counter reaches zero or when the time base counter reaches period There are some cases when the action based on the new value can be delayed by one period or the action based on the old value can take effect for an extra period Some PWM configurations avoid this situation These include but are not limited to the following Us...

Page 1521: ...s incrementing the CMPA match will pull the PWM output high Likewise when the counter is decrementing the compare match will pull the PWM signal low When CMPA 0 the PWM signal is low for the entire period giving the 0 duty waveform When CMPA TBPRD the PWM signal is high achieving 100 duty When using this configuration in practice if you load CMPA CMPB on zero then use CMPA CMPB values greater than...

Page 1522: ...2 contains initialization and runtime register configurations for the waveforms in Figure 15 27 Figure 15 27 Up Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Active High 1 PWM period TBPRD 1 TTBCLK 2 Duty modulation for EPWMxA is set by CMPA and is active high that is high time duty proportional to CMPA 3 Duty modulation for EPWMxB is set by CMPB and is active hi...

Page 1523: ...Eh Compare A 350 TBCLK counts CMPB CMPB 200 C8h Compare B 200 TBCLK counts CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA ZRO AQ_SET CAU AQ_CLEAR AQCTLB ZRO AQ_SET CBU AQ_CLEAR Table 15 22 EPWMx Run Time Changes for Figure 15 27 Register Bit Value Comments CMPA CMPA Duty1A Adjust duty for output EPWM1A CMPB CMPB Duty1B ...

Page 1524: ... and is active low that is the low time duty is proportional to CMPA 3 Duty modulation for EPWMxB is set by CMPB and is active low that is the low time duty is proportional to CMPB 4 The Do Nothing actions X are shown for completeness here but will not be shown on subsequent diagrams 5 Actions at zero and period although appearing to occur concurrently are actually separated by one TBCLK period TB...

Page 1525: ...Eh Compare A 350 TBCLK counts CMPB CMPB 200 C8h Compare B 200 TBCLK counts CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA PRD AQ_CLEAR CAU AQ_SET AQCTLB PRD AQ_CLEAR CBU AQ_SET Table 15 24 EPWMx Run Time Changes for Figure 15 28 Register Bit Value Comments CMPA CMPA Duty1A Adjust duty for output EPWM1A CMPB CMPB Duty1B ...

Page 1526: ... Up Count Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA 1 PWM frequency 1 TBPRD 1 TTBCLK 2 Pulse can be placed anywhere within the PWM cycle 0000h TBPRD 3 High time duty proportional to CMPB CMPA 4 EPWMxB can be used to generate a 50 duty square wave with frequency 1 2 TBPRD 1 TBCLK 1526Pulse Width Modulation Subsystem PWMSS SPRUH73H October 2011 Revised April 2013 Subm...

Page 1527: ...1 CMPA CMPA 200 C8h Compare A 200 TBCLK counts CMPB CMPB 400 190h Compare B 400 TBCLK counts CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET CBU AQ_CLEAR AQCTLB ZRO AQ_TOGGLE Table 15 26 EPWMx Run Time Changes for Figure 15 29 Register Bit Value Comments CMPA CMPA EdgePosA Adjust duty for output EPWM1A CMPB CM...

Page 1528: ...pendent Modulation on EPWMxA and EPWMxB Active Low 1 PWM period 2 x TBPRD TTBCLK 2 Duty modulation for EPWMxA is set by CMPA and is active low that is the low time duty is proportional to CMPA 3 Duty modulation for EPWMxB is set by CMPB and is active low that is the low time duty is proportional to CMPB 4 Outputs EPWMxA and EPWMxB can drive independent power switches 1528Pulse Width Modulation Sub...

Page 1529: ...90h Compare A 400 TBCLK counts CMPB CMPB 500 1F4h Compare B 500 TBCLK counts CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET CAD AQ_CLEAR AQCTLB CBU AQ_SET CBD AQ_CLEAR Table 15 28 EPWMx Run Time Changes for Figure 15 30 Register Bit Value Comments CMPA CMPA Duty1A Adjust duty for output EPWM1A CMPB CMPB Duty1...

Page 1530: ...TTBCLK 2 Duty modulation for EPWMxA is set by CMPA and is active low i e low time duty proportional to CMPA 3 Duty modulation for EPWMxB is set by CMPB and is active high i e high time duty proportional to CMPB 4 Outputs EPWMx can drive upper lower complementary power switches 5 Dead band CMPB CMPA fully programmable edge placement by software Note the dead band module is also available if the mor...

Page 1531: ...5Eh Compare A 350 TBCLK counts CMPB CMPB 400 190h Compare B 400 TBCLK counts CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET CAD AQ_CLEAR AQCTLB CBU AQ_CLEAR CBD AQ_SET Table 15 30 EPWMx Run Time Changes for Figure 15 31 Register Bit Value Comments CMPA CMPA Duty1A Adjust duty for output EPWM1A CMPB CMPB Duty1...

Page 1532: ...ng edge and falling edge can be asymmetrically positioned within a PWM cycle This allows for pulse placement techniques 3 Duty modulation for EPWMxA is set by CMPA and CMPB 4 Low time duty for EPWMxA is proportional to CMPA CMPB 5 To change this example to active high CMPA and CMPB actions need to be inverted i e Set Clear and Clear Set 6 Duty modulation for EPWMxB is fixed at 50 utilizes spare ac...

Page 1533: ...MPA CMPA 250 FAh Compare A 250 TBCLK counts CMPB CMPB 450 1C2h Compare B 450 TBCLK counts CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET CBD AQ_CLEAR AQCTLB ZRO AQ_CLEAR PRD AQ_SET Table 15 32 EPWMx Run Time Changes for Figure 15 32 Register Bit Value Comments CMPA CMPA EdgePosA Adjust duty for output EPWM1A ...

Page 1534: ...hen the dead band generator submodule should be used The key functions of the dead band generator submodule are Generating appropriate signal pairs EPWMxA and EPWMxB with dead band relationship from a single EPWMxA input Programming signal pairs for Active high AH Active low AL Active high complementary AHC Active low complementary ALC Adding programmable delay to rising edges RED Adding programma...

Page 1535: ...n is the source for both falling edge and rising edge delay This is the default mode EPWMxA In is the source for falling edge delay EPWMxB In is the source for rising edge delay EPWMxA In is the source for rising edge delay EPWMxB In is the source for falling edge delay EPWMxB In is the source for both falling edge and rising edge delay Output Mode Control The output mode is configured by way of t...

Page 1536: ...bmodule to generate the signal as shown for EPWMxA Mode 6 Bypass rising edge delay and Mode 7 Bypass falling edge delay Finally the last two entries in Table 15 34 show combinations where either the falling edge delay FED or rising edge delay RED blocks are bypassed Table 15 34 Classical Dead Band Operating Modes DBCTL POLSEL DBCTL OUT_MODE Mode Mode Description 1 S3 S2 S1 S0 1 EPWMxA and EPWMxB P...

Page 1537: ...ing edge RED and falling edge FED delays The amount of delay is programmed using the DBRED and DBFED registers These are 10 bit registers and their value represents the number of time base clock TBCLK periods a signal edge is delayed by For example the formula to calculate falling edge delay and rising edge delay are FED DBFED TTBCLK RED DBRED TTBCLK Where TTBCLK is the period of TBCLK the prescal...

Page 1538: ...bility is important if you need pulse transformer based gate drivers to control the power switching elements Figure 15 36 PWM Chopper Submodule 15 2 2 7 1 Purpose of the PWM Chopper Submodule The key functions of the PWM chopper submodule are Programmable chopping carrier frequency Programmable pulse width of first pulse Programmable duty cycle of second and subsequent pulses Can be fully bypassed...

Page 1539: ...SYSCLKOUT Its frequency and duty cycle are controlled via the CHPFREQ and CHPDUTY bits in the PCCTL register The one shot block is a feature that provides a high energy first pulse to ensure hard and fast power switch turn on while the subsequent pulses sustain pulses ensuring the power switch remains on The one shot width is programmed via the OSHTWTH bits The PWM chopper submodule can be fully d...

Page 1540: ...ction Only 15 2 2 7 4 1 One Shot Pulse The width of the first pulse can be programmed to any of 16 possible pulse width values The width or period of the first pulse is given by T1stpulse TSYSCLKOUT 8 OSHTWTH Where TSYSCLKOUT is the period of the system clock SYSCLKOUT and OSHTWTH is the four control bits value from 1 to 16 Figure 15 39 shows the first and subsequent sustaining pulses Figure 15 39...

Page 1541: ...rogrammable These sustaining pulses ensure the correct drive strength and polarity is maintained on the power switch gate during the on period and hence a programmable duty cycle allows a design to be tuned or optimized via software control Figure 15 40 shows the duty cycle control that is possible by programming the CHPDUTY bits One of seven possible duty ratios can be selected ranging from 12 5 ...

Page 1542: ...e number of trip zone pins available for the device Figure 15 41 Trip Zone Submodule 15 2 2 8 1 Purpose of the Trip Zone Submodule The key functions of the trip zone submodule are Trip inputs TZ1 to TZn can be flexibly mapped to any ePWM module Upon a fault condition outputs EPWMxA and EPWMxB can be forced to one of the following High Low High impedance No action taken Support for one shot trip OS...

Page 1543: ...configuration is determined by the TZSEL CBCn and TZSEL OSHTn bits where n corresponds to the trip pin respectively Cycle by Cycle CBC When a cycle by cycle trip event occurs the action specified in the TZCTL register is carried out immediately on the EPWMxA and or EPWMxB output Table 15 37 lists the possible actions In addition the cycle by cycle trip event flag TZFLG CBC is set and a EPWMxTZINT ...

Page 1544: ...ZB 1 EPWM2B will be forced high on a trip event Scenario B A cycle by cycle event on TZ5 pulls both EPWM1A EPWM1B low A one shot event on TZ1 or TZ6 puts EPWM2A into a high impedance state Configure the ePWM1 registers as follows TZSEL CBC5 1 enables TZ5 as a one shot event source for ePWM1 TZCTL TZA 2 EPWM1A will be forced low on a trip event TZCTL TZB 2 EPWM1B will be forced low on a trip event ...

Page 1545: ...CBC1 to CBCn TZCLR OST TZFRC OSHT Sync Trip logic Trip Trip CBC trip event OSHT trip event EPWMxA EPWMxB EPWMxA EPWMxB TZCTL TZB TZCTL TZA Async Trip Set Clear TZFLG CBC TZCLR CBC Set Clear TZFLG OST TZn TZ1 TZSEL OSHT1 to OSHTn TZn www ti com Enhanced PWM ePWM Module Figure 15 42 Trip Zone Submodule Mode Control Logic Figure 15 43 Trip Zone Submodule Interrupt Logic 1545 SPRUH73H October 2011 Rev...

Page 1546: ...uts generated by the time base and counter compare submodules Uses the time base direction information for up down event qualification Uses prescaling logic to issue interrupt requests at Every event Every second event Every third event Provides full visibility of event generation via event counters and flags 15 2 2 9 2 Controlling and Monitoring the Event Trigger Submodule The key registers used ...

Page 1547: ...e interrupt request line connected to the interrupt controller as shown in Figure 15 45 Figure 15 45 Event Trigger Submodule Inter Connectivity to Interrupt Controller The event trigger submodule monitors various event conditions the left side inputs to event trigger submodule shown in Figure 15 46 and can be configured to prescale these events before issuing an Interrupt request The event trigger...

Page 1548: ...t counter ETPS INTCNT register bits That is when the specified event occurs the ETPS INTCNT bits are incremented until they reach the value specified by ETPS INTPRD When ETPS INTCNT ETPS INTPRD the counter stops counting and its output is set The counter is only cleared when an interrupt is sent to the interrupt controller When ETPS INTCNT reaches ETPS INTPRD one of the following behaviors will oc...

Page 1549: ...FLG INT ETSEL INTSEL 000 001 010 011 100 101 111 101 0 0 CTRU CMPA CTRD CMPA CTRU CMPB CTRD CMPB CTR 0 CTR PRD www ti com Enhanced PWM ePWM Module Figure 15 47 Event Trigger Interrupt Generator 1549 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsystem PWMSS Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1550: ...WM zone TZ Trip CTR 0 EPWMxA EPWMxB EPWMxTZINT TZ1 to TZn HiRes PWM HRPWM CTR PRD CTR 0 CTR CMPB CTR CMPA CTR_Dir Event trigger and interrupt ET EPWMxINT CTR 0 Enhanced PWM ePWM Module www ti com 15 2 2 10 High Resolution PWM HRPWM Submodule Figure 15 48 shows the high resolution PWM HRPWM submodule in the ePWM system Some devices include the high resolution PWM submodule see Section 15 1 2 to det...

Page 1551: ...entionally Generated PWM If the required PWM operating frequency does not offer sufficient resolution in PWM mode you may want to consider HRPWM As an example of improved performance offered by HRPWM Table 15 39 shows resolution in bits for various PWM frequencies Table 15 39 values assume a MEP step size of 180 ps See your device specific data manual for typical and maximum performance specificat...

Page 1552: ...ng MEP A For MEP range and rounding adjustment To generate an HRPWM waveform configure the TBM CCM and AQM registers as you would to generate a conventional PWM of a given frequency and polarity The HRPWM works together with the TBM CCM and AQM registers to extend edge resolution and should be configured accordingly Although many programming combinations are possible only a few are needed and prac...

Page 1553: ...tion has no effect 15 2 2 10 5 Operational Highlights for the High Resolution PWM Submodule The MEP logic is capable of placing an edge in one of 255 8 bits discrete time steps each of which has a time resolution on the order of 150 ps The MEP works with the TBM and CCM registers to be certain that time steps are optimally applied and that edge placement accuracy is maintained over a wide range of...

Page 1554: ...h closer to the desired point of 324 ns Table 15 42 shows that in addition to the CMPA value 22 steps of the MEP CMPAHR register will position the edge at 323 96 ns resulting in almost zero error In this example it is assumed that the MEP has a step resolution of 180 ns Figure 15 51 Required PWM Waveform for a Requested Duty 40 5 Table 15 42 CMPA vs Duty left and CMPA CMPAHR vs Duty right CMPA DUT...

Page 1555: ...aling procedure is required Assumptions for this example System clock SYSCLKOUT 10 ns 100 MHz PWM frequency 1 25 MHz 1 800 ns Required PWM duty cycle PWMDuty 0 405 40 5 PWM period in terms of coarse steps 80 PWMperiod 800 ns 10 ns Number of MEP steps per coarse step at 55 180 ps 10 ns 180 ps MEP_SF Value to keep CMPAHR within the range of 1 255 and fractional rounding constant default value 180h S...

Page 1556: ...operational down to 0 duty In most applications this should not be an issue as the controller regulation point is usually not designed to be close to 0 duty cycle Figure 15 52 Low Duty Cycle Range Limitation Example When PWM Frequency 1 MHz If the application demands HRPWM operation in the low percent duty cycle region then the HRPWM can be configured to operate in count down mode with the rising ...

Page 1557: ...peration of a single module To facilitate the understanding of multiple modules working together in a system the ePWM module described in reference is represented by the more simplified block diagram shown in Figure 15 54 This simplified ePWM block shows only the key resources needed to explain how a multiswitch power topology is controlled with multiple ePWM modules working together Figure 15 54 ...

Page 1558: ... No sync to other modules SyncOut connected to X disabled Options for SyncOut Sync flow through SyncOut connected to SyncIn Master mode provides a sync at PWM boundaries SyncOut connected to CTR PRD Master mode provides a sync at any programmable point in time SyncOut connected to CTR CMPB Module is in standalone mode and provides No sync to other modules SyncOut connected to X disabled For each c...

Page 1559: ... as a master can control two buck stages with the same PWM frequency If independent frequency control is required for each buck converter then one ePWM module must be allocated for each converter stage Figure 15 56 shows four buck stages each running at independent frequencies In this case all four ePWM modules are configured as Masters and no synchronization is used Figure 15 57 shows the wavefor...

Page 1560: ...ggers an interrupt I P I P I P I Enhanced PWM ePWM Module www ti com Figure 15 57 Buck Waveforms for Figure 15 56 Note Only three bucks shown here 1560Pulse Width Modulation Subsystem PWMSS SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1561: ...CTRMODE TB_UP PHSEN TB_DISABLE Phase loading disabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_DISABLE CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA PRD AQ_CLEAR CAU AQ_SET Table 15 45 EPWM3 Initialization for Figure 15 57 Register Bit Value Comments TBPRD TBPRD 800 320h Period 801 TBCLK counts TBPHS TBPHS 0 Clear Phase Regist...

Page 1562: ...just duty for output EPWM2A EPwm3Regs CMPA half CMPA 500 adjust duty for output EPWM3A 15 2 3 4 Controlling Multiple Buck Converters With Same Frequencies If synchronization is a requirement ePWM module 2 can be configured as a slave and can operate at integer multiple N frequencies of module 1 The sync signal from master to slave ensures these modules remain locked Figure 15 58 shows such a confi...

Page 1563: ...B CB CB CB CA CA CA CA CB CB CB CB www ti com Enhanced PWM ePWM Module Figure 15 59 Buck Waveforms for Figure 15 58 Note FPWM2 FPWM1 1563 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsystem PWMSS Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1564: ...PHS TBPHS 0 Clear Phase Register to 0 TBCTL CTRMODE TB_UPDOWN PHSEN TB_ENABLE Phase loading enabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_IN Sync flow through CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET Set actions for EPWM2A CAD AQ_CLEAR AQCTLB CBU AQ_SET Set actions for EPWM2B CBD AQ_CLEAR Example 15 4 Code S...

Page 1565: ...can be extended to multiple stages Figure 15 60 shows control of two synchronized Half H bridge stages where stage 2 can operate at integer multiple N frequencies of stage 1 Figure 15 61 shows the waveforms generated by the configuration shown in Figure 15 60 Module 2 slave is configured for Sync flow through if required this configuration allows for a third Half H bridge to be controlled by PWM m...

Page 1566: ...enter Z A CB CA A CB CA Z A CB CA Z A CB Z CA A CB Z CA Enhanced PWM ePWM Module www ti com Figure 15 61 Half H Bridge Waveforms for Figure 15 60 Note Here FPWM2 FPWM1 1566Pulse Width Modulation Subsystem PWMSS SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1567: ...PHS TBPHS 0 Clear Phase Register to 0 TBCTL CTRMODE TB_UPDOWN PHSEN TB_ENABLE Phase loading enabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_IN Sync flow through CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA ZRO AQ_SET Set actions for EPWM2A CAU AQ_CLEAR AQCTLB ZRO AQ_CLEAR Set actions for EPWM2B CAD AQ_SET Example 15 5 Code S...

Page 1568: ... Inverter case In such a case six switching elements can be controlled using three PWM modules one for each leg of the inverter Each leg must switch at the same frequency and all legs must be synchronized A master two slaves configuration can easily address this requirement Figure 15 62 shows how six PWM modules can control two independent 3 phase Inverters each running a motor As in the cases sho...

Page 1569: ... CA Z I A P CA CA CA CA CA CA CA CA CA CA www ti com Enhanced PWM ePWM Module Figure 15 63 3 Phase Inverter Waveforms for Figure 15 62 Only One Inverter Shown 1569 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsystem PWMSS Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1570: ...DBFED 50 FED 50 TBCLKs DBRED 50 RED 50 TBCLKs Table 15 51 EPWM2 Initialization for Figure 15 62 Register Bit Value Comments TBPRD TBPRD 800 320h Period 1600 TBCLK counts TBPHS TBPHS 0 Clear Phase Register to 0 TBCTL CTRMODE TB_UPDOWN PHSEN TB_ENABLE Slave module PRDLD TB_SHADOW SYNCOSEL TB_SYNC_IN Sync flow through CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 ...

Page 1571: ...ET Set actions for EPWM3A CAD AQ_CLEAR DBCTL MODE DB_FULL_ENABLE Enable Dead band module POLSEL DB_ACTV_HIC Active Hi complementary DBFED DBFED 50 FED 50 TBCLKs DBRED 50 RED 50 TBCLKs Example 15 6 Code Snippet for Configuration in Figure 15 62 Run Time Note Example execution of one run time instance EPwm1Regs CMPA half CMPA 500 adjust duty for output EPWM1A EPwm2Regs CMPA half CMPA 600 adjust duty...

Page 1572: ...e section a PWM module can be configured to allow a SyncIn pulse to cause the TBPHS register to be loaded into the TBCNT register To illustrate this concept Figure 15 64 shows a master and slave module with a phase relationship of 120 that is the slave leads the master Figure 15 64 Configuring Two PWM Modules for Phase Control Figure 15 65 shows the associated timing waveforms for this configurati...

Page 1573: ... 3 and 2 3 of the period value respectively For example if the period register is loaded with a value of 600 counts then TBPHS slave 2 200 and TBPHS slave 3 400 Both slave modules are synchronized to the master 1 module This concept can be extended to four or more phases by setting the TBPHS values appropriately The following formula gives the TBPHS values for N phases TBPHS N M TBPRD N M 1 Where ...

Page 1574: ...B SyncOut X EPWM3B Phase reg Slave En SyncIn EPWM3A 1 2 3 VIN EPWM2B EPWM2A EPWM3A EPWM3B VOUT Φ 0 Φ 120 Φ 120 Φ 240 Enhanced PWM ePWM Module www ti com Figure 15 66 Control of a 3 Phase Interleaved DC DC Converter 1574 Pulse Width Modulation Subsystem PWMSS SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1575: ... Z I Z I Z I Z I A P CA CA A P CA CA A P CA CA www ti com Enhanced PWM ePWM Module Figure 15 67 3 Phase Interleaved DC DC Converter Waveforms for Figure 15 66 1575 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsystem PWMSS Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1576: ...TBCLKs DBRED 20 RED 20 TBCLKs Table 15 54 EPWM2 Initialization for Figure 15 66 Register Bit Value Comments TBPRD TBPRD 450 1C2h Period 900 TBCLK counts TBPHS TBPHS 300 Phase 300 900 360 120 TBCTL CTRMODE TB_UPDOWN PHSEN TB_ENABLE Slave module PRDLD TB_SHADOW SYNCOSEL TB_SYNC_IN Sync flow through PHSDIR TB_DOWN Count DOWN on sync CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO...

Page 1577: ...CTLA CAU AQ_SET Set actions for EPWM3A CAD AQ_CLEAR DBCTL MODE DB_FULL_ENABLE Enable Dead band module POLSEL DB_ACTV_HIC Active Hi complementary DBFED DBFED 20 FED 20 TBCLKs DBRED 20 RED 20 TBCLKs Example 15 7 Code Snippet for Configuration in Figure 15 66 Run Time Note Example execution of one run time instance EPwm1Regs CMPA half CMPA 285 adjust duty for output EPWM1A EPwm2Regs CMPA half CMPA 28...

Page 1578: ...hed full bridge Here the controlled parameter is not duty cycle this is kept constant at approximately 50 percent instead it is the phase relationship between legs Such a system can be implemented by allocating the resources of two PWM modules to control a single power stage which in turn requires control of four switching elements Figure 15 69 shows a master slave module combination synchronized ...

Page 1579: ...sition ZVS transition Z CA Z I Z I Z I Z CB A CA CB A Z Z CB A CA Z Z CB A CA www ti com Enhanced PWM ePWM Module Figure 15 69 ZVS Full H Bridge Waveforms 1579 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsystem PWMSS Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1580: ...BCTL CTRMODE TB_UP PHSEN TB_ENABLE Slave module PRDLD TB_SHADOW SYNCOSEL TB_SYNC_IN Sync flow through CMPA CMPA 600 258h Set 50 duty for EPWM2A CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA ZRO AQ_SET Set actions for EPWM2A CAU AQ_CLEAR DBCTL MODE DB_FULL_ENABLE Enable Dead band module POLSEL DB_ACTV_HIC Active Hi comp...

Page 1581: ...r Control Register DBRED 20h 1 No Dead Band Generator Rising Edge Delay Count Register DBFED 22h 1 No Dead Band Generator Falling Edge Delay Count Register Trip Zone Submodule Registers Section 15 2 4 5 TZSEL 24h 1 No Trip Zone Select Register TZCTL 28h 1 No Trip Zone Control Register TZEINT 2Ah 1 No Trip Zone Enable Interrupt Register TZFLG 2Ch 1 No Trip Zone Flag Register TZCLR 2Eh 1 No Trip Zon...

Page 1582: ...SWFSYNC SYNCOSEL PRDLD PHSEN CTRMODE R W 1 R W 0 R W 0 R W 0 R W 0 R W 3h LEGEND R W Read Write R Read only n value after reset Table 15 60 Time Base Control Register TBCTL Field Descriptions Bit Field Value Description 15 14 FREE SOFT 0 3h Emulation Mode Bits These bits select the behavior of the ePWM time base counter during emulation events 0 Stop after the next time base counter increment or d...

Page 1583: ...NCI is selected by SYNCOSEL 00 5 4 SYNCOSEL 0 3h Synchronization Output Select These bits select the source of the EPWMxSYNCO signal 0 EPWMxSYNC 1h CTR 0 Time base counter equal to zero TBCNT 0000h 2h CTR CMPB Time base counter equal to counter compare B TBCNT CMPB 3h Disable EPWMxSYNCO signal 3 PRDLD Active Period Register Load From Shadow Register Select 0 The period register TBPRD is loaded fro...

Page 1584: ...er Max Latched Status Bit 0 Reading a 0 indicates the time base counter never reached its maximum value Writing a 0 will have no effect 1 Reading a 1 on this bit indicates that the time base counter reached the max value 0xFFFF Writing a 1 to this bit will clear the latched event 1 SYNCI Input Synchronization Latched Status Bit 0 Writing a 0 will have no effect Reading a 0 indicates no external sy...

Page 1585: ... a software forced synchronization 15 2 4 1 4 Time Base Counter Register TBCNT The time base counter register TBCNT is shown in Figure 15 73 and described in Table 15 63 Figure 15 73 Time Base Counter Register TBCNT 15 0 TBCNT R W 0 LEGEND R W Read Write n value after reset Table 15 63 Time Base Counter Register TBCNT Field Descriptions Bits Name Value Description 15 0 TBCNT 0 FFFFh Reading these ...

Page 1586: ... directly to the active register that is the register actively controlling the hardware The active and shadow registers share the same memory map address 15 2 4 2 Counter Compare Submodule Registers Table 15 65 lists the memory mapped registers for the counter compare submodule All other register offset addresses not listed in Table 15 65 should be considered as reserved locations and the register...

Page 1587: ...rved 6 SHDWBMODE Counter compare B CMPB Register Operating Mode 0 Shadow mode Operates as a double buffer All writes via the CPU access the shadow register 1 Immediate mode Only the active compare B register is used All writes and reads directly access the active register for immediate compare action 5 Reserved Reserved 4 SHDWAMODE Counter compare A CMPA Register Operating Mode 0 Shadow mode Opera...

Page 1588: ...TLA and AQCTLB registers include Do nothing the event is ignored Clear Pull the EPWMxA and or EPWMxB signal low Set Pull the EPWMxA and or EPWMxB signal high Toggle the EPWMxA and or EPWMxB signal Shadowing of this register is enabled and disabled by the CMPCTL SHDWAMODE bit By default this register is shadowed If CMPCTL SHDWAMODE 0 then the shadow is enabled and any write or read will automatical...

Page 1589: ... the shadow is enabled and any write or read will automatically go to the shadow register In this case the CMPCTL LOADBMODE bit field determines which event will load the active register from the shadow register Before a write the CMPCTL SHDWBFULL bit can be read to determine if the shadow register is currently full If CMPCTL SHDWBMODE 1 then the shadow register is disabled and any write or read w...

Page 1590: ...e CMPA register and the counter is decrementing 0 Do nothing action disabled 1h Clear force EPWMxA output low 2h Set force EPWMxA output high 3h Toggle EPWMxA output low output signal will be forced high and a high signal will be forced low 5 4 CAU 0 3h Action when the counter equals the active CMPA register and the counter is incrementing 0 Do nothing action disabled 1h Clear force EPWMxA output ...

Page 1591: ...A register and the counter is decrementing 0 Do nothing action disabled 1h Clear force EPWMxB output low 2h Set force EPWMxB output high 3h Toggle EPWMxB output low output signal will be forced high and a high signal will be forced low 5 4 CAU 0 3h Action when the counter equals the active CMPA register and the counter is incrementing 0 Do nothing action disabled 1h Clear force EPWMxB output low 2...

Page 1592: ...ng a 0 zero has no effect Always reads back a 0 This bit is auto cleared once a write to this register is complete that is a forced event is initiated This is a one shot forced event It can be overridden by another subsequent event on output B 1 Initiates a single s w forced event 4 3 ACTSFB 0 3h Action when One Time Software Force B Is invoked 0 Does nothing action disabled 1h Clear low 2h Set hi...

Page 1593: ... no effect 1 0 CSFA 0 3h Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register 0 Forcing disabled that is has no effect 1h Forces a continuous low on output A 2h Forces a continuous high on output A 3h Software forcing is disabl...

Page 1594: ...espond to classical upper lower switch control as found in one leg of a digital motor control inverter These assume that DBCTL OUT_MODE 1 1 and DBCTL IN_MODE 0 0 Other enhanced modes are also possible but not regarded as typical usage modes 0 Active high AH mode Neither EPWMxA nor EPWMxB is inverted default 1h Active low complementary ALC mode EPWMxA is inverted 2h Active high complementary AHC EP...

Page 1595: ...g Edge Delay Count 10 bit counter 15 2 4 4 3 Dead Band Generator Falling Edge Delay Register DBFED The dead band generator falling edge delay register DBFED is shown in Figure 15 84 and described in Table 15 77 Figure 15 84 Dead Band Generator Falling Edge Delay Register DBFED 15 10 9 0 Reserved DEL R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 15 77 Dead Band Generator Fal...

Page 1596: ...e your device specific data manual Table 15 79 Trip Zone Submodule Select Register TZSEL Field Descriptions Bits Name Value Description 15 8 OSHTn Trip zone n TZn select One Shot OSHT trip zone enable disable When any of the enabled pins go low a one shot trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register Section 15 2 4 5 2 is taken on the EPWMxA ...

Page 1597: ... 0 High impedance EPWMxA High impedance state 1h Force EPWMxA to a high state 2h Force EPWMxA to a low state 3h Do nothing no action is taken on EPWMxA 15 2 4 5 3 Trip Zone Enable Interrupt Register TZEINT The trip zone enable interrupt register TZEINT is shown in Figure 15 87 and described in Table 15 81 Figure 15 87 Trip Zone Enable Interrupt Register TZEINT 15 3 2 1 0 Reserved OST CBC Rsvd R 0 ...

Page 1598: ... If the cycle by cycle trip event is still present when the CBC bit is cleared then CBC will be immediately set again The specified condition on the pins is automatically cleared when the ePWM time base counter reaches zero TBCNT 0000h if the trip condition is no longer present The condition on the pins is only cleared when the TBCNT 0000h no matter where in the cycle the CBC flag is cleared This ...

Page 1599: ...cleared If the TZFLG INT bit is cleared and any of the other flag bits are set then another interrupt pulse will be generated Clearing all flag bits will prevent further interrupts 15 2 4 5 6 Trip Zone Force Register TZFRC The trip zone force register TZFRC is shown in Figure 15 90 and described in Table 15 84 Figure 15 90 Trip Zone Force Register TZFRC 15 3 2 1 0 Reserved OST CBC Rsvd R 0 R W 0 R...

Page 1600: ...escribed in Table 15 86 Figure 15 91 Event Trigger Selection Register ETSEL 15 4 3 2 0 Reserved INTEN INTSEL R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 15 86 Event Trigger Selection Register ETSEL Field Descriptions Bits Name Value Description 15 4 Reserved 0 Reserved 3 INTEN Enable ePWM Interrupt EPWMx_INT Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_I...

Page 1601: ...L INTSEL events need to occur before an interrupt is generated To be generated the interrupt must be enabled ETSEL INT 1 If the interrupt status flag is set from a previous interrupt ETFLG INT 1 then no interrupt will be generated until the flag is cleared via the ETCLR INT bit This allows for one interrupt to be pending while another is still being serviced Once the interrupt is generated the ETP...

Page 1602: ...it will not be generated until after the ETFLG INT bit is cleared Refer to Figure 15 47 15 2 4 6 4 Event Trigger Clear Register ETCLR The event trigger clear register ETCLR is shown in Figure 15 94 and described in Table 15 89 Figure 15 94 Event Trigger Clear Register ETCLR 15 1 0 Reserved INT R 0 R 0 LEGEND R Read only n value after reset Table 15 89 Event Trigger Clear Register ETCLR Field Descr...

Page 1603: ...Field Descriptions Bits Name Value Description 15 1 Reserved 0 Reserved 0 INT INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set regardless 0 Writing 0 to this bit will be ignored Always reads back a 0 1 Generates an interrupt on EPWMxINT and set the INT flag bit This bit is used for test purposes 1603 SPRUH73H October 2011...

Page 1604: ... OSHTWTH 0 Fh One Shot Pulse Width 0 1 SYSCLKOUT 8 wide 1h 2 SYSCLKOUT 8 wide 2h 3 SYSCLKOUT 8 wide 3h Fh 4 SYSCLKOUT 8 wide to 16 SYSCLKOUT 8 wide 0 CHPEN PWM chopping Enable 0 Disable bypass PWM chopping function 1 Enable chopping function 15 2 4 8 High Resolution PWM Submodule Registers Table 15 92 lists the memory mapped registers for the high resolution PWM submodule All other register offset...

Page 1605: ... A High Resolution Register CMPAHR The counter compare A high resolution register CMPAHR is shown in Figure 15 98 and described in Table 15 94 Figure 15 98 Counter Compare A High Resolution Register CMPAHR 15 8 7 0 CMPAHR Reserved R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 15 94 Counter Compare A High Resolution Register CMPAHR Field Descriptions Bit Field Value Descri...

Page 1606: ... the CMPCTL LOADMODE bits in the EPWM module as follows 0 CNT_zero pulse 1h PRD_eq pulse 2h CNT_zero or PRD_eq should not use with HRPWM 3h No loads should not use with HRPWM 2 DELBUSSE Delay Bus Select Bit Selects which bus is used to select the delay for the PWM pulse L 0 Select CMPAHR 8 bus from compare module of EPWM default on reset 1 Select TBPHSHR 8 bus from time base module 1 0 DELMODE 0 3...

Page 1607: ... module includes the following features 32 bit time base counter 4 event time stamp registers each 32 bits Edge polarity selection for up to four sequenced time stamp capture events Interrupt on either of the four events Single shot capture of up to four event time stamps Continuous mode capture of time stamps in a four deep circular buffer Absolute time stamp capture Difference Delta mode time st...

Page 1608: ... pin rising falling edges Independent edge polarity rising falling edge selection for all 4 events Input capture signal prescaling from 2 62 One shot compare register 2 bits to freeze captures after 1 to 4 time stamp events Control for continuous time stamp captures using a 4 deep circular buffer CAP1 CAP4 scheme Interrupt capabilities on any of the 4 capture events Multiple identical eCAP modules...

Page 1609: ... pulse width modulation PWM waveforms The CAP1 and CAP2 registers become the active period and compare registers respectively while CAP3 and CAP4 registers become the period and capture shadow registers respectively Figure 15 101 is a high level view of both the capture and auxiliary pulse width modulator APWM modes of operation Figure 15 101 Capture and APWM Modes of Operation 1 A single pin is s...

Page 1610: ...RD 0 31 CMP 0 31 CMPEQ PRDEQ CTR_OVF OVF APWM mode Delta mode SYNC 4 Capture events CEVT 1 4 APRD shadow 32 32 MODE SELECT ECCTL2 SYNCI_EN SYNCOSEL SWSYNC ECCTL2 CAP APWM Edge Polarity Select ECCTL1 CAPxPOL ECCTL1 EVTPS ECCTL1 CAPLDEN CTRRSTx ECCTL2 RE ARM CONT ONESHT STOP_WRAP Registers ECEINT ECFLG ECCLR ECFRC Enhanced Capture eCAP Module www ti com 15 3 2 2 Capture Mode Description Figure 15 10...

Page 1611: ...r This is useful when very high frequency signals are used as inputs Figure 15 103 shows a functional diagram and Figure 15 104 shows the operation of the prescale function Figure 15 103 Event Prescale Control 1 When a prescale value of 1 is chosen ECCTL1 13 9 0000 the input capture signal by passes the prescale logic completely Figure 15 104 Prescale Function Waveforms 1611 SPRUH73H October 2011 ...

Page 1612: ...nhibits further loads of the CAP1 CAP4 registers This occurs during one shot operation The continuous one shot block Figure 15 105 controls the start stop and reset zero functions of the Mod4 counter via a mono shot type of action that can be triggered by the stop value comparator and re armed via software control Once armed the eCAP module waits for 1 4 defined by stop value capture events before...

Page 1613: ...d to achieve synchronization with other counters via a hardware and software forced sync This is useful in APWM mode when a phase offset between modules is needed On any of the four event loads an option to reset the 32 bit counter is given This is useful for time difference capture The 32 bit counter value is captured first then it is reset to 0 by any of the LD1 LD4 signals Figure 15 106 Counter...

Page 1614: ...errupt flag register ECFLG indicates if any interrupt event has been latched and contains the global interrupt flag bit INT An interrupt pulse is generated to the interrupt controller only if any of the interrupt events are enabled the flag bit is 1 and the INT flag bit is 0 The interrupt service routine must clear the global interrupt flag bit and the serviced event via the interrupt clear regist...

Page 1615: ...LG Latch Clear Latch Set CMPEQ ECFRC ECCLR ECCLR Clear ECFLG ECEINT Clear Latch Set ECFRC CNTOVF ECFLG 0 1 0 Generate interrupt pulse when input 1 Latch Clear Set ECCLR ECAPxINT ECFLG www ti com Enhanced Capture eCAP Module Figure 15 107 Interrupts in eCAP Module 1615 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsystem PWMSS Submit Documentation Feedback Copyright 2011 2013 T...

Page 1616: ...ation you must write to the active registers for both period and compare This automatically copies the initial values into the shadow values For subsequent compare updates during run time you only need to use the shadow registers Figure 15 108 PWM Waveform Details Of APWM Mode Operation The behavior of APWM active high mode APWMPOL 0 is CMP 0x00000000 output low for duration of period 0 duty CMP 0...

Page 1617: ...ure eCAP Module CMP PERIOD 1 output low for complete period 1617 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsystem PWMSS Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1618: ...define EC_DIV8 0x4 define EC_DIV10 0x5 ECCTL2 ECAP Control Reg 2 CONT ONESHOT bit define EC_CONTINUOUS 0x0 define EC_ONESHOT 0x1 STOPVALUE bit define EC_EVENT1 0x0 define EC_EVENT2 0x1 define EC_EVENT3 0x2 define EC_EVENT4 0x3 RE ARM bit define EC_ARM 0x1 TSCTRSTOP bit define EC_FREEZE 0x0 define EC_RUN 0x1 SYNCO_SEL bit define EC_SYNCIN 0x0 define EC_CTR_PRD 0x1 define EC_SYNCO_DIS 0x2 CAP APWM m...

Page 1619: ...TSCTR contents time stamp is first captured then Mod4 counter is incremented to the next state When the TSCTR reaches FFFF FFFFh maximum value it wraps around to 0000 0000h not shown in Figure 15 109 if this occurs the CNTOVF counter overflow flag is set and an interrupt if enabled occurs CNTOVF counter overflow Flag is set and an Interrupt if enabled occurs Captured time stamps are valid at the p...

Page 1620: ..._EN EC_DISABLE ECCTL2 TSCTRSTOP EC_RUN Example 15 9 Code Snippet for CAP Mode Absolute Time Rising Edge Trigger Code snippet for CAP mode Absolute Time Rising edge trigger Run Time e g CEVT4 triggered ISR call TSt1 ECAPxRegs CAP1 Fetch Time Stamp captured at t1 TSt2 ECAPxRegs CAP2 Fetch Time Stamp captured at t2 TSt3 ECAPxRegs CAP3 Fetch Time Stamp captured at t3 TSt4 ECAPxRegs CAP4 Fetch Time Sta...

Page 1621: ...e 15 110 the eCAP operating mode is almost the same as in the previous section except capture events are qualified as either rising or falling edge this now gives both period and duty cycle information Period1 t3 t1 Period2 t5 t3 etc Duty Cycle1 on time t2 t1 Period1 x 100 etc Duty Cycle1 off time t3 t2 Period1 x 100 etc Figure 15 110 Capture Sequence for Absolute Time Stamp Rising and Falling Edg...

Page 1622: ..._DISABLE ECCTL2 TSCTRSTOP EC_RUN Example 15 10 Code Snippet for CAP Mode Absolute Time Rising and Falling Edge Trigger Code snippet for CAP mode Absolute Time Rising Falling edge triggers Run Time e g CEVT4 triggered ISR call TSt1 ECAPxRegs CAP1 Fetch Time Stamp captured at t1 TSt2 ECAPxRegs CAP2 Fetch Time Stamp captured at t2 TSt3 ECAPxRegs CAP3 Fetch Time Stamp captured at t3 TSt4 ECAPxRegs CAP...

Page 1623: ...re qualified as Rising edge only On an event TSCTR contents time stamp is captured first and then TSCTR is reset to Zero The Mod4 counter then increments to the next state If TSCTR reaches FFFF FFFFh maximum value before the next event it wraps around to 0000 0000h and continues a CNTOVF counter overflow Flag is set and an Interrupt if enabled occurs The advantage of Delta time Mode is that the CA...

Page 1624: ...EL EC_SYNCO_DIS ECCTL2 SYNCI_EN EC_DISABLE ECCTL2 TSCTRSTOP EC_RUN Example 15 11 Code Snippet for CAP Mode Delta Time Rising Edge Trigger Code snippet for CAP mode Delta Time Rising edge trigger Run Time e g CEVT1 triggered ISR call Note here Time stamp directly represents the Period value Period4 ECAPxRegs CAP1 Fetch Time Stamp captured at T1 Period1 ECAPxRegs CAP2 Fetch Time Stamp captured at T2...

Page 1625: ...ther Rising or Falling edge this now gives both Period and Duty cycle information Period1 T1 T2 Period2 T3 T4 etc Duty Cycle1 on time T1 Period1 100 etc Duty Cycle1 off time T2 Period1 100 etc During initialization you must write to the active registers for both period and compare This will then automatically copy the init values into the shadow values For subsequent compare updates that is during...

Page 1626: ...TSCTRSTOP EC_RUN Example 15 12 Code Snippet for CAP Mode Delta Time Rising and Falling Edge Triggers Code snippet for CAP mode Delta Time Rising and Falling edge triggers Run Time e g CEVT1 triggered ISR call Note here Time stamp directly represents the Duty cycle values DutyOnTime1 ECAPxRegs CAP2 Fetch Time Stamp captured at T2 DutyOffTime1 ECAPxRegs CAP3 Fetch Time Stamp captured at T3 DutyOnTim...

Page 1627: ...nnel PWM waveform is generated from output pin APWMn The PWM polarity is active high which means that the compare value CAP2 reg is now a compare register represents the on time high level of the period Alternatively if the APWMPOL bit is configured for active low then the compare value represents the off time Figure 15 113 PWM Waveform Details of APWM Mode Operation 1627 SPRUH73H October 2011 Rev...

Page 1628: ... with Synchronization Example Figure 15 114 takes advantage of the synchronization feature between eCAP modules Here 4 independent PWM channels are required with different frequencies but at integer multiples of each other to avoid beat frequencies Hence one eCAP module is configured as the Master and the remaining 3 are Slaves all receiving their synch pulse CTR PRD from the master Note the Maste...

Page 1629: ... module Time Time APRD 1 ACMP 1 0000 0000 APWM1 o p pin PRDEQ SyncOut 20 000 7 000 TSCTR FFFF FFFFh dc dc dc www ti com Enhanced Capture eCAP Module Figure 15 114 Multichannel PWM Example Using 4 eCAP Modules 1629 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsystem PWMSS Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1630: ...O_SEL EC_SYNCI ECCTL2 TSCTRSTOP EC_RUN Table 15 103 ECAP3 Initialization for Multichannel PWM Generation with Synchronization Register Bit Value CAP1 CAP1 5000 CTRPHS CTRPHS 0 ECCTL2 CAP_APWM EC_APWM_MODE ECCTL2 APWMPOL EC_ACTV_HI ECCTL2 SYNCI_EN EC_ENABLE ECCTL2 SYNCO_SEL EC_SYNCI ECCTL2 TSCTRSTOP EC_RUN Table 15 104 ECAP4 Initialization for Multichannel PWM Generation with Synchronization Regist...

Page 1631: ...ample In Figure 15 115 the Phase control feature of the APWM mode is used to control a 3 phase Interleaved DC DC converter topology This topology requires each phase to be off set by 120 from each other Hence if Leg 1 controlled by APWM1 is the reference Leg or phase that is 0 then Leg 2 need 120 off set and Leg 3 needs 240 off set The waveforms in Figure 15 115 show the timing relationship betwee...

Page 1632: ...ulse PRDEQ APWM1 ɸ2 120 ɸ3 240 CTRPHS 2 800 CTRPHS 3 400 APWM2 APWM3 TSCTR Enhanced Capture eCAP Module www ti com Figure 15 115 Multiphase channel Interleaved PWM Example Using 3 eCAP Modules 1632Pulse Width Modulation Subsystem PWMSS SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1633: ...nitialization for Multichannel PWM Generation with Phase Control Register Bit Value CAP1 CAP1 1200 CTRPHS CTRPHS 400 ECCTL2 CAP_APWM EC_APWM_MODE ECCTL2 APWMPOL EC_ACTV_HI ECCTL2 SYNCI_EN EC_ENABLE ECCTL2 SYNCO_SEL EC_SYNCO_DIS ECCTL2 TSCTRSTOP EC_RUN Example 15 15 Code Snippet for Multichannel PWM Generation with Phase Control Code snippet for APWM mode Example 3 Run Time Note Example execution o...

Page 1634: ...ISTERS Offset Acronym Register Name Section 0h TSCTR Time Stamp Counter Register Section 15 3 4 1 1 4h CTRPHS Counter Phase Offset Value Register Section 15 3 4 1 2 8h CAP1 Capture 1 Register Section 15 3 4 1 3 Ch CAP2 Capture 2 Register Section 15 3 4 1 4 10h CAP3 Capture 3 Register Section 15 3 4 1 5 14h CAP4 Capture 4 Register Section 15 3 4 1 6 28h ECCTL1 Capture Control Register 1 Section 15 ...

Page 1635: ...8 7 6 5 4 3 2 1 0 TSCTR R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 15 109 TSCTR Register Field Descriptions Bit Field Type Reset Description 31 0 TSCTR R W 0h Active 32 bit counter register that is used as the capture time base 1635 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsystem PWMSS Submit Documentation Feedback Copyr...

Page 1636: ...after reset Table 15 110 CTRPHS Register Field Descriptions Bit Field Type Reset Description 31 0 CTRPHS R W 0h Counter phase value register that can be programmed for phase lag lead This register shadows TSCTR and is loaded into TSCTR upon either a SYNCI event or S W force via a control bit Used to achieve phase control synchronization with respect to other eCAP and EPWM time bases 1636 Pulse Wid...

Page 1637: ... only W1toCl Write 1 to clear bit n value after reset Table 15 111 CAP1 Register Field Descriptions Bit Field Type Reset Description 31 0 CAP1 R W 0h This register can be loaded written by a Time Stamp that is counter value during a capture event b Software may be useful for test purposes c APRD active register when used in APWM mode 1637 SPRUH73H October 2011 Revised April 2013 Pulse Width Modula...

Page 1638: ... only W1toCl Write 1 to clear bit n value after reset Table 15 112 CAP2 Register Field Descriptions Bit Field Type Reset Description 31 0 CAP2 R W 0h This register can be loaded written by a Time Stamp that is counter value during a capture event b Software may be useful for test purposes c APRD active register when used in APWM mode 1638 Pulse Width Modulation Subsystem PWMSS SPRUH73H October 201...

Page 1639: ...only W1toCl Write 1 to clear bit n value after reset Table 15 113 CAP3 Register Field Descriptions Bit Field Type Reset Description 31 0 CAP3 R W 0h In CMP mode this is a time stamp capture register In APWM mode this is the period shadow APRD register You update the PWM period value through this register In this mode CAP3 shadows CAP1 1639 SPRUH73H October 2011 Revised April 2013 Pulse Width Modul...

Page 1640: ...nly W1toCl Write 1 to clear bit n value after reset Table 15 114 CAP4 Register Field Descriptions Bit Field Type Reset Description 31 0 CAP4 R W 0h In CMP mode this is a time stamp capture register In APWM mode this is the compare shadow ACMP register You update the PWM compare value through this register In this mode CAP4 shadows CAP2 1640 Pulse Width Modulation Subsystem PWMSS SPRUH73H October 2...

Page 1641: ... 0x4 Divide by 8 0x5 Divide by 10 0x1E Divide by 60 0x1F Divide by 62 8 CAPLDEN R W 0h Enable Loading of CAP 1 4 registers on a capture event 0x0 Disable CAP1 4 register loads at capture event time 0x1 Enable CAP1 4 register loads at capture event time 7 CTRRST4 R W 0h Counter Reset on Capture Event 4 0x0 Do not reset counter on Capture Event 4 absolute time stamp operation 0x1 Reset counter after...

Page 1642: ... 2 triggered on a rising edge RE 0x1 Capture Event 2 triggered on a falling edge FE 1 CTRRST1 R W 0h Counter Reset on Capture Event 1 0x0 Do not reset counter on Capture Event 1 absolute time stamp 0x1 Reset counter after Event 1 time stamp has been captured used in difference mode operation 0 CAP1POL R W 0h Capture Event 1 Polarity select 0x0 Capture Event 1 triggered on a rising edge RE 0x1 Capt...

Page 1643: ...boundary Permits shadow loading on CAP1 and 2 registers Disables loading of time stamps into CAP1 4 registers ECAPn APWMn pin operates as a APWM output 8 SWSYNC R W 0h Software forced Counter TSCTR Synchronizing This provides a convenient software method to synchronize some or all ECAP time bases In APWM mode the synchronizing can also be done via the PRDEQ event Note Selecting PRDEQ is meaningful...

Page 1644: ...circular buffer wraps around and starts again Notes STOP_WRAP is compared to Mod4 counter and when equal two actions occur 1 Mod4 counter is stopped frozen 2 Capture register loads are inhibited In one shot mode further interrupt events are blocked until re armed 0x0 Stop after Capture Event 1 in one shot mode Wrap after Capture Event 1 in continuous mode 0x1 Stop after Capture Event 2 in one shot...

Page 1645: ... 7 CMPEQ R W 0h Counter Equal Compare Interrupt Enable 0x0 Disable Compare Equal as an Interrupt source 0x1 Enable Compare Equal as an Interrupt source 6 PRDEQ R W 0h Counter Equal Period Interrupt Enable 0x0 Disable Period Equal as an Interrupt source 0x1 Enable Period Equal as an Interrupt source 5 CNTOVF R W 0h Counter Overflow Interrupt Enable 0x0 Disable counter Overflow as an Interrupt sourc...

Page 1646: ...rflow Status Flag This flag is active in CAP and APWM mode 0x0 Indicates no event occurred 0x1 Indicates the counter TSCTR has made the transition from 0xFFFFFFFF to 0x00000000 4 CEVT4 R 0h Capture Event 4 Status Flag This flag is only active in CAP mode 0x0 Indicates no event occurred 0x1 Indicates the fourth event occurred at ECAPn pin 3 CEVT3 R 0h Capture Event 3 Status Flag This flag is active...

Page 1647: ...ag 0x0 Writing a 0 has no effect Always reads back a 0 0x1 Writing a 1 clears the CNTOVF flag condition 4 CEVT4 R W 0h Capture Event 4 Status Flag 0x0 Writing a 0 has no effect Always reads back a 0 0x1 Writing a 1 clears the CEVT3 flag condition 3 CEVT3 R W 0h Capture Event 3 Status Flag 0x0 Writing a 0 has no effect Always reads back a 0 0x1 Writing a 1 clears the CEVT3 flag condition 2 CEVT2 R ...

Page 1648: ...Counter Equal Period Interrupt 0x0 No effect Always reads back a 0 0x1 Writing a 1 sets the PRDEQ flag bit 5 CNTOVF R W 0h Force Counter Overflow 0x0 No effect Always reads back a 0 0x1 Writing a 1 to this bit sets the CNTOVF flag bit 4 CEVT4 R W 0h Force Capture Event 4 0x0 No effect Always reads back a 0 0x1 Writing a 1 sets the CEVT4 flag bit 3 CEVT3 R W 0h Force Capture Event 3 0x0 No effect A...

Page 1649: ... 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REV R 44D22100h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 15 121 REVID Register Field Descriptions Bit Field Type Reset Description 31 0 REV R 44D22100h Revision ID 1649 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsystem PWMSS Submit Documentation Feedback Copyright 2011 2013 Texas ...

Page 1650: ...zed with a reticle or mask that restricts the view of the photo element to the desired part of the disk lines As the disk rotates the two photo elements generate signals that are shifted 90 degrees out of phase from each other These are commonly called the quadrature QEPA and QEPB signals The clockwise direction for most encoders is defined as the QEPA channel going positive before the QEPB channe...

Page 1651: ...ment Quadrature encoders from different manufacturers come with two forms of index pulse gated index pulse or ungated index pulse as shown in Figure 15 131 A nonstandard form of index pulse is ungated In the ungated configuration the index edges are not necessarily coincident with A and B signals The gated index pulse is aligned to any of the four quadrature edges and width of the index pulse and ...

Page 1652: ...he resolution of the position sensor and the unit time period T For example consider a 500 line per revolution quadrature encoder with a velocity calculation rate of 400 Hz When used for position the quadrature encoder gives a four fold increase in resolution in this case 2000 counts per revolution The minimum rotation that can be detected is therefore 0 0005 revolutions which gives a velocity res...

Page 1653: ...me position encoders have this type of output instead of quadrature output The QEPA pin provides the clock input and the QEPB pin provides the direction input QEPI Index or Zero Marker The eQEP encoder uses an index signal to assign an absolute start position from which position information is incrementally encoded using quadrature pulses This pin is connected to the index output of the eQEP encod...

Page 1654: ...QEPxSOE GPIO MUX EQEPxA XCLK EQEPxB XDIR EQEPxS EQEPxI QPOSCMP QEINT QFRC 32 QCLR QPOSCTL 16 32 QPOSCNT QPOSMAX QPOSINIT Interrupt Controller EQEPxINT Enhanced QEP eQEP peripheral System control registers QCTMR QCPRD 16 16 QCAPCTL EQEPxENCLK SYSCLKOUT Data bus To CPU Enhanced Quadrature Encoder Pulse eQEP Module www ti com Figure 15 132 Functional Block Diagram of the eQEP Peripheral 1654 Pulse Wi...

Page 1655: ... PCSOUT EQEPxIOE EQEPxSOE EQEPxIOUT EQEPxSOUT EQEPxSIN EQEPxIIN EQEPxBIN EQEPxAIN QDECCTL SWAP QEPSTS QDF EQEPA EQEPB www ti com Enhanced Quadrature Encoder Pulse eQEP Module 15 4 2 3 Quadrature Decoder Unit QDU Figure 15 133 shows a functional block diagram of the QDU Figure 15 133 Functional Block Diagram of Decoder Unit 1655 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsys...

Page 1656: ...rees out of phase The phase error flag PHE is set in the QFLG register when edge transition is detected simultaneously on the QEPA and QEPB signals to optionally generate interrupts State transitions marked by dashed lines in Figure 15 134 are invalid transitions that generate a phase error Count Multiplication The eQEP position counter provides 4x times the resolution of an input clock by generat...

Page 1657: ...ment counter Increment counter Decrement counter Decrement counter Increment counter Increment counter www ti com Enhanced Quadrature Encoder Pulse eQEP Module Figure 15 134 Quadrature Decoder State Machine Figure 15 135 Quadrature clock and Direction Decoding 1657 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsystem PWMSS Submit Documentation Feedback Copyright 2011 2013 Texa...

Page 1658: ...he position counter register QPOSCNT and the position compare register QPOSCMP This sync signal can be output using an index pin or strobe pin of the EQEP peripheral Setting the SOEN bit in the eQEP decoder control register QDECCTL enables the position compare sync output and the SPSEL bit in QDECCTL selects either an eQEP index pin or an eQEP strobe pin 15 4 2 4 Position Counter and Control Unit ...

Page 1659: ...o remembers the quadrature edge on the first index marker so that same relative quadrature transition is used for index event reset operation For example if the first reset operation occurs on the falling edge of QEPB during the forward direction then all the subsequent reset must be aligned with the falling edge of QEPB for the forward rotation and on the rising edge of QEPB for the reverse rotat...

Page 1660: ...rse movement and position counter underflow flag is set Figure 15 137 shows the position counter reset operation in this mode First index marker is defined as the quadrature edge following the first index edge The eQEP peripheral records the occurrence of the first index marker QEPSTS FIMF and direction on the first index event marker QEPSTS FIDF in the QEPSTS registers it also remembers the quadr...

Page 1661: ... required to operate the position counter in full 32 bit mode QEPCTL PCRM 01 and QEPCTL PCRM 10 modes In such cases the eQEP position counter can be configured to latch on the following events and direction information is recorded in the QEPSTS QDLF bit on every index event marker Latch on Rising edge QEPCTL IEL 01 Latch on Falling edge QEPCTL IEL 10 Latch on Index Event Marker QEPCTL IEL 11 This ...

Page 1662: ...interrupt index event marker QPOSILAT QEPSTS QDLF Enhanced Quadrature Encoder Pulse eQEP Module www ti com Figure 15 138 Software Index Marker for 1000 line Encoder QEPCTL IEL 1 1662 Pulse Width Modulation Subsystem PWMSS SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1663: ...he QEPCTL SEL bit is set then the position counter value is latched to the QPOSSLAT register on the rising edge of the strobe input for forward direction and on the falling edge of the strobe input for reverse direction as shown in Figure 15 139 The strobe event latch interrupt flag QFLG SEL is set when the position counter is latched to the QPOSSLAT register Figure 15 139 Strobe Event Latch QEPCT...

Page 1664: ...INIT register on the rising edge of strobe input for forward direction and on the falling edge of strobe input for reverse direction The strobe event initialization interrupt flag QFLG SEI is set when the position counter is initialized with a value in the QPOSINIT register Software Initialization SWI The position counter can be initialized in software by writing a 1 to the QEPCTL SWI bit which wi...

Page 1665: ...nsitions of the eQEP position counter for reverse counting direction see Figure 15 141 Figure 15 163 shows the layout of the eQEP Position Compare Control Register QPOSCTL and Table 15 138 describes the QPOSCTL bit fields Figure 15 141 eQEP Position compare Event Generation Points The pulse stretcher logic in the position compare unit generates a programmable position compare sync pulse output on ...

Page 1666: ...counts have occurred between unit position events No direction change between unit position events The capture unit sets the eQEP overflow error flag QEPSTS COEF in the event of capture timer overflow between unit position events If a direction change occurs between the unit position events then an error flag is set in the status register QEPSTS CDEF Capture Timer QCTMR and Capture period register...

Page 1667: ... QEPCTL UTE QUTMR QUPRD SYSCLKOUT QFLG UTO UTIME 4 QCAPCTL UPPS UTOUT QEPSTS UPEVNT UPEVNT www ti com Enhanced Quadrature Encoder Pulse eQEP Module Figure 15 143 eQEP Edge Capture Unit Figure 15 144 Unit Position Event for Low Speed Measurement QCAPCTL UPPS 0010 N Number of quadrature periods selected using QCAPCTL UPPS bits 1667 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subs...

Page 1668: ...nverse of velocity calculation rate ΔX Incremental position movement in unit time X Fixed unit position ΔT Incremental time elapsed for unit position movement t k Time instant k t k 1 Time instant k 1 Unit time T and unit period X are configured using the QUPRD and QCAPCTL UPPS registers Incremental position output and incremental time output is available in the QPOSLAT and QCPRDLAT registers 1668...

Page 1669: ...g timer that monitors the quadrature clock to indicate proper operation of the motion control system The eQEP watchdog timer is clocked from SYSCLKOUT 64 and the quadrate clock event pulse resets the watchdog timer If no quadrature clock event is detected until a period match QWDPRD QWDTMR then the watchdog timer will time out and the watchdog interrupt flag will be set QFLG WTO The time out value...

Page 1670: ...rupt Structure Figure 15 148 shows how the interrupt mechanism works in the EQEP module Figure 15 148 EQEP Interrupt Generation Eleven interrupt events PCE PHE QDC WTO PCU PCO PCR PCM SEL IEL and UTO can be generated The interrupt control register QEINT is used to enable disable individual interrupt event sources The interrupt flag register QFLG indicates if any interrupt event has been latched an...

Page 1671: ... as DMA events The interrupt registers should be used to enable and clear the current DMA event in order for the eQEP module to generate subsequent DMA events 1671 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsystem PWMSS Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1672: ... 10 26h QWDPRD eQEP Watchdog Period Register 1 0 Section 15 4 3 11 28h QDECCTL eQEP Decoder Control Register 1 0 Section 15 4 3 12 2Ah QEPCTL eQEP Control Register 1 0 Section 15 4 3 13 2Ch QCAPCTL eQEP Capture Control Register 1 0 Section 15 4 3 14 2Eh QPOSCTL eQEP Position Compare Control Register 1 0 Section 15 4 3 15 30h QEINT eQEP Interrupt Enable Register 1 0 Section 15 4 3 16 32h QFLG eQEP ...

Page 1673: ... LEGEND R W Read Write R Read only n value after reset Table 15 125 eQEP Position Counter Initialization Register QPOSINIT Field Descriptions Bits Name Value Description 31 0 QPOSINIT 0 FFFF FFFFh This register contains the position value that is used to initialize the position counter based on external strobe or index event The position counter can be initialized through software 15 4 3 3 eQEP Ma...

Page 1674: ...Read only n value after reset Table 15 128 eQEP Index Position Latch Register QPOSILAT Field Descriptions Bits Name Value Description 31 0 QPOSILAT 0 FFFF FFFFh The position counter value is latched into this register on an index event as defined by the QEPCTL IEL bits 15 4 3 6 eQEP Strobe Position Latch Register QPOSSLAT Figure 15 154 eQEP Strobe Position Latch Register QPOSSLAT 31 0 QPOSSLAT R 0...

Page 1675: ...R Field Descriptions Bits Name Value Description 31 0 QUTMR 0 FFFF FFFFh This register acts as time base for unit time event generation When this timer value matches with unit time period value unit time event is generated 15 4 3 9 eQEP Unit Period Register QUPRD Figure 15 157 eQEP Unit Period Register QUPRD 31 0 QUPRD R W 0 LEGEND R W Read Write R Read only n value after reset Table 15 132 eQEP U...

Page 1676: ...register is reset upon edge transition in quadrature clock indicating the motion 15 4 3 11 eQEP Watchdog Period Register QWDPRD Figure 15 159 eQEP Watchdog Period Register QWDPRD 15 0 QWDPRD R W 0 LEGEND R W Read Write R Read only n value after reset Table 15 134 eQEP Watchdog Period Register QWDPRD Field Description Bits Name Value Description 15 0 QWDPRD 0 FFFFh This register contains the time o...

Page 1677: ...Enable position compare sync output 12 SPSEL Sync output pin selection 0 Index pin is used for sync output 1 Strobe pin is used for sync output 11 XCR External clock rate 0 2 resolution Count the rising falling edge 1 1 resolution Count the rising edge only 10 SWAP Swap quadrature clock inputs This swaps the input to the quadrature decoder reversing the counting direction 0 Quadrature clock inputs...

Page 1678: ...h 3h Capture Timer is unaffected by emulation suspend 13 12 PCRM 0 3h Position counter reset mode 0 Position counter reset on an index event 1h Position counter reset on the maximum position 2h Position counter reset on the first index event 3h Position counter reset on a unit time event 11 10 SEI 0 3h Strobe event initialization of position counter 0 Does nothing action disabled 1h Does nothing a...

Page 1679: ... The position counter is latched to the QPOSILAT register and the direction flag is latched in the QEPSTS QDLF bit This mode is useful for software index marking 3 PHEN Quadrature position counter enable software reset 0 Reset the eQEP peripheral internal operating flags read only registers Control configuration registers are not disturbed by a software reset 1 eQEP position counter is enabled 2 Q...

Page 1680: ...0 Always write as 0 6 4 CCPS 0 7h eQEP capture timer clock prescaler 0 CAPCLK SYSCLKOUT 1 1h CAPCLK SYSCLKOUT 2 2h CAPCLK SYSCLKOUT 4 3h CAPCLK SYSCLKOUT 8 4h CAPCLK SYSCLKOUT 16 5h CAPCLK SYSCLKOUT 32 6h CAPCLK SYSCLKOUT 64 7h CAPCLK SYSCLKOUT 128 3 0 UPPS 0 Fh Unit position event prescaler 0 UPEVNT QCLK 1 1h UPEVNT QCLK 2 2h UPEVNT QCLK 4 3h UPEVNT QCLK 8 4h UPEVNT QCLK 16 5h UPEVNT QCLK 32 6h U...

Page 1681: ...le 0 Shadow disabled load Immediate 1 Shadow enabled 14 PCLOAD Position compare shadow load mode 0 Load on QPOSCNT 0 1 Load when QPOSCNT QPOSCMP 13 PCPOL Polarity of sync output 0 Active HIGH pulse output 1 Active LOW pulse output 12 PCE Position compare enable disable 0 Disable position compare unit 1 Enable position compare unit 11 0 PCSPW 0 FFFh Select position compare sync output pulse width 0...

Page 1682: ...errupt is enabled 8 PCM Position compare match interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled 7 PCR Position compare ready interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled 6 PCO Position counter overflow interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled 5 PCU Position counter underflow interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled 4 W...

Page 1683: ...rupt generated 1 This bit is set on position compare match 7 PCR Position compare ready interrupt flag 0 No interrupt generated 1 This bit is set after transferring the shadow register value to the active position compare register 6 PCO Position counter overflow interrupt flag 0 No interrupt generated 1 This bit is set on position counter overflow 5 PCU Position counter underflow interrupt flag 0 ...

Page 1684: ...flag 0 No effect 1 Clears the interrupt flag 10 IEL Clear index event latch interrupt flag 0 No effect 1 Clears the interrupt flag 9 SEL Clear strobe event latch interrupt flag 0 No effect 1 Clears the interrupt flag 8 PCM Clear eQEP compare match event interrupt flag 0 No effect 1 Clears the interrupt flag 7 PCR Clear position compare ready interrupt flag 0 No effect 1 Clears the interrupt flag 6...

Page 1685: ...ears the interrupt flag 1 PCE Clear position counter error interrupt flag 0 No effect 1 Clears the interrupt flag 0 INT Global interrupt clear flag 0 No effect 1 Clears the interrupt flag and enables further interrupts to be generated if an event flags is set to 1 1685 SPRUH73H October 2011 Revised April 2013 Pulse Width Modulation Subsystem PWMSS Submit Documentation Feedback Copyright 2011 2013 ...

Page 1686: ...h interrupt 0 No effect 1 Force the interrupt 8 PCM Force position compare match interrupt 0 No effect 1 Force the interrupt 7 PCR Force position compare ready interrupt 0 No effect 1 Force the interrupt 6 PCO Force position counter overflow interrupt 0 No effect 1 Force the interrupt 5 PCU Force position counter underflow interrupt 0 No effect 1 Force the interrupt 4 WTO Force watchdog time out i...

Page 1687: ...flag 0 Counter clockwise rotation or reverse movement 1 Clockwise rotation or forward movement 4 QDLF eQEP direction latch flag Status of direction is latched on every index event marker 0 Counter clockwise rotation or reverse movement on index event marker 1 Clockwise rotation or forward movement on index event marker 3 COEF Capture overflow error flag 0 Sticky bit cleared by writing 1 1 Overflow...

Page 1688: ...od Register QCPRD Field Descriptions Bits Name Value Description 15 0 QCPRD 0 FFFFh This register holds the period count value between the last successive eQEP position events 15 4 3 23 eQEP Capture Timer Latch Register QCTMRLAT Figure 15 171 eQEP Capture Timer Latch Register QCTMRLAT 15 0 QCTMRLAT R LEGEND R W Read Write R Read only n value after reset Table 15 146 eQEP Capture Timer Latch Regist...

Page 1689: ...P capture period value can be latched into this register on two events viz unit timeout event reading the eQEP position counter 15 4 3 25 eQEP Revision ID Register REVID Figure 15 173 eQEP Revision ID Register REVID 31 0 REV R 44D3 1103h LEGEND R Read only n value after reset Table 15 148 eQEP Revision ID Register REVID Field Descriptions Bits Name Value Description 31 0 REV 44D3 1103h eQEP revisi...

Page 1690: ... of the device Topic Page 16 1 Introduction 1691 16 2 Integration 1694 16 3 Functional Description 1697 16 4 Supported Use Cases 1759 16 5 USB Registers 1760 1690 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1691: ...ithin the descriptions of the USB subsystem that would follow the term USB controller or USB PHY is used to mean refer to any of the two USB controllers or PHYs existing within the USB subsystem The term USB module is used to mean refer to any of the two USB modules USB0 is used to refer to one of the USB modules and USB1 is used to refer to the other USB module 16 1 1 Acronyms Abbreviations and D...

Page 1692: ...Includes a 32K endpoint FIFO RAM and supports programmable FIFO sizes Includes RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB Includes CDC Linux mode for accelerating CDC type protocols using short packet termination over USB Includes an RNDIS like mode for terminating RNDIS type protocols without using short packet termination for support of MSC applicati...

Page 1693: ...d USB OTG and PHY Features This device supports USBOTG module host device and OTG features 1693 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1694: ...tion This device implements the USB2 0 OTG dual port module and PHY for interfacing to USB as a peripheral or host Figure 16 1 shows the integration of the USB module on this device Figure 16 1 USB Integration 16 2 1 USB Connectivity Attributes The USB module itself has a very large number of interrupt outputs For ease of integration these outputs are all routed to a pair of interrupt aggregators ...

Page 1695: ...O clkdcoldo_po Phy reference clock From Per PLL 16 2 3 USB Pin List The USB external interface signals are shown in Table 16 3 Table 16 3 USB Pin List Pin Type Description USBx_DP 1 USB Analog I O USBx data differential pair USBx_DM 1 GPIO Digital I O USBx_DRVVBUS Digital output USBx VBUS supply control USBx_VBUS Analog input USBx VBUS input only for voltage sensing USBx_ID Analog input USBx OTG i...

Page 1696: ...ere only 1 PHY is bonded out to pins e g 13x13 package the following procedures must be followed in order to ensure that the unbonded PHY pads do not cause issues with USBOTGSS operation The USB Controller corresponding to the unbonded PHY must be placed in Host Mode by setting Bit2 of the USB Core DEVCTL register The unbonded PHY must be placed in the SUSPEND state by setting Bits 1 0 of the USB ...

Page 1697: ...form data transfer The CPPI DMA can be used to service Endpoints 1 to 15 not Endpoint 0 CPU access method is used to service Endpoint 0 transactions 16 3 1 VBUS Voltage Sourcing Control When any of the USB controllers assumes the role of a host the USB is required to supply a 5V power source to an attached device through its VBUS line In order to achieve this task the USB controller requires the u...

Page 1698: ... 1C0Eh for USB0 and USB1 respectively of the controller By programming the INDEX register with the corresponding endpoint number the control and status register corresponding to that particular endpoint is accessible from this Indexed Region In other words Index Register region behaves as a proxy to access a selected endpoint registers Non indexed Endpoint Control Status Register Space These regio...

Page 1699: ... the firmware is required to program the respective USB Mode Register IDDIG bit field with a value of 1 prior to the USB controller goes into session can consider this as a s w option Similarly for a USB host configuration the user has the option of using the cable end to select the role by attaching the mini or micro a side of the cable can consider this as a h w option or use the optional method...

Page 1700: ... and an external host is sourcing power on the USBx_VBUSIN line then the USB2 0 controller will set the DEVCTL SESSION bit instructing the controller to go into session Not that the voltage on the USBx_VBUSIN pin must be within Vbus Valid range i e greater or equal to 4 4V When the controller goes into session it will force the USB2 0 Controller to sense the state of the iddig signal Once it sense...

Page 1701: ...als so that the clock to the controller can be restarted Resume Signaling When resume signaling occurs on the bus first the clock to the controller must be restarted if necessary Then the controller will automatically exit Suspend mode If the Resume interrupt is enabled an interrupt will be generated Initiating a remote wakeup If the software wants to initiate a remote wakeup while the controller ...

Page 1702: ...ame time When the host moves to the status stage of the request a second endpoint 0 interrupt will be generated to indicate that the request has completed No further action is required from the software The second interrupt is just a confirmation that the request completed successfully For SET_ADDRESS command the address should be written to FADDR register at the completion of the command i e when...

Page 1703: ...ION GET_INTERFACE GET_DESCRIPTOR GET_STATUS SYNCH_FRAME The sequence of events will begin as with all requests when the software receives an endpoint 0 interrupt The RXPKTRDY bit of PERI_CSR0 bit 0 will also have been set The 8 byte command should then be read from the endpoint 0 FIFO and decoded The PERI_CSR0 register should then be written to set the SERV_RXPKTRDY bit bit 6 indicating that the c...

Page 1704: ... the device request is unloaded from the FIFO the controller decodes the descriptor to find whether there is a data phase and if so the direction of the data phase of the control transfer in order to set the FIFO direction See Figure 16 3 Depending on the direction of the data phase endpoint 0 goes into either TX state or RX state If there is no Data phase endpoint 0 remains in IDLE state to accep...

Page 1705: ... Set TxPktRdy Load FIFO Set TxPktRdy Set DataEnd Unload Device Req Clear RxPktRdy CPU actions UnLoad FIFO Clear RxPktRdy Unload Device Req Clear RxPktRdy Unload FIFO Clear RxPktRdy Unload FIFO Clear RxPktRdy Set DataEnd Interrupts Status Phase IN Setup Interrupts Idle CPU actions Unload Device Req Clear RxPktRdy Set DataEnd NO DATA Phase www ti com Functional Description Figure 16 4 Sequence of Tr...

Page 1706: ...en depends on the endpoint state If endpoint 0 is in IDLE state the only valid reason an interrupt can be generated is as a result of the controller receiving data from the bus The service routine must check for this by testing the RXPKTRDY bit of PERI_CSR0 bit 0 If this bit is set then the controller has received a SETUP packet This must be unloaded from the FIFO and decoded to determine the acti...

Page 1707: ...IDLE mode is the mode the Endpoint 0 control needs to select at power on or reset and is the mode to which the Endpoint 0 control should return when the RX and TX modes are terminated It is also the mode in which the SETUP phase of control transfer is handled as outlined in Figure 16 5 Figure 16 5 Flow Chart of Setup Stage of a Control Transfer in Peripheral Mode 1707 SPRUH73H October 2011 Revised...

Page 1708: ... SETUPEND condition bit 4 of PERI_CSR0 is set 2 The firmware sends a packet containing less than the maximum packet size for Endpoint 0 3 The firmware sends an empty data packet Until the transaction is terminated the firmware simply needs to load the FIFO when it receives an interrupt which indicates that a packet has been sent from the FIFO An interrupt is generated when TXPKTRDY is cleared When...

Page 1709: ... setting bit 4 of PERI_CSR0 2 The host sends a packet which contains less than the maximum packet size for endpoint 0 3 The host sends an empty data packet Until the transaction is terminated the software unloads the FIFO when it receives an interrupt that indicates new data has arrived setting RXPKTRDY bit of PERI_CSR0 and to clear RXPKTRDY by setting the SERV_RXPKTRDY bit of PERI_CSR0 bit 6 When...

Page 1710: ...er because it cannot process the command or has some other internal error then it should set the SENDSTALL bit bit 5 of PERI_CSR0 The controller will then send a STALL packet to the host set the SENTSTALL bit bit 2 of PERI_CSR0 and generate an endpoint 0 interrupt 16 3 8 1 1 5 Additional Conditions Control Transfer of Peripheral Mode When working as a peripheral device the controller automatically...

Page 1711: ...I_TXCSR register DMAEN and DMAMODE bit fields should be set when using DMA Table 16 4 displays the PERI_TXCSR setting when used for Bulk transfer Table 16 4 PERI_TXCSR Register Bit Configuration for Bulk IN Transactions Bit Field Bit Name Description Bit 15 AUTOSET Cleared to 0 if using DMA For CPU Mode use if AUTOSET bit is set the TXPKTRDY bit will be automatically set when data of the maximum p...

Page 1712: ...arate section detailing the use of the DMA is discussed within a latter section Suffix is to say that the PERI_TXCSR DMAEN and DMAMODE bit fields need to be set and the PERI_TXCSR AUTOSET bit cleared at the core level when using the DMA with an endpoint configured for any IN transaction transfer 16 3 8 1 2 1 3 Error Handling of Bulk IN Transfer Peripheral Mode If the software wants to shut down th...

Page 1713: ...y the RXPKTRDY bit bit 0 of PERI_RXCSR being set they should be flushed by setting the FLUSHFIFO bit bit 4 of PERI_RXCSR NOTE It may be necessary to set this bit twice in succession if double buffering is enabled 16 3 8 1 2 2 2 Bulk OUT Operation Peripheral Mode When a data packet is received by a Bulk Rx endpoint the RXPKTRDY bit bit 0 of PERI_RXCSR is set and an interrupt is generated The softwa...

Page 1714: ...ntroller should never respond with a NYET handshake only ACK NAK STALL To ensure this the DISNYET bit in the PERI_RXCSR register bit 12 should be set to disable the transmission of NYET handshakes in high speed mode Though DMA can be used with an interrupt OUT endpoint it generally offers little benefit as interrupt endpoints are usually expected to transfer all their data in a single packet 16 3 ...

Page 1715: ...ad requests If the data source for the endpoint is coming from some external hardware it may be more convenient to wait until the end of each frame microframe before loading the FIFO as this will minimize the requirement for additional buffering This can be done by using either the SOF interrupt or the external SOF_PULSE signal from the controller to trigger the loading of the next data packet The...

Page 1716: ...ly useful with Isochronous endpoints because the packets transferred are often not maximum packet size and the PERI_RXCSR register needs to be accessed following every packet to check for Overrun or CRC errors When DMA is enabled endpoint interrupt will not be generated for completion of packet reception Endpoint interrupt will be generated only in the error conditions 16 3 8 1 4 2 1 Isochronous O...

Page 1717: ...T Error Handling Peripheral Mode If there is no space in the FIFO to store a packet when it is received from the host the OVERRUN bit in the PERI_RXCSR register bit 2 will be set This is an indication that the software is not unloading data fast enough for the host It is up to the application to determine how this error condition is handled If the controller finds that a received packet has a CRC ...

Page 1718: ... Signaling When the application requires the controller to leave suspend mode it needs to clear the SUSPENDM bit in the POWER register set the RESUME bit and leave it set for 20ms While the RESUME bit is high the controller will generate Resume signaling on the bus After 20 ms the CPU should clear the RESUME bit at which point the frame counter and transaction scheduler will be started Responding ...

Page 1719: ... 1 Setup Phase of Control Transaction Host Mode For the SETUP Phase of a control transaction Figure 16 8 the software driving the USB host device needs to 1 Load the 8 bytes of the required Device request command into the Endpoint 0 FIFO 2 Set SETUPPKT and TXPKTRDY bits 3 and 1 of HOST_CSR0 respectively NOTE These bits must be set together The controller then proceeds to send a SETUP token followe...

Page 1720: ...unctional Description www ti com Figure 16 8 Flow Chart of Setup Stage of a Control Transfer in Host Mode 16 3 8 2 1 2 Data Phase IN Data Phase of a Control Transaction Host Mode For the IN Data Phase of a control transaction Figure 16 9 the software driving the USB host device needs to 1 Set REQPKT bit of HOST_CSR0 bit 5 2 Wait while the controller sends the IN token and receives the required dat...

Page 1721: ...ived a NAK response to each attempt to send the IN token for longer than the time set in HOST_NAKLIMIT0 The controller can then be directed either to continue trying this transaction until it times out again by clearing the NAK_TIMEOUT bit or to abort the transaction by clearing REQPKT before clearing the NAK_TIMEOUT bit 4 If RXPKTRDY has been set the software should read the data from the Endpoin...

Page 1722: ...llowing data packet three times without getting any response If NAK_TIMEOUT is set it means that the controller has received a NAK response to each attempt to send the OUT token for longer than the time set in the HOST_NAKLIMIT0 register The controller can then be directed either to continue trying this transaction until it times out again by clearing the NAK_TIMEOUT bit or to abort the transactio...

Page 1723: ...ntrol Transaction Host Mode IN Status Phase of a control transfer exists for a Zero Data Request or for a Write Request of a control transfer The IN Status Phase follows the Setup Stage if no Data Stage of a control transfer exists or OUT Data Phase of a Data Stage of a control transfer For the IN Status Phase of a control transaction Figure 16 11 the software driving the USB Host device needs to ...

Page 1724: ...ach attempt to send the IN token for longer than the time set in the HOST_NAKLIMIT0 register The controller can then be directed either to continue trying this transaction until it times out again by clearing the NAK_TIMEOUT bit or to abort the transaction by clearing REQPKT bit and STATUSPKT bit before clearing the NAK_TIMEOUT bit 4 The CPU should clear the STATUSPPKT bit of HOST_CSR0 together wi...

Page 1725: ...R bit is set it means that the controller has tried to send the STATUS Packet and the following data packet three times without getting any response If NAK_TIMEOUT bit is set it means that the controller has received a NAK response to each attempt to send the IN token for longer than the time set in the HOST_NAKLIMIT0 register The controller can then be directed either to continue trying this tran...

Page 1726: ...s Yes Yes No TxPktRdy Cleared Error Count Cleared Interrupt Generated Functional Description www ti com Figure 16 12 Chart of Status Stage of a Read Request of a Control Transfer in Host Mode 16 3 8 2 2 Bulk Transfer Host Mode Bulk transactions are handled by endpoints other than endpoint 0 It is used to handle non periodic large bursty communication typically used for a transfer that use any avai...

Page 1727: ...written with the maximum packet size in bytes for the transfer This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for the target endpoint The HOST_RXINTERVAL register needs to be written with the required value for the NAK limit 2 215 frames microframes or set to zero if the NAK timeout feature is not required The relevant interrupt enable bit in the INTR...

Page 1728: ...abort the transaction by clearing REQPKT bit before clearing the DATAERR_NAKTIMEOUT bit The packets received should not exceed the size specified in the RXMAXP register as this should be the value set in the wMaxPacketSize field of the endpoint descriptor sent to the host In the general case the application software if CPU is servicing the endpoint will need to read each packet from the FIFO indiv...

Page 1729: ...ation in automatically setting the TXPKTRDY bit when servicing transactions using CPU Note If DMA is needs to be used in place of the CPU the following table displays the setting of the core register HOST_TXCSR register in Host mode For the CPPI DMA registers settings consult the section on CPPI DMA within this document Bit Field Bit Name Description Bit 15 AUTOSET Cleared to 0 if using DMA For CP...

Page 1730: ...s with an Interrupt endpoint on the USB peripheral device are handled in very much the same way as the equivalent Bulk transactions described in previous sections The principal difference as far as operational steps are concerned is that the PROT field of HOST_RXTYPE and HOST_TXTYPE bits 5 4 need to be set binary value to represent an Interrupt transaction The required polling interval also needs ...

Page 1731: ...2 to 0 to allow normal PING flow control This will only affect High Speed transactions Clear DMAMODE bit bit 11 to 0 If DMA is enabled AUTOREQ register can be set for generating IN tokens automatically after receiving the data Set the bit field RXn_AUTOREQ where n is the endpoint number with binary value 01 or 11 For detailed information on using CPPI DMA consult related section within this docume...

Page 1732: ...re initiating any Isochronous OUT transactions The target function address needs to be set in the TXFUNCADDR register for the selected controller endpoint TXFUNCADDR register is available for all endpoints from EP0 to EP4 The HOST_TXTYPE register for the endpoint that is to be used needs to be programmed as Operating speed in the SPEED bit field bits 7 and 6 Set 01 binary value in the PROT field f...

Page 1733: ...load requests If the data source for the endpoint is coming from some external hardware it may be more convenient to wait until the end of each frame before loading the FIFO as this will minimize the requirement for additional buffering This can be done by using the SOF_PULSE signal from the controller to trigger the loading of the next data packet The SOF_PULSE is generated once per frame microfr...

Page 1734: ...ty or full CPPI DMA CDMA The CDMA is responsible for transferring data between the CPPI FIFO and Main Memory It acquires free Buffer Descriptor from the QM Receive Submit Queue for storage of received data posts received packets pointers to the Receive Completion Queue transmits packets stored on the Transmit Submit Queue Transmit Queue and posts completed transmit packets to the Transmit Completi...

Page 1735: ...list of available descriptors with pre linked empty buffers that are to be used by the receive ports for host type descriptors Free Descriptor Buffer Queues are implemented by the Queue Manager Teardown Descriptor Teardown Descriptor is a special structure which is not used to describe either a packet or a buffer but is instead used to describe the completion of a channel halt and teardown event C...

Page 1736: ...scriptors is application dependent Port will make use of the first 32 bytes only From a general USB use perspective a 32 byte descriptor size is suffix and the use of this size is expected for a normal USB usage The packet descriptor layout is shown in Figure 16 13 and described within Table 16 9 through Table 16 16 Figure 16 13 Packet Descriptor Layout Table 16 9 Packet Descriptor Word 0 PD0 Bit ...

Page 1737: ...a For transmit if a packet has this bit set the XDMA will ignore the CPPI packet size and send a zero length packet to the USB controller This field contains protocol specific flags information that can be assigned 18 16 Protocol specific based on the packet type Not used for USB This field indicates the return policy for this packet The CPU initializes 15 Return policy this field 0 Entire packet ...

Page 1738: ...o determine the actual 21 0 Original buffer 0 pointer buffer location as allocated by the CPU at initialization Since the buffer pointer in Word 4 is overwritten by the Rx port during reception this field is necessary to permanently store the buffer pointer information 16 3 9 2 2 Host Buffer Descriptor Buffer Descriptor BD The buffer descriptor is identical in size and organization to a Packet Des...

Page 1739: ...h is 14 On chip on chip memory space 1 or in external memory 0 This field indicates which queue manager in the system the descriptor is to be returned to after transmission is complete This field is not altered by 13 12 Packet return queue mgr the DMA during transmission or reception and is initialized by the CPU There is only 1 queue manager in the USB HS FS device controller This field must alwa...

Page 1740: ...t overwritten during reception This value is read by the Rx DMA to determine the actual 31 0 Original buffer 0 pointer buffer location as allocated by the CPU at initialization Since the buffer pointer in Word 4 is overwritten by the Rx port during reception this field is necessary to permanently store the buffer pointer information 16 3 9 2 3 Teardown Descriptor The Teardown Descriptor is not lik...

Page 1741: ... RxCSR register must be set The following is the Transmit teardown procedure highlighting the steps required to be followed 1 Set the TX_TEARDOWN bit in the CPPI DMA TX channel n global configuration register TXGCRn 2 Set the appropriate TX_TDOWN bit in the USBOTG controller s USB teardown register TEARDOWN Write Tx Endpoint Number to teardown to TEARDOWN TX_TDOWN field 3 Check if the teardown des...

Page 1742: ...within the CPPI 4 1 DMA Regardless of the type of queue queues are used to hold pointers to Packet or Buffer Descriptors while they are being passed between the Host and or any of the ports in the system All queues are maintained within the single Queue Manager module The following types of Queues exist Free descriptor queue unassigned to specific endpoint but assigned to specific endpoint type re...

Page 1743: ... 92 1 Reserved 93 1 USB0 Tx Endpoint 1 completion queue 94 1 USB0 Tx Endpoint 2 completion queue 95 1 USB0 Tx Endpoint 3 completion queue 96 1 USB0 Tx Endpoint 4 completion queue 97 1 USB0 Tx Endpoint 5 completion queue 98 1 USB0 Tx Endpoint 6 completion queue 99 1 USB0 Tx Endpoint 7 completion queue 100 1 USB0 Tx Endpoint 8 completion queue 101 1 USB0 Tx Endpoint 9 completion queue 102 1 USB0 Tx ...

Page 1744: ...x Endpoint 8 completion queue 133 1 USB1 Tx Endpoint 9 completion queue 134 1 USB1 Tx Endpoint 10 completion queue 135 1 USB1 Tx Endpoint 11 completion queue 136 1 USB1 Tx Endpoint 12 completion queue 137 1 USB1 Tx Endpoint 13 completion queue 138 1 USB1 Tx Endpoint 14 completion queue 139 1 USB1 Tx Endpoint 15 completion queue 140 1 Reserved 141 1 USB1 Rx Endpoint 1 completion queue 142 1 USB1 Rx...

Page 1745: ...Queues are also used to return packet Descriptors when performing a Transmit channel teardown operation 16 3 9 3 5 Receive Completion Return Queue Receive ports use packet queues referred to as receive completion queues to return packet descriptors to the port after packets have been received A singe queue is reserved to be used by a single receive endpoint Application s w needs to insure that the...

Page 1746: ...ptors with different sizes cannot be housed within a single memory region These 64K descriptors are referenced internally in the queue manager by a 16 bit quantity index The information about the Linking RAM regions and the size that are allocated is communicated to the CPPI DMA via three registers dedicated for this purpose Two of the three registers are used to store the 32 bit aligned start add...

Page 1747: ...ready signal which is used to stall the scheduler until it can accept the credit The DMA controller only asserts the sched_ready signal when it is in the IDLE state b Once a credit has been accepted indicated by sched_req and sched_ready both asserted the scheduler will increment the index to the next entry and will start again at step 2 4 If the channel in question is not currently capable of pro...

Page 1748: ...edit for EP2 Tx This requirement is satisfied by allocating any two of the four entries to EP1 Tx endpoint Again for this example scheduler Table WORD 0 would suffice since it can handle the first 4 entries Even though several scenarios exist to programming the order of service for this case one scenario would be to allow servicing EP1 Tx to back to back followed by the other enabled endpoints Pro...

Page 1749: ... large DMA transfer and the DMA interrupt is generated only at the end of the complete reception of DMA transfer The protocol defines the end of the complete transfer by receiving a short USB packet smaller than USB MaxPktSize as mentioned in USB specification 2 0 If the DMA packet size is an exact multiple of USB MaxPktSize the DMA controller waits for a zero byte packet at the end of complete tr...

Page 1750: ...e the field that correspond to the USB module endpoint using the corresponding USB0 1 TX RX Mode Register i e TXMODE0 1 TXn_MODE 11b and RXMODE0 1 RXn_MODE 11b 16 3 9 8 4 Linux CDC DMA Transfer Linux CDC DMA transfer mode acts in the same manner as RNDIS packets except for the case where the last data matches the max USB packet size requiring additional zero byte packet transfer in RNDIS mode and ...

Page 1751: ... descriptor with packet length this is NOT data buffer length the term packet used here is to mean a transfer length not USB packet field of 608 bytes and a Data Buffer of size 256 Bytes linked to the 1st host buffer descriptor Two buffer descriptors with first buffer descriptor this is the one linked to the packet descriptor defining the second data buffer size of 256 Bytes which in turn is linke...

Page 1752: ...RXCQ Receive Completion Queue or Receive Return Queue for USB0 Rx EP1 use Queue 109 for USB1 Rx EP1 use Queue 141 RXSQ Receive Free Buffer Descriptor Queue or Receive Submit Queue For USB0 Rx EP1 Queue 0 is used and for USB1 Rx EP1 Queue 16 should be used 16 3 9 9 1 Transmit USB Data Flow Using DMA The transmit descriptors and queue status configuration prior to the transfer taking place is shown ...

Page 1753: ...erforms the following steps for transmit initialization 1 Initializes Memory Region 0 base address and Memory Region 0 size Link RAM0 Base address Link RAM0 data size and Link RAM1 Base address 2 Creates PD BDs and DBs in main memory and link as indicated in Figure 16 19 3 Initializes and configures the Queue Manager Channel Setup DMA Scheduler and Mentor USB 2 0 Core 4 Adds pushes the PPD and the...

Page 1754: ... the CPPI FIFO b The XDMA sees FIFO_empty not asserted and transfers 64 byte block from CPPI FIFO to Endpoint FIFO c The CDMA performs the above two steps a and b three more times since the data size of the HPD is 256 bytes 5 The CDMA reads the first buffer descriptor pointer PBD 6 For each 64 byte block of data in the packet data payload a The CDMA transfers a max burst of 64 byte block from the ...

Page 1755: ... also generate the required termination packet depending on the termination mode configured for the endpoint 16 3 9 9 1 4 Return Packet to Completion Queue and Interrupt CPU for Tx Step 4 1 After all data for the packet has been transmitted as specified by the packet size field the CDMA will write the pointer of the Packet Descriptor only to the TX Completion Queue specified in the return queue ma...

Page 1756: ...3 9 9 2 1 Receive Initialization Step 1 1 The CPU initializes Queue Manager with the Memory Region 0 base address and Memory Region 0 size Link RAM0 Base address Link RAM0 data size and Link RAM1 Base address 2 The CPU creates BDs and DBs in main memory and link them creating a BD and DB pairs 3 CPU then initializes the RXCQ queue and configures the Queue Manager Channel Setup DMA Scheduler and US...

Page 1757: ...s a transaction credit to the CDMA 2 The CDMA begins packet reception by fetching the first PBD from the Queue Manager using the Free Descriptor Buffer Queue 0 Rx Submit Queue index that was initialized in the RX port DMA state for that channel 3 The CDMA will then begin writing the 64 byte block of packet data into this DB 4 The CDMA will continue filling the buffer with additional 64 byte blocks...

Page 1758: ...ansmits a continuous J on the bus 16 3 10 3 TEST_K To enter the Test_K test mode the software should set the TEST_K bit in the TESTMODE register to 1 The USB controller will then go into a mode in which it transmits a continuous K on the bus 16 3 10 4 TEST_PACKET To execute the Test_Packet the software should 1 Start a session if the core is being used in Host mode 2 Write the standard test packet...

Page 1759: ... The data that was loaded in the Tx FIFO can now be read out of the Rx FIFO 16 3 10 6 FORCE_HOST The Force Host test mode enables you to instruct the core to operate in Host mode regardless of whether it is actually connected to any peripheral that is the state of the CID input and the LINESTATE and HOSTDISCON signals are ignored While in this mode the state of the HOSTDISCON signal can be read fr...

Page 1760: ...Ch IRQDMATHOLDTX13 Section 16 5 1 18 130h IRQDMATHOLDRX10 Section 16 5 1 19 134h IRQDMATHOLDRX11 Section 16 5 1 20 138h IRQDMATHOLDRX12 Section 16 5 1 21 13Ch IRQDMATHOLDRX13 Section 16 5 1 22 140h IRQDMAENABLE0 Section 16 5 1 23 144h IRQDMAENABLE1 Section 16 5 1 24 200h IRQFRAMETHOLDTX00 Section 16 5 1 25 204h IRQFRAMETHOLDTX01 Section 16 5 1 26 208h IRQFRAMETHOLDTX02 Section 16 5 1 27 20Ch IRQFR...

Page 1761: ...www ti com USB Registers 1761 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1762: ... n value after reset Table 16 30 REVREG Register Field Descriptions Bit Field Type Reset Description 31 30 SCHEME R 1h Used to distinguish between legacy interface scheme and current 0 Legacy 1 Current 27 16 FUNC R EA2h Function indicates a software compatible module family 15 11 R_RTL R 1h RTL revision Will vary depending on release 10 8 X_MAJOR R 0h Major revision 7 6 CUSTOM R 0h Custom revision...

Page 1763: ...tmi_clk 0 enable 1 disable 9 USB1_OCP_EN_N R W 0h Active low clock enable for usb1_ocp_clk 0 enable 1 disable 8 PHY1_UTMI_EN_N R W 0h Active low clock enable for phy1_utmi_clk 0 enable 1 disable 5 4 STANDBY_MODE R W 2h Configuration of the local initiator state management mode 0 force standby mode 1 no standby mode 2 smart standby mode 3 Reserved 3 2 IDLEMODE R W 2h Configuration of the local targ...

Page 1764: ...1 Rx CPPI DMA packet completion status 10 TX_PKT_CMP_1 R W 0h Interrupt status for USB1 Tx CPPI DMA packet completion status 9 RX_PKT_CMP_0 R W 0h Interrupt status for USB0 Rx CPPI DMA packet completion status 8 TX_PKT_CMP_0 R W 0h Interrupt status for USB0 Tx CPPI DMA packet completion status 2 PD_CMP_FLAG R W 0h Interrupt status when the packet is completed the differ bits is set and the Packet ...

Page 1765: ... CPPI DMA packet completion status 10 TX_PKT_CMP_1 R W 0h Interrupt status for USB1 Tx CPPI DMA packet completion status 9 RX_PKT_CMP_0 R W 0h Interrupt status for USB0 Rx CPPI DMA packet completion status 8 TX_PKT_CMP_0 R W 0h Interrupt status for USB0 Tx CPPI DMA packet completion status 2 PD_CMP_FLAG R W 0h Interrupt status when the packet is completed the differ bits is set and the Packet Desc...

Page 1766: ...1 Rx CPPI DMA packet completion status 10 TX_PKT_CMP_1 R W 0h Interrupt enable for USB1 Tx CPPI DMA packet completion status 9 RX_PKT_CMP_0 R W 0h Interrupt enable for USB0 Rx CPPI DMA packet completion status 8 TX_PKT_CMP_0 R W 0h Interrupt enable for USB0 Tx CPPI DMA packet completion status 2 PD_CMP_FLAG R W 0h Interrupt enable when the packet is completed the differ bits is set and the Packet ...

Page 1767: ...Rx CPPI DMA packet completion status 10 TX_PKT_CMP_1 R W 0h Interrupt enable for USB1 Tx CPPI DMA packet completion status 9 RX_PKT_CMP_0 R W 0h Interrupt enable for USB0 Rx CPPI DMA packet completion status 8 TX_PKT_CMP_0 R W 0h Interrupt enable for USB0 Tx CPPI DMA packet completion status 2 PD_CMP_FLAG R W 0h Interrupt enable when the packet is completed the differ bits is set and the Packet De...

Page 1768: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 36 IRQDMATHOLDTX00 Register Field Descriptions Bit Field Type Reset Description 31 24 DMA_THRES_TX0_3 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 3 23 16 DMA_THRES_TX0_2 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 2 15 8 DMA_THRES_TX0_1 R W 0h DMA threshold value for tx_pkt_cmp_0 for U...

Page 1769: ...ue after reset Table 16 37 IRQDMATHOLDTX01 Register Field Descriptions Bit Field Type Reset Description 31 24 DMA_THRES_TX0_7 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 7 23 16 DMA_THRES_TX0_6 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 6 15 8 DMA_THRES_TX0_5 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 5 7 0 DMA_THRES_TX0_4 R W 0h DMA threshol...

Page 1770: ...e after reset Table 16 38 IRQDMATHOLDTX02 Register Field Descriptions Bit Field Type Reset Description 31 24 DMA_THRES_TX0_11 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 11 23 16 DMA_THRES_TX0_10 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 10 15 8 DMA_THRES_TX0_9 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 9 7 0 DMA_THRES_TX0_8 R W 0h DMA thres...

Page 1771: ...e after reset Table 16 39 IRQDMATHOLDTX03 Register Field Descriptions Bit Field Type Reset Description 31 24 DMA_THRES_TX0_15 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 15 23 16 DMA_THRES_TX0_14 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 14 15 8 DMA_THRES_TX0_13 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB0 Endpoint 13 7 0 DMA_THRES_TX0_12 R W 0h DMA th...

Page 1772: ...ead Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 40 IRQDMATHOLDRX00 Register Field Descriptions Bit Field Type Reset Description 31 24 DMA_THRES_RX0_3 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 3 23 16 DMA_THRES_RX0_2 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 2 15 8 DMA_THRES_RX0_1 R W 0h DMA threshold value for rx_pkt_cmp_0 for ...

Page 1773: ...lue after reset Table 16 41 IRQDMATHOLDRX01 Register Field Descriptions Bit Field Type Reset Description 31 24 DMA_THRES_RX0_7 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 7 23 16 DMA_THRES_RX0_6 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 6 15 8 DMA_THRES_RX0_5 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 5 7 0 DMA_THRES_RX0_4 R W 0h DMA thresho...

Page 1774: ...ue after reset Table 16 42 IRQDMATHOLDRX02 Register Field Descriptions Bit Field Type Reset Description 31 24 DMA_THRES_RX0_11 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 11 23 16 DMA_THRES_RX0_10 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 10 15 8 DMA_THRES_RX0_9 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 9 7 0 DMA_THRES_RX0_8 R W 0h DMA thre...

Page 1775: ...e after reset Table 16 43 IRQDMATHOLDRX03 Register Field Descriptions Bit Field Type Reset Description 31 24 DMA_THRES_RX0_15 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 15 23 16 DMA_THRES_RX0_14 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 14 15 8 DMA_THRES_RX0_13 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB0 Endpoint 13 7 0 DMA_THRES_RX0_12 R W 0h DMA th...

Page 1776: ...ead Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 44 IRQDMATHOLDTX10 Register Field Descriptions Bit Field Type Reset Description 31 24 DMA_THRES_TX1_3 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 3 23 16 DMA_THRES_TX1_2 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 2 15 8 DMA_THRES_TX1_1 R W 0h DMA threshold value for tx_pkt_cmp_0 for ...

Page 1777: ...lue after reset Table 16 45 IRQDMATHOLDTX11 Register Field Descriptions Bit Field Type Reset Description 31 24 DMA_THRES_TX1_7 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 7 23 16 DMA_THRES_TX1_6 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 6 15 8 DMA_THRES_TX1_5 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 5 7 0 DMA_THRES_TX1_4 R W 0h DMA thresho...

Page 1778: ...ue after reset Table 16 46 IRQDMATHOLDTX12 Register Field Descriptions Bit Field Type Reset Description 31 24 DMA_THRES_TX1_11 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 11 23 16 DMA_THRES_TX1_10 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 10 15 8 DMA_THRES_TX1_9 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 9 7 0 DMA_THRES_TX1_8 R W 0h DMA thre...

Page 1779: ...e after reset Table 16 47 IRQDMATHOLDTX13 Register Field Descriptions Bit Field Type Reset Description 31 24 DMA_THRES_TX1_15 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 15 23 16 DMA_THRES_TX1_14 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 14 15 8 DMA_THRES_TX1_13 R W 0h DMA threshold value for tx_pkt_cmp_0 for USB1 Endpoint 13 7 0 DMA_THRES_TX1_12 R W 0h DMA th...

Page 1780: ...ead Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 48 IRQDMATHOLDRX10 Register Field Descriptions Bit Field Type Reset Description 31 24 DMA_THRES_RX1_3 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 3 23 16 DMA_THRES_RX1_2 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 2 15 8 DMA_THRES_RX1_1 R W 0h DMA threshold value for rx_pkt_cmp_0 for ...

Page 1781: ...lue after reset Table 16 49 IRQDMATHOLDRX11 Register Field Descriptions Bit Field Type Reset Description 31 24 DMA_THRES_RX1_7 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 7 23 16 DMA_THRES_RX1_6 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 6 15 8 DMA_THRES_RX1_5 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 5 7 0 DMA_THRES_RX1_4 R W 0h DMA thresho...

Page 1782: ...ue after reset Table 16 50 IRQDMATHOLDRX12 Register Field Descriptions Bit Field Type Reset Description 31 24 DMA_THRES_RX1_11 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 11 23 16 DMA_THRES_RX1_10 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 10 15 8 DMA_THRES_RX1_9 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 9 7 0 DMA_THRES_RX1_8 R W 0h DMA thre...

Page 1783: ...e after reset Table 16 51 IRQDMATHOLDRX13 Register Field Descriptions Bit Field Type Reset Description 31 24 DMA_THRES_RX1_15 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 15 23 16 DMA_THRES_RX1_14 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 14 15 8 DMA_THRES_RX1_13 R W 0h DMA threshold value for rx_pkt_cmp_0 for USB1 Endpoint 13 7 0 DMA_THRES_RX1_12 R W 0h DMA th...

Page 1784: ...alue after reset Table 16 52 IRQDMAENABLE0 Register Field Descriptions Bit Field Type Reset Description 31 DMA_EN_RX0_15 R W 0h DMA threshold enable value for rx_pkt_cmp_0 for USB0 Endpoint 15 17 DMA_EN_RX0_1 R W 0h DMA threshold enable value for rx_pkt_cmp_0 for USB0 Endpoint 1 15 DMA_EN_TX0_15 R W 0h DMA threshold enable value for tx_pkt_cmp_0 for USB0 Endpoint 15 2 DMA_EN_TX0_2 R W 0h DMA thres...

Page 1785: ...y W1toCl Write 1 to clear bit n value after reset Table 16 53 IRQDMAENABLE1 Register Field Descriptions Bit Field Type Reset Description 31 DMA_EN_RX1_15 R W 0h DMA threshold enable value for rx_pkt_cmp_1 for USB1 Endpoint 15 17 DMA_EN_RX1_1 R W 0h DMA threshold enable value for rx_pkt_cmp_1 for USB1 Endpoint 1 15 DMA_EN_TX1_15 R W 0h DMA threshold enable value for tx_pkt_cmp_1 for USB1 Endpoint 1...

Page 1786: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 54 IRQFRAMETHOLDTX00 Register Field Descriptions Bit Field Type Reset Description 31 24 FRAME_THRES_TX1_3 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint 3 23 16 FRAME_THRES_TX1_2 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint 2 15 8 FRAME_THRES_TX1_1 R W 0h FRAME threshold value for tx_p...

Page 1787: ... after reset Table 16 55 IRQFRAMETHOLDTX01 Register Field Descriptions Bit Field Type Reset Description 31 24 FRAME_THRES_TX1_7 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint 7 23 16 FRAME_THRES_TX1_6 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint 6 15 8 FRAME_THRES_TX1_5 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint 5 7 0 FRAME_THRES_TX1_4 R W 0...

Page 1788: ...after reset Table 16 56 IRQFRAMETHOLDTX02 Register Field Descriptions Bit Field Type Reset Description 31 24 FRAME_THRES_TX1_11 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint 11 23 16 FRAME_THRES_TX1_10 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint 10 15 8 FRAME_THRES_TX1_9 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint 9 7 0 FRAME_THRES_TX1_8 R ...

Page 1789: ...fter reset Table 16 57 IRQFRAMETHOLDTX03 Register Field Descriptions Bit Field Type Reset Description 31 24 FRAME_THRES_TX1_15 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint 15 23 16 FRAME_THRES_TX1_14 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint 14 15 8 FRAME_THRES_TX1_13 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB0 Endpoint 13 7 0 FRAME_THRES_TX1_12 ...

Page 1790: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 58 IRQFRAMETHOLDRX00 Register Field Descriptions Bit Field Type Reset Description 31 24 FRAME_THRES_RX1_3 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint 3 23 16 FRAME_THRES_RX1_2 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint 2 15 8 FRAME_THRES_RX1_1 R W 0h FRAME threshold value for rx_p...

Page 1791: ... after reset Table 16 59 IRQFRAMETHOLDRX01 Register Field Descriptions Bit Field Type Reset Description 31 24 FRAME_THRES_RX1_7 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint 7 23 16 FRAME_THRES_RX1_6 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint 6 15 8 FRAME_THRES_RX1_5 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint 5 7 0 FRAME_THRES_RX1_4 R W 0...

Page 1792: ...after reset Table 16 60 IRQFRAMETHOLDRX02 Register Field Descriptions Bit Field Type Reset Description 31 24 FRAME_THRES_RX1_11 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint 11 23 16 FRAME_THRES_RX1_10 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint 10 15 8 FRAME_THRES_RX1_9 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint 9 7 0 FRAME_THRES_RX1_8 R ...

Page 1793: ...fter reset Table 16 61 IRQFRAMETHOLDRX03 Register Field Descriptions Bit Field Type Reset Description 31 24 FRAME_THRES_RX1_15 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint 15 23 16 FRAME_THRES_RX1_14 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint 14 15 8 FRAME_THRES_RX1_13 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB0 Endpoint 13 7 0 FRAME_THRES_RX1_12 ...

Page 1794: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 62 IRQFRAMETHOLDTX10 Register Field Descriptions Bit Field Type Reset Description 31 24 FRAME_THRES_TX1_3 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint 3 23 16 FRAME_THRES_TX1_2 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint 2 15 8 FRAME_THRES_TX1_1 R W 0h FRAME threshold value for tx_p...

Page 1795: ... after reset Table 16 63 IRQFRAMETHOLDTX11 Register Field Descriptions Bit Field Type Reset Description 31 24 FRAME_THRES_TX1_7 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint 7 23 16 FRAME_THRES_TX1_6 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint 6 15 8 FRAME_THRES_TX1_5 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint 5 7 0 FRAME_THRES_TX1_4 R W 0...

Page 1796: ...after reset Table 16 64 IRQFRAMETHOLDTX12 Register Field Descriptions Bit Field Type Reset Description 31 24 FRAME_THRES_TX1_11 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint 11 23 16 FRAME_THRES_TX1_10 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint 10 15 8 FRAME_THRES_TX1_9 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint 9 7 0 FRAME_THRES_TX1_8 R ...

Page 1797: ...fter reset Table 16 65 IRQFRAMETHOLDTX13 Register Field Descriptions Bit Field Type Reset Description 31 24 FRAME_THRES_TX1_15 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint 15 23 16 FRAME_THRES_TX1_14 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint 14 15 8 FRAME_THRES_TX1_13 R W 0h FRAME threshold value for tx_pkt_cmp_0 for USB1 Endpoint 13 7 0 FRAME_THRES_TX1_12 ...

Page 1798: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 66 IRQFRAMETHOLDRX10 Register Field Descriptions Bit Field Type Reset Description 31 24 FRAME_THRES_RX1_3 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint 3 23 16 FRAME_THRES_RX1_2 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint 2 15 8 FRAME_THRES_RX1_1 R W 0h FRAME threshold value for rx_p...

Page 1799: ... after reset Table 16 67 IRQFRAMETHOLDRX11 Register Field Descriptions Bit Field Type Reset Description 31 24 FRAME_THRES_RX1_7 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint 7 23 16 FRAME_THRES_RX1_6 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint 6 15 8 FRAME_THRES_RX1_5 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint 5 7 0 FRAME_THRES_RX1_4 R W 0...

Page 1800: ...after reset Table 16 68 IRQFRAMETHOLDRX12 Register Field Descriptions Bit Field Type Reset Description 31 24 FRAME_THRES_RX1_11 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint 11 23 16 FRAME_THRES_RX1_10 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint 10 15 8 FRAME_THRES_RX1_9 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint 9 7 0 FRAME_THRES_RX1_8 R ...

Page 1801: ...fter reset Table 16 69 IRQFRAMETHOLDRX13 Register Field Descriptions Bit Field Type Reset Description 31 24 FRAME_THRES_RX1_15 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint 15 23 16 FRAME_THRES_RX1_14 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint 14 15 8 FRAME_THRES_RX1_13 R W 0h FRAME threshold value for rx_pkt_cmp_0 for USB1 Endpoint 13 7 0 FRAME_THRES_RX1_12 ...

Page 1802: ...W1toCl Write 1 to clear bit n value after reset Table 16 70 IRQFRAMEENABLE0 Register Field Descriptions Bit Field Type Reset Description 31 FRAME_EN_RX0_15 R W 0h FRAME threshold enable value for rx_pkt_cmp_0 for USB0 Endpoint 15 17 FRAME_EN_RX0_1 R W 0h FRAME threshold enable value for rx_pkt_cmp_0 for USB0 Endpoint 1 15 FRAME_EN_TX0_15 R W 0h FRAME threshold enable value for tx_pkt_cmp_0 for USB...

Page 1803: ...r rx_pkt_cmp_1 for USB1 Endpoint 1 15 FRAME_EN_TX1_15 R W 0h FRAME threshold enable value for tx_pkt_cmp_1 for USB1 Endpoint 15 1 FRAME_EN_TX1_1 R W 0h FRAME threshold enable value for tx_pkt_cmp_1 for USB1 Endpoint 1 16 5 2 USB0_CTRL Registers Table 16 72 lists the memory mapped registers for the USB0_CTRL All register offset addresses not listed in Table 16 72 should be considered as reserved lo...

Page 1804: ...ENRNDISEP6 Section 16 5 2 20 98h USB0GENRNDISEP7 Section 16 5 2 21 9Ch USB0GENRNDISEP8 Section 16 5 2 22 A0h USB0GENRNDISEP9 Section 16 5 2 23 A4h USB0GENRNDISEP10 Section 16 5 2 24 A8h USB0GENRNDISEP11 Section 16 5 2 25 ACh USB0GENRNDISEP12 Section 16 5 2 26 B0h USB0GENRNDISEP13 Section 16 5 2 27 B4h USB0GENRNDISEP14 Section 16 5 2 28 B8h USB0GENRNDISEP15 Section 16 5 2 29 D0h USB0AUTOREQ Section...

Page 1805: ...it n value after reset Table 16 73 USB0REV Register Field Descriptions Bit Field Type Reset Description 31 30 SCHEME R 1h Used to distinguish between legacy interface scheme and current 0 Legacy 1 Current 27 16 FUNC R EA2h Function indicates a software compatible module family 15 11 R_RTL R 1h RTL revision Will vary depending on release 10 8 X_MAJOR R 0h Major revision 7 6 CUSTOM R 0h Custom revis...

Page 1806: ...ix Time Register 5 SOFT_RESET_ISOLATIO R W 0h Soft reset isolation N When high this bit forces all USB0 signals that connect to the USBSS to known values during a soft reset via bit 0 of this register This bit should be set high prior to setting bit 0 and cleared after bit 0 is cleared 4 RNDIS R W 0h Global RNDIS mode enable for all endpoints 3 UINT R W 0h USB interrupt enable 1 Legacy 0 Current r...

Page 1807: ...ultiplexers This removes the possibility of timing errors due to the asynchronous resets All USB0 registers will be reset The USB0 resets will be de asserted The reset isolation multiplexer inputs will be de selected Both the soft_reset and soft_reset_isolation bits will be automatically cleared Setting only the soft_reset_isolation bit will cause all USB0 output signals to go to a known constant ...

Page 1808: ...2 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DRV VBU S R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 75 USB0STAT Register Field Descriptions Bit Field Type Reset Description 0 DRVVBUS R 0h Current DRVVBUS value USB0 Status Register 1808 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas...

Page 1809: ... Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 76 USB0IRQMSTAT Register Field Descriptions Bit Field Type Reset Description 1 BANK1 R 0h 0 No events pending from IRQ_STATUS_1 1 At least one event is pending from IRQ_STATUS_1 0 BANK0 R 0h 0 No events pending from IRQ_STATUS_0 1 At least one event is pending from IRQ_STATUS_0 USB0 IRQ_MERGED_STATUS Register 1809 SPRUH73H...

Page 1810: ...h Interrupt status for RX endpoint 12 27 RX_EP_11 R W 0h Interrupt status for RX endpoint 11 26 RX_EP_10 R W 0h Interrupt status for RX endpoint 10 25 RX_EP_9 R W 0h Interrupt status for RX endpoint 9 24 RX_EP_8 R W 0h Interrupt status for RX endpoint 8 23 RX_EP_7 R W 0h Interrupt status for RX endpoint 7 22 RX_EP_6 R W 0h Interrupt status for RX endpoint 6 21 RX_EP_5 R W 0h Interrupt status for R...

Page 1811: ...s for TX endpoint 4 3 TX_EP_3 R W 0h Interrupt status for TX endpoint 3 2 TX_EP_2 R W 0h Interrupt status for TX endpoint 2 1 TX_EP_1 R W 0h Interrupt status for TX endpoint 1 0 TX_EP_0 R W 0h Interrupt status for TX endpoint 0 USB0 IRQ_STATUS_RAW_0 Register 1811 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments In...

Page 1812: ... endpoint 11 26 TX_FIFO_10 R W 0h Interrupt status for TX FIFO endpoint 10 25 TX_FIFO_9 R W 0h Interrupt status for TX FIFO endpoint 9 24 TX_FIFO_8 R W 0h Interrupt status for TX FIFO endpoint 8 23 TX_FIFO_7 R W 0h Interrupt status for TX FIFO endpoint 7 22 TX_FIFO_6 R W 0h Interrupt status for TX FIFO endpoint 6 21 TX_FIFO_5 R W 0h Interrupt status for TX FIFO endpoint 5 20 TX_FIFO_4 R W 0h Inter...

Page 1813: ...cription 1 USB_1 R W 0h Interrupt status for Resume signaling detected 0 USB_0 R W 0h Interrupt status for Suspend signaling detected USB0 IRQ_STATUS_RAW_1 Register 1813 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1814: ...rrupt status for RX endpoint 12 27 RX_EP_11 R W 0h Interrupt status for RX endpoint 11 26 RX_EP_10 R W 0h Interrupt status for RX endpoint 10 25 RX_EP_9 R W 0h Interrupt status for RX endpoint 9 24 RX_EP_8 R W 0h Interrupt status for RX endpoint 8 23 RX_EP_7 R W 0h Interrupt status for RX endpoint 7 22 RX_EP_6 R W 0h Interrupt status for RX endpoint 6 21 RX_EP_5 R W 0h Interrupt status for RX endp...

Page 1815: ...s for TX endpoint 4 3 TX_EP_3 R W 0h Interrupt status for TX endpoint 3 2 TX_EP_2 R W 0h Interrupt status for TX endpoint 2 1 TX_EP_1 R W 0h Interrupt status for TX endpoint 1 0 TX_EP_0 R W 0h Interrupt status for TX endpoint 0 USB0 IRQ_STATUS_0 Register 1815 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorp...

Page 1816: ...int 11 26 TX_FIFO_10 R W 0h Interrupt status for TX FIFO endpoint 10 25 TX_FIFO_9 R W 0h Interrupt status for TX FIFO endpoint 9 24 TX_FIFO_8 R W 0h Interrupt status for TX FIFO endpoint 8 23 TX_FIFO_7 R W 0h Interrupt status for TX FIFO endpoint 7 22 TX_FIFO_6 R W 0h Interrupt status for TX FIFO endpoint 6 21 TX_FIFO_5 R W 0h Interrupt status for TX FIFO endpoint 5 20 TX_FIFO_4 R W 0h Interrupt s...

Page 1817: ...scription 1 USB_1 R W 0h Interrupt status for Resume signaling detected 0 USB_0 R W 0h Interrupt status for Suspend signaling detected USB0 IRQ_STATUS_1 Register 1817 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1818: ... W 0h Interrupt enable for RX endpoint 12 27 RX_EP_11 R W 0h Interrupt enable for RX endpoint 11 26 RX_EP_10 R W 0h Interrupt enable for RX endpoint 10 25 RX_EP_9 R W 0h Interrupt enable for RX endpoint 9 24 RX_EP_8 R W 0h Interrupt enable for RX endpoint 8 23 RX_EP_7 R W 0h Interrupt enable for RX endpoint 7 22 RX_EP_6 R W 0h Interrupt enable for RX endpoint 6 21 RX_EP_5 R W 0h Interrupt enable f...

Page 1819: ...le for TX endpoint 4 3 TX_EP_3 R W 0h Interrupt enable for TX endpoint 3 2 TX_EP_2 R W 0h Interrupt enable for TX endpoint 2 1 TX_EP_1 R W 0h Interrupt enable for TX endpoint 1 0 TX_EP_0 R W 0h Interrupt enable for TX endpoint 0 USB0 IRQ_ENABLE_SET_0 Register 1819 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments I...

Page 1820: ...FIFO endpoint 11 26 TX_FIFO_10 R W 0h Interrupt enable for TX FIFO endpoint 10 25 TX_FIFO_9 R W 0h Interrupt enable for TX FIFO endpoint 9 24 TX_FIFO_8 R W 0h Interrupt enable for TX FIFO endpoint 8 23 TX_FIFO_7 R W 0h Interrupt enable for TX FIFO endpoint 7 22 TX_FIFO_6 R W 0h Interrupt enable for TX FIFO endpoint 6 21 TX_FIFO_5 R W 0h Interrupt enable for TX FIFO endpoint 5 20 TX_FIFO_4 R W 0h I...

Page 1821: ...scription 1 USB_1 R W 0h Interrupt enable for Resume signaling detected 0 USB_0 R W 0h Interrupt enable for Suspend signaling detected USB0 IRQ_ENABLE_SET_1 Register 1821 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1822: ... W 0h Interrupt enable for RX endpoint 12 27 RX_EP_11 R W 0h Interrupt enable for RX endpoint 11 26 RX_EP_10 R W 0h Interrupt enable for RX endpoint 10 25 RX_EP_9 R W 0h Interrupt enable for RX endpoint 9 24 RX_EP_8 R W 0h Interrupt enable for RX endpoint 8 23 RX_EP_7 R W 0h Interrupt enable for RX endpoint 7 22 RX_EP_6 R W 0h Interrupt enable for RX endpoint 6 21 RX_EP_5 R W 0h Interrupt enable f...

Page 1823: ...le for TX endpoint 4 3 TX_EP_3 R W 0h Interrupt enable for TX endpoint 3 2 TX_EP_2 R W 0h Interrupt enable for TX endpoint 2 1 TX_EP_1 R W 0h Interrupt enable for TX endpoint 1 0 TX_EP_0 R W 0h Interrupt enable for TX endpoint 0 USB0 IRQ_ENABLE_CLR_0 Register 1823 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments I...

Page 1824: ...FIFO endpoint 11 26 TX_FIFO_10 R W 0h Interrupt enable for TX FIFO endpoint 10 25 TX_FIFO_9 R W 0h Interrupt enable for TX FIFO endpoint 9 24 TX_FIFO_8 R W 0h Interrupt enable for TX FIFO endpoint 8 23 TX_FIFO_7 R W 0h Interrupt enable for TX FIFO endpoint 7 22 TX_FIFO_6 R W 0h Interrupt enable for TX FIFO endpoint 6 21 TX_FIFO_5 R W 0h Interrupt enable for TX FIFO endpoint 5 20 TX_FIFO_4 R W 0h I...

Page 1825: ...scription 1 USB_1 R W 0h Interrupt enable for Resume signaling detected 0 USB_0 R W 0h Interrupt enable for Suspend signaling detected USB0 IRQ_ENABLE_CLR_1 Register 1825 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1826: ...rent Mode on TX endpoint 12 01 RNDIS Mode on TX endpoint 12 10 CDC Mode on TX endpoint 12 11 Generic RNDIS Mode on TX endpoint 12 23 22 TX12_MODE R W 0h 00 Transparent Mode on TX endpoint 11 01 RNDIS Mode on TX endpoint 11 10 CDC Mode on TX endpoint 11 11 Generic RNDIS Mode on TX endpoint 11 21 20 TX11_MODE R W 0h 00 Transparent Mode on TX endpoint 10 01 RNDIS Mode on TX endpoint 10 10 CDC Mode on...

Page 1827: ...int 3 10 CDC Mode on TX endpoint 3 11 Generic RNDIS Mode on TX endpoint 3 5 4 TX3_MODE R W 0h 00 Transparent Mode on TX endpoint 2 01 RNDIS Mode on TX endpoint 2 10 CDC Mode on TX endpoint 2 11 Generic RNDIS Mode on TX endpoint 2 3 2 TX2_MODE R W 0h 00 Transparent Mode on TX endpoint 1 01 RNDIS Mode on TX endpoint 1 10 CDC Mode on TX endpoint 1 11 Generic RNDIS Mode on TX endpoint 1 1 0 TX1_MODE R...

Page 1828: ... 12 01 RNDIS Mode on RX endpoint 12 10 CDC Mode on RX endpoint 12 11 Generic RNDIS or Infinite Mode on RX endpoint 12 23 22 RX12_MODE R W 0h 00 Transparent Mode on RX endpoint 11 01 RNDIS Mode on RX endpoint 11 10 CDC Mode on RX endpoint 11 11 Generic RNDIS or Infinite Mode on RX endpoint 11 21 20 RX11_MODE R W 0h 00 Transparent Mode on RX endpoint 10 01 RNDIS Mode on RX endpoint 10 10 CDC Mode on...

Page 1829: ...4 7 6 RX4_MODE R W 0h 00 Transparent Mode on RX endpoint 3 01 RNDIS Mode on RX endpoint 3 10 CDC Mode on RX endpoint 3 11 Generic RNDIS or Infinite Mode on RX endpoint 3 5 4 RX3_MODE R W 0h 00 Transparent Mode on RX endpoint 2 01 RNDIS Mode on RX endpoint 2 10 CDC Mode on RX endpoint 2 11 Generic RNDIS or Infinite Mode on RX endpoint 2 3 2 RX2_MODE R W 0h 00 Transparent Mode on RX endpoint 1 01 RN...

Page 1830: ...ultiple of the USB max packet size a zero length terminating packet is used XDMA recognizes this terminating packet on reception and generates it on transmission Designed for use in an RNDIS compliant networking type of USB device and bulk endpoints Linux CDC mode b10 Same as RNDIS mode except terminating packet has 1 byte of 0 data Designed for use with a Linux OS and USB driver stack and bulk en...

Page 1831: ...ets from the Mentor controller until a short packet is received When the CPPI is configured for chaining mode the Buffer Descriptor sizes must be integer multiples of the RXMAXP size Transmit mode is not supported USB0 or USB1 Auto Req register should be set to AUTO REQ ALWAYS 1831 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 T...

Page 1832: ...0 9 8 7 6 5 4 3 2 1 0 Reserved EP1_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 87 USB0GENRNDISEP1 Register Field Descriptions Bit Field Type Reset Description 16 0 EP1_SIZE R W 0h Generic RNDIS packet size USB0 Generic RNDIS EP N Size Register 1832 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedb...

Page 1833: ...0 9 8 7 6 5 4 3 2 1 0 Reserved EP2_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 88 USB0GENRNDISEP2 Register Field Descriptions Bit Field Type Reset Description 16 0 EP2_SIZE R W 0h Generic RNDIS packet size USB0 Generic RNDIS EP N Size Register 1833 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedb...

Page 1834: ...0 9 8 7 6 5 4 3 2 1 0 Reserved EP3_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 89 USB0GENRNDISEP3 Register Field Descriptions Bit Field Type Reset Description 16 0 EP3_SIZE R W 0h Generic RNDIS packet size USB0 Generic RNDIS EP N Size Register 1834 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedb...

Page 1835: ...0 9 8 7 6 5 4 3 2 1 0 Reserved EP4_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 90 USB0GENRNDISEP4 Register Field Descriptions Bit Field Type Reset Description 16 0 EP4_SIZE R W 0h Generic RNDIS packet size USB0 Generic RNDIS EP N Size Register 1835 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedb...

Page 1836: ...0 9 8 7 6 5 4 3 2 1 0 Reserved EP5_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 91 USB0GENRNDISEP5 Register Field Descriptions Bit Field Type Reset Description 16 0 EP5_SIZE R W 0h Generic RNDIS packet size USB0 Generic RNDIS EP N Size Register 1836 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedb...

Page 1837: ...0 9 8 7 6 5 4 3 2 1 0 Reserved EP6_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 92 USB0GENRNDISEP6 Register Field Descriptions Bit Field Type Reset Description 16 0 EP6_SIZE R W 0h Generic RNDIS packet size USB0 Generic RNDIS EP N Size Register 1837 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedb...

Page 1838: ...0 9 8 7 6 5 4 3 2 1 0 Reserved EP7_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 93 USB0GENRNDISEP7 Register Field Descriptions Bit Field Type Reset Description 16 0 EP7_SIZE R W 0h Generic RNDIS packet size USB0 Generic RNDIS EP N Size Register 1838 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedb...

Page 1839: ...0 9 8 7 6 5 4 3 2 1 0 Reserved EP8_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 94 USB0GENRNDISEP8 Register Field Descriptions Bit Field Type Reset Description 16 0 EP8_SIZE R W 0h Generic RNDIS packet size USB0 Generic RNDIS EP N Size Register 1839 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedb...

Page 1840: ...0 9 8 7 6 5 4 3 2 1 0 Reserved EP9_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 95 USB0GENRNDISEP9 Register Field Descriptions Bit Field Type Reset Description 16 0 EP9_SIZE R W 0h Generic RNDIS packet size USB0 Generic RNDIS EP N Size Register 1840 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedb...

Page 1841: ...0 9 8 7 6 5 4 3 2 1 0 Reserved EP10_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 96 USB0GENRNDISEP10 Register Field Descriptions Bit Field Type Reset Description 16 0 EP10_SIZE R W 0h Generic RNDIS packet size USB0 Generic RNDIS EP N Size Register 1841 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Fe...

Page 1842: ...0 9 8 7 6 5 4 3 2 1 0 Reserved EP11_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 97 USB0GENRNDISEP11 Register Field Descriptions Bit Field Type Reset Description 16 0 EP11_SIZE R W 0h Generic RNDIS packet size USB0 Generic RNDIS EP N Size Register 1842 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Fe...

Page 1843: ...0 9 8 7 6 5 4 3 2 1 0 Reserved EP12_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 98 USB0GENRNDISEP12 Register Field Descriptions Bit Field Type Reset Description 16 0 EP12_SIZE R W 0h Generic RNDIS packet size USB0 Generic RNDIS EP N Size Register 1843 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Fe...

Page 1844: ...0 9 8 7 6 5 4 3 2 1 0 Reserved EP13_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 99 USB0GENRNDISEP13 Register Field Descriptions Bit Field Type Reset Description 16 0 EP13_SIZE R W 0h Generic RNDIS packet size USB0 Generic RNDIS EP N Size Register 1844 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Fe...

Page 1845: ...0 9 8 7 6 5 4 3 2 1 0 Reserved EP14_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 100 USB0GENRNDISEP14 Register Field Descriptions Bit Field Type Reset Description 16 0 EP14_SIZE R W 0h Generic RNDIS packet size USB0 Generic RNDIS EP N Size Register 1845 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation F...

Page 1846: ...0 9 8 7 6 5 4 3 2 1 0 Reserved EP15_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 101 USB0GENRNDISEP15 Register Field Descriptions Bit Field Type Reset Description 16 0 EP15_SIZE R W 0h Generic RNDIS packet size USB0 Generic RNDIS EP N Size Register 1846 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation F...

Page 1847: ...ys 27 26 RX14_AUTOREQ R W 0h RX endpoint 13 Auto Req enable 00 no auto req 01 auto req on all but EOP 10 reserved 11 auto req always 25 24 RX13_AUTOREQ R W 0h RX endpoint 12 Auto Req enable 00 no auto req 01 auto req on all but EOP 10 reserved 11 auto req always 23 22 RX12_AUTOREQ R W 0h RX endpoint 11 Auto Req enable 00 no auto req 01 auto req on all but EOP 10 reserved 11 auto req always 21 20 R...

Page 1848: ...o req always 7 6 RX4_AUTOREQ R W 0h RX endpoint 3 Auto Req enable 00 no auto req 01 auto req on all but EOP 10 reserved 11 auto req always 5 4 RX3_AUTOREQ R W 0h RX endpoint 2 Auto Req enable 00 no auto req 01 auto req on all but EOP 10 reserved 11 auto req always 3 2 RX2_AUTOREQ R W 0h RX endpoint 1 Auto Req enable 00 no auto req 01 auto req on all but EOP 10 reserved 11 auto req always 1 0 RX1_A...

Page 1849: ... 4 3 2 1 0 SRPFIXTIME R W 280DE80h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 103 USB0SRPFIXTIME Register Field Descriptions Bit Field Type Reset Description 31 0 SRPFIXTIME R W 280DE80h SRP Fix maximum time in 60 MHz cycles Default is 700 ms USB0 SRP Fix Time Register 1849 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Docu...

Page 1850: ...ead Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 104 USB0_TDOWN Register Field Descriptions Bit Field Type Reset Description 31 17 TX_TDOWN R W 0h Tx Endpoint Teardown Write 1 to corresponding bit to set Read as 0 Bit 31 Endpoint 15 Bit 17 Endpoint 1 15 1 RX_TDOWN R W 0h RX Endpoint Teardown Write 1 to corresponding bit to set Read as 0 Bit 15 Endpoint 15 Bit 1 Endpoi...

Page 1851: ...ITSTUFFEN R W 0h PHY UTMI input for signal txbitstuffen 22 TXBITSTUFFENH R W 0h PHY UTMI input for signal txbitstuffenh 21 OTGDISABLE R W 1h PHY UTMI input for signal otgdisable 20 VBUSVLDEXTSEL R W 0h PHY UTMI input for signal vbusvldextsel 19 VBUSVLDEXT R W 0h PHY UTMI input for signal vbusvldext 18 TXENABLEN R W 0h PHY UTMI input for signal txenablen 17 FSXCVROWNER R W 0h PHY UTMI input for sig...

Page 1852: ...e for opmode 25 TXVALID R 0h loopback test observed value for txvalid 24 23 XCVRSEL R 0h loopback test observed value for xcvrsel 22 TERMSEL R 0h loopback test observed value for termsel 21 DRVVBUS R 0h loopback test observed value for drvvbus 20 CHRGVBUS R 0h loopback test observed value for chrgvbus 19 DISCHRGVBUS R 0h loopback test observed value for dischrgvbus 18 DPPULLDOWN R 0h loopback test...

Page 1853: ...K R W 0h Loopback test mode 0 Normal mode 1 Loopback test mode USB0 Mode Register 16 5 3 USB1_CTRL Registers Table 16 108 lists the memory mapped registers for the USB1_CTRL All register offset addresses not listed in Table 16 108 should be considered as reserved locations and the register contents should not be modified Table 16 108 USB1_CTRL REGISTERS Offset Acronym Register Name Section 0h USB1...

Page 1854: ... 16 5 3 22 A0h USB1GENRNDISEP9 Section 16 5 3 23 A4h USB1GENRNDISEP10 Section 16 5 3 24 A8h USB1GENRNDISEP11 Section 16 5 3 25 ACh USB1GENRNDISEP12 Section 16 5 3 26 B0h USB1GENRNDISEP13 Section 16 5 3 27 B4h USB1GENRNDISEP14 Section 16 5 3 28 B8h USB1GENRNDISEP15 Section 16 5 3 29 D0h USB1AUTOREQ Section 16 5 3 30 D4h USB1SRPFIXTIME Section 16 5 3 31 D8h USB1TDOWN Section 16 5 3 32 E0h USB1UTMI S...

Page 1855: ...it n value after reset Table 16 109 USB1REV Register Field Descriptions Bit Field Type Reset Description 31 30 SCHEME R 1h Used to distinguish between legacy interface scheme and current 0 Legacy 1 Current 27 16 FUNC R EA2h Function indicates a software compatible module family 15 11 R_RTL R 1h RTL revision Will vary depending on release 10 8 X_MAJOR R 0h Major revision 7 6 CUSTOM R 0h Custom revi...

Page 1856: ... Fix Time Register 5 SOFT_RESET_ISOLATIO R W 0h Soft reset isolation N When high this bit forces all USB1 signals that connect to the USBSS to known values during a soft reset via bit 0 of this register This bit should be set high prior to setting bit 0 and cleared after bit 0 is cleared 4 RNDIS R W 0h Global RNDIS mode enable for all endpoints 3 UINT R W 0h USB interrupt enable 1 Legacy 0 Current...

Page 1857: ...multiplexers This removes the possibility of timing errors due to the asynchronous resets All USB0 registers will be reset The USB0 resets will be de asserted The reset isolation multiplexer inputs will be de selected Both the soft_reset and soft_reset_isolation bits will be automatically cleared Setting only the soft_reset_isolation bit will cause all USB0 output signals to go to a known constant...

Page 1858: ...12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DRV VBU S R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 111 USB1STAT Register Field Descriptions Bit Field Type Reset Description 0 DRVVBUS R 0h Current DRVVBUS value USB1 Status Register 1858 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Tex...

Page 1859: ...d Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 112 USB1IRQMSTAT Register Field Descriptions Bit Field Type Reset Description 1 BANK1 R 0h 0 No events pending from IRQ_STATUS_1 1 At least one event is pending from IRQ_STATUS_1 0 BANK0 R 0h 0 No events pending from IRQ_STATUS_0 1 At least one event is pending from IRQ_STATUS_0 USB1 IRQ_MERGED_STATUS Register 1859 SPRUH7...

Page 1860: ... 0h Interrupt status for RX endpoint 12 27 RX_EP_11 R W 0h Interrupt status for RX endpoint 11 26 RX_EP_10 R W 0h Interrupt status for RX endpoint 10 25 RX_EP_9 R W 0h Interrupt status for RX endpoint 9 24 RX_EP_8 R W 0h Interrupt status for RX endpoint 8 23 RX_EP_7 R W 0h Interrupt status for RX endpoint 7 22 RX_EP_6 R W 0h Interrupt status for RX endpoint 6 21 RX_EP_5 R W 0h Interrupt status for...

Page 1861: ...s for TX endpoint 4 3 TX_EP_3 R W 0h Interrupt status for TX endpoint 3 2 TX_EP_2 R W 0h Interrupt status for TX endpoint 2 1 TX_EP_1 R W 0h Interrupt status for TX endpoint 1 0 TX_EP_0 R W 0h Interrupt status for TX endpoint 0 USB1 IRQ_STATUS_RAW_0 Register 1861 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments In...

Page 1862: ...dpoint 11 26 TX_FIFO_10 R W 0h Interrupt status for TX FIFO endpoint 10 25 TX_FIFO_9 R W 0h Interrupt status for TX FIFO endpoint 9 24 TX_FIFO_8 R W 0h Interrupt status for TX FIFO endpoint 8 23 TX_FIFO_7 R W 0h Interrupt status for TX FIFO endpoint 7 22 TX_FIFO_6 R W 0h Interrupt status for TX FIFO endpoint 6 21 TX_FIFO_5 R W 0h Interrupt status for TX FIFO endpoint 5 20 TX_FIFO_4 R W 0h Interrup...

Page 1863: ...ntinued Bit Field Type Reset Description 0 USB_0 R W 0h Interrupt status for Suspend signaling detected USB1 IRQ_STATUS_RAW_1 Register 1863 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1864: ...terrupt status for RX endpoint 12 27 RX_EP_11 R W 0h Interrupt status for RX endpoint 11 26 RX_EP_10 R W 0h Interrupt status for RX endpoint 10 25 RX_EP_9 R W 0h Interrupt status for RX endpoint 9 24 RX_EP_8 R W 0h Interrupt status for RX endpoint 8 23 RX_EP_7 R W 0h Interrupt status for RX endpoint 7 22 RX_EP_6 R W 0h Interrupt status for RX endpoint 6 21 RX_EP_5 R W 0h Interrupt status for RX en...

Page 1865: ...us for TX endpoint 4 3 TX_EP_3 R W 0h Interrupt status for TX endpoint 3 2 TX_EP_2 R W 0h Interrupt status for TX endpoint 2 1 TX_EP_1 R W 0h Interrupt status for TX endpoint 1 0 TX_EP_0 R W 0h Interrupt status for TX endpoint 0 USB1 IRQ_STATUS_0 Register 1865 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incor...

Page 1866: ... 11 26 TX_FIFO_10 R W 0h Interrupt status for TX FIFO endpoint 10 25 TX_FIFO_9 R W 0h Interrupt status for TX FIFO endpoint 9 24 TX_FIFO_8 R W 0h Interrupt status for TX FIFO endpoint 8 23 TX_FIFO_7 R W 0h Interrupt status for TX FIFO endpoint 7 22 TX_FIFO_6 R W 0h Interrupt status for TX FIFO endpoint 6 21 TX_FIFO_5 R W 0h Interrupt status for TX FIFO endpoint 5 20 TX_FIFO_4 R W 0h Interrupt stat...

Page 1867: ...ntinued Bit Field Type Reset Description 0 USB_0 R W 0h Interrupt status for Suspend signaling detected USB1 IRQ_STATUS_1 Register 1867 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1868: ... R W 0h Interrupt enable for RX endpoint 12 27 RX_EP_11 R W 0h Interrupt enable for RX endpoint 11 26 RX_EP_10 R W 0h Interrupt enable for RX endpoint 10 25 RX_EP_9 R W 0h Interrupt enable for RX endpoint 9 24 RX_EP_8 R W 0h Interrupt enable for RX endpoint 8 23 RX_EP_7 R W 0h Interrupt enable for RX endpoint 7 22 RX_EP_6 R W 0h Interrupt enable for RX endpoint 6 21 RX_EP_5 R W 0h Interrupt enable...

Page 1869: ...le for TX endpoint 4 3 TX_EP_3 R W 0h Interrupt enable for TX endpoint 3 2 TX_EP_2 R W 0h Interrupt enable for TX endpoint 2 1 TX_EP_1 R W 0h Interrupt enable for TX endpoint 1 0 TX_EP_0 R W 0h Interrupt enable for TX endpoint 0 USB1 IRQ_ENABLE_SET_0 Register 1869 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments I...

Page 1870: ...O endpoint 11 26 TX_FIFO_10 R W 0h Interrupt enable for TX FIFO endpoint 10 25 TX_FIFO_9 R W 0h Interrupt enable for TX FIFO endpoint 9 24 TX_FIFO_8 R W 0h Interrupt enable for TX FIFO endpoint 8 23 TX_FIFO_7 R W 0h Interrupt enable for TX FIFO endpoint 7 22 TX_FIFO_6 R W 0h Interrupt enable for TX FIFO endpoint 6 21 TX_FIFO_5 R W 0h Interrupt enable for TX FIFO endpoint 5 20 TX_FIFO_4 R W 0h Inte...

Page 1871: ...ontinued Bit Field Type Reset Description 0 USB_0 R W 0h Interrupt enable for Suspend signaling detected USB1 IRQ_ENABLE_SET_1 Register 1871 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1872: ... R W 0h Interrupt enable for RX endpoint 12 27 RX_EP_11 R W 0h Interrupt enable for RX endpoint 11 26 RX_EP_10 R W 0h Interrupt enable for RX endpoint 10 25 RX_EP_9 R W 0h Interrupt enable for RX endpoint 9 24 RX_EP_8 R W 0h Interrupt enable for RX endpoint 8 23 RX_EP_7 R W 0h Interrupt enable for RX endpoint 7 22 RX_EP_6 R W 0h Interrupt enable for RX endpoint 6 21 RX_EP_5 R W 0h Interrupt enable...

Page 1873: ...le for TX endpoint 4 3 TX_EP_3 R W 0h Interrupt enable for TX endpoint 3 2 TX_EP_2 R W 0h Interrupt enable for TX endpoint 2 1 TX_EP_1 R W 0h Interrupt enable for TX endpoint 1 0 TX_EP_0 R W 0h Interrupt enable for TX endpoint 0 USB1 IRQ_ENABLE_CLR_0 Register 1873 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments I...

Page 1874: ...O endpoint 11 26 TX_FIFO_10 R W 0h Interrupt enable for TX FIFO endpoint 10 25 TX_FIFO_9 R W 0h Interrupt enable for TX FIFO endpoint 9 24 TX_FIFO_8 R W 0h Interrupt enable for TX FIFO endpoint 8 23 TX_FIFO_7 R W 0h Interrupt enable for TX FIFO endpoint 7 22 TX_FIFO_6 R W 0h Interrupt enable for TX FIFO endpoint 6 21 TX_FIFO_5 R W 0h Interrupt enable for TX FIFO endpoint 5 20 TX_FIFO_4 R W 0h Inte...

Page 1875: ...ontinued Bit Field Type Reset Description 0 USB_0 R W 0h Interrupt enable for Suspend signaling detected USB1 IRQ_ENABLE_CLR_1 Register 1875 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1876: ...parent Mode on TX endpoint 12 01 RNDIS Mode on TX endpoint 12 10 CDC Mode on TX endpoint 12 11 Generic RNDIS Mode on TX endpoint 12 23 22 TX12_MODE R W 0h 00 Transparent Mode on TX endpoint 11 01 RNDIS Mode on TX endpoint 11 10 CDC Mode on TX endpoint 11 11 Generic RNDIS Mode on TX endpoint 11 21 20 TX11_MODE R W 0h 00 Transparent Mode on TX endpoint 10 01 RNDIS Mode on TX endpoint 10 10 CDC Mode ...

Page 1877: ...oint 3 10 CDC Mode on TX endpoint 3 11 Generic RNDIS Mode on TX endpoint 3 5 4 TX3_MODE R W 0h 00 Transparent Mode on TX endpoint 2 01 RNDIS Mode on TX endpoint 2 10 CDC Mode on TX endpoint 2 11 Generic RNDIS Mode on TX endpoint 2 3 2 TX2_MODE R W 0h 00 Transparent Mode on TX endpoint 1 01 RNDIS Mode on TX endpoint 1 10 CDC Mode on TX endpoint 1 11 Generic RNDIS Mode on TX endpoint 1 1 0 TX1_MODE ...

Page 1878: ...01 RNDIS Mode on RX endpoint 12 10 CDC Mode on RX endpoint 12 11 Generic RNDIS or Infinite Mode on RX endpoint 12 23 22 RX12_MODE R W 0h 00 Transparent Mode on RX endpoint 11 01 RNDIS Mode on RX endpoint 11 10 CDC Mode on RX endpoint 11 11 Generic RNDIS or Infinite Mode on RX endpoint 11 21 20 RX11_MODE R W 0h 00 Transparent Mode on RX endpoint 10 01 RNDIS Mode on RX endpoint 10 10 CDC Mode on RX ...

Page 1879: ...C Mode on RX endpoint 3 11 Generic RNDIS or Infinite Mode on RX endpoint 3 5 4 RX3_MODE R W 0h 00 Transparent Mode on RX endpoint 2 01 RNDIS Mode on RX endpoint 2 10 CDC Mode on RX endpoint 2 11 Generic RNDIS or Infinite Mode on RX endpoint 2 3 2 RX2_MODE R W 0h 00 Transparent Mode on RX endpoint 1 01 RNDIS Mode on RX endpoint 1 10 CDC Mode on RX endpoint 1 11 Generic RNDIS or Infinite Mode on RX ...

Page 1880: ...10 9 8 7 6 5 4 3 2 1 0 Reserved EP1_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 123 USB1GENRNDISEP1 Register Field Descriptions Bit Field Type Reset Description 16 0 EP1_SIZE R W 0h Generic RNDIS packet size USB1 Generic RNDIS EP N Size Register 1880 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Fee...

Page 1881: ...10 9 8 7 6 5 4 3 2 1 0 Reserved EP2_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 124 USB1GENRNDISEP2 Register Field Descriptions Bit Field Type Reset Description 16 0 EP2_SIZE R W 0h Generic RNDIS packet size USB1 Generic RNDIS EP N Size Register 1881 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Fee...

Page 1882: ...10 9 8 7 6 5 4 3 2 1 0 Reserved EP3_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 125 USB1GENRNDISEP3 Register Field Descriptions Bit Field Type Reset Description 16 0 EP3_SIZE R W 0h Generic RNDIS packet size USB1 Generic RNDIS EP N Size Register 1882 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Fee...

Page 1883: ...10 9 8 7 6 5 4 3 2 1 0 Reserved EP4_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 126 USB1GENRNDISEP4 Register Field Descriptions Bit Field Type Reset Description 16 0 EP4_SIZE R W 0h Generic RNDIS packet size USB1 Generic RNDIS EP N Size Register 1883 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Fee...

Page 1884: ...10 9 8 7 6 5 4 3 2 1 0 Reserved EP5_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 127 USB1GENRNDISEP5 Register Field Descriptions Bit Field Type Reset Description 16 0 EP5_SIZE R W 0h Generic RNDIS packet size USB1 Generic RNDIS EP N Size Register 1884 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Fee...

Page 1885: ...10 9 8 7 6 5 4 3 2 1 0 Reserved EP6_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 128 USB1GENRNDISEP6 Register Field Descriptions Bit Field Type Reset Description 16 0 EP6_SIZE R W 0h Generic RNDIS packet size USB1 Generic RNDIS EP N Size Register 1885 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Fee...

Page 1886: ...10 9 8 7 6 5 4 3 2 1 0 Reserved EP7_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 129 USB1GENRNDISEP7 Register Field Descriptions Bit Field Type Reset Description 16 0 EP7_SIZE R W 0h Generic RNDIS packet size USB1 Generic RNDIS EP N Size Register 1886 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Fee...

Page 1887: ...10 9 8 7 6 5 4 3 2 1 0 Reserved EP8_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 130 USB1GENRNDISEP8 Register Field Descriptions Bit Field Type Reset Description 16 0 EP8_SIZE R W 0h Generic RNDIS packet size USB1 Generic RNDIS EP N Size Register 1887 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Fee...

Page 1888: ...10 9 8 7 6 5 4 3 2 1 0 Reserved EP9_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 131 USB1GENRNDISEP9 Register Field Descriptions Bit Field Type Reset Description 16 0 EP9_SIZE R W 0h Generic RNDIS packet size USB1 Generic RNDIS EP N Size Register 1888 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Fee...

Page 1889: ...10 9 8 7 6 5 4 3 2 1 0 Reserved EP10_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 132 USB1GENRNDISEP10 Register Field Descriptions Bit Field Type Reset Description 16 0 EP10_SIZE R W 0h Generic RNDIS packet size USB1 Generic RNDIS EP N Size Register 1889 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation ...

Page 1890: ...10 9 8 7 6 5 4 3 2 1 0 Reserved EP11_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 133 USB1GENRNDISEP11 Register Field Descriptions Bit Field Type Reset Description 16 0 EP11_SIZE R W 0h Generic RNDIS packet size USB1 Generic RNDIS EP N Size Register 1890 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation ...

Page 1891: ...10 9 8 7 6 5 4 3 2 1 0 Reserved EP12_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 134 USB1GENRNDISEP12 Register Field Descriptions Bit Field Type Reset Description 16 0 EP12_SIZE R W 0h Generic RNDIS packet size USB1 Generic RNDIS EP N Size Register 1891 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation ...

Page 1892: ...10 9 8 7 6 5 4 3 2 1 0 Reserved EP13_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 135 USB1GENRNDISEP13 Register Field Descriptions Bit Field Type Reset Description 16 0 EP13_SIZE R W 0h Generic RNDIS packet size USB1 Generic RNDIS EP N Size Register 1892 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation ...

Page 1893: ...10 9 8 7 6 5 4 3 2 1 0 Reserved EP14_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 136 USB1GENRNDISEP14 Register Field Descriptions Bit Field Type Reset Description 16 0 EP14_SIZE R W 0h Generic RNDIS packet size USB1 Generic RNDIS EP N Size Register 1893 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation ...

Page 1894: ...10 9 8 7 6 5 4 3 2 1 0 Reserved EP15_SIZE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 137 USB1GENRNDISEP15 Register Field Descriptions Bit Field Type Reset Description 16 0 EP15_SIZE R W 0h Generic RNDIS packet size USB1 Generic RNDIS EP N Size Register 1894 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation ...

Page 1895: ...ays 27 26 RX14_AUTOREQ R W 0h RX endpoint 13 Auto Req enable 00 no auto req 01 auto req on all but EOP 10 reserved 11 auto req always 25 24 RX13_AUTOREQ R W 0h RX endpoint 12 Auto Req enable 00 no auto req 01 auto req on all but EOP 10 reserved 11 auto req always 23 22 RX12_AUTOREQ R W 0h RX endpoint 11 Auto Req enable 00 no auto req 01 auto req on all but EOP 10 reserved 11 auto req always 21 20 ...

Page 1896: ...o req always 7 6 RX4_AUTOREQ R W 0h RX endpoint 3 Auto Req enable 00 no auto req 01 auto req on all but EOP 10 reserved 11 auto req always 5 4 RX3_AUTOREQ R W 0h RX endpoint 2 Auto Req enable 00 no auto req 01 auto req on all but EOP 10 reserved 11 auto req always 3 2 RX2_AUTOREQ R W 0h RX endpoint 1 Auto Req enable 00 no auto req 01 auto req on all but EOP 10 reserved 11 auto req always 1 0 RX1_A...

Page 1897: ...5 4 3 2 1 0 SRPFIXTIME R W 280DE80h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 139 USB1SRPFIXTIME Register Field Descriptions Bit Field Type Reset Description 31 0 SRPFIXTIME R W 280DE80h SRP Fix maximum time in 60 MHz cycles Default is 700 ms USB1 SRP Fix Time Register 1897 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Doc...

Page 1898: ...ead Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 140 USB1TDOWN Register Field Descriptions Bit Field Type Reset Description 31 17 TX_TDOWN R W 0h Tx Endpoint Teardown Write 1 to corresponding bit to set Read as 0 Bit 31 Endpoint 15 Bit 17 Endpoint 1 15 1 RX_TDOWN R W 0h RX Endpoint Teardown Write 1 to corresponding bit to set Read as 0 Bit 15 Endpoint 15 Bit 1 Endpoin...

Page 1899: ...BITSTUFFEN R W 0h PHY UTMI input for signal txbitstuffen 22 TXBITSTUFFENH R W 0h PHY UTMI input for signal txbitstuffenh 21 OTGDISABLE R W 1h PHY UTMI input for signal otgdisable 20 VBUSVLDEXTSEL R W 0h PHY UTMI input for signal vbusvldextsel 19 VBUSVLDEXT R W 0h PHY UTMI input for signal vbusvldext 18 TXENABLEN R W 0h PHY UTMI input for signal txenablen 17 FSXCVROWNER R W 0h PHY UTMI input for si...

Page 1900: ... opmode 25 TXVALID R 0h loopback test observed value for txvalid 24 23 XCVRSEL R 0h loopback test observed value for xcvrsel 22 TERMSEL R 0h loopback test observed value for termsel 21 DRVVBUS R 0h loopback test observed value for drvvbus 20 CHRGVBUS R 0h loopback test observed value for chrgvbus 19 DISCHRGVBUS R 0h loopback test observed value for dischrgvbus 18 DPPULLDOWN R 0h loopback test obse...

Page 1901: ...PHY test mode 0 LOOPBACK R W 0h Loopback test mode 0 Normal mode 1 Loopback test mode USB1 Mode Register 16 5 4 USB2PHY Registers Table 16 144 lists the memory mapped registers for the USB2PHY All register offset addresses not listed in Table 16 144 should be considered as reserved locations and the register contents should not be modified Table 16 144 USB2PHY REGISTERS Offset Acronym Register Nam...

Page 1902: ... Section 16 5 4 14 44h AD_INTERFACE_REG1 Section 16 5 4 15 48h AD_INTERFACE_REG2 Section 16 5 4 16 4Ch AD_INTERFACE_REG3 Section 16 5 4 17 54h ANA_CONFIG2 Section 16 5 4 18 1902 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1903: ...s on 27 24 FS_CODE_SEL R W 1h FS Code selection control 23 22 Reserved R W 0h 21 USE_RTERM_RMX_REG R W 0h Override termination resistor trim code with RTERM_RMX from this register 20 14 RTERM_RMX R W 0h When read this field returns the current Termination resistor trim code Read value is valid only if VDDLDO is on The value written to this field is used as Termination resistor trim code if bit 21 ...

Page 1904: ... 1 Code is updated from calibration logic when bit 30 0 23 HSRX_COMP_OUT R 0h The output of the HSRX comparator Read value is valid only if VDDLDO is on 22 HSRX_CAL_DONE R 0h Signal that indicates that the HSRX calibration is done This gets reset at every restart Read value is valid only if VDDLDO is on 21 USE_SQ_OFF_DAC1 R W 0h Override Squelch offset DAC1 code when 1 20 15 SQ_OFF_CODE_DAC1 R W 0...

Page 1905: ...TART_SQ_CAL for more description Read value is valid only if VDDLDO is on 0 RESTART_SQ_CAL R W 0h the squelch calibration continuously goes through restart cycles when this bit is 1 i e restarts waits for done then restarts again etc 1905 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1906: ...EN R W 0h R W 1h R W Fh LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 147 DLLHS_2 Register Field Descriptions Bit Field Type Reset Description 31 24 DLLHS_CNTRL_LDO R W 0h See DFT spec for details 23 16 DLLHS_STATUS_LDO R 0h See DFT spec for details 15 5 Reserved R W 0h 4 LINESTATE_DEBOUNCE R W 1h Enables the linestate debounce filter _EN 3 0 LINESTATE_...

Page 1907: ...Description 31 HSOSREVERSAL R W 0h Swaps the dataout from HSOS 30 HSOSBITINVERSION R W 0h Inverts the HSOS bits 29 PHYCLKOUTINVERSION R W 0h This inverts the phase for the PHYCLKOUT 28 RXPIDERR R 0h Flags if the RX data packet has PID error NOT IMPLEMENTED YET 27 USEINTDATAOUT R W 0h This will bypass the analog and will send data packet to controller incase of receiver Faking the receive data data...

Page 1908: ...t value of charger detect input When USE_CHG_DET_REG 1 the value written to this field overrides the corresponding charger detect input 26 SINK_ON_DP R W 0h When read returns current value of charger detect input When USE_CHG_DET_REG 1 the value written to this field overrides the corresponding charger detect input 25 CHG_DET_EXT_CTL R W 0h When read returns current value of charger detect input W...

Page 1909: ...ee charger detect section for details 6 5 Reserved R W 0h 4 3 CHG_DET_ICTRL R W 0h Charger detect current control 2 1 CHG_DET_VCTRL R W 0h Charger detect voltage buffer control 0 FOR_CE R W 0h Force CE 1 when this bit is set 1909 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1910: ...et is de asserted 29 VMAIN_GLOBAL_RESET R 0h Goes high when LDO domain is up and PLL LOCK is available _DONE 28 RESETDONEMCLK R 0h Goes high when the RESET is synchronized to MCLK 27 RESETDONE_CHGDET R 0h Goes high when the RESET is synchronized to charger detect oscillator clock domain 26 12 LDOPWRCOUNTER R W 400h This is the value of the counter used for LDO power up RESET to default 11 FORCEPLL...

Page 1911: ...erface register 30 15 UTMIDATAIN R W 0h Override value for the UTMIDATAIN 14 Reserved R W 0h 13 USEDATABUSREG R W 0h When set to 1 use bit 12 from register instead of interface 12 DATABUS16OR8 R W 0h Override value for UTMI signal DATABUS16OR8 11 USEOPMODEREG R W 0h When set to 1 use bit 10 9 from register instead of interface 10 9 OPMODE R W 0h Override value for UTMI signal OPMODE 1 0 8 OVERRIDE...

Page 1912: ...nly if VDDLDO is on 28 HOSTDISCONNECT R 0h Read for UTMI signal Read value is valid only if VDDLDO is on 27 26 LINESTATE R 0h Read for UTMI signal Read value is valid only if VDDLDO is on 25 RXVALID R 0h Read for UTMI signal Read value is valid only if VDDLDO is on 24 RXVALIDH R 0h Read for UTMI signal Read value is valid only if VDDLDO is on 23 RXACTIVE R 0h Read for UTMI signal Read value is val...

Page 1913: ... for signal TXENABLEN 4 1 Reserved R W 0h 0 sig_bypass_suspendmpul R W 0h If the suspend signal is asserted for very short time it is pulse se_incr extended so that all the sampling logic samples it reliably This pulse extention can be bypassed by writin a 1 to this bit so that IP s behaviour is similar to previous versions 1913 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Sub...

Page 1914: ...UCED_SWING R W 0h When 1 the TX swing is reduced in BIST mode 29 BIST_CRC_CALC_EN R W 0h Enables CRC calculation during BIST when set to 1 28 20 BIST_PKT_LENGTH R W 0h Address for which BIST to select 19 LOOPBACK_EN R W 0h Enables the loopback mode 18 16 BIST_OP_PHASE_SEL R W 0h Selects which phase to use for data transmission during BIST 15 SWEEP_EN R W 0h Enables freq sweep on CDR 14 12 SWEEP_MO...

Page 1915: ...0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BIST_CRC R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 154 BIST_CRC Register Field Descriptions Bit Field Type Reset Description 31 0 BIST_CRC R W 0h The CRC value from the BIST 1915 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 20...

Page 1916: ...dr Bist_end_addr R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 155 CDR_BIST2 Register Field Descriptions Bit Field Type Reset Description 31 CDR_EXE_EN R W 0h CDR debug bits 30 28 CDR_EXE_MODE R W 0h CDR debug bits 27 25 NUM_DECISIONS R W 0h CDR debug bits 24 22 CDR_CHOSEN_PHASE R 0h 21 19 FORCE_CDR_PHASE R 0h 18 DISABLE_CDR_FREQ_T R 0h RA...

Page 1917: ...om this register instead of primary inputs 30 GPIOMODE R W 0h Overrides the corresponding primary input 29 DPGPIOGZ R W 0h Overrides the corresponding primary input 28 DMGPIOGZ R W 0h Overrides the corresponding primary input 27 DPGPIOA R W 0h Overrides the corresponding primary input 26 DMGPIOA R W 0h Overrides the corresponding primary input 25 DPGPIOY R 0h The GPIO Y output is stored here 24 DM...

Page 1918: ...h Connect to DLLHS_TEST_LDO 0 on AFE interface see DFT spec for details 20 19 DLL_LOCKCHK R W 0h Connect to DLLHS_TEST_LDO 2 1 on AFE interface see DFT spec for details 18 16 DLL_SEL_COD R W 0h Connect to DLLHS_TEST_LDO 5 3 on AFE interface see DFT spec for details 15 DLL_PHS0_8 R W 1h Connect to DLLHS_TEST_LDO 6 on AFE interface see DFT spec for details 14 9 DLL_FORCED_CODE R W 0h Connect to the ...

Page 1919: ...h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 158 USB2PHYCM_CONFIG Register Field Descriptions Bit Field Type Reset Description 31 24 CONFIGURECM R W 0h Connects to the CONFIGURECM pins see DFT spec for details 23 18 CMSTATUS R 0h Reads the CMSTATUS bits see DFT spec for details 17 2 LDOCONFIG R W 0h The LDOCONFIG bit settings See DFT spec for de...

Page 1920: ... 5 4 3 2 1 0 TEST_RTERM_CAL_ RTERM_CAL_EN DLL_RX_DATA DISCON_DETECT USE_LSHOST_REG LSHOSTMODE LSFS_RX_DATA SQUELCH CONTROL R W 0h R W 0h R 0h R 0h R W 0h R W 0h R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 159 AD_INTERFACE_REG1 Register Field Descriptions Bit Field Type Reset Description 31 USE_AD_DATA_REG R W 0h Override for bits 30 29 30 HS...

Page 1921: ...7 TEST_RTERM_CAL_CO R W 0h Override for bits 6 NTROL 6 RTERM_CAL_EN R W 0h 5 DLL_RX_DATA R 0h 4 DISCON_DETECT R 0h 3 USE_LSHOST_REG R W 0h Use bit 2 for this reg 2 LSHOSTMODE R W 0h 1 LSFS_RX_DATA R 0h 0 SQUELCH R 0h 1921 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1922: ...W 0h R W 0h 7 6 5 4 3 2 1 0 DM_PULLDOWN_EN DP_DM_5V_SHORT SPARE_IN_CORE PORZ _CORE R W 0h R 0h R W 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 160 AD_INTERFACE_REG2 Register Field Descriptions Bit Field Type Reset Description 31 USE_SUSP_DRV_REG R W 0h Use bits 27 30 from this register as overrides 30 SUS_DRV_DP_DATA R W 0h 29 SUS_DRV_DP_EN R ...

Page 1923: ...7 DM_PULLDOWN_EN_CO R W 0h RE 6 DP_DM_5V_SHORT R 0h 5 1 SPARE_IN_CORE R W 0h 0 PORZ R 0h Read only bit andgt the PORZ generated from the digital registered on the A D interface 1923 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 1924: ...9 8 SPARE_IN_LDO SPARE_OUT_LDO R W 0h R 0h 7 6 5 4 3 2 1 0 SPARE_OUT_LDO USE_FARCORE_RE FARCORE G R 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 161 AD_INTERFACE_REG3 Register Field Descriptions Bit Field Type Reset Description 31 USE_HSOS_DATA_REG R W 0h Use bits 30 23 in this register as bypass bits 30 23 HSOS_DATA R W 0h 22 USE_FS_R...

Page 1925: ...All other values are reserved 19 18 Reserved R W 0h Reserved 17 15 RTERM_TEST R W 0h 000b Typical termination impedance default 011b Decreases the termination impedance by 2 to 3 and can be used to increase the vertical eye diagram amplitude by 1 to 1 5 All other values reserved 14 0 Reserved R W 0h Reserved 16 5 5 CPPI_DMA Registers Table 16 163 lists the memory mapped registers for the CPPI_DMA ...

Page 1926: ...TXGCR7 Section 16 5 5 32 8E8h RXGCR7 Section 16 5 5 33 8ECh RXHPCRA7 Section 16 5 5 34 8F0h RXHPCRB7 Section 16 5 5 35 900h TXGCR8 Section 16 5 5 36 908h RXGCR8 Section 16 5 5 37 90Ch RXHPCRA8 Section 16 5 5 38 910h RXHPCRB8 Section 16 5 5 39 920h TXGCR9 Section 16 5 5 40 928h RXGCR9 Section 16 5 5 41 92Ch RXHPCRA9 Section 16 5 5 42 930h RXHPCRB9 Section 16 5 5 43 940h TXGCR10 Section 16 5 5 44 94...

Page 1927: ...RXHPCRB18 Section 16 5 5 79 A60h TXGCR19 Section 16 5 5 80 A68h RXGCR19 Section 16 5 5 81 A6Ch RXHPCRA19 Section 16 5 5 82 A70h RXHPCRB19 Section 16 5 5 83 A80h TXGCR20 Section 16 5 5 84 A88h RXGCR20 Section 16 5 5 85 A8Ch RXHPCRA20 Section 16 5 5 86 A90h RXHPCRB20 Section 16 5 5 87 AA0h TXGCR21 Section 16 5 5 88 AA8h RXGCR21 Section 16 5 5 89 AACh RXHPCRA21 Section 16 5 5 90 AB0h RXHPCRB21 Sectio...

Page 1928: ...TXGCR27 Section 16 5 5 112 B68h RXGCR27 Section 16 5 5 113 B6Ch RXHPCRA27 Section 16 5 5 114 B70h RXHPCRB27 Section 16 5 5 115 B80h TXGCR28 Section 16 5 5 116 B88h RXGCR28 Section 16 5 5 117 B8Ch RXHPCRA28 Section 16 5 5 118 B90h RXHPCRB28 Section 16 5 5 119 BA0h TXGCR29 Section 16 5 5 120 BA8h RXGCR29 Section 16 5 5 121 BACh RXHPCRA29 Section 16 5 5 122 BB0h RXHPCRB29 Section 16 5 5 123 1928 Univ...

Page 1929: ...VMIN R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 164 DMAREVID Register Field Descriptions Bit Field Type Reset Description 29 16 MODID R 0 0 Module ID field 15 11 REVRTL R 0 0 RTL revision Will vary depending on release 10 8 REVMAJ R 0 0 Major revision 7 0 REVMIN R 0 0 Minor revision CPPI DMA Revision Register 1929 SPRUH73H October 2011 Revised Ap...

Page 1930: ...165 TDFDQ Register Field Descriptions Bit Field Type Reset Description 13 12 TD_DESC_QMGR R W 0h This field controls which of the 4 Queue Managers the DMA will access in order to allocate a channel teardown descriptor from the teardown descriptor queue 11 0 TD_DESC_QNUM R W 0h This field controls which of the 2K queues in the indicated queue manager should be read in order to allocate channel tear...

Page 1931: ...h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 166 DMAEMU Register Field Descriptions Bit Field Type Reset Description 1 SOFT R W 0h Control for emulation pause request 1 Does not force emu_pause_req low 0 Forces emu_pause_req low 0 FREE R W 0h Enable for emulation suspend CPPI DMA Emulation Control Register 1931 SPRUH73H October 2011 Revised April 201...

Page 1932: ...bles the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors back...

Page 1933: ... is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subsequ...

Page 1934: ...icates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI FI...

Page 1935: ...ription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a ...

Page 1936: ...iption 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in a ...

Page 1937: ...bles the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors back...

Page 1938: ... is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subsequ...

Page 1939: ...icates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI FI...

Page 1940: ...ription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a ...

Page 1941: ...ription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in a...

Page 1942: ...ables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors bac...

Page 1943: ...l is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subseq...

Page 1944: ...icates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI FI...

Page 1945: ...ription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a ...

Page 1946: ...ription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in a...

Page 1947: ...ables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors bac...

Page 1948: ...l is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subseq...

Page 1949: ...icates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI FI...

Page 1950: ...ription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a ...

Page 1951: ...ription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in a...

Page 1952: ...ables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors bac...

Page 1953: ...l is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subseq...

Page 1954: ...icates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI FI...

Page 1955: ...ription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a ...

Page 1956: ...ription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in a...

Page 1957: ...ables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors bac...

Page 1958: ...l is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subseq...

Page 1959: ...icates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI FI...

Page 1960: ...ription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a ...

Page 1961: ...ription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in a...

Page 1962: ...ables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors bac...

Page 1963: ...l is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subseq...

Page 1964: ...icates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI FI...

Page 1965: ...ription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a ...

Page 1966: ...ription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in a...

Page 1967: ...ables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors bac...

Page 1968: ...l is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subseq...

Page 1969: ...icates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI FI...

Page 1970: ...ription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a ...

Page 1971: ...ription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in a...

Page 1972: ...ables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors bac...

Page 1973: ...l is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subseq...

Page 1974: ...icates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI FI...

Page 1975: ...ription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a ...

Page 1976: ...ription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in a...

Page 1977: ...ables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors bac...

Page 1978: ...l is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subseq...

Page 1979: ...icates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI FI...

Page 1980: ...ription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a ...

Page 1981: ...ription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in a...

Page 1982: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 1983: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 1984: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 1985: ...scription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in ...

Page 1986: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 1987: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 1988: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 1989: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 1990: ...scription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in ...

Page 1991: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 1992: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 1993: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 1994: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 1995: ...scription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in ...

Page 1996: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 1997: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 1998: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 1999: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 2000: ...scription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in ...

Page 2001: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 2002: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 2003: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 2004: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 2005: ...scription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in ...

Page 2006: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 2007: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 2008: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 2009: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 2010: ...scription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in ...

Page 2011: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 2012: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 2013: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 2014: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 2015: ...scription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in ...

Page 2016: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 2017: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 2018: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 2019: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 2020: ...scription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in ...

Page 2021: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 2022: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 2023: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 2024: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 2025: ...scription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in ...

Page 2026: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 2027: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 2028: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 2029: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 2030: ...scription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in ...

Page 2031: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 2032: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 2033: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 2034: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 2035: ...scription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in ...

Page 2036: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 2037: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 2038: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 2039: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 2040: ...scription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in ...

Page 2041: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 2042: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 2043: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 2044: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 2045: ...scription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in ...

Page 2046: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 2047: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 2048: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 2049: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 2050: ...scription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in ...

Page 2051: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 2052: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 2053: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 2054: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 2055: ...escription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in...

Page 2056: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 2057: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 2058: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 2059: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 2060: ...escription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in...

Page 2061: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 2062: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 2063: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 2064: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 2065: ...escription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in...

Page 2066: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 2067: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 2068: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 2069: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 2070: ...escription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in...

Page 2071: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 2072: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 2073: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 2074: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 2075: ...escription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in...

Page 2076: ...scription 29 28 RX_HOST_FDQ3_QMGR W 0h This field specifies which Manager should be used for the 4th or later Rx buffers in a host type packet 27 16 RX_HOST_FDQ3_QNUM W 0h This field specifies which Free Descriptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in...

Page 2077: ...isables the channel 0 channel is disabled 1 channel is enabled This field will be cleared after a channel teardown is complete 30 TX_TEARDOWN R W 0h Setting this bit will request the channel to be torn down This field will remain set after a channel teardown is complete 13 12 TX_DEFAULT_QMGR W 0h This field controls the default queue manager number that will be used to queue teardown descriptors b...

Page 2078: ...nel is not in a packet then drop the credit 24 RX_ERROR_HANDLING W 0h This bit controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occurs 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in subs...

Page 2079: ...dicates the default receive queue manager that this R channel should use The actual receive queue manager index can be overridden by information provided in the CPPI FIFO data block 11 0 RX_DEFAULT_RQ_QNU W 0h This field indicates the default receive queue that this channel should M use The actual receive queue that will be used for reception can be overridden by information provided in the CPPI F...

Page 2080: ...escription 29 28 RX_HOST_FDQ1_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in a host type packet 27 16 RX_HOST_FDQ1_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 2nd Rx buffer in a host type packet 13 12 RX_HOST_FDQ0_QMGR W 0h This field specifies which Buffer Manager should be used for the second Rx buffer in...

Page 2081: ...iptor Queue should be used for the 4th or later Rx buffers in a host type packet 13 12 RX_HOST_FDQ2_QMGR W 0h This field specifies which Buffer Manager should be used for the 3rd Rx buffer in a host type packet 11 0 RX_HOST_FDQ2_QNUM W 0h This field specifies which Free Descriptor Buffer Pool should be used for the 3rd Rx buffer in a host type packet Table 101 Rx Channel N Host Packet Configuratio...

Page 2082: ...d is encoded as follows 0 scheduler is disabled and will no longer fetch entries from the scheduler table or pass credits to the DMA controller 1 scheduler is enabled This bit should only be set after the table has been initialized 7 0 LAST_ENTRY R W 0h This field indicates the last valid entry in the scheduler table There are 64 words in the table and there are 4 entries in each word The table ca...

Page 2083: ... carry traffic for more than 1 Rx DMA channel the exact channel number that is given in the Rx credit will actually be the channel number which is currently on the head element of that Rx FIFO which is not necessarily the channel number given in the scheduler table entry 23 ENTRY2_RXTX W 0h This bit indicates if this entry is for a Tx or an Rx channel and is encoded as follows 0 Tx Channel 1 Rx Ch...

Page 2084: ...e Rx FIFO that is associated with this channel For Rx FIFOs which carry traffic for more than 1 Rx DMA channel the exact channel number that is given in the Rx credit will actually be the channel number which is currently on the head element of that Rx FIFO which is not necessarily the channel number given in the scheduler table entry 16 5 7 QUEUE_MGR Registers Table 16 290 lists the memory mapped...

Page 2085: ...h QUEUE_1_D Section 16 5 7 42 2020h QUEUE_2_A Section 16 5 7 43 2024h QUEUE_2_B Section 16 5 7 44 2028h QUEUE_2_C Section 16 5 7 45 202Ch QUEUE_2_D Section 16 5 7 46 2030h QUEUE_3_A Section 16 5 7 47 2034h QUEUE_3_B Section 16 5 7 48 2038h QUEUE_3_C Section 16 5 7 49 203Ch QUEUE_3_D Section 16 5 7 50 2040h QUEUE_4_A Section 16 5 7 51 2044h QUEUE_4_B Section 16 5 7 52 2048h QUEUE_4_C Section 16 5 7...

Page 2086: ...tion 16 5 7 89 20DCh QUEUE_13_D Section 16 5 7 90 20E0h QUEUE_14_A Section 16 5 7 91 20E4h QUEUE_14_B Section 16 5 7 92 20E8h QUEUE_14_C Section 16 5 7 93 20ECh QUEUE_14_D Section 16 5 7 94 20F0h QUEUE_15_A Section 16 5 7 95 20F4h QUEUE_15_B Section 16 5 7 96 20F8h QUEUE_15_C Section 16 5 7 97 20FCh QUEUE_15_D Section 16 5 7 98 2100h QUEUE_16_A Section 16 5 7 99 2104h QUEUE_16_B Section 16 5 7 100...

Page 2087: ...25_B Section 16 5 7 136 2198h QUEUE_25_C Section 16 5 7 137 219Ch QUEUE_25_D Section 16 5 7 138 21A0h QUEUE_26_A Section 16 5 7 139 21A4h QUEUE_26_B Section 16 5 7 140 21A8h QUEUE_26_C Section 16 5 7 141 21ACh QUEUE_26_D Section 16 5 7 142 21B0h QUEUE_27_A Section 16 5 7 143 21B4h QUEUE_27_B Section 16 5 7 144 21B8h QUEUE_27_C Section 16 5 7 145 21BCh QUEUE_27_D Section 16 5 7 146 21C0h QUEUE_28_A...

Page 2088: ...37_A Section 16 5 7 183 2254h QUEUE_37_B Section 16 5 7 184 2258h QUEUE_37_C Section 16 5 7 185 225Ch QUEUE_37_D Section 16 5 7 186 2260h QUEUE_38_A Section 16 5 7 187 2264h QUEUE_38_B Section 16 5 7 188 2268h QUEUE_38_C Section 16 5 7 189 226Ch QUEUE_38_D Section 16 5 7 190 2270h QUEUE_39_A Section 16 5 7 191 2274h QUEUE_39_B Section 16 5 7 192 2278h QUEUE_39_C Section 16 5 7 193 227Ch QUEUE_39_D...

Page 2089: ...48_D Section 16 5 7 230 2310h QUEUE_49_A Section 16 5 7 231 2314h QUEUE_49_B Section 16 5 7 232 2318h QUEUE_49_C Section 16 5 7 233 231Ch QUEUE_49_D Section 16 5 7 234 2320h QUEUE_50_A Section 16 5 7 235 2324h QUEUE_50_B Section 16 5 7 236 2328h QUEUE_50_C Section 16 5 7 237 232Ch QUEUE_50_D Section 16 5 7 238 2330h QUEUE_51_A Section 16 5 7 239 2334h QUEUE_51_B Section 16 5 7 240 2338h QUEUE_51_C...

Page 2090: ...60_C Section 16 5 7 277 23CCh QUEUE_60_D Section 16 5 7 278 23D0h QUEUE_61_A Section 16 5 7 279 23D4h QUEUE_61_B Section 16 5 7 280 23D8h QUEUE_61_C Section 16 5 7 281 23DCh QUEUE_61_D Section 16 5 7 282 23E0h QUEUE_62_A Section 16 5 7 283 23E4h QUEUE_62_B Section 16 5 7 284 23E8h QUEUE_62_C Section 16 5 7 285 23ECh QUEUE_62_D Section 16 5 7 286 23F0h QUEUE_63_A Section 16 5 7 287 23F4h QUEUE_63_B...

Page 2091: ...72_B Section 16 5 7 324 2488h QUEUE_72_C Section 16 5 7 325 248Ch QUEUE_72_D Section 16 5 7 326 2490h QUEUE_73_A Section 16 5 7 327 2494h QUEUE_73_B Section 16 5 7 328 2498h QUEUE_73_C Section 16 5 7 329 249Ch QUEUE_73_D Section 16 5 7 330 24A0h QUEUE_74_A Section 16 5 7 331 24A4h QUEUE_74_B Section 16 5 7 332 24A8h QUEUE_74_C Section 16 5 7 333 24ACh QUEUE_74_D Section 16 5 7 334 24B0h QUEUE_75_A...

Page 2092: ...84_A Section 16 5 7 371 2544h QUEUE_84_B Section 16 5 7 372 2548h QUEUE_84_C Section 16 5 7 373 254Ch QUEUE_84_D Section 16 5 7 374 2550h QUEUE_85_A Section 16 5 7 375 2554h QUEUE_85_B Section 16 5 7 376 2558h QUEUE_85_C Section 16 5 7 377 255Ch QUEUE_85_D Section 16 5 7 378 2560h QUEUE_86_A Section 16 5 7 379 2564h QUEUE_86_B Section 16 5 7 380 2568h QUEUE_86_C Section 16 5 7 381 256Ch QUEUE_86_D...

Page 2093: ...Section 16 5 7 418 2600h QUEUE_96_A Section 16 5 7 419 2604h QUEUE_96_B Section 16 5 7 420 2608h QUEUE_96_C Section 16 5 7 421 260Ch QUEUE_96_D Section 16 5 7 422 2610h QUEUE_97_A Section 16 5 7 423 2614h QUEUE_97_B Section 16 5 7 424 2618h QUEUE_97_C Section 16 5 7 425 261Ch QUEUE_97_D Section 16 5 7 426 2620h QUEUE_98_A Section 16 5 7 427 2624h QUEUE_98_B Section 16 5 7 428 2628h QUEUE_98_C Sect...

Page 2094: ...7_C Section 16 5 7 465 26BCh QUEUE_107_D Section 16 5 7 466 26C0h QUEUE_108_A Section 16 5 7 467 26C4h QUEUE_108_B Section 16 5 7 468 26C8h QUEUE_108_C Section 16 5 7 469 26CCh QUEUE_108_D Section 16 5 7 470 26D0h QUEUE_109_A Section 16 5 7 471 26D4h QUEUE_109_B Section 16 5 7 472 26D8h QUEUE_109_C Section 16 5 7 473 26DCh QUEUE_109_D Section 16 5 7 474 26E0h QUEUE_110_A Section 16 5 7 475 26E4h Q...

Page 2095: ..._B Section 16 5 7 512 2778h QUEUE_119_C Section 16 5 7 513 277Ch QUEUE_119_D Section 16 5 7 514 2780h QUEUE_120_A Section 16 5 7 515 2784h QUEUE_120_B Section 16 5 7 516 2788h QUEUE_120_C Section 16 5 7 517 278Ch QUEUE_120_D Section 16 5 7 518 2790h QUEUE_121_A Section 16 5 7 519 2794h QUEUE_121_B Section 16 5 7 520 2798h QUEUE_121_C Section 16 5 7 521 279Ch QUEUE_121_D Section 16 5 7 522 27A0h QU...

Page 2096: ...1_A Section 16 5 7 559 2834h QUEUE_131_B Section 16 5 7 560 2838h QUEUE_131_C Section 16 5 7 561 283Ch QUEUE_131_D Section 16 5 7 562 2840h QUEUE_132_A Section 16 5 7 563 2844h QUEUE_132_B Section 16 5 7 564 2848h QUEUE_132_C Section 16 5 7 565 284Ch QUEUE_132_D Section 16 5 7 566 2850h QUEUE_133_A Section 16 5 7 567 2854h QUEUE_133_B Section 16 5 7 568 2858h QUEUE_133_C Section 16 5 7 569 285Ch Q...

Page 2097: ..._D Section 16 5 7 606 28F0h QUEUE_143_A Section 16 5 7 607 28F4h QUEUE_143_B Section 16 5 7 608 28F8h QUEUE_143_C Section 16 5 7 609 28FCh QUEUE_143_D Section 16 5 7 610 2900h QUEUE_144_A Section 16 5 7 611 2904h QUEUE_144_B Section 16 5 7 612 2908h QUEUE_144_C Section 16 5 7 613 290Ch QUEUE_144_D Section 16 5 7 614 2910h QUEUE_145_A Section 16 5 7 615 2914h QUEUE_145_B Section 16 5 7 616 2918h QU...

Page 2098: ...6 5 7 654 29B0h QUEUE_155_A Section 16 5 7 655 29B4h QUEUE_155_B Section 16 5 7 656 29B8h QUEUE_155_C Section 16 5 7 657 29BCh QUEUE_155_D Section 16 5 7 658 3000h QUEUE_0_STATUS_A Section 16 5 7 659 3004h QUEUE_0_STATUS_B Section 16 5 7 660 3008h QUEUE_0_STATUS_C Section 16 5 7 661 3010h QUEUE_1_STATUS_A Section 16 5 7 662 3014h QUEUE_1_STATUS_B Section 16 5 7 663 3018h QUEUE_1_STATUS_C Section 1...

Page 2099: ...5 7 700 30E0h QUEUE_14_STATUS_A Section 16 5 7 701 30E4h QUEUE_14_STATUS_B Section 16 5 7 702 30E8h QUEUE_14_STATUS_C Section 16 5 7 703 30F0h QUEUE_15_STATUS_A Section 16 5 7 704 30F4h QUEUE_15_STATUS_B Section 16 5 7 705 30F8h QUEUE_15_STATUS_C Section 16 5 7 706 3100h QUEUE_16_STATUS_A Section 16 5 7 707 3104h QUEUE_16_STATUS_B Section 16 5 7 708 3108h QUEUE_16_STATUS_C Section 16 5 7 709 3110h...

Page 2100: ...on 16 5 7 747 31D8h QUEUE_29_STATUS_C Section 16 5 7 748 31E0h QUEUE_30_STATUS_A Section 16 5 7 749 31E4h QUEUE_30_STATUS_B Section 16 5 7 750 31E8h QUEUE_30_STATUS_C Section 16 5 7 751 31F0h QUEUE_31_STATUS_A Section 16 5 7 752 31F4h QUEUE_31_STATUS_B Section 16 5 7 753 31F8h QUEUE_31_STATUS_C Section 16 5 7 754 3200h QUEUE_32_STATUS_A Section 16 5 7 755 3204h QUEUE_32_STATUS_B Section 16 5 7 756...

Page 2101: ...n 16 5 7 794 32D4h QUEUE_45_STATUS_B Section 16 5 7 795 32D8h QUEUE_45_STATUS_C Section 16 5 7 796 32E0h QUEUE_46_STATUS_A Section 16 5 7 797 32E4h QUEUE_46_STATUS_B Section 16 5 7 798 32E8h QUEUE_46_STATUS_C Section 16 5 7 799 32F0h QUEUE_47_STATUS_A Section 16 5 7 800 32F4h QUEUE_47_STATUS_B Section 16 5 7 801 32F8h QUEUE_47_STATUS_C Section 16 5 7 802 3300h QUEUE_48_STATUS_A Section 16 5 7 803 ...

Page 2102: ...on 16 5 7 841 33D0h QUEUE_61_STATUS_A Section 16 5 7 842 33D4h QUEUE_61_STATUS_B Section 16 5 7 843 33D8h QUEUE_61_STATUS_C Section 16 5 7 844 33E0h QUEUE_62_STATUS_A Section 16 5 7 845 33E4h QUEUE_62_STATUS_B Section 16 5 7 846 33E8h QUEUE_62_STATUS_C Section 16 5 7 847 33F0h QUEUE_63_STATUS_A Section 16 5 7 848 33F4h QUEUE_63_STATUS_B Section 16 5 7 849 33F8h QUEUE_63_STATUS_C Section 16 5 7 850...

Page 2103: ...n 16 5 7 888 34C8h QUEUE_76_STATUS_C Section 16 5 7 889 34D0h QUEUE_77_STATUS_A Section 16 5 7 890 34D4h QUEUE_77_STATUS_B Section 16 5 7 891 34D8h QUEUE_77_STATUS_C Section 16 5 7 892 34E0h QUEUE_78_STATUS_A Section 16 5 7 893 34E4h QUEUE_78_STATUS_B Section 16 5 7 894 34E8h QUEUE_78_STATUS_C Section 16 5 7 895 34F0h QUEUE_79_STATUS_A Section 16 5 7 896 34F4h QUEUE_79_STATUS_B Section 16 5 7 897 ...

Page 2104: ...n 16 5 7 935 35C4h QUEUE_92_STATUS_B Section 16 5 7 936 35C8h QUEUE_92_STATUS_C Section 16 5 7 937 35D0h QUEUE_93_STATUS_A Section 16 5 7 938 35D4h QUEUE_93_STATUS_B Section 16 5 7 939 35D8h QUEUE_93_STATUS_C Section 16 5 7 940 35E0h QUEUE_94_STATUS_A Section 16 5 7 941 35E4h QUEUE_94_STATUS_B Section 16 5 7 942 35E8h QUEUE_94_STATUS_C Section 16 5 7 943 35F0h QUEUE_95_STATUS_A Section 16 5 7 944 ...

Page 2105: ...5 7 982 36C0h QUEUE_108_STATUS_A Section 16 5 7 983 36C4h QUEUE_108_STATUS_B Section 16 5 7 984 36C8h QUEUE_108_STATUS_C Section 16 5 7 985 36D0h QUEUE_109_STATUS_A Section 16 5 7 986 36D4h QUEUE_109_STATUS_B Section 16 5 7 987 36D8h QUEUE_109_STATUS_C Section 16 5 7 988 36E0h QUEUE_110_STATUS_A Section 16 5 7 989 36E4h QUEUE_110_STATUS_B Section 16 5 7 990 36E8h QUEUE_110_STATUS_C Section 16 5 7 ...

Page 2106: ...6 5 7 1029 37B8h QUEUE_123_STATUS_C Section 16 5 7 1030 37C0h QUEUE_124_STATUS_A Section 16 5 7 1031 37C4h QUEUE_124_STATUS_B Section 16 5 7 1032 37C8h QUEUE_124_STATUS_C Section 16 5 7 1033 37D0h QUEUE_125_STATUS_A Section 16 5 7 1034 37D4h QUEUE_125_STATUS_B Section 16 5 7 1035 37D8h QUEUE_125_STATUS_C Section 16 5 7 1036 37E0h QUEUE_126_STATUS_A Section 16 5 7 1037 37E4h QUEUE_126_STATUS_B Sect...

Page 2107: ... 5 7 1076 38B4h QUEUE_139_STATUS_B Section 16 5 7 1077 38B8h QUEUE_139_STATUS_C Section 16 5 7 1078 38C0h QUEUE_140_STATUS_A Section 16 5 7 1079 38C4h QUEUE_140_STATUS_B Section 16 5 7 1080 38C8h QUEUE_140_STATUS_C Section 16 5 7 1081 38D0h QUEUE_141_STATUS_A Section 16 5 7 1082 38D4h QUEUE_141_STATUS_B Section 16 5 7 1083 38D8h QUEUE_141_STATUS_C Section 16 5 7 1084 38E0h QUEUE_142_STATUS_A Secti...

Page 2108: ... 5 7 1112 3974h QUEUE_151_STATUS_B Section 16 5 7 1113 3978h QUEUE_151_STATUS_C Section 16 5 7 1114 3980h QUEUE_152_STATUS_A Section 16 5 7 1115 3984h QUEUE_152_STATUS_B Section 16 5 7 1116 3988h QUEUE_152_STATUS_C Section 16 5 7 1117 3990h QUEUE_153_STATUS_A Section 16 5 7 1118 3994h QUEUE_153_STATUS_B Section 16 5 7 1119 3998h QUEUE_153_STATUS_C Section 16 5 7 1120 39A0h QUEUE_154_STATUS_A Secti...

Page 2109: ... W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 291 QMGRREVID Register Field Descriptions Bit Field Type Reset Description 31 30 SCHEME R 0 0 Scheme that this register is compliant with 27 16 FUNCTION R 0 0 Function 15 11 REVRTL R 0 0 RTL revision 10 8 REVMAJ R 0 0 Major revision 7 6 REVCUSTOM R 0 0 Custom revision 5 0 REVMIN R 0 0 Minor revision Queue Manager Re...

Page 2110: ...1 HEAD_TAIL W 0 0 Indicates whether queue contents should be merged on to head or tail of destination queue Clear this field for head and set for tail 29 16 DEST_QNUM W 0 0 Destination Queue Number 13 0 SOURCE_QNUM W 0 0 Source Queue Number Queue Manager Queue Diversion Register Note CBA write transactions to this register cause the QMGR to start processing an internal state machine This disables ...

Page 2111: ...a the CPPI DMA This field is cleared when read via the cpu 23 16 FDBQ2_STARVE_CNT R 0 0 This field increments each time the Free Descriptor Buffer Queue 2 is read while it is empty via the CPPI DMA This field is cleared when read via the cpu 15 8 FDBQ1_STARVE_CNT R 0 0 This field increments each time the Free Descriptor Buffer Queue 1 is read while it is empty via the CPPI DMA This field is cleare...

Page 2112: ...a the CPPI DMA This field is cleared when read via the cpu 23 16 FDBQ6_STARVE_CNT R 0 0 This field increments each time the Free Descriptor Buffer Queue 6 is read while it is empty via the CPPI DMA This field is cleared when read via the cpu 15 8 FDBQ5_STARVE_CNT R 0 0 This field increments each time the Free Descriptor Buffer Queue 5 is read while it is empty via the CPPI DMA This field is cleare...

Page 2113: ...ia the CPPI DMA This field is cleared when read via the cpu 23 16 FDBQ10_STARVE_CNT R 0 0 This field increments each time the Free Descriptor Buffer Queue 10 is read while it is empty via the CPPI DMA This field is cleared when read via the cpu 15 8 FDBQ9_STARVE_CNT R 0 0 This field increments each time the Free Descriptor Buffer Queue 9 is read while it is empty via the CPPI DMA This field is cle...

Page 2114: ...a the CPPI DMA This field is cleared when read via the cpu 23 16 FDBQ14_STARVE_CNT R 0 0 This field increments each time the Free Descriptor Buffer Queue 14 is read while it is empty via the CPPI DMA This field is cleared when read via the cpu 15 8 FDBQ13_STARVE_CNT R 0 0 This field increments each time the Free Descriptor Buffer Queue 13 is read while it is empty via the CPPI DMA This field is cl...

Page 2115: ...a the CPPI DMA This field is cleared when read via the cpu 23 16 FDBQ18_STARVE_CNT R 0 0 This field increments each time the Free Descriptor Buffer Queue 18 is read while it is empty via the CPPI DMA This field is cleared when read via the cpu 15 8 FDBQ17_STARVE_CNT R 0 0 This field increments each time the Free Descriptor Buffer Queue 17 is read while it is empty via the CPPI DMA This field is cl...

Page 2116: ...a the CPPI DMA This field is cleared when read via the cpu 23 16 FDBQ22_STARVE_CNT R 0 0 This field increments each time the Free Descriptor Buffer Queue 22 is read while it is empty via the CPPI DMA This field is cleared when read via the cpu 15 8 FDBQ21_STARVE_CNT R 0 0 This field increments each time the Free Descriptor Buffer Queue 21 is read while it is empty via the CPPI DMA This field is cl...

Page 2117: ...a the CPPI DMA This field is cleared when read via the cpu 23 16 FDBQ26_STARVE_CNT R 0 0 This field increments each time the Free Descriptor Buffer Queue 26 is read while it is empty via the CPPI DMA This field is cleared when read via the cpu 15 8 FDBQ25_STARVE_CNT R 0 0 This field increments each time the Free Descriptor Buffer Queue 25 is read while it is empty via the CPPI DMA This field is cl...

Page 2118: ...ia the CPPI DMA This field is cleared when read via the cpu 23 16 FDBQ30_STARVE_CNT R 0 0 This field increments each time the Free Descriptor Buffer Queue 30 is read while it is empty via the CPPI DMA This field is cleared when read via the cpu 15 8 FDBQ29_STARVE_CNT R 0 0 This field increments each time the Free Descriptor Buffer Queue 29 is read while it is empty via the CPPI DMA This field is c...

Page 2119: ...ead Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 301 LRAM0BASE Register Field Descriptions Bit Field Type Reset Description 31 2 REGION0_BASE R W 0 0 This field stores the base address for the first region of the linking RAM This may be anywhere in 32 bit address space but would be typically located in on chip memory 2119 SPRUH73H October 2011 Revised April 2013 Unive...

Page 2120: ...EGION0_SIZE R W 0 0 This field indicates the number of entries that are contained in the linking RAM region 0 A descriptor with index less than region0_size value has its linking location in region 0 A descriptor with index greater than region0_size has its linking location in region 1 The queue manager will add the index left shifted by 2 bits to the appropriate regionX_base_addr to get the absol...

Page 2121: ...ad Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 303 LRAM1BASE Register Field Descriptions Bit Field Type Reset Description 31 2 REGION1_BASE R W 0 0 This field stores the base address for the second region of the linking RAM This may be anywhere in 32 bit address space but would be typically located in off chip memory 2121 SPRUH73H October 2011 Revised April 2013 Univ...

Page 2122: ...0 9 8 7 6 5 4 3 2 1 0 QPEND0 R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 304 PEND0 Register Field Descriptions Bit Field Type Reset Description 31 0 QPEND0 R 0 0 This field indicates the queue pending status for queues 31 0 2122 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texa...

Page 2123: ... QPEND1 R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 305 PEND1 Register Field Descriptions Bit Field Type Reset Description 31 0 QPEND1 R 0 0 This field indicates the queue pending status for queues 63 32 Table 118 QMGR_Queue_Pending_1 Register 1 2123 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Co...

Page 2124: ... QPEND2 R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 306 PEND2 Register Field Descriptions Bit Field Type Reset Description 31 0 QPEND2 R 0 0 This field indicates the queue pending status for queues 95 64 Queue_Manager_Queue_Pending_2 Register 2 2124 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Cop...

Page 2125: ... QPEND3 R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 307 PEND3 Register Field Descriptions Bit Field Type Reset Description 31 0 QPEND3 R 0 0 This field indicates the queue pending status for queues 127 96 Queue_Manager_Queue_Pending_3 Register 3 2125 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Co...

Page 2126: ...QPEND4 R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 308 PEND4 Register Field Descriptions Bit Field Type Reset Description 31 0 QPEND4 R 0 0 This field indicates the queue pending status for queues 159 128 Queue_Manager_Queue_Pending_4 Register 4 2126 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Co...

Page 2127: ...11 10 9 8 7 6 5 4 3 2 1 0 REG Reserved R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 309 QMEMRBASE0 Register Field Descriptions Bit Field Type Reset Description 31 5 REG R W 0 0 This field contains the base address of the memory region R 2127 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright ...

Page 2128: ...in terms of number of descriptors It is an encoded value that specifies region size as 2 5 reg_size number of descriptors Queue Manager Memory Region R Control Registers The following sections describe each of the four register locations that may be present for each queue in the queues region For reasons of implementation and area efficiency these registers are not actually implemented as a huge a...

Page 2129: ...11 10 9 8 7 6 5 4 3 2 1 0 REG Reserved R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 311 QMEMRBASE1 Register Field Descriptions Bit Field Type Reset Description 31 5 REG R W 0 0 This field contains the base address of the memory region R 2129 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright ...

Page 2130: ...in terms of number of descriptors It is an encoded value that specifies region size as 2 5 reg_size number of descriptors Queue Manager Memory Region R Control Registers The following sections describe each of the four register locations that may be present for each queue in the queues region For reasons of implementation and area efficiency these registers are not actually implemented as a huge a...

Page 2131: ...11 10 9 8 7 6 5 4 3 2 1 0 REG Reserved R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 313 QMEMRBASE2 Register Field Descriptions Bit Field Type Reset Description 31 5 REG R W 0 0 This field contains the base address of the memory region R 2131 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright ...

Page 2132: ...in terms of number of descriptors It is an encoded value that specifies region size as 2 5 reg_size number of descriptors Queue Manager Memory Region R Control Registers The following sections describe each of the four register locations that may be present for each queue in the queues region For reasons of implementation and area efficiency these registers are not actually implemented as a huge a...

Page 2133: ...11 10 9 8 7 6 5 4 3 2 1 0 REG Reserved R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 315 QMEMRBASE3 Register Field Descriptions Bit Field Type Reset Description 31 5 REG R W 0 0 This field contains the base address of the memory region R 2133 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright ...

Page 2134: ...in terms of number of descriptors It is an encoded value that specifies region size as 2 5 reg_size number of descriptors Queue Manager Memory Region R Control Registers The following sections describe each of the four register locations that may be present for each queue in the queues region For reasons of implementation and area efficiency these registers are not actually implemented as a huge a...

Page 2135: ...11 10 9 8 7 6 5 4 3 2 1 0 REG Reserved R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 317 QMEMRBASE4 Register Field Descriptions Bit Field Type Reset Description 31 5 REG R W 0 0 This field contains the base address of the memory region R 2135 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright ...

Page 2136: ...in terms of number of descriptors It is an encoded value that specifies region size as 2 5 reg_size number of descriptors Queue Manager Memory Region R Control Registers The following sections describe each of the four register locations that may be present for each queue in the queues region For reasons of implementation and area efficiency these registers are not actually implemented as a huge a...

Page 2137: ...11 10 9 8 7 6 5 4 3 2 1 0 REG Reserved R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 319 QMEMRBASE5 Register Field Descriptions Bit Field Type Reset Description 31 5 REG R W 0 0 This field contains the base address of the memory region R 2137 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright ...

Page 2138: ...in terms of number of descriptors It is an encoded value that specifies region size as 2 5 reg_size number of descriptors Queue Manager Memory Region R Control Registers The following sections describe each of the four register locations that may be present for each queue in the queues region For reasons of implementation and area efficiency these registers are not actually implemented as a huge a...

Page 2139: ...11 10 9 8 7 6 5 4 3 2 1 0 REG Reserved R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 321 QMEMRBASE6 Register Field Descriptions Bit Field Type Reset Description 31 5 REG R W 0 0 This field contains the base address of the memory region R 2139 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright ...

Page 2140: ...in terms of number of descriptors It is an encoded value that specifies region size as 2 5 reg_size number of descriptors Queue Manager Memory Region R Control Registers The following sections describe each of the four register locations that may be present for each queue in the queues region For reasons of implementation and area efficiency these registers are not actually implemented as a huge a...

Page 2141: ...11 10 9 8 7 6 5 4 3 2 1 0 REG Reserved R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 323 QMEMRBASE7 Register Field Descriptions Bit Field Type Reset Description 31 5 REG R W 0 0 This field contains the base address of the memory region R 2141 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus USB Submit Documentation Feedback Copyright ...

Page 2142: ...in terms of number of descriptors It is an encoded value that specifies region size as 2 5 reg_size number of descriptors Queue Manager Memory Region R Control Registers The following sections describe each of the four register locations that may be present for each queue in the queues region For reasons of implementation and area efficiency these registers are not actually implemented as a huge a...

Page 2143: ...1toCl Write 1 to clear bit n value after reset Table 16 325 QUEUE_0_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2143 SPRUH73H October 2...

Page 2144: ...YTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 326 QUEUE_0_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2144 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Su...

Page 2145: ...r reset Table 16 327 QUEUE_0_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overwri...

Page 2146: ... to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that is r...

Page 2147: ...1toCl Write 1 to clear bit n value after reset Table 16 329 QUEUE_1_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2147 SPRUH73H October 2...

Page 2148: ...YTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 330 QUEUE_1_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2148 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Su...

Page 2149: ...r reset Table 16 331 QUEUE_1_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overwri...

Page 2150: ... to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that is r...

Page 2151: ...1toCl Write 1 to clear bit n value after reset Table 16 333 QUEUE_2_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2151 SPRUH73H October 2...

Page 2152: ...YTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 334 QUEUE_2_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2152 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Su...

Page 2153: ...r reset Table 16 335 QUEUE_2_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overwri...

Page 2154: ... to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that is r...

Page 2155: ...1toCl Write 1 to clear bit n value after reset Table 16 337 QUEUE_3_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2155 SPRUH73H October 2...

Page 2156: ...YTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 338 QUEUE_3_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2156 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Su...

Page 2157: ...r reset Table 16 339 QUEUE_3_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overwri...

Page 2158: ... to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that is r...

Page 2159: ...1toCl Write 1 to clear bit n value after reset Table 16 341 QUEUE_4_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2159 SPRUH73H October 2...

Page 2160: ...YTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 342 QUEUE_4_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2160 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Su...

Page 2161: ...r reset Table 16 343 QUEUE_4_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overwri...

Page 2162: ... to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that is r...

Page 2163: ...1toCl Write 1 to clear bit n value after reset Table 16 345 QUEUE_5_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2163 SPRUH73H October 2...

Page 2164: ...YTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 346 QUEUE_5_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2164 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Su...

Page 2165: ...r reset Table 16 347 QUEUE_5_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overwri...

Page 2166: ... to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that is r...

Page 2167: ...1toCl Write 1 to clear bit n value after reset Table 16 349 QUEUE_6_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2167 SPRUH73H October 2...

Page 2168: ...YTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 350 QUEUE_6_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2168 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Su...

Page 2169: ...r reset Table 16 351 QUEUE_6_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overwri...

Page 2170: ... to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that is r...

Page 2171: ...1toCl Write 1 to clear bit n value after reset Table 16 353 QUEUE_7_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2171 SPRUH73H October 2...

Page 2172: ...YTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 354 QUEUE_7_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2172 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Su...

Page 2173: ...r reset Table 16 355 QUEUE_7_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overwri...

Page 2174: ... to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that is r...

Page 2175: ...1toCl Write 1 to clear bit n value after reset Table 16 357 QUEUE_8_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2175 SPRUH73H October 2...

Page 2176: ...YTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 358 QUEUE_8_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2176 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Su...

Page 2177: ...r reset Table 16 359 QUEUE_8_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overwri...

Page 2178: ... to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that is r...

Page 2179: ...1toCl Write 1 to clear bit n value after reset Table 16 361 QUEUE_9_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2179 SPRUH73H October 2...

Page 2180: ...YTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 362 QUEUE_9_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2180 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 Su...

Page 2181: ...r reset Table 16 363 QUEUE_9_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overwri...

Page 2182: ... to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that is r...

Page 2183: ...W1toCl Write 1 to clear bit n value after reset Table 16 365 QUEUE_10_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2183 SPRUH73H October...

Page 2184: ...BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 366 QUEUE_10_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2184 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 ...

Page 2185: ...er reset Table 16 367 QUEUE_10_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2186: ...on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that is...

Page 2187: ...W1toCl Write 1 to clear bit n value after reset Table 16 369 QUEUE_11_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2187 SPRUH73H October...

Page 2188: ...BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 370 QUEUE_11_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2188 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 ...

Page 2189: ...er reset Table 16 371 QUEUE_11_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2190: ...on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that is...

Page 2191: ...W1toCl Write 1 to clear bit n value after reset Table 16 373 QUEUE_12_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2191 SPRUH73H October...

Page 2192: ...BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 374 QUEUE_12_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2192 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 ...

Page 2193: ...er reset Table 16 375 QUEUE_12_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2194: ...on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that is...

Page 2195: ...W1toCl Write 1 to clear bit n value after reset Table 16 377 QUEUE_13_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2195 SPRUH73H October...

Page 2196: ...BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 378 QUEUE_13_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2196 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 ...

Page 2197: ...er reset Table 16 379 QUEUE_13_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2198: ...on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that is...

Page 2199: ...W1toCl Write 1 to clear bit n value after reset Table 16 381 QUEUE_14_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2199 SPRUH73H October...

Page 2200: ...BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 382 QUEUE_14_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2200 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 ...

Page 2201: ...er reset Table 16 383 QUEUE_14_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2202: ...on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that is...

Page 2203: ...W1toCl Write 1 to clear bit n value after reset Table 16 385 QUEUE_15_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2203 SPRUH73H October...

Page 2204: ...BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 386 QUEUE_15_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2204 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013 ...

Page 2205: ...er reset Table 16 387 QUEUE_15_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2206: ...on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that is...

Page 2207: ...W1toCl Write 1 to clear bit n value after reset Table 16 389 QUEUE_16_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2207 SPRUH73H October...

Page 2208: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 390 QUEUE_16_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2208 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2209: ...er reset Table 16 391 QUEUE_16_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2210: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2211: ... W1toCl Write 1 to clear bit n value after reset Table 16 393 QUEUE_17_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2211 SPRUH73H Octobe...

Page 2212: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 394 QUEUE_17_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2212 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2213: ...er reset Table 16 395 QUEUE_17_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2214: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2215: ... W1toCl Write 1 to clear bit n value after reset Table 16 397 QUEUE_18_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2215 SPRUH73H Octobe...

Page 2216: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 398 QUEUE_18_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2216 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2217: ...er reset Table 16 399 QUEUE_18_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2218: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2219: ... W1toCl Write 1 to clear bit n value after reset Table 16 401 QUEUE_19_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2219 SPRUH73H Octobe...

Page 2220: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 402 QUEUE_19_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2220 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2221: ...er reset Table 16 403 QUEUE_19_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2222: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2223: ... W1toCl Write 1 to clear bit n value after reset Table 16 405 QUEUE_20_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2223 SPRUH73H Octobe...

Page 2224: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 406 QUEUE_20_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2224 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2225: ...er reset Table 16 407 QUEUE_20_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2226: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2227: ... W1toCl Write 1 to clear bit n value after reset Table 16 409 QUEUE_21_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2227 SPRUH73H Octobe...

Page 2228: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 410 QUEUE_21_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2228 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2229: ...er reset Table 16 411 QUEUE_21_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2230: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2231: ... W1toCl Write 1 to clear bit n value after reset Table 16 413 QUEUE_22_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2231 SPRUH73H Octobe...

Page 2232: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 414 QUEUE_22_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2232 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2233: ...er reset Table 16 415 QUEUE_22_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2234: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2235: ... W1toCl Write 1 to clear bit n value after reset Table 16 417 QUEUE_23_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2235 SPRUH73H Octobe...

Page 2236: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 418 QUEUE_23_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2236 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2237: ...er reset Table 16 419 QUEUE_23_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2238: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2239: ... W1toCl Write 1 to clear bit n value after reset Table 16 421 QUEUE_24_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2239 SPRUH73H Octobe...

Page 2240: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 422 QUEUE_24_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2240 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2241: ...er reset Table 16 423 QUEUE_24_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2242: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2243: ... W1toCl Write 1 to clear bit n value after reset Table 16 425 QUEUE_25_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2243 SPRUH73H Octobe...

Page 2244: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 426 QUEUE_25_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2244 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2245: ...er reset Table 16 427 QUEUE_25_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2246: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2247: ... W1toCl Write 1 to clear bit n value after reset Table 16 429 QUEUE_26_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2247 SPRUH73H Octobe...

Page 2248: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 430 QUEUE_26_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2248 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2249: ...er reset Table 16 431 QUEUE_26_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2250: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2251: ... W1toCl Write 1 to clear bit n value after reset Table 16 433 QUEUE_27_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2251 SPRUH73H Octobe...

Page 2252: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 434 QUEUE_27_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2252 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2253: ...er reset Table 16 435 QUEUE_27_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2254: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2255: ... W1toCl Write 1 to clear bit n value after reset Table 16 437 QUEUE_28_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2255 SPRUH73H Octobe...

Page 2256: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 438 QUEUE_28_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2256 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2257: ...er reset Table 16 439 QUEUE_28_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2258: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2259: ... W1toCl Write 1 to clear bit n value after reset Table 16 441 QUEUE_29_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2259 SPRUH73H Octobe...

Page 2260: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 442 QUEUE_29_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2260 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2261: ...er reset Table 16 443 QUEUE_29_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2262: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2263: ... W1toCl Write 1 to clear bit n value after reset Table 16 445 QUEUE_30_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2263 SPRUH73H Octobe...

Page 2264: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 446 QUEUE_30_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2264 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2265: ...er reset Table 16 447 QUEUE_30_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2266: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2267: ... W1toCl Write 1 to clear bit n value after reset Table 16 449 QUEUE_31_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2267 SPRUH73H Octobe...

Page 2268: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 450 QUEUE_31_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2268 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2269: ...er reset Table 16 451 QUEUE_31_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2270: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2271: ... W1toCl Write 1 to clear bit n value after reset Table 16 453 QUEUE_32_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2271 SPRUH73H Octobe...

Page 2272: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 454 QUEUE_32_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2272 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2273: ...er reset Table 16 455 QUEUE_32_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2274: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2275: ... W1toCl Write 1 to clear bit n value after reset Table 16 457 QUEUE_33_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2275 SPRUH73H Octobe...

Page 2276: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 458 QUEUE_33_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2276 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2277: ...er reset Table 16 459 QUEUE_33_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2278: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2279: ... W1toCl Write 1 to clear bit n value after reset Table 16 461 QUEUE_34_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2279 SPRUH73H Octobe...

Page 2280: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 462 QUEUE_34_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2280 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2281: ...er reset Table 16 463 QUEUE_34_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2282: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2283: ... W1toCl Write 1 to clear bit n value after reset Table 16 465 QUEUE_35_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2283 SPRUH73H Octobe...

Page 2284: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 466 QUEUE_35_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2284 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2285: ...er reset Table 16 467 QUEUE_35_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2286: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2287: ... W1toCl Write 1 to clear bit n value after reset Table 16 469 QUEUE_36_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2287 SPRUH73H Octobe...

Page 2288: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 470 QUEUE_36_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2288 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2289: ...er reset Table 16 471 QUEUE_36_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2290: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2291: ... W1toCl Write 1 to clear bit n value after reset Table 16 473 QUEUE_37_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2291 SPRUH73H Octobe...

Page 2292: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 474 QUEUE_37_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2292 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2293: ...er reset Table 16 475 QUEUE_37_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2294: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2295: ... W1toCl Write 1 to clear bit n value after reset Table 16 477 QUEUE_38_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2295 SPRUH73H Octobe...

Page 2296: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 478 QUEUE_38_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2296 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2297: ...er reset Table 16 479 QUEUE_38_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2298: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2299: ... W1toCl Write 1 to clear bit n value after reset Table 16 481 QUEUE_39_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2299 SPRUH73H Octobe...

Page 2300: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 482 QUEUE_39_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2300 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2301: ...er reset Table 16 483 QUEUE_39_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2302: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2303: ... W1toCl Write 1 to clear bit n value after reset Table 16 485 QUEUE_40_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2303 SPRUH73H Octobe...

Page 2304: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 486 QUEUE_40_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2304 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2305: ...er reset Table 16 487 QUEUE_40_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2306: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2307: ... W1toCl Write 1 to clear bit n value after reset Table 16 489 QUEUE_41_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2307 SPRUH73H Octobe...

Page 2308: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 490 QUEUE_41_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2308 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2309: ...er reset Table 16 491 QUEUE_41_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2310: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2311: ... W1toCl Write 1 to clear bit n value after reset Table 16 493 QUEUE_42_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2311 SPRUH73H Octobe...

Page 2312: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 494 QUEUE_42_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2312 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2313: ...er reset Table 16 495 QUEUE_42_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2314: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2315: ... W1toCl Write 1 to clear bit n value after reset Table 16 497 QUEUE_43_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2315 SPRUH73H Octobe...

Page 2316: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 498 QUEUE_43_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2316 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2317: ...er reset Table 16 499 QUEUE_43_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2318: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2319: ... W1toCl Write 1 to clear bit n value after reset Table 16 501 QUEUE_44_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2319 SPRUH73H Octobe...

Page 2320: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 502 QUEUE_44_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2320 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2321: ...er reset Table 16 503 QUEUE_44_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2322: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2323: ... W1toCl Write 1 to clear bit n value after reset Table 16 505 QUEUE_45_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2323 SPRUH73H Octobe...

Page 2324: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 506 QUEUE_45_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2324 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2325: ...er reset Table 16 507 QUEUE_45_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2326: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2327: ... W1toCl Write 1 to clear bit n value after reset Table 16 509 QUEUE_46_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2327 SPRUH73H Octobe...

Page 2328: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 510 QUEUE_46_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2328 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2329: ...er reset Table 16 511 QUEUE_46_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2330: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2331: ... W1toCl Write 1 to clear bit n value after reset Table 16 513 QUEUE_47_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2331 SPRUH73H Octobe...

Page 2332: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 514 QUEUE_47_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2332 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2333: ...er reset Table 16 515 QUEUE_47_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2334: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2335: ... W1toCl Write 1 to clear bit n value after reset Table 16 517 QUEUE_48_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2335 SPRUH73H Octobe...

Page 2336: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 518 QUEUE_48_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2336 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2337: ...er reset Table 16 519 QUEUE_48_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2338: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2339: ... W1toCl Write 1 to clear bit n value after reset Table 16 521 QUEUE_49_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2339 SPRUH73H Octobe...

Page 2340: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 522 QUEUE_49_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2340 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2341: ...er reset Table 16 523 QUEUE_49_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2342: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2343: ... W1toCl Write 1 to clear bit n value after reset Table 16 525 QUEUE_50_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2343 SPRUH73H Octobe...

Page 2344: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 526 QUEUE_50_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2344 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2345: ...er reset Table 16 527 QUEUE_50_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2346: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2347: ... W1toCl Write 1 to clear bit n value after reset Table 16 529 QUEUE_51_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2347 SPRUH73H Octobe...

Page 2348: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 530 QUEUE_51_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2348 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2349: ...er reset Table 16 531 QUEUE_51_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2350: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2351: ... W1toCl Write 1 to clear bit n value after reset Table 16 533 QUEUE_52_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2351 SPRUH73H Octobe...

Page 2352: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 534 QUEUE_52_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2352 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2353: ...er reset Table 16 535 QUEUE_52_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2354: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2355: ... W1toCl Write 1 to clear bit n value after reset Table 16 537 QUEUE_53_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2355 SPRUH73H Octobe...

Page 2356: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 538 QUEUE_53_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2356 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2357: ...er reset Table 16 539 QUEUE_53_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2358: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2359: ... W1toCl Write 1 to clear bit n value after reset Table 16 541 QUEUE_54_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2359 SPRUH73H Octobe...

Page 2360: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 542 QUEUE_54_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2360 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2361: ...er reset Table 16 543 QUEUE_54_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2362: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2363: ... W1toCl Write 1 to clear bit n value after reset Table 16 545 QUEUE_55_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2363 SPRUH73H Octobe...

Page 2364: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 546 QUEUE_55_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2364 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2365: ...er reset Table 16 547 QUEUE_55_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2366: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2367: ... W1toCl Write 1 to clear bit n value after reset Table 16 549 QUEUE_56_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2367 SPRUH73H Octobe...

Page 2368: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 550 QUEUE_56_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2368 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2369: ...er reset Table 16 551 QUEUE_56_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2370: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2371: ... W1toCl Write 1 to clear bit n value after reset Table 16 553 QUEUE_57_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2371 SPRUH73H Octobe...

Page 2372: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 554 QUEUE_57_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2372 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2373: ...er reset Table 16 555 QUEUE_57_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2374: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2375: ... W1toCl Write 1 to clear bit n value after reset Table 16 557 QUEUE_58_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2375 SPRUH73H Octobe...

Page 2376: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 558 QUEUE_58_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2376 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2377: ...er reset Table 16 559 QUEUE_58_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2378: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2379: ... W1toCl Write 1 to clear bit n value after reset Table 16 561 QUEUE_59_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2379 SPRUH73H Octobe...

Page 2380: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 562 QUEUE_59_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2380 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2381: ...er reset Table 16 563 QUEUE_59_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2382: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2383: ... W1toCl Write 1 to clear bit n value after reset Table 16 565 QUEUE_60_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2383 SPRUH73H Octobe...

Page 2384: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 566 QUEUE_60_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2384 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2385: ...er reset Table 16 567 QUEUE_60_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2386: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2387: ... W1toCl Write 1 to clear bit n value after reset Table 16 569 QUEUE_61_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2387 SPRUH73H Octobe...

Page 2388: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 570 QUEUE_61_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2388 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2389: ...er reset Table 16 571 QUEUE_61_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2390: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2391: ... W1toCl Write 1 to clear bit n value after reset Table 16 573 QUEUE_62_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2391 SPRUH73H Octobe...

Page 2392: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 574 QUEUE_62_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2392 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2393: ...er reset Table 16 575 QUEUE_62_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2394: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2395: ... W1toCl Write 1 to clear bit n value after reset Table 16 577 QUEUE_63_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2395 SPRUH73H Octobe...

Page 2396: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 578 QUEUE_63_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2396 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2397: ...er reset Table 16 579 QUEUE_63_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2398: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2399: ... W1toCl Write 1 to clear bit n value after reset Table 16 581 QUEUE_64_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2399 SPRUH73H Octobe...

Page 2400: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 582 QUEUE_64_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2400 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2401: ...er reset Table 16 583 QUEUE_64_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2402: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2403: ... W1toCl Write 1 to clear bit n value after reset Table 16 585 QUEUE_65_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2403 SPRUH73H Octobe...

Page 2404: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 586 QUEUE_65_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2404 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2405: ...er reset Table 16 587 QUEUE_65_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2406: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2407: ... W1toCl Write 1 to clear bit n value after reset Table 16 589 QUEUE_66_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2407 SPRUH73H Octobe...

Page 2408: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 590 QUEUE_66_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2408 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2409: ...er reset Table 16 591 QUEUE_66_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2410: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2411: ... W1toCl Write 1 to clear bit n value after reset Table 16 593 QUEUE_67_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2411 SPRUH73H Octobe...

Page 2412: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 594 QUEUE_67_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2412 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2413: ...er reset Table 16 595 QUEUE_67_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2414: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2415: ... W1toCl Write 1 to clear bit n value after reset Table 16 597 QUEUE_68_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2415 SPRUH73H Octobe...

Page 2416: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 598 QUEUE_68_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2416 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2417: ...er reset Table 16 599 QUEUE_68_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2418: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2419: ... W1toCl Write 1 to clear bit n value after reset Table 16 601 QUEUE_69_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2419 SPRUH73H Octobe...

Page 2420: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 602 QUEUE_69_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2420 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2421: ...er reset Table 16 603 QUEUE_69_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2422: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2423: ... W1toCl Write 1 to clear bit n value after reset Table 16 605 QUEUE_70_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2423 SPRUH73H Octobe...

Page 2424: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 606 QUEUE_70_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2424 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2425: ...er reset Table 16 607 QUEUE_70_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2426: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2427: ... W1toCl Write 1 to clear bit n value after reset Table 16 609 QUEUE_71_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2427 SPRUH73H Octobe...

Page 2428: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 610 QUEUE_71_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2428 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2429: ...er reset Table 16 611 QUEUE_71_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2430: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2431: ... W1toCl Write 1 to clear bit n value after reset Table 16 613 QUEUE_72_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2431 SPRUH73H Octobe...

Page 2432: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 614 QUEUE_72_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2432 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2433: ...er reset Table 16 615 QUEUE_72_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2434: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2435: ... W1toCl Write 1 to clear bit n value after reset Table 16 617 QUEUE_73_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2435 SPRUH73H Octobe...

Page 2436: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 618 QUEUE_73_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2436 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2437: ...er reset Table 16 619 QUEUE_73_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2438: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2439: ... W1toCl Write 1 to clear bit n value after reset Table 16 621 QUEUE_74_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2439 SPRUH73H Octobe...

Page 2440: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 622 QUEUE_74_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2440 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2441: ...er reset Table 16 623 QUEUE_74_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2442: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2443: ... W1toCl Write 1 to clear bit n value after reset Table 16 625 QUEUE_75_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2443 SPRUH73H Octobe...

Page 2444: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 626 QUEUE_75_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2444 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2445: ...er reset Table 16 627 QUEUE_75_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2446: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2447: ... W1toCl Write 1 to clear bit n value after reset Table 16 629 QUEUE_76_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2447 SPRUH73H Octobe...

Page 2448: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 630 QUEUE_76_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2448 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2449: ...er reset Table 16 631 QUEUE_76_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2450: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2451: ... W1toCl Write 1 to clear bit n value after reset Table 16 633 QUEUE_77_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2451 SPRUH73H Octobe...

Page 2452: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 634 QUEUE_77_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2452 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2453: ...er reset Table 16 635 QUEUE_77_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2454: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2455: ... W1toCl Write 1 to clear bit n value after reset Table 16 637 QUEUE_78_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2455 SPRUH73H Octobe...

Page 2456: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 638 QUEUE_78_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2456 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2457: ...er reset Table 16 639 QUEUE_78_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2458: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2459: ... W1toCl Write 1 to clear bit n value after reset Table 16 641 QUEUE_79_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2459 SPRUH73H Octobe...

Page 2460: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 642 QUEUE_79_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2460 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2461: ...er reset Table 16 643 QUEUE_79_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2462: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2463: ... W1toCl Write 1 to clear bit n value after reset Table 16 645 QUEUE_80_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2463 SPRUH73H Octobe...

Page 2464: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 646 QUEUE_80_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2464 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2465: ...er reset Table 16 647 QUEUE_80_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2466: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2467: ... W1toCl Write 1 to clear bit n value after reset Table 16 649 QUEUE_81_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2467 SPRUH73H Octobe...

Page 2468: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 650 QUEUE_81_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2468 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2469: ...er reset Table 16 651 QUEUE_81_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2470: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2471: ... W1toCl Write 1 to clear bit n value after reset Table 16 653 QUEUE_82_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2471 SPRUH73H Octobe...

Page 2472: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 654 QUEUE_82_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2472 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2473: ...er reset Table 16 655 QUEUE_82_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2474: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2475: ... W1toCl Write 1 to clear bit n value after reset Table 16 657 QUEUE_83_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2475 SPRUH73H Octobe...

Page 2476: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 658 QUEUE_83_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2476 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2477: ...er reset Table 16 659 QUEUE_83_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2478: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2479: ... W1toCl Write 1 to clear bit n value after reset Table 16 661 QUEUE_84_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2479 SPRUH73H Octobe...

Page 2480: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 662 QUEUE_84_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2480 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2481: ...er reset Table 16 663 QUEUE_84_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2482: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2483: ... W1toCl Write 1 to clear bit n value after reset Table 16 665 QUEUE_85_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2483 SPRUH73H Octobe...

Page 2484: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 666 QUEUE_85_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2484 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2485: ...er reset Table 16 667 QUEUE_85_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2486: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2487: ... W1toCl Write 1 to clear bit n value after reset Table 16 669 QUEUE_86_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2487 SPRUH73H Octobe...

Page 2488: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 670 QUEUE_86_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2488 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2489: ...er reset Table 16 671 QUEUE_86_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2490: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2491: ... W1toCl Write 1 to clear bit n value after reset Table 16 673 QUEUE_87_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2491 SPRUH73H Octobe...

Page 2492: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 674 QUEUE_87_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2492 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2493: ...er reset Table 16 675 QUEUE_87_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2494: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2495: ... W1toCl Write 1 to clear bit n value after reset Table 16 677 QUEUE_88_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2495 SPRUH73H Octobe...

Page 2496: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 678 QUEUE_88_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2496 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2497: ...er reset Table 16 679 QUEUE_88_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2498: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2499: ... W1toCl Write 1 to clear bit n value after reset Table 16 681 QUEUE_89_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2499 SPRUH73H Octobe...

Page 2500: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 682 QUEUE_89_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2500 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2501: ...er reset Table 16 683 QUEUE_89_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2502: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2503: ... W1toCl Write 1 to clear bit n value after reset Table 16 685 QUEUE_90_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2503 SPRUH73H Octobe...

Page 2504: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 686 QUEUE_90_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2504 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2505: ...er reset Table 16 687 QUEUE_90_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2506: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2507: ... W1toCl Write 1 to clear bit n value after reset Table 16 689 QUEUE_91_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2507 SPRUH73H Octobe...

Page 2508: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 690 QUEUE_91_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2508 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2509: ...er reset Table 16 691 QUEUE_91_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2510: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2511: ... W1toCl Write 1 to clear bit n value after reset Table 16 693 QUEUE_92_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2511 SPRUH73H Octobe...

Page 2512: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 694 QUEUE_92_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2512 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2513: ...er reset Table 16 695 QUEUE_92_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2514: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2515: ... W1toCl Write 1 to clear bit n value after reset Table 16 697 QUEUE_93_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2515 SPRUH73H Octobe...

Page 2516: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 698 QUEUE_93_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2516 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2517: ...er reset Table 16 699 QUEUE_93_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2518: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2519: ... W1toCl Write 1 to clear bit n value after reset Table 16 701 QUEUE_94_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2519 SPRUH73H Octobe...

Page 2520: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 702 QUEUE_94_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2520 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2521: ...er reset Table 16 703 QUEUE_94_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2522: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2523: ... W1toCl Write 1 to clear bit n value after reset Table 16 705 QUEUE_95_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2523 SPRUH73H Octobe...

Page 2524: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 706 QUEUE_95_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2524 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2525: ...er reset Table 16 707 QUEUE_95_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2526: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2527: ... W1toCl Write 1 to clear bit n value after reset Table 16 709 QUEUE_96_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2527 SPRUH73H Octobe...

Page 2528: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 710 QUEUE_96_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2528 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2529: ...er reset Table 16 711 QUEUE_96_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2530: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2531: ... W1toCl Write 1 to clear bit n value after reset Table 16 713 QUEUE_97_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2531 SPRUH73H Octobe...

Page 2532: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 714 QUEUE_97_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2532 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2533: ...er reset Table 16 715 QUEUE_97_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2534: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2535: ... W1toCl Write 1 to clear bit n value after reset Table 16 717 QUEUE_98_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2535 SPRUH73H Octobe...

Page 2536: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 718 QUEUE_98_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2536 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2537: ...er reset Table 16 719 QUEUE_98_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2538: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2539: ... W1toCl Write 1 to clear bit n value after reset Table 16 721 QUEUE_99_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2539 SPRUH73H Octobe...

Page 2540: ..._BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 722 QUEUE_99_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2540 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2013...

Page 2541: ...er reset Table 16 723 QUEUE_99_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly overw...

Page 2542: ... on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that i...

Page 2543: ...y W1toCl Write 1 to clear bit n value after reset Table 16 725 QUEUE_100_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2543 SPRUH73H Octo...

Page 2544: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 726 QUEUE_100_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2544 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2545: ...ter reset Table 16 727 QUEUE_100_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2546: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2547: ...y W1toCl Write 1 to clear bit n value after reset Table 16 729 QUEUE_101_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2547 SPRUH73H Octo...

Page 2548: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 730 QUEUE_101_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2548 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2549: ...ter reset Table 16 731 QUEUE_101_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2550: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2551: ...y W1toCl Write 1 to clear bit n value after reset Table 16 733 QUEUE_102_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2551 SPRUH73H Octo...

Page 2552: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 734 QUEUE_102_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2552 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2553: ...ter reset Table 16 735 QUEUE_102_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2554: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2555: ...y W1toCl Write 1 to clear bit n value after reset Table 16 737 QUEUE_103_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2555 SPRUH73H Octo...

Page 2556: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 738 QUEUE_103_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2556 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2557: ...ter reset Table 16 739 QUEUE_103_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2558: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2559: ...y W1toCl Write 1 to clear bit n value after reset Table 16 741 QUEUE_104_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2559 SPRUH73H Octo...

Page 2560: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 742 QUEUE_104_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2560 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2561: ...ter reset Table 16 743 QUEUE_104_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2562: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2563: ...y W1toCl Write 1 to clear bit n value after reset Table 16 745 QUEUE_105_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2563 SPRUH73H Octo...

Page 2564: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 746 QUEUE_105_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2564 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2565: ...ter reset Table 16 747 QUEUE_105_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2566: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2567: ...y W1toCl Write 1 to clear bit n value after reset Table 16 749 QUEUE_106_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2567 SPRUH73H Octo...

Page 2568: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 750 QUEUE_106_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2568 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2569: ...ter reset Table 16 751 QUEUE_106_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2570: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2571: ...y W1toCl Write 1 to clear bit n value after reset Table 16 753 QUEUE_107_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2571 SPRUH73H Octo...

Page 2572: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 754 QUEUE_107_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2572 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2573: ...ter reset Table 16 755 QUEUE_107_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2574: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2575: ...y W1toCl Write 1 to clear bit n value after reset Table 16 757 QUEUE_108_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2575 SPRUH73H Octo...

Page 2576: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 758 QUEUE_108_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2576 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2577: ...ter reset Table 16 759 QUEUE_108_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2578: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2579: ...y W1toCl Write 1 to clear bit n value after reset Table 16 761 QUEUE_109_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2579 SPRUH73H Octo...

Page 2580: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 762 QUEUE_109_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2580 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2581: ...ter reset Table 16 763 QUEUE_109_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2582: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2583: ...y W1toCl Write 1 to clear bit n value after reset Table 16 765 QUEUE_110_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2583 SPRUH73H Octo...

Page 2584: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 766 QUEUE_110_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2584 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2585: ...ter reset Table 16 767 QUEUE_110_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2586: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2587: ...y W1toCl Write 1 to clear bit n value after reset Table 16 769 QUEUE_111_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2587 SPRUH73H Octo...

Page 2588: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 770 QUEUE_111_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2588 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2589: ...ter reset Table 16 771 QUEUE_111_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2590: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2591: ...y W1toCl Write 1 to clear bit n value after reset Table 16 773 QUEUE_112_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2591 SPRUH73H Octo...

Page 2592: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 774 QUEUE_112_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2592 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2593: ...ter reset Table 16 775 QUEUE_112_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2594: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2595: ...y W1toCl Write 1 to clear bit n value after reset Table 16 777 QUEUE_113_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2595 SPRUH73H Octo...

Page 2596: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 778 QUEUE_113_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2596 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2597: ...ter reset Table 16 779 QUEUE_113_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2598: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2599: ...y W1toCl Write 1 to clear bit n value after reset Table 16 781 QUEUE_114_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2599 SPRUH73H Octo...

Page 2600: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 782 QUEUE_114_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2600 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2601: ...ter reset Table 16 783 QUEUE_114_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2602: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2603: ...y W1toCl Write 1 to clear bit n value after reset Table 16 785 QUEUE_115_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2603 SPRUH73H Octo...

Page 2604: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 786 QUEUE_115_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2604 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2605: ...ter reset Table 16 787 QUEUE_115_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2606: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2607: ...y W1toCl Write 1 to clear bit n value after reset Table 16 789 QUEUE_116_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2607 SPRUH73H Octo...

Page 2608: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 790 QUEUE_116_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2608 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2609: ...ter reset Table 16 791 QUEUE_116_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2610: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2611: ...y W1toCl Write 1 to clear bit n value after reset Table 16 793 QUEUE_117_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2611 SPRUH73H Octo...

Page 2612: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 794 QUEUE_117_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2612 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2613: ...ter reset Table 16 795 QUEUE_117_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2614: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2615: ...y W1toCl Write 1 to clear bit n value after reset Table 16 797 QUEUE_118_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2615 SPRUH73H Octo...

Page 2616: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 798 QUEUE_118_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2616 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2617: ...ter reset Table 16 799 QUEUE_118_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2618: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2619: ...y W1toCl Write 1 to clear bit n value after reset Table 16 801 QUEUE_119_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2619 SPRUH73H Octo...

Page 2620: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 802 QUEUE_119_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2620 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2621: ...ter reset Table 16 803 QUEUE_119_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2622: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2623: ...y W1toCl Write 1 to clear bit n value after reset Table 16 805 QUEUE_120_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2623 SPRUH73H Octo...

Page 2624: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 806 QUEUE_120_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2624 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2625: ...ter reset Table 16 807 QUEUE_120_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2626: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2627: ...y W1toCl Write 1 to clear bit n value after reset Table 16 809 QUEUE_121_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2627 SPRUH73H Octo...

Page 2628: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 810 QUEUE_121_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2628 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2629: ...ter reset Table 16 811 QUEUE_121_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2630: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2631: ...y W1toCl Write 1 to clear bit n value after reset Table 16 813 QUEUE_122_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2631 SPRUH73H Octo...

Page 2632: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 814 QUEUE_122_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2632 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2633: ...ter reset Table 16 815 QUEUE_122_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2634: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2635: ...y W1toCl Write 1 to clear bit n value after reset Table 16 817 QUEUE_123_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2635 SPRUH73H Octo...

Page 2636: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 818 QUEUE_123_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2636 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2637: ...ter reset Table 16 819 QUEUE_123_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2638: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2639: ...y W1toCl Write 1 to clear bit n value after reset Table 16 821 QUEUE_124_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2639 SPRUH73H Octo...

Page 2640: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 822 QUEUE_124_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2640 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2641: ...ter reset Table 16 823 QUEUE_124_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2642: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2643: ...y W1toCl Write 1 to clear bit n value after reset Table 16 825 QUEUE_125_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2643 SPRUH73H Octo...

Page 2644: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 826 QUEUE_125_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2644 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2645: ...ter reset Table 16 827 QUEUE_125_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2646: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2647: ...y W1toCl Write 1 to clear bit n value after reset Table 16 829 QUEUE_126_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2647 SPRUH73H Octo...

Page 2648: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 830 QUEUE_126_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2648 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2649: ...ter reset Table 16 831 QUEUE_126_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2650: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2651: ...y W1toCl Write 1 to clear bit n value after reset Table 16 833 QUEUE_127_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2651 SPRUH73H Octo...

Page 2652: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 834 QUEUE_127_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2652 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2653: ...ter reset Table 16 835 QUEUE_127_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2654: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2655: ...y W1toCl Write 1 to clear bit n value after reset Table 16 837 QUEUE_128_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2655 SPRUH73H Octo...

Page 2656: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 838 QUEUE_128_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2656 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2657: ...ter reset Table 16 839 QUEUE_128_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2658: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2659: ...y W1toCl Write 1 to clear bit n value after reset Table 16 841 QUEUE_129_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2659 SPRUH73H Octo...

Page 2660: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 842 QUEUE_129_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2660 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2661: ...ter reset Table 16 843 QUEUE_129_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2662: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2663: ...y W1toCl Write 1 to clear bit n value after reset Table 16 845 QUEUE_130_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2663 SPRUH73H Octo...

Page 2664: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 846 QUEUE_130_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2664 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2665: ...ter reset Table 16 847 QUEUE_130_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2666: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2667: ...y W1toCl Write 1 to clear bit n value after reset Table 16 849 QUEUE_131_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2667 SPRUH73H Octo...

Page 2668: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 850 QUEUE_131_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2668 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2669: ...ter reset Table 16 851 QUEUE_131_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2670: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2671: ...y W1toCl Write 1 to clear bit n value after reset Table 16 853 QUEUE_132_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2671 SPRUH73H Octo...

Page 2672: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 854 QUEUE_132_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2672 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2673: ...ter reset Table 16 855 QUEUE_132_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2674: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2675: ...y W1toCl Write 1 to clear bit n value after reset Table 16 857 QUEUE_133_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2675 SPRUH73H Octo...

Page 2676: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 858 QUEUE_133_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2676 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2677: ...ter reset Table 16 859 QUEUE_133_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2678: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2679: ...y W1toCl Write 1 to clear bit n value after reset Table 16 861 QUEUE_134_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2679 SPRUH73H Octo...

Page 2680: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 862 QUEUE_134_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2680 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2681: ...ter reset Table 16 863 QUEUE_134_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2682: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2683: ...y W1toCl Write 1 to clear bit n value after reset Table 16 865 QUEUE_135_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2683 SPRUH73H Octo...

Page 2684: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 866 QUEUE_135_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2684 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2685: ...ter reset Table 16 867 QUEUE_135_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2686: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2687: ...y W1toCl Write 1 to clear bit n value after reset Table 16 869 QUEUE_136_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2687 SPRUH73H Octo...

Page 2688: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 870 QUEUE_136_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2688 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2689: ...ter reset Table 16 871 QUEUE_136_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2690: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2691: ...y W1toCl Write 1 to clear bit n value after reset Table 16 873 QUEUE_137_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2691 SPRUH73H Octo...

Page 2692: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 874 QUEUE_137_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2692 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2693: ...ter reset Table 16 875 QUEUE_137_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2694: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2695: ...y W1toCl Write 1 to clear bit n value after reset Table 16 877 QUEUE_138_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2695 SPRUH73H Octo...

Page 2696: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 878 QUEUE_138_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2696 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2697: ...ter reset Table 16 879 QUEUE_138_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2698: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2699: ...y W1toCl Write 1 to clear bit n value after reset Table 16 881 QUEUE_139_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2699 SPRUH73H Octo...

Page 2700: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 882 QUEUE_139_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2700 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2701: ...ter reset Table 16 883 QUEUE_139_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2702: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2703: ...y W1toCl Write 1 to clear bit n value after reset Table 16 885 QUEUE_140_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2703 SPRUH73H Octo...

Page 2704: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 886 QUEUE_140_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2704 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2705: ...ter reset Table 16 887 QUEUE_140_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2706: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2707: ...y W1toCl Write 1 to clear bit n value after reset Table 16 889 QUEUE_141_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2707 SPRUH73H Octo...

Page 2708: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 890 QUEUE_141_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2708 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2709: ...ter reset Table 16 891 QUEUE_141_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2710: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2711: ...y W1toCl Write 1 to clear bit n value after reset Table 16 893 QUEUE_142_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2711 SPRUH73H Octo...

Page 2712: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 894 QUEUE_142_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2712 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2713: ...ter reset Table 16 895 QUEUE_142_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2714: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2715: ...y W1toCl Write 1 to clear bit n value after reset Table 16 897 QUEUE_143_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2715 SPRUH73H Octo...

Page 2716: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 898 QUEUE_143_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2716 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2717: ...ter reset Table 16 899 QUEUE_143_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2718: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2719: ...y W1toCl Write 1 to clear bit n value after reset Table 16 901 QUEUE_144_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2719 SPRUH73H Octo...

Page 2720: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 902 QUEUE_144_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2720 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2721: ...ter reset Table 16 903 QUEUE_144_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2722: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2723: ...y W1toCl Write 1 to clear bit n value after reset Table 16 905 QUEUE_145_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2723 SPRUH73H Octo...

Page 2724: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 906 QUEUE_145_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2724 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2725: ...ter reset Table 16 907 QUEUE_145_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2726: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2727: ...y W1toCl Write 1 to clear bit n value after reset Table 16 909 QUEUE_146_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2727 SPRUH73H Octo...

Page 2728: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 910 QUEUE_146_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2728 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2729: ...ter reset Table 16 911 QUEUE_146_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2730: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2731: ...y W1toCl Write 1 to clear bit n value after reset Table 16 913 QUEUE_147_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2731 SPRUH73H Octo...

Page 2732: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 914 QUEUE_147_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2732 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2733: ...ter reset Table 16 915 QUEUE_147_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2734: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2735: ...y W1toCl Write 1 to clear bit n value after reset Table 16 917 QUEUE_148_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2735 SPRUH73H Octo...

Page 2736: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 918 QUEUE_148_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2736 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2737: ...ter reset Table 16 919 QUEUE_148_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2738: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2739: ...y W1toCl Write 1 to clear bit n value after reset Table 16 921 QUEUE_149_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2739 SPRUH73H Octo...

Page 2740: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 922 QUEUE_149_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2740 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2741: ...ter reset Table 16 923 QUEUE_149_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2742: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2743: ...y W1toCl Write 1 to clear bit n value after reset Table 16 925 QUEUE_150_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2743 SPRUH73H Octo...

Page 2744: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 926 QUEUE_150_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2744 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2745: ...ter reset Table 16 927 QUEUE_150_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2746: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2747: ...y W1toCl Write 1 to clear bit n value after reset Table 16 929 QUEUE_151_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2747 SPRUH73H Octo...

Page 2748: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 930 QUEUE_151_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2748 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2749: ...ter reset Table 16 931 QUEUE_151_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2750: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2751: ...y W1toCl Write 1 to clear bit n value after reset Table 16 933 QUEUE_152_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2751 SPRUH73H Octo...

Page 2752: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 934 QUEUE_152_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2752 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2753: ...ter reset Table 16 935 QUEUE_152_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2754: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2755: ...y W1toCl Write 1 to clear bit n value after reset Table 16 937 QUEUE_153_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2755 SPRUH73H Octo...

Page 2756: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 938 QUEUE_153_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2756 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2757: ...ter reset Table 16 939 QUEUE_153_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2758: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2759: ...y W1toCl Write 1 to clear bit n value after reset Table 16 941 QUEUE_154_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2759 SPRUH73H Octo...

Page 2760: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 942 QUEUE_154_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2760 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2761: ...ter reset Table 16 943 QUEUE_154_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2762: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2763: ...y W1toCl Write 1 to clear bit n value after reset Table 16 945 QUEUE_155_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue This count is incremented by 1 whenever a packet is added to the queue This count is decremented by 1 whenever a packet is popped from the queue 2763 SPRUH73H Octo...

Page 2764: ...E_BYTE_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 946 QUEUE_155_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue 2764 Universal Serial Bus USB SPRUH73H October 2011 Revised April 20...

Page 2765: ...ter reset Table 16 947 QUEUE_155_C Register Field Descriptions Bit Field Type Reset Description 31 HEAD_TAIL W 0 0 Head Tail Push Control Set to zero in order to push packet onto tail of queue and set to one in order to push packet onto head of queue 13 0 PACKET_SIZE R W 0 0 packet_size This field indicates packet size and is assumed to be zero on each packet add unless the value is explicitly ove...

Page 2766: ...so on to 148 bytes This field will return a 0x0 when an empty queue is read Queue Manager Queue N Registers D To save hardware resources the queue manager internally stores descriptor size desc_size information in four bits However register D has five LSBs that specify descriptor size As a consequence the value of desc_size that is pushed may not be same as that is read during a pop The value that...

Page 2767: ...ed QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 949 QUEUE_0_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2767 SPRUH73H October 2011 Revised April 2013 Universal Seri...

Page 2768: ...LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 950 QUEUE_0_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2768 Universal Serial Bus USB SPRUH73...

Page 2769: ... 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 951 QUEUE_0_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2769 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus US...

Page 2770: ...ed QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 952 QUEUE_1_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2770 Universal Serial Bus USB SPRUH73H October 2011 Revised ...

Page 2771: ...LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 953 QUEUE_1_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2771 SPRUH73H October 2011 Revised Ap...

Page 2772: ... 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 954 QUEUE_1_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2772 Universal Serial Bus USB SPRUH73H October 2011 Revised April 201...

Page 2773: ...ed QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 955 QUEUE_2_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2773 SPRUH73H October 2011 Revised April 2013 Universal Seri...

Page 2774: ...LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 956 QUEUE_2_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2774 Universal Serial Bus USB SPRUH73...

Page 2775: ... 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 957 QUEUE_2_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2775 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus US...

Page 2776: ...ed QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 958 QUEUE_3_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2776 Universal Serial Bus USB SPRUH73H October 2011 Revised ...

Page 2777: ...LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 959 QUEUE_3_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2777 SPRUH73H October 2011 Revised Ap...

Page 2778: ... 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 960 QUEUE_3_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2778 Universal Serial Bus USB SPRUH73H October 2011 Revised April 201...

Page 2779: ...ed QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 961 QUEUE_4_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2779 SPRUH73H October 2011 Revised April 2013 Universal Seri...

Page 2780: ...LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 962 QUEUE_4_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2780 Universal Serial Bus USB SPRUH73...

Page 2781: ... 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 963 QUEUE_4_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2781 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus US...

Page 2782: ...ed QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 964 QUEUE_5_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2782 Universal Serial Bus USB SPRUH73H October 2011 Revised ...

Page 2783: ...LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 965 QUEUE_5_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2783 SPRUH73H October 2011 Revised Ap...

Page 2784: ... 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 966 QUEUE_5_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2784 Universal Serial Bus USB SPRUH73H October 2011 Revised April 201...

Page 2785: ...ed QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 967 QUEUE_6_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2785 SPRUH73H October 2011 Revised April 2013 Universal Seri...

Page 2786: ...LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 968 QUEUE_6_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2786 Universal Serial Bus USB SPRUH73...

Page 2787: ... 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 969 QUEUE_6_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2787 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus US...

Page 2788: ...ed QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 970 QUEUE_7_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2788 Universal Serial Bus USB SPRUH73H October 2011 Revised ...

Page 2789: ...LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 971 QUEUE_7_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2789 SPRUH73H October 2011 Revised Ap...

Page 2790: ... 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 972 QUEUE_7_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2790 Universal Serial Bus USB SPRUH73H October 2011 Revised April 201...

Page 2791: ...ed QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 973 QUEUE_8_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2791 SPRUH73H October 2011 Revised April 2013 Universal Seri...

Page 2792: ...LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 974 QUEUE_8_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2792 Universal Serial Bus USB SPRUH73...

Page 2793: ... 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 975 QUEUE_8_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2793 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus US...

Page 2794: ...ed QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 976 QUEUE_9_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2794 Universal Serial Bus USB SPRUH73H October 2011 Revised ...

Page 2795: ...LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 977 QUEUE_9_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2795 SPRUH73H October 2011 Revised Ap...

Page 2796: ... 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 978 QUEUE_9_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2796 Universal Serial Bus USB SPRUH73H October 2011 Revised April 201...

Page 2797: ...ved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 979 QUEUE_10_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2797 SPRUH73H October 2011 Revised April 2013 Universal Se...

Page 2798: ... LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 980 QUEUE_10_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2798 Universal Serial Bus USB SPRUH...

Page 2799: ...1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 981 QUEUE_10_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2799 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus ...

Page 2800: ...ved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 982 QUEUE_11_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2800 Universal Serial Bus USB SPRUH73H October 2011 Revise...

Page 2801: ... LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 983 QUEUE_11_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2801 SPRUH73H October 2011 Revised ...

Page 2802: ...1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 984 QUEUE_11_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2802 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2...

Page 2803: ...ved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 985 QUEUE_12_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2803 SPRUH73H October 2011 Revised April 2013 Universal Se...

Page 2804: ... LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 986 QUEUE_12_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2804 Universal Serial Bus USB SPRUH...

Page 2805: ...1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 987 QUEUE_12_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2805 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus ...

Page 2806: ...ved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 988 QUEUE_13_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2806 Universal Serial Bus USB SPRUH73H October 2011 Revise...

Page 2807: ... LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 989 QUEUE_13_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2807 SPRUH73H October 2011 Revised ...

Page 2808: ...1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 990 QUEUE_13_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2808 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2...

Page 2809: ...ved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 991 QUEUE_14_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2809 SPRUH73H October 2011 Revised April 2013 Universal Se...

Page 2810: ... LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 992 QUEUE_14_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2810 Universal Serial Bus USB SPRUH...

Page 2811: ...1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 993 QUEUE_14_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2811 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus ...

Page 2812: ...ved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 994 QUEUE_15_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2812 Universal Serial Bus USB SPRUH73H October 2011 Revise...

Page 2813: ... LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 995 QUEUE_15_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2813 SPRUH73H October 2011 Revised ...

Page 2814: ...1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 996 QUEUE_15_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2814 Universal Serial Bus USB SPRUH73H October 2011 Revised April 2...

Page 2815: ...ved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 997 QUEUE_16_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2815 SPRUH73H October 2011 Revised April 2013 Universal Se...

Page 2816: ... LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 998 QUEUE_16_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2816 Universal Serial Bus USB SPRUH...

Page 2817: ...1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 999 QUEUE_16_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2817 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus ...

Page 2818: ...ved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1000 QUEUE_17_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2818 Universal Serial Bus USB SPRUH73H October 2011 Revis...

Page 2819: ... LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1001 QUEUE_17_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2819 SPRUH73H October 2011 Revised...

Page 2820: ...1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1002 QUEUE_17_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2820 Universal Serial Bus USB SPRUH73H October 2011 Revised April ...

Page 2821: ...ved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1003 QUEUE_18_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2821 SPRUH73H October 2011 Revised April 2013 Universal S...

Page 2822: ... LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1004 QUEUE_18_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2822 Universal Serial Bus USB SPRU...

Page 2823: ...1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1005 QUEUE_18_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2823 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus...

Page 2824: ...ved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1006 QUEUE_19_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2824 Universal Serial Bus USB SPRUH73H October 2011 Revis...

Page 2825: ... LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1007 QUEUE_19_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2825 SPRUH73H October 2011 Revised...

Page 2826: ...1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1008 QUEUE_19_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2826 Universal Serial Bus USB SPRUH73H October 2011 Revised April ...

Page 2827: ...ved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1009 QUEUE_20_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2827 SPRUH73H October 2011 Revised April 2013 Universal S...

Page 2828: ... LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1010 QUEUE_20_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2828 Universal Serial Bus USB SPRU...

Page 2829: ...1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1011 QUEUE_20_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2829 SPRUH73H October 2011 Revised April 2013 Universal Serial Bus...

Page 2830: ...ved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1012 QUEUE_21_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2830 Universal Serial Bus USB SPRUH73H October 2011 Revis...

Page 2831: ... LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1013 QUEUE_21_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2831 SPRUH73H October 2011 Revised...

Page 2832: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1014 QUEUE_21_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2832 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2833: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1015 QUEUE_22_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2833 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2834: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1016 QUEUE_22_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2834 Universal Serial Bus USB SPR...

Page 2835: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1017 QUEUE_22_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2835 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2836: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1018 QUEUE_23_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2836 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2837: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1019 QUEUE_23_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2837 SPRUH73H October 2011 Revise...

Page 2838: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1020 QUEUE_23_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2838 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2839: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1021 QUEUE_24_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2839 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2840: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1022 QUEUE_24_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2840 Universal Serial Bus USB SPR...

Page 2841: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1023 QUEUE_24_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2841 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2842: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1024 QUEUE_25_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2842 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2843: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1025 QUEUE_25_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2843 SPRUH73H October 2011 Revise...

Page 2844: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1026 QUEUE_25_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2844 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2845: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1027 QUEUE_26_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2845 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2846: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1028 QUEUE_26_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2846 Universal Serial Bus USB SPR...

Page 2847: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1029 QUEUE_26_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2847 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2848: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1030 QUEUE_27_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2848 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2849: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1031 QUEUE_27_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2849 SPRUH73H October 2011 Revise...

Page 2850: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1032 QUEUE_27_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2850 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2851: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1033 QUEUE_28_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2851 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2852: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1034 QUEUE_28_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2852 Universal Serial Bus USB SPR...

Page 2853: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1035 QUEUE_28_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2853 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2854: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1036 QUEUE_29_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2854 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2855: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1037 QUEUE_29_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2855 SPRUH73H October 2011 Revise...

Page 2856: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1038 QUEUE_29_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2856 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2857: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1039 QUEUE_30_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2857 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2858: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1040 QUEUE_30_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2858 Universal Serial Bus USB SPR...

Page 2859: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1041 QUEUE_30_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2859 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2860: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1042 QUEUE_31_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2860 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2861: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1043 QUEUE_31_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2861 SPRUH73H October 2011 Revise...

Page 2862: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1044 QUEUE_31_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2862 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2863: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1045 QUEUE_32_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2863 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2864: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1046 QUEUE_32_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2864 Universal Serial Bus USB SPR...

Page 2865: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1047 QUEUE_32_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2865 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2866: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1048 QUEUE_33_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2866 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2867: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1049 QUEUE_33_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2867 SPRUH73H October 2011 Revise...

Page 2868: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1050 QUEUE_33_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2868 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2869: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1051 QUEUE_34_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2869 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2870: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1052 QUEUE_34_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2870 Universal Serial Bus USB SPR...

Page 2871: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1053 QUEUE_34_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2871 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2872: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1054 QUEUE_35_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2872 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2873: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1055 QUEUE_35_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2873 SPRUH73H October 2011 Revise...

Page 2874: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1056 QUEUE_35_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2874 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2875: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1057 QUEUE_36_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2875 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2876: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1058 QUEUE_36_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2876 Universal Serial Bus USB SPR...

Page 2877: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1059 QUEUE_36_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2877 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2878: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1060 QUEUE_37_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2878 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2879: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1061 QUEUE_37_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2879 SPRUH73H October 2011 Revise...

Page 2880: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1062 QUEUE_37_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2880 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2881: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1063 QUEUE_38_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2881 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2882: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1064 QUEUE_38_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2882 Universal Serial Bus USB SPR...

Page 2883: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1065 QUEUE_38_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2883 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2884: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1066 QUEUE_39_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2884 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2885: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1067 QUEUE_39_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2885 SPRUH73H October 2011 Revise...

Page 2886: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1068 QUEUE_39_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2886 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2887: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1069 QUEUE_40_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2887 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2888: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1070 QUEUE_40_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2888 Universal Serial Bus USB SPR...

Page 2889: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1071 QUEUE_40_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2889 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2890: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1072 QUEUE_41_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2890 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2891: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1073 QUEUE_41_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2891 SPRUH73H October 2011 Revise...

Page 2892: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1074 QUEUE_41_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2892 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2893: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1075 QUEUE_42_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2893 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2894: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1076 QUEUE_42_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2894 Universal Serial Bus USB SPR...

Page 2895: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1077 QUEUE_42_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2895 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2896: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1078 QUEUE_43_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2896 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2897: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1079 QUEUE_43_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2897 SPRUH73H October 2011 Revise...

Page 2898: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1080 QUEUE_43_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2898 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2899: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1081 QUEUE_44_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2899 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2900: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1082 QUEUE_44_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2900 Universal Serial Bus USB SPR...

Page 2901: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1083 QUEUE_44_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2901 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2902: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1084 QUEUE_45_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2902 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2903: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1085 QUEUE_45_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2903 SPRUH73H October 2011 Revise...

Page 2904: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1086 QUEUE_45_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2904 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2905: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1087 QUEUE_46_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2905 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2906: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1088 QUEUE_46_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2906 Universal Serial Bus USB SPR...

Page 2907: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1089 QUEUE_46_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2907 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2908: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1090 QUEUE_47_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2908 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2909: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1091 QUEUE_47_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2909 SPRUH73H October 2011 Revise...

Page 2910: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1092 QUEUE_47_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2910 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2911: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1093 QUEUE_48_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2911 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2912: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1094 QUEUE_48_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2912 Universal Serial Bus USB SPR...

Page 2913: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1095 QUEUE_48_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2913 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2914: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1096 QUEUE_49_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2914 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2915: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1097 QUEUE_49_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2915 SPRUH73H October 2011 Revise...

Page 2916: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1098 QUEUE_49_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2916 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2917: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1099 QUEUE_50_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2917 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2918: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1100 QUEUE_50_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2918 Universal Serial Bus USB SPR...

Page 2919: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1101 QUEUE_50_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2919 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2920: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1102 QUEUE_51_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2920 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2921: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1103 QUEUE_51_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2921 SPRUH73H October 2011 Revise...

Page 2922: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1104 QUEUE_51_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2922 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2923: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1105 QUEUE_52_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2923 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2924: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1106 QUEUE_52_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2924 Universal Serial Bus USB SPR...

Page 2925: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1107 QUEUE_52_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2925 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2926: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1108 QUEUE_53_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2926 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2927: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1109 QUEUE_53_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2927 SPRUH73H October 2011 Revise...

Page 2928: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1110 QUEUE_53_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2928 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2929: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1111 QUEUE_54_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2929 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2930: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1112 QUEUE_54_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2930 Universal Serial Bus USB SPR...

Page 2931: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1113 QUEUE_54_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2931 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2932: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1114 QUEUE_55_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2932 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2933: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1115 QUEUE_55_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2933 SPRUH73H October 2011 Revise...

Page 2934: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1116 QUEUE_55_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2934 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2935: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1117 QUEUE_56_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2935 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2936: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1118 QUEUE_56_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2936 Universal Serial Bus USB SPR...

Page 2937: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1119 QUEUE_56_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2937 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2938: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1120 QUEUE_57_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2938 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2939: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1121 QUEUE_57_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2939 SPRUH73H October 2011 Revise...

Page 2940: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1122 QUEUE_57_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2940 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2941: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1123 QUEUE_58_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2941 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2942: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1124 QUEUE_58_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2942 Universal Serial Bus USB SPR...

Page 2943: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1125 QUEUE_58_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2943 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2944: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1126 QUEUE_59_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2944 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2945: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1127 QUEUE_59_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2945 SPRUH73H October 2011 Revise...

Page 2946: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1128 QUEUE_59_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2946 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2947: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1129 QUEUE_60_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2947 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2948: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1130 QUEUE_60_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2948 Universal Serial Bus USB SPR...

Page 2949: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1131 QUEUE_60_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2949 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2950: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1132 QUEUE_61_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2950 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2951: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1133 QUEUE_61_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2951 SPRUH73H October 2011 Revise...

Page 2952: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1134 QUEUE_61_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2952 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2953: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1135 QUEUE_62_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2953 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2954: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1136 QUEUE_62_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2954 Universal Serial Bus USB SPR...

Page 2955: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1137 QUEUE_62_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2955 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2956: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1138 QUEUE_63_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2956 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2957: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1139 QUEUE_63_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2957 SPRUH73H October 2011 Revise...

Page 2958: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1140 QUEUE_63_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2958 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2959: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1141 QUEUE_64_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2959 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2960: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1142 QUEUE_64_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2960 Universal Serial Bus USB SPR...

Page 2961: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1143 QUEUE_64_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2961 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2962: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1144 QUEUE_65_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2962 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2963: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1145 QUEUE_65_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2963 SPRUH73H October 2011 Revise...

Page 2964: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1146 QUEUE_65_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2964 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2965: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1147 QUEUE_66_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2965 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2966: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1148 QUEUE_66_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2966 Universal Serial Bus USB SPR...

Page 2967: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1149 QUEUE_66_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2967 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2968: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1150 QUEUE_67_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2968 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2969: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1151 QUEUE_67_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2969 SPRUH73H October 2011 Revise...

Page 2970: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1152 QUEUE_67_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2970 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2971: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1153 QUEUE_68_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2971 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2972: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1154 QUEUE_68_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2972 Universal Serial Bus USB SPR...

Page 2973: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1155 QUEUE_68_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2973 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2974: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1156 QUEUE_69_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2974 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2975: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1157 QUEUE_69_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2975 SPRUH73H October 2011 Revise...

Page 2976: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1158 QUEUE_69_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2976 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2977: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1159 QUEUE_70_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2977 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2978: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1160 QUEUE_70_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2978 Universal Serial Bus USB SPR...

Page 2979: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1161 QUEUE_70_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2979 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2980: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1162 QUEUE_71_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2980 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2981: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1163 QUEUE_71_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2981 SPRUH73H October 2011 Revise...

Page 2982: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1164 QUEUE_71_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2982 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2983: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1165 QUEUE_72_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2983 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2984: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1166 QUEUE_72_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2984 Universal Serial Bus USB SPR...

Page 2985: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1167 QUEUE_72_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2985 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2986: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1168 QUEUE_73_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2986 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2987: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1169 QUEUE_73_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2987 SPRUH73H October 2011 Revise...

Page 2988: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1170 QUEUE_73_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2988 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2989: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1171 QUEUE_74_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2989 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2990: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1172 QUEUE_74_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2990 Universal Serial Bus USB SPR...

Page 2991: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1173 QUEUE_74_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2991 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2992: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1174 QUEUE_75_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2992 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2993: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1175 QUEUE_75_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2993 SPRUH73H October 2011 Revise...

Page 2994: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1176 QUEUE_75_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2994 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 2995: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1177 QUEUE_76_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2995 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 2996: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1178 QUEUE_76_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2996 Universal Serial Bus USB SPR...

Page 2997: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1179 QUEUE_76_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 2997 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 2998: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1180 QUEUE_77_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 2998 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 2999: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1181 QUEUE_77_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 2999 SPRUH73H October 2011 Revise...

Page 3000: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1182 QUEUE_77_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3000 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 3001: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1183 QUEUE_78_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3001 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 3002: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1184 QUEUE_78_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3002 Universal Serial Bus USB SPR...

Page 3003: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1185 QUEUE_78_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3003 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 3004: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1186 QUEUE_79_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3004 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 3005: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1187 QUEUE_79_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3005 SPRUH73H October 2011 Revise...

Page 3006: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1188 QUEUE_79_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3006 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 3007: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1189 QUEUE_80_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3007 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 3008: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1190 QUEUE_80_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3008 Universal Serial Bus USB SPR...

Page 3009: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1191 QUEUE_80_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3009 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 3010: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1192 QUEUE_81_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3010 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 3011: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1193 QUEUE_81_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3011 SPRUH73H October 2011 Revise...

Page 3012: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1194 QUEUE_81_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3012 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 3013: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1195 QUEUE_82_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3013 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 3014: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1196 QUEUE_82_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3014 Universal Serial Bus USB SPR...

Page 3015: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1197 QUEUE_82_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3015 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 3016: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1198 QUEUE_83_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3016 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 3017: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1199 QUEUE_83_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3017 SPRUH73H October 2011 Revise...

Page 3018: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1200 QUEUE_83_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3018 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 3019: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1201 QUEUE_84_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3019 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 3020: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1202 QUEUE_84_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3020 Universal Serial Bus USB SPR...

Page 3021: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1203 QUEUE_84_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3021 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 3022: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1204 QUEUE_85_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3022 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 3023: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1205 QUEUE_85_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3023 SPRUH73H October 2011 Revise...

Page 3024: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1206 QUEUE_85_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3024 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 3025: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1207 QUEUE_86_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3025 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 3026: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1208 QUEUE_86_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3026 Universal Serial Bus USB SPR...

Page 3027: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1209 QUEUE_86_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3027 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 3028: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1210 QUEUE_87_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3028 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 3029: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1211 QUEUE_87_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3029 SPRUH73H October 2011 Revise...

Page 3030: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1212 QUEUE_87_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3030 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 3031: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1213 QUEUE_88_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3031 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 3032: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1214 QUEUE_88_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3032 Universal Serial Bus USB SPR...

Page 3033: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1215 QUEUE_88_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3033 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 3034: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1216 QUEUE_89_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3034 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 3035: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1217 QUEUE_89_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3035 SPRUH73H October 2011 Revise...

Page 3036: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1218 QUEUE_89_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3036 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 3037: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1219 QUEUE_90_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3037 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 3038: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1220 QUEUE_90_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3038 Universal Serial Bus USB SPR...

Page 3039: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1221 QUEUE_90_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3039 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 3040: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1222 QUEUE_91_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3040 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 3041: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1223 QUEUE_91_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3041 SPRUH73H October 2011 Revise...

Page 3042: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1224 QUEUE_91_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3042 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 3043: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1225 QUEUE_92_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3043 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 3044: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1226 QUEUE_92_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3044 Universal Serial Bus USB SPR...

Page 3045: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1227 QUEUE_92_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3045 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 3046: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1228 QUEUE_93_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3046 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 3047: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1229 QUEUE_93_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3047 SPRUH73H October 2011 Revise...

Page 3048: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1230 QUEUE_93_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3048 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 3049: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1231 QUEUE_94_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3049 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 3050: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1232 QUEUE_94_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3050 Universal Serial Bus USB SPR...

Page 3051: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1233 QUEUE_94_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3051 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 3052: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1234 QUEUE_95_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3052 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 3053: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1235 QUEUE_95_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3053 SPRUH73H October 2011 Revise...

Page 3054: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1236 QUEUE_95_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3054 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 3055: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1237 QUEUE_96_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3055 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 3056: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1238 QUEUE_96_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3056 Universal Serial Bus USB SPR...

Page 3057: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1239 QUEUE_96_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3057 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 3058: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1240 QUEUE_97_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3058 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 3059: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1241 QUEUE_97_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3059 SPRUH73H October 2011 Revise...

Page 3060: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1242 QUEUE_97_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3060 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 3061: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1243 QUEUE_98_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3061 SPRUH73H October 2011 Revised April 2013 Universal ...

Page 3062: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1244 QUEUE_98_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3062 Universal Serial Bus USB SPR...

Page 3063: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1245 QUEUE_98_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3063 SPRUH73H October 2011 Revised April 2013 Universal Serial Bu...

Page 3064: ...rved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1246 QUEUE_99_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3064 Universal Serial Bus USB SPRUH73H October 2011 Revi...

Page 3065: ...0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1247 QUEUE_99_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3065 SPRUH73H October 2011 Revise...

Page 3066: ... 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1248 QUEUE_99_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3066 Universal Serial Bus USB SPRUH73H October 2011 Revised April...

Page 3067: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1249 QUEUE_100_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3067 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3068: ... 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1250 QUEUE_100_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3068 Universal Serial Bus USB S...

Page 3069: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1251 QUEUE_100_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3069 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3070: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1252 QUEUE_101_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3070 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3071: ... 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1253 QUEUE_101_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3071 SPRUH73H October 2011 Revi...

Page 3072: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1254 QUEUE_101_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3072 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3073: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1255 QUEUE_102_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3073 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3074: ... 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1256 QUEUE_102_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3074 Universal Serial Bus USB S...

Page 3075: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1257 QUEUE_102_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3075 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3076: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1258 QUEUE_103_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3076 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3077: ... 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1259 QUEUE_103_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3077 SPRUH73H October 2011 Revi...

Page 3078: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1260 QUEUE_103_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3078 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3079: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1261 QUEUE_104_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3079 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3080: ... 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1262 QUEUE_104_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3080 Universal Serial Bus USB S...

Page 3081: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1263 QUEUE_104_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3081 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3082: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1264 QUEUE_105_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3082 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3083: ... 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1265 QUEUE_105_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3083 SPRUH73H October 2011 Revi...

Page 3084: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1266 QUEUE_105_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3084 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3085: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1267 QUEUE_106_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3085 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3086: ... 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1268 QUEUE_106_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3086 Universal Serial Bus USB S...

Page 3087: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1269 QUEUE_106_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3087 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3088: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1270 QUEUE_107_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3088 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3089: ... 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1271 QUEUE_107_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3089 SPRUH73H October 2011 Revi...

Page 3090: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1272 QUEUE_107_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3090 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3091: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1273 QUEUE_108_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3091 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3092: ... 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1274 QUEUE_108_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3092 Universal Serial Bus USB S...

Page 3093: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1275 QUEUE_108_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3093 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3094: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1276 QUEUE_109_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3094 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3095: ... 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1277 QUEUE_109_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3095 SPRUH73H October 2011 Revi...

Page 3096: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1278 QUEUE_109_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3096 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3097: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1279 QUEUE_110_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3097 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3098: ... 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1280 QUEUE_110_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3098 Universal Serial Bus USB S...

Page 3099: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1281 QUEUE_110_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3099 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3100: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1282 QUEUE_111_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3100 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3101: ... 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1283 QUEUE_111_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3101 SPRUH73H October 2011 Revi...

Page 3102: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1284 QUEUE_111_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3102 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3103: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1285 QUEUE_112_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3103 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3104: ... 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1286 QUEUE_112_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3104 Universal Serial Bus USB S...

Page 3105: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1287 QUEUE_112_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3105 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3106: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1288 QUEUE_113_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3106 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3107: ... 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1289 QUEUE_113_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3107 SPRUH73H October 2011 Revi...

Page 3108: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1290 QUEUE_113_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3108 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3109: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1291 QUEUE_114_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3109 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3110: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1292 QUEUE_114_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3110 Universal Serial Bus USB ...

Page 3111: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1293 QUEUE_114_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3111 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3112: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1294 QUEUE_115_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3112 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3113: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1295 QUEUE_115_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3113 SPRUH73H October 2011 Rev...

Page 3114: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1296 QUEUE_115_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3114 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3115: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1297 QUEUE_116_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3115 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3116: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1298 QUEUE_116_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3116 Universal Serial Bus USB ...

Page 3117: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1299 QUEUE_116_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3117 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3118: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1300 QUEUE_117_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3118 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3119: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1301 QUEUE_117_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3119 SPRUH73H October 2011 Rev...

Page 3120: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1302 QUEUE_117_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3120 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3121: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1303 QUEUE_118_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3121 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3122: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1304 QUEUE_118_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3122 Universal Serial Bus USB ...

Page 3123: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1305 QUEUE_118_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3123 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3124: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1306 QUEUE_119_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3124 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3125: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1307 QUEUE_119_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3125 SPRUH73H October 2011 Rev...

Page 3126: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1308 QUEUE_119_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3126 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3127: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1309 QUEUE_120_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3127 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3128: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1310 QUEUE_120_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3128 Universal Serial Bus USB ...

Page 3129: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1311 QUEUE_120_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3129 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3130: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1312 QUEUE_121_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3130 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3131: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1313 QUEUE_121_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3131 SPRUH73H October 2011 Rev...

Page 3132: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1314 QUEUE_121_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3132 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3133: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1315 QUEUE_122_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3133 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3134: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1316 QUEUE_122_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3134 Universal Serial Bus USB ...

Page 3135: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1317 QUEUE_122_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3135 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3136: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1318 QUEUE_123_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3136 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3137: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1319 QUEUE_123_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3137 SPRUH73H October 2011 Rev...

Page 3138: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1320 QUEUE_123_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3138 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3139: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1321 QUEUE_124_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3139 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3140: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1322 QUEUE_124_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3140 Universal Serial Bus USB ...

Page 3141: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1323 QUEUE_124_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3141 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3142: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1324 QUEUE_125_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3142 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3143: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1325 QUEUE_125_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3143 SPRUH73H October 2011 Rev...

Page 3144: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1326 QUEUE_125_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3144 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3145: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1327 QUEUE_126_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3145 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3146: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1328 QUEUE_126_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3146 Universal Serial Bus USB ...

Page 3147: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1329 QUEUE_126_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3147 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3148: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1330 QUEUE_127_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3148 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3149: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1331 QUEUE_127_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3149 SPRUH73H October 2011 Rev...

Page 3150: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1332 QUEUE_127_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3150 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3151: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1333 QUEUE_128_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3151 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3152: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1334 QUEUE_128_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3152 Universal Serial Bus USB ...

Page 3153: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1335 QUEUE_128_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3153 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3154: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1336 QUEUE_129_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3154 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3155: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1337 QUEUE_129_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3155 SPRUH73H October 2011 Rev...

Page 3156: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1338 QUEUE_129_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3156 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3157: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1339 QUEUE_130_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3157 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3158: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1340 QUEUE_130_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3158 Universal Serial Bus USB ...

Page 3159: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1341 QUEUE_130_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3159 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3160: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1342 QUEUE_131_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3160 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3161: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1343 QUEUE_131_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3161 SPRUH73H October 2011 Rev...

Page 3162: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1344 QUEUE_131_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3162 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3163: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1345 QUEUE_132_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3163 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3164: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1346 QUEUE_132_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3164 Universal Serial Bus USB ...

Page 3165: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1347 QUEUE_132_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3165 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3166: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1348 QUEUE_133_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3166 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3167: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1349 QUEUE_133_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3167 SPRUH73H October 2011 Rev...

Page 3168: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1350 QUEUE_133_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3168 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3169: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1351 QUEUE_134_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3169 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3170: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1352 QUEUE_134_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3170 Universal Serial Bus USB ...

Page 3171: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1353 QUEUE_134_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3171 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3172: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1354 QUEUE_135_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3172 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3173: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1355 QUEUE_135_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3173 SPRUH73H October 2011 Rev...

Page 3174: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1356 QUEUE_135_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3174 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3175: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1357 QUEUE_136_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3175 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3176: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1358 QUEUE_136_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3176 Universal Serial Bus USB ...

Page 3177: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1359 QUEUE_136_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3177 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3178: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1360 QUEUE_137_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3178 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3179: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1361 QUEUE_137_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3179 SPRUH73H October 2011 Rev...

Page 3180: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1362 QUEUE_137_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3180 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3181: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1363 QUEUE_138_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3181 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3182: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1364 QUEUE_138_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3182 Universal Serial Bus USB ...

Page 3183: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1365 QUEUE_138_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3183 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3184: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1366 QUEUE_139_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3184 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3185: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1367 QUEUE_139_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3185 SPRUH73H October 2011 Rev...

Page 3186: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1368 QUEUE_139_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3186 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3187: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1369 QUEUE_140_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3187 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3188: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1370 QUEUE_140_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3188 Universal Serial Bus USB ...

Page 3189: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1371 QUEUE_140_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3189 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3190: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1372 QUEUE_141_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3190 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3191: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1373 QUEUE_141_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3191 SPRUH73H October 2011 Rev...

Page 3192: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1374 QUEUE_141_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3192 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3193: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1375 QUEUE_142_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3193 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3194: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1376 QUEUE_142_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3194 Universal Serial Bus USB ...

Page 3195: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1377 QUEUE_142_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3195 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3196: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1378 QUEUE_143_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3196 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3197: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1379 QUEUE_143_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3197 SPRUH73H October 2011 Rev...

Page 3198: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1380 QUEUE_143_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3198 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3199: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1381 QUEUE_144_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3199 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3200: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1382 QUEUE_144_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3200 Universal Serial Bus USB ...

Page 3201: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1383 QUEUE_144_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3201 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3202: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1384 QUEUE_145_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3202 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3203: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1385 QUEUE_145_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3203 SPRUH73H October 2011 Rev...

Page 3204: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1386 QUEUE_145_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3204 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3205: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1387 QUEUE_146_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3205 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3206: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1388 QUEUE_146_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3206 Universal Serial Bus USB ...

Page 3207: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1389 QUEUE_146_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3207 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3208: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1390 QUEUE_147_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3208 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3209: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1391 QUEUE_147_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3209 SPRUH73H October 2011 Rev...

Page 3210: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1392 QUEUE_147_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3210 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3211: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1393 QUEUE_148_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3211 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3212: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1394 QUEUE_148_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3212 Universal Serial Bus USB ...

Page 3213: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1395 QUEUE_148_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3213 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3214: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1396 QUEUE_149_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3214 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3215: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1397 QUEUE_149_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3215 SPRUH73H October 2011 Rev...

Page 3216: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1398 QUEUE_149_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3216 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3217: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1399 QUEUE_150_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3217 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3218: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1400 QUEUE_150_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3218 Universal Serial Bus USB ...

Page 3219: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1401 QUEUE_150_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3219 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3220: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1402 QUEUE_151_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3220 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3221: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1403 QUEUE_151_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3221 SPRUH73H October 2011 Rev...

Page 3222: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1404 QUEUE_151_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3222 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3223: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1405 QUEUE_152_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3223 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3224: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1406 QUEUE_152_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3224 Universal Serial Bus USB ...

Page 3225: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1407 QUEUE_152_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3225 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3226: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1408 QUEUE_153_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3226 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3227: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1409 QUEUE_153_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3227 SPRUH73H October 2011 Rev...

Page 3228: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1410 QUEUE_153_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3228 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3229: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1411 QUEUE_154_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3229 SPRUH73H October 2011 Revised April 2013 Universa...

Page 3230: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1412 QUEUE_154_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3230 Universal Serial Bus USB ...

Page 3231: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1413 QUEUE_154_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3231 SPRUH73H October 2011 Revised April 2013 Universal Serial ...

Page 3232: ...erved QUEUE_ENTRY_COUNT R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1414 QUEUE_155_STATUS_A Register Field Descriptions Bit Field Type Reset Description 13 0 QUEUE_ENTRY_COUNT R 0 0 This field indicates how many packets are currently queued on the queue Queue Manager Queue N Status Registers A 3232 Universal Serial Bus USB SPRUH73H October 2011 Re...

Page 3233: ...R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1415 QUEUE_155_STATUS_B Register Field Descriptions Bit Field Type Reset Description 27 0 QUEUE_BYTE_COUNT R 0 0 This field indicates how many bytes total are contained in all of the packets which are currently queued on this queue Queue_Manager_Queue_n_Status_B Registers B 3233 SPRUH73H October 2011 Rev...

Page 3234: ...2 1 0 Reserved PACKET_SIZE R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 16 1416 QUEUE_155_STATUS_C Register Field Descriptions Bit Field Type Reset Description 13 0 PACKET_SIZE R 0 0 This field indicates packet size of the head element of a queue Queue_Manager_Queue_N_Status_C Registers C 3234 Universal Serial Bus USB SPRUH73H October 2011 Revised Apr...

Page 3235: ...tion This chapter describes the interprocessor communication of the device Topic Page 17 1 Mailbox 3236 17 2 Spinlock 3306 3235 SPRUH73H October 2011 Revised April 2013 Interprocessor Communication Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3236: ...ion between 2 initiators Flexible mailbox initiators assignment scheme 4 messages per mailbox sub module 32 bit message width Support of 16 32 bit addressing scheme Non intrusive emulation 4 interrupts one per user 1 to MPU Subsystem 2 to PRU ICSS and 1 to WakeM3 17 1 1 2 Unsupported Features There are no unsupported features for Mailbox on this device 3236 Interprocessor Communication SPRUH73H Oc...

Page 3237: ...4_Wakeup peripherals it does not have access to the Mailbox registers A mailbox interrupt can still be sent to the M3 to trigger message notification The actual message payload must be placed in either M3 internal memory or in the Control Module Interprocessor Message registers IPC_MSG_REG 0 7 Figure 17 1 Mailbox Integration 17 1 2 1 Mailbox Connectivity Attributes The general connectivity for the...

Page 3238: ...l mailbox modules 8 for the system mailbox instance or FIFOs can associate or de associate with any of the processors using the MAILBOX_IRQENABLE_SET_u or MAILBOX_IRQENABLE_CLR_u register The system mailbox module includes the following user subsystems User 0 MPU Subsystem u 0 User 1 PRU_ICSS PRU0 u 1 User 2 PRU_ICSS PRU1 u 2 User 3 WakeM3 u 3 Each user has a dedicated interrupt signal from the co...

Page 3239: ...status of the software reset Read 1 the software reset is on going Read 0 the software reset is complete The software must ensure that the software reset completes before doing mailbox operations 17 1 3 3 Power Management Table 17 4 describes power management features available for the mailbox module Table 17 4 Local Power Management Features Feature Registers Description Clock autogating NA Featu...

Page 3240: ...u 0 m 2 _SET_u 0 m 2 new message SGSTATUSUUMBm SGSTATUSUUMBm NEWMSGSTATUSUUM NEWMSGSTATUSUUM Bm Bm MAILBOX_IRQSTATUS MAILBOX_IRQSTATUS MAILBOX_IRQENABLE MAILBOX_IRQENABLE Mailbox m message _RAW_u 1 m 2 NOTF _CLR_u 1 m 2 NOTFU _CLR_u 1 m 2 _SET_u 1 m 2 queue is not full ULLSTATUSUMBm LLSTATUSUMBm NOTFULLSTATUSUMB NOTFULLSTATUSUMB m m 1 MAILBOX MAILBOX_IRQSTATUS_RAW_u register is mostly used for deb...

Page 3241: ...is full In this case the sender can enable the queue not full interrupt for its mailbox in the appropriate MAILBOX_IRQENABLE_SET_u register This allows the sender to be notified by interrupt only when a FIFO queue has at least one available entry Reading the MAILBOX_IRQSTATUS_CLR_u register determines the status of the new message and the queue not full interrupts for a particular user Writing 1 t...

Page 3242: ...egisters The update of the FIFO queue contents and the associated status registers and possible interrupt generation occurs only when the most significant 16 bits of a MAILBOX_MESSAGE_m are accessed 17 1 4 Programming Guide 17 1 4 1 Low level Programming Models This section covers the low level hardware programming sequences for configuration and usage of the mailbox module 17 1 4 1 1 Global Initi...

Page 3243: ...thod Step Register Bitfield Programming Model Value IF Is FIFO full MAILBOX_FIFOSTATUS_m 0 FIFOFULL 1h MB Wait until at least one message slot is MAILBOX_FIFOSTATUS_m 0 FIFOFULL 0h available MB ELSE Write message MAILBOX_MESSAGE_m 31 0 MESSAG h EVALUEMBM ENDIF 17 1 4 1 2 2 Main Sequence Sending a Message Interrupt Method Table 17 9 Sending a Message Interrupt Method Step Register Bitfield Programm...

Page 3244: ...in sending mode Table 17 12 Events Servicing in Sending Mode Step Register Bitfield Programming Model Value Read interrupt status bit MAILBOX_IRQSTATUS_CLR_u 1 m 2 1 Write message MAILBOX_MESSAGE_m 31 0 MESSAG h EVALUEMBM Write 1 to acknowledge interrupt MAILBOX_IRQSTATUS_CLR_u 1 m 2 1 17 1 4 1 3 2 Receiving Mode Table 17 13 describes the events servicing in receiving mode Table 17 13 Events Servi...

Page 3245: ...h MESSAGE_7 The message register stores the next to be read Section 17 1 5 10 message of the mailbox Reads remove the message from the FIFO queue 80h FIFOSTATUS_0 The message register stores the next to be read Section 17 1 5 11 message of the mailbox Reads remove the message from the FIFO queue 84h FIFOSTATUS_1 The message register stores the next to be read Section 17 1 5 12 message of the mailb...

Page 3246: ...ding user This register is write 1 to clear 110h IRQSTATUS_RAW_1 The interrupt status register has the status for each Section 17 1 5 31 event that may be responsible for the generation of an interrupt to the corresponding user write 1 to a given bit resets this bit This register is mainly used for debug purpose 114h IRQSTATUS_CLR_1 The interrupt status register has the status combined Section 17 ...

Page 3247: ...ATUS_CLR_3 The interrupt status register has the status combined Section 17 1 5 40 with irq enable for each event that may be responsible for the generation of an interrupt to the corresponding user write 1 to a given bit resets this bit 138h IRQENABLE_SET_3 The interrupt enable register enables to unmask the Section 17 1 5 41 module internal source of interrupt to the corresponding user This regi...

Page 3248: ...INOR R 10h R 400h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 15 REVISION Register Field Descriptions Bit Field Type Reset Description 31 30 SCHEME R 0h Not defined yet 29 28 RES R 0h Reserved 27 16 FUNC R 0h Not defined yet 15 11 RTL R 0h Not defined yet 10 8 MAJOR R 4h IP Major Revision 7 6 Custom R 10h Not Defined Yet 5 0 MINOR R 400h IP Minor Revi...

Page 3249: ...R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 16 SYSCONFIG Register Field Descriptions Bit Field Type Reset Description 31 4 Reserved R W 0h Write 0 s for future compatibility Reads returns 0 3 2 SIdleMode R W 2h 1 Reserved R W 4h Write 0 s for future compatibility Read returns 0 0 SoftReset R W 8h Software reset This bit is automatically reset by the hardware...

Page 3250: ...12 11 10 9 8 7 6 5 4 3 2 1 0 MESSAGEVALUEMBM R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 17 MESSAGE_0 Register Field Descriptions Bit Field Type Reset Description 31 0 MESSAGEVALUEMBM R W 0 0 Message in Mailbox The message register stores the next to be read message of the mailbox Reads remove the message from the FIFO queue 3250 Interprocessor ...

Page 3251: ...12 11 10 9 8 7 6 5 4 3 2 1 0 MESSAGEVALUEMBM R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 18 MESSAGE_1 Register Field Descriptions Bit Field Type Reset Description 31 0 MESSAGEVALUEMBM R W 0 0 Message in Mailbox The message register stores the next to be read message of the mailbox Reads remove the message from the FIFO queue 3251 SPRUH73H Octobe...

Page 3252: ...12 11 10 9 8 7 6 5 4 3 2 1 0 MESSAGEVALUEMBM R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 19 MESSAGE_2 Register Field Descriptions Bit Field Type Reset Description 31 0 MESSAGEVALUEMBM R W 0 0 Message in Mailbox The message register stores the next to be read message of the mailbox Reads remove the message from the FIFO queue 3252 Interprocessor ...

Page 3253: ...12 11 10 9 8 7 6 5 4 3 2 1 0 MESSAGEVALUEMBM R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 20 MESSAGE_3 Register Field Descriptions Bit Field Type Reset Description 31 0 MESSAGEVALUEMBM R W 0 0 Message in Mailbox The message register stores the next to be read message of the mailbox Reads remove the message from the FIFO queue 3253 SPRUH73H Octobe...

Page 3254: ...12 11 10 9 8 7 6 5 4 3 2 1 0 MESSAGEVALUEMBM R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 21 MESSAGE_4 Register Field Descriptions Bit Field Type Reset Description 31 0 MESSAGEVALUEMBM R W 0 0 Message in Mailbox The message register stores the next to be read message of the mailbox Reads remove the message from the FIFO queue 3254 Interprocessor ...

Page 3255: ... 12 11 10 9 8 7 6 5 4 3 2 1 0 MESSAGEVALUEMBM R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 22 MESSAGE_5 Register Field Descriptions Bit Field Type Reset Description 31 0 MESSAGEVALUEMBM R W 0 0 Message in Mailbox The message register stores the next to be read message of the mailbox Reads remove the message from the FIFO queue 3255 SPRUH73H Octob...

Page 3256: ... 12 11 10 9 8 7 6 5 4 3 2 1 0 MESSAGEVALUEMBM R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 23 MESSAGE_6 Register Field Descriptions Bit Field Type Reset Description 31 0 MESSAGEVALUEMBM R W 0 0 Message in Mailbox The message register stores the next to be read message of the mailbox Reads remove the message from the FIFO queue 3256 Interprocessor...

Page 3257: ...3 12 11 10 9 8 7 6 5 4 3 2 1 0 MESSAGEVALUEMBM R W 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 24 MESSAGE_7 Register Field Descriptions Bit Field Type Reset Description 31 0 MESSAGEVALUEMBM R W 0 0 Message in Mailbox The message register stores the next to be read message of the mailbox Reads remove the message from the FIFO queue 3257 SPRUH73H Octo...

Page 3258: ...2 1 0 MESSAGEVALUEMBM FIFOFULLMBM R W 0 R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 25 FIFOSTATUS_0 Register Field Descriptions Bit Field Type Reset Description 31 1 MESSAGEVALUEMBM R W 0 0 Message in Mailbox The message register stores the next to be read message of the mailbox Reads remove the message from the FIFO queue 0 FIFOFULLMBM R 0 0 Full...

Page 3259: ...2 1 0 MESSAGEVALUEMBM FIFOFULLMBM R W 0 R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 26 FIFOSTATUS_1 Register Field Descriptions Bit Field Type Reset Description 31 1 MESSAGEVALUEMBM R W 0 0 Message in Mailbox The message register stores the next to be read message of the mailbox Reads remove the message from the FIFO queue 0 FIFOFULLMBM R 0 0 Full...

Page 3260: ...2 1 0 MESSAGEVALUEMBM FIFOFULLMBM R W 0 R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 27 FIFOSTATUS_2 Register Field Descriptions Bit Field Type Reset Description 31 1 MESSAGEVALUEMBM R W 0 0 Message in Mailbox The message register stores the next to be read message of the mailbox Reads remove the message from the FIFO queue 0 FIFOFULLMBM R 0 0 Full...

Page 3261: ...2 1 0 MESSAGEVALUEMBM FIFOFULLMBM R W 0 R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 28 FIFOSTATUS_3 Register Field Descriptions Bit Field Type Reset Description 31 1 MESSAGEVALUEMBM R W 0 0 Message in Mailbox The message register stores the next to be read message of the mailbox Reads remove the message from the FIFO queue 0 FIFOFULLMBM R 0 0 Full...

Page 3262: ...2 1 0 MESSAGEVALUEMBM FIFOFULLMBM R W 0 R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 29 FIFOSTATUS_4 Register Field Descriptions Bit Field Type Reset Description 31 1 MESSAGEVALUEMBM R W 0 0 Message in Mailbox The message register stores the next to be read message of the mailbox Reads remove the message from the FIFO queue 0 FIFOFULLMBM R 0 0 Full...

Page 3263: ...2 1 0 MESSAGEVALUEMBM FIFOFULLMBM R W 0 R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 30 FIFOSTATUS_5 Register Field Descriptions Bit Field Type Reset Description 31 1 MESSAGEVALUEMBM R W 0 0 Message in Mailbox The message register stores the next to be read message of the mailbox Reads remove the message from the FIFO queue 0 FIFOFULLMBM R 0 0 Full...

Page 3264: ...2 1 0 MESSAGEVALUEMBM FIFOFULLMBM R W 0 R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 31 FIFOSTATUS_6 Register Field Descriptions Bit Field Type Reset Description 31 1 MESSAGEVALUEMBM R W 0 0 Message in Mailbox The message register stores the next to be read message of the mailbox Reads remove the message from the FIFO queue 0 FIFOFULLMBM R 0 0 Full...

Page 3265: ...2 1 0 MESSAGEVALUEMBM FIFOFULLMBM R W 0 R 0 LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 32 FIFOSTATUS_7 Register Field Descriptions Bit Field Type Reset Description 31 1 MESSAGEVALUEMBM R W 0 0 Message in Mailbox The message register stores the next to be read message of the mailbox Reads remove the message from the FIFO queue 0 FIFOFULLMBM R 0 0 Full...

Page 3266: ... 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved NBOFMSGMBM R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 33 MSGSTATUS_0 Register Field Descriptions Bit Field Type Reset Description 2 0 NBOFMSGMBM R 0h Number of unread messages in Mailbox Limited to four messages per mailbox 3266 Interprocessor Communication SPRUH73H October 2011 Revised April...

Page 3267: ... 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved NBOFMSGMBM R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 34 MSGSTATUS_1 Register Field Descriptions Bit Field Type Reset Description 2 0 NBOFMSGMBM R 0h Number of unread messages in Mailbox Limited to four messages per mailbox 3267 SPRUH73H October 2011 Revised April 2013 Interprocessor Communic...

Page 3268: ... 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved NBOFMSGMBM R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 35 MSGSTATUS_2 Register Field Descriptions Bit Field Type Reset Description 2 0 NBOFMSGMBM R 0h Number of unread messages in Mailbox Limited to four messages per mailbox 3268 Interprocessor Communication SPRUH73H October 2011 Revised April...

Page 3269: ... 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved NBOFMSGMBM R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 36 MSGSTATUS_3 Register Field Descriptions Bit Field Type Reset Description 2 0 NBOFMSGMBM R 0h Number of unread messages in Mailbox Limited to four messages per mailbox 3269 SPRUH73H October 2011 Revised April 2013 Interprocessor Communic...

Page 3270: ... 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved NBOFMSGMBM R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 37 MSGSTATUS_4 Register Field Descriptions Bit Field Type Reset Description 2 0 NBOFMSGMBM R 0h Number of unread messages in Mailbox Limited to four messages per mailbox 3270 Interprocessor Communication SPRUH73H October 2011 Revised April...

Page 3271: ... 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved NBOFMSGMBM R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 38 MSGSTATUS_5 Register Field Descriptions Bit Field Type Reset Description 2 0 NBOFMSGMBM R 0h Number of unread messages in Mailbox Limited to four messages per mailbox 3271 SPRUH73H October 2011 Revised April 2013 Interprocessor Communic...

Page 3272: ... 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved NBOFMSGMBM R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 39 MSGSTATUS_6 Register Field Descriptions Bit Field Type Reset Description 2 0 NBOFMSGMBM R 0h Number of unread messages in Mailbox Limited to four messages per mailbox 3272 Interprocessor Communication SPRUH73H October 2011 Revised April...

Page 3273: ... 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved NBOFMSGMBM R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 40 MSGSTATUS_7 Register Field Descriptions Bit Field Type Reset Description 2 0 NBOFMSGMBM R 0h Number of unread messages in Mailbox Limited to four messages per mailbox 3273 SPRUH73H October 2011 Revised April 2013 Interprocessor Communic...

Page 3274: ...ption 15 NotFullStatusUuMB7 R W 0h Not Full Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 14 NewMSGStatusUuMB7 R W 0h New Message Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 13 NotFullStatusUuMB6 R W 0h Not Full Status bit for User u Mailbox 6 0 NoAction No action 1 SetEvent Set the event for debug 12 NewMSGStatu...

Page 3275: ...the event for debug 3 NotFullStatusUuMB1 R W 0h Not Full Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 2 NewMSGStatusUuMB1 R W 0h New Message Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 1 NotFullStatusUuMB0 R W 0h Not Full Status bit for User u Mailbox 0 0 NoAction No action 1 SetEvent Set the event for debug 0 N...

Page 3276: ...tFullStatusUuMB7 R W 0h Not Full Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 14 NewMSGStatusUuMB7 R W 0h New Message Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 13 NotFullStatusUuMB6 R W 0h Not Full Status bit for User u Mailbox 6 0 NoAction No action 1 SetEvent Set the event for debug 12 NewMSGStatusUuMB6 R W ...

Page 3277: ...the event for debug 3 NotFullStatusUuMB1 R W 0h Not Full Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 2 NewMSGStatusUuMB1 R W 0h New Message Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 1 NotFullStatusUuMB0 R W 0h Not Full Status bit for User u Mailbox 0 0 NoAction No action 1 SetEvent Set the event for debug 0 N...

Page 3278: ...l Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 14 NewMSGStatusUuMB7 R W 0h New Message Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 13 NotFullStatusUuMB6 R W 0h Not Full Status bit for User u Mailbox 6 0 NoAction No action 1 SetEvent Set the event for debug 12 NewMSGStatusUuMB6 R W 0h New Message Status bit for U...

Page 3279: ...the event for debug 3 NotFullStatusUuMB1 R W 0h Not Full Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 2 NewMSGStatusUuMB1 R W 0h New Message Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 1 NotFullStatusUuMB0 R W 0h Not Full Status bit for User u Mailbox 0 0 NoAction No action 1 SetEvent Set the event for debug 0 N...

Page 3280: ...l Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 14 NewMSGStatusUuMB7 R W 0h New Message Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 13 NotFullStatusUuMB6 R W 0h Not Full Status bit for User u Mailbox 6 0 NoAction No action 1 SetEvent Set the event for debug 12 NewMSGStatusUuMB6 R W 0h New Message Status bit for U...

Page 3281: ...the event for debug 3 NotFullStatusUuMB1 R W 0h Not Full Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 2 NewMSGStatusUuMB1 R W 0h New Message Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 1 NotFullStatusUuMB0 R W 0h Not Full Status bit for User u Mailbox 0 0 NoAction No action 1 SetEvent Set the event for debug 0 N...

Page 3282: ...ption 15 NotFullStatusUuMB7 R W 0h Not Full Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 14 NewMSGStatusUuMB7 R W 0h New Message Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 13 NotFullStatusUuMB6 R W 0h Not Full Status bit for User u Mailbox 6 0 NoAction No action 1 SetEvent Set the event for debug 12 NewMSGStatu...

Page 3283: ...the event for debug 3 NotFullStatusUuMB1 R W 0h Not Full Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 2 NewMSGStatusUuMB1 R W 0h New Message Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 1 NotFullStatusUuMB0 R W 0h Not Full Status bit for User u Mailbox 0 0 NoAction No action 1 SetEvent Set the event for debug 0 N...

Page 3284: ...tFullStatusUuMB7 R W 0h Not Full Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 14 NewMSGStatusUuMB7 R W 0h New Message Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 13 NotFullStatusUuMB6 R W 0h Not Full Status bit for User u Mailbox 6 0 NoAction No action 1 SetEvent Set the event for debug 12 NewMSGStatusUuMB6 R W ...

Page 3285: ...the event for debug 3 NotFullStatusUuMB1 R W 0h Not Full Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 2 NewMSGStatusUuMB1 R W 0h New Message Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 1 NotFullStatusUuMB0 R W 0h Not Full Status bit for User u Mailbox 0 0 NoAction No action 1 SetEvent Set the event for debug 0 N...

Page 3286: ...l Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 14 NewMSGStatusUuMB7 R W 0h New Message Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 13 NotFullStatusUuMB6 R W 0h Not Full Status bit for User u Mailbox 6 0 NoAction No action 1 SetEvent Set the event for debug 12 NewMSGStatusUuMB6 R W 0h New Message Status bit for U...

Page 3287: ...the event for debug 3 NotFullStatusUuMB1 R W 0h Not Full Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 2 NewMSGStatusUuMB1 R W 0h New Message Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 1 NotFullStatusUuMB0 R W 0h Not Full Status bit for User u Mailbox 0 0 NoAction No action 1 SetEvent Set the event for debug 0 N...

Page 3288: ...l Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 14 NewMSGStatusUuMB7 R W 0h New Message Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 13 NotFullStatusUuMB6 R W 0h Not Full Status bit for User u Mailbox 6 0 NoAction No action 1 SetEvent Set the event for debug 12 NewMSGStatusUuMB6 R W 0h New Message Status bit for U...

Page 3289: ...the event for debug 3 NotFullStatusUuMB1 R W 0h Not Full Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 2 NewMSGStatusUuMB1 R W 0h New Message Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 1 NotFullStatusUuMB0 R W 0h Not Full Status bit for User u Mailbox 0 0 NoAction No action 1 SetEvent Set the event for debug 0 N...

Page 3290: ...ption 15 NotFullStatusUuMB7 R W 0h Not Full Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 14 NewMSGStatusUuMB7 R W 0h New Message Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 13 NotFullStatusUuMB6 R W 0h Not Full Status bit for User u Mailbox 6 0 NoAction No action 1 SetEvent Set the event for debug 12 NewMSGStatu...

Page 3291: ...the event for debug 3 NotFullStatusUuMB1 R W 0h Not Full Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 2 NewMSGStatusUuMB1 R W 0h New Message Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 1 NotFullStatusUuMB0 R W 0h Not Full Status bit for User u Mailbox 0 0 NoAction No action 1 SetEvent Set the event for debug 0 N...

Page 3292: ...tFullStatusUuMB7 R W 0h Not Full Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 14 NewMSGStatusUuMB7 R W 0h New Message Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 13 NotFullStatusUuMB6 R W 0h Not Full Status bit for User u Mailbox 6 0 NoAction No action 1 SetEvent Set the event for debug 12 NewMSGStatusUuMB6 R W ...

Page 3293: ...the event for debug 3 NotFullStatusUuMB1 R W 0h Not Full Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 2 NewMSGStatusUuMB1 R W 0h New Message Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 1 NotFullStatusUuMB0 R W 0h Not Full Status bit for User u Mailbox 0 0 NoAction No action 1 SetEvent Set the event for debug 0 N...

Page 3294: ...l Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 14 NewMSGStatusUuMB7 R W 0h New Message Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 13 NotFullStatusUuMB6 R W 0h Not Full Status bit for User u Mailbox 6 0 NoAction No action 1 SetEvent Set the event for debug 12 NewMSGStatusUuMB6 R W 0h New Message Status bit for U...

Page 3295: ...the event for debug 3 NotFullStatusUuMB1 R W 0h Not Full Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 2 NewMSGStatusUuMB1 R W 0h New Message Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 1 NotFullStatusUuMB0 R W 0h Not Full Status bit for User u Mailbox 0 0 NoAction No action 1 SetEvent Set the event for debug 0 N...

Page 3296: ...l Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 14 NewMSGStatusUuMB7 R W 0h New Message Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 13 NotFullStatusUuMB6 R W 0h Not Full Status bit for User u Mailbox 6 0 NoAction No action 1 SetEvent Set the event for debug 12 NewMSGStatusUuMB6 R W 0h New Message Status bit for U...

Page 3297: ...the event for debug 3 NotFullStatusUuMB1 R W 0h Not Full Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 2 NewMSGStatusUuMB1 R W 0h New Message Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 1 NotFullStatusUuMB0 R W 0h Not Full Status bit for User u Mailbox 0 0 NoAction No action 1 SetEvent Set the event for debug 0 N...

Page 3298: ...ption 15 NotFullStatusUuMB7 R W 0h Not Full Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 14 NewMSGStatusUuMB7 R W 0h New Message Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 13 NotFullStatusUuMB6 R W 0h Not Full Status bit for User u Mailbox 6 0 NoAction No action 1 SetEvent Set the event for debug 12 NewMSGStatu...

Page 3299: ...the event for debug 3 NotFullStatusUuMB1 R W 0h Not Full Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 2 NewMSGStatusUuMB1 R W 0h New Message Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 1 NotFullStatusUuMB0 R W 0h Not Full Status bit for User u Mailbox 0 0 NoAction No action 1 SetEvent Set the event for debug 0 N...

Page 3300: ...tFullStatusUuMB7 R W 0h Not Full Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 14 NewMSGStatusUuMB7 R W 0h New Message Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 13 NotFullStatusUuMB6 R W 0h Not Full Status bit for User u Mailbox 6 0 NoAction No action 1 SetEvent Set the event for debug 12 NewMSGStatusUuMB6 R W ...

Page 3301: ...the event for debug 3 NotFullStatusUuMB1 R W 0h Not Full Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 2 NewMSGStatusUuMB1 R W 0h New Message Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 1 NotFullStatusUuMB0 R W 0h Not Full Status bit for User u Mailbox 0 0 NoAction No action 1 SetEvent Set the event for debug 0 N...

Page 3302: ...l Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 14 NewMSGStatusUuMB7 R W 0h New Message Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 13 NotFullStatusUuMB6 R W 0h Not Full Status bit for User u Mailbox 6 0 NoAction No action 1 SetEvent Set the event for debug 12 NewMSGStatusUuMB6 R W 0h New Message Status bit for U...

Page 3303: ...the event for debug 3 NotFullStatusUuMB1 R W 0h Not Full Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 2 NewMSGStatusUuMB1 R W 0h New Message Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 1 NotFullStatusUuMB0 R W 0h Not Full Status bit for User u Mailbox 0 0 NoAction No action 1 SetEvent Set the event for debug 0 N...

Page 3304: ...l Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 14 NewMSGStatusUuMB7 R W 0h New Message Status bit for User u Mailbox 7 0 NoAction No action 1 SetEvent Set the event for debug 13 NotFullStatusUuMB6 R W 0h Not Full Status bit for User u Mailbox 6 0 NoAction No action 1 SetEvent Set the event for debug 12 NewMSGStatusUuMB6 R W 0h New Message Status bit for U...

Page 3305: ...the event for debug 3 NotFullStatusUuMB1 R W 0h Not Full Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 2 NewMSGStatusUuMB1 R W 0h New Message Status bit for User u Mailbox 1 0 NoAction No action 1 SetEvent Set the event for debug 1 NotFullStatusUuMB0 R W 0h Not Full Status bit for User u Mailbox 0 0 NoAction No action 1 SetEvent Set the event for debug 0 N...

Page 3306: ...egister is read when attempting to acquire a lock Section 17 2 1 7 The lock is automatically taken if it was not taken and the value returned by the read is zero If the lock was already taken then the read returns one Writing a zero to this register frees the lock 810h LOCK_REG_4 This register is read when attempting to acquire a lock Section 17 2 1 8 The lock is automatically taken if it was not ...

Page 3307: ...hen the read returns one Writing a zero to this register frees the lock 83Ch LOCK_REG_15 This register is read when attempting to acquire a lock Section 17 2 1 19 The lock is automatically taken if it was not taken and the value returned by the read is zero If the lock was already taken then the read returns one Writing a zero to this register frees the lock 840h LOCK_REG_16 This register is read ...

Page 3308: ... Section 17 2 1 30 The lock is automatically taken if it was not taken and the value returned by the read is zero If the lock was already taken then the read returns one Writing a zero to this register frees the lock 86Ch LOCK_REG_27 This register is read when attempting to acquire a lock Section 17 2 1 31 The lock is automatically taken if it was not taken and the value returned by the read is ze...

Page 3309: ...re 17 45 REV Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REV R 50020000h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 58 REV Register Field Descriptions Bit Field Type Reset Description 31 0 REV R 50020000h IP Revision Code 3309 SPRUH73H October 2011 Revised April 2013 Interprocessor Communication Subm...

Page 3310: ...be switched off 1 REQUIRED OCP clock is required by the module even during idle mode 7 5 Reserved R 0h 4 3 SIDLEMODE R 2h Control of the slave interface power management IDLE request acknowledgement 0 FORCEIDLE IDLE request is acknowledged unconditionally and immediately 1 NOIDLE IDLE request is never acknowledged 2 SMARTIDLE IDLE request acknowledgement is based on the internal module activity 3 ...

Page 3311: ...0 SYSTATUS Register Field Descriptions Bit Field Type Reset Description 31 24 NUMLOCKS R 1h 23 16 Reserved R 100h 15 IU7 R 200h 14 IU6 R 400h 13 IU5 R 800h 12 IU4 R 1000h 11 IU3 R 2000h 10 IU2 R 4000h 9 IU1 R 8000h In Use flag 1 covering lock registers 32 63 Reads as one only if one or more lock registers in this range are TAKEN If no lock registers are implemented in this range then this flag alw...

Page 3312: ...register frees the lock Figure 17 48 LOCK_REG_0 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 61 LOCK_REG_0 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 T...

Page 3313: ...register frees the lock Figure 17 49 LOCK_REG_1 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 62 LOCK_REG_1 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 T...

Page 3314: ...register frees the lock Figure 17 50 LOCK_REG_2 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 63 LOCK_REG_2 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 T...

Page 3315: ...register frees the lock Figure 17 51 LOCK_REG_3 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 64 LOCK_REG_3 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 T...

Page 3316: ...register frees the lock Figure 17 52 LOCK_REG_4 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 65 LOCK_REG_4 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 T...

Page 3317: ...register frees the lock Figure 17 53 LOCK_REG_5 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 66 LOCK_REG_5 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 T...

Page 3318: ...register frees the lock Figure 17 54 LOCK_REG_6 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 67 LOCK_REG_6 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 T...

Page 3319: ...register frees the lock Figure 17 55 LOCK_REG_7 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 68 LOCK_REG_7 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 T...

Page 3320: ...register frees the lock Figure 17 56 LOCK_REG_8 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 69 LOCK_REG_8 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 T...

Page 3321: ...register frees the lock Figure 17 57 LOCK_REG_9 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 70 LOCK_REG_9 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 T...

Page 3322: ...register frees the lock Figure 17 58 LOCK_REG_10 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 71 LOCK_REG_10 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3323: ...register frees the lock Figure 17 59 LOCK_REG_11 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 72 LOCK_REG_11 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3324: ...register frees the lock Figure 17 60 LOCK_REG_12 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 73 LOCK_REG_12 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3325: ...register frees the lock Figure 17 61 LOCK_REG_13 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 74 LOCK_REG_13 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3326: ...register frees the lock Figure 17 62 LOCK_REG_14 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 75 LOCK_REG_14 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3327: ...register frees the lock Figure 17 63 LOCK_REG_15 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 76 LOCK_REG_15 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3328: ...register frees the lock Figure 17 64 LOCK_REG_16 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 77 LOCK_REG_16 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3329: ...register frees the lock Figure 17 65 LOCK_REG_17 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 78 LOCK_REG_17 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3330: ...register frees the lock Figure 17 66 LOCK_REG_18 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 79 LOCK_REG_18 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3331: ...register frees the lock Figure 17 67 LOCK_REG_19 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 80 LOCK_REG_19 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3332: ...register frees the lock Figure 17 68 LOCK_REG_20 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 81 LOCK_REG_20 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3333: ...register frees the lock Figure 17 69 LOCK_REG_21 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 82 LOCK_REG_21 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3334: ...register frees the lock Figure 17 70 LOCK_REG_22 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 83 LOCK_REG_22 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3335: ...register frees the lock Figure 17 71 LOCK_REG_23 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 84 LOCK_REG_23 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3336: ...register frees the lock Figure 17 72 LOCK_REG_24 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 85 LOCK_REG_24 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3337: ...register frees the lock Figure 17 73 LOCK_REG_25 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 86 LOCK_REG_25 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3338: ...register frees the lock Figure 17 74 LOCK_REG_26 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 87 LOCK_REG_26 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3339: ...register frees the lock Figure 17 75 LOCK_REG_27 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 88 LOCK_REG_27 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3340: ...register frees the lock Figure 17 76 LOCK_REG_28 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 89 LOCK_REG_28 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3341: ...register frees the lock Figure 17 77 LOCK_REG_29 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 90 LOCK_REG_29 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3342: ...register frees the lock Figure 17 78 LOCK_REG_30 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 91 LOCK_REG_30 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3343: ...register frees the lock Figure 17 79 LOCK_REG_31 Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved TAKEN R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 17 92 LOCK_REG_31 Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0...

Page 3344: ...ice Topic Page 18 1 Introduction 3345 18 2 Integration 3346 18 3 Functional Description 3350 18 4 Low Level Programming Models 3384 18 5 Multimedia Card Registers 3389 3344 Multimedia Card MMC SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3345: ...ommand response sets as defined in the SD Physical Layer specification v2 00 SDIO command response sets and interrupt read wait suspend resume operations as defined in the SD part E1 specification v 2 00 SD Host Controller Standard Specification sets as defined in the SD card specification Part A2 v2 00 18 1 2 Unsupported MMCHS Features The MMCHS module features not supported in this device are sh...

Page 3346: ...MMC_CLK Integration www ti com 18 2 Integration This device contains three instances of the Multimedia Card MMC Secure Digital SD and Secure Digital I O SDIO high speed interface module MMCHS The controller provides an interface to an MMC SD memory card or SDIO card The application interface is responsible for managing transaction semantics the MMC SDIO host controller deals with MMC SDIO protocol...

Page 3347: ... Attributes The general connectivity attributes for the three MMCHS modules are shown in Table 18 2 Table 18 2 MMCHS Connectivity Attributes Attributes Type Power Domain Peripheral Domain Clock Domain PD_PER_L4LS_GCLK OCP PD_PER_MMC_FCLK Func CLK_32KHZ Debounce Reset Signals PER_DOM_RST_N Idle Wakeup Signals Smart Idle Interrupt Requests 1 interrupt per instance to MPU Subsystem MMCSDxINT DMA Requ...

Page 3348: ...O read wait output MMCx_DAT 7 3 I O MMC SD data signals MMCx_POW O MMC SD power supply control MMCHS 0 only MMCx_SDCD I SD card detect from connector MMCx_SDWP I SD write protect from connector MMCx_OBI I MMC out of band interrupt 1 This output signal is also used as a retiming input The associated CONF_ module _ pin _RXACTIVE bit for the output clock must be set to 1 to enable the clock input bac...

Page 3349: ...Q 0 ADPDATDIROQ 0 1 0 1 0 1 0 1 0 DAT 2 ADPDATDIRLS 2 ADPDATDIRLS 2 ADPDATDIRLS 2 ADPDATDIRLS 2 ADPDATDIRLS 2 0 0 1 0 1 0 1 0 1 ADPDATDIROQ 2 ADPDATDIROQ 2 ADPDATDIROQ 2 ADPDATDIROQ 2 ADPDATDIROQ 2 1 1 0 1 0 1 0 1 0 DAT 1 ADPDATDIRLS 1 ADPDATDIRLS 1 ADPDATDIRLS 1 ADPDATDIRLS 1 ADPDATDIRLS 1 0 0 1 0 1 0 0 1 DAT 3 ADPDATDIROQ 1 ADPDATDIROQ 1 ADPDATDIROQ 1 ADPDATDIROQ 1 ADPDATDIROQ 1 1 1 0 1 0 1 1 0 ...

Page 3350: ...or example two SD cards one MMC card and one SD card are not supported through a single controller 18 3 1 MMC SD SDIO Functional Modes 18 3 1 1 MMC SD SDIO Connected to an MMC an SD Card or an SDIO Card Figure 18 4 shows the MMC SD SDIO1 and MMC SD SDIO2 host controllers connected to an MMC an SD or an SDIO card and its related external connections Figure 18 4 MMC SD1 2 Connectivity to an MMC SD C...

Page 3351: ...lock to time the inputs Table 18 7 provides a summary of these pins Table 18 7 MMC SD SDIO Controller Pins and Descriptions Pin Type 1 Bit Mode 4 Bit Mode 8 Bit Mode Reset Value MMC_CLK 1 O Clock Line Clock Line Clock Line High impedance MMC_CMD I O Command Line Command Line Command Line High impedance MMC_DAT0 I O Data Line 0 Data Line 0 Data Line 0 0 MMC_DAT1 I O not used Data Line 1 Data Line 1...

Page 3352: ... any of the active data lines the card sends a negative CRC status on mmc_dat0 In the case of successful transmission over all active data lines the card sends a positive CRC status on mmc_dat0 and starts the data programming procedure 3352 Multimedia Card MMC SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3353: ...oriented See the Multimedia Card System Specification the SD Memory Card Specifications and the SDIO Card Specification Part E1 for details about commands and programming sequences supported by the MMC SD and SDIO cards CAUTION Stream commands are supported only by MMC cards Figure 18 6 and Figure 18 7 show how sequential operations are defined Sequential operation is only for 1 bit transfer and i...

Page 3354: ...and follows on the mmc_cmd line These operations are available for all kinds of cards Figure 18 8 Multiple Block Read Operation MMC Cards Only Figure 18 9 Multiple Block Write Operation MMC Cards Only NOTE 1 The card busy signal is not always generated by the card the previous examples show a particular case 2 It is the software s responsibility to do a software reset after a data timeout to ensur...

Page 3355: ...the card the SD_CMD register must be configured differently to avoid false CRC or index errors to be flagged on command response see Table 18 8 For more details about response types see the Multimedia Card System Specification the SD Memory Card Specification or the SDIO Card Specification Table 18 8 Response Type Summary 1 Response Type Index Check Enable CRC Check Enable SD_CMD 17 16 SD_CMD 20 S...

Page 3356: ...t0 Functional Description www ti com Coding Scheme for Data Token Data tokens always start with 0 and end with 1 see Figure 18 13 Figure 18 14 Figure 18 15 and Figure 18 16 Figure 18 13 Data Packet for Sequential Transfer 1 Bit Figure 18 14 Data Packet for Block Transfer 1 Bit Figure 18 15 Data Packet for Block Transfer 4 Bit 3356 Multimedia Card MMC SPRUH73H October 2011 Revised April 2013 Submit...

Page 3357: ...omains This hardware reset signal has a global reset action on the module All configuration registers and all state machines are reset in all clock domains 18 3 2 2 Software Reset The module is reinitialized by software through the SD_SYSCONFIG 1 SOFTRESET bit This bit has the same action on the module logic as the hardware signal except for Debounce logic SD_PSTATE SD_CAPA and SD_CUR_CAPA registe...

Page 3358: ...he following conditions are met The SD_SYSCONFIG 0 AUTOIDLE bit is set to 1 There is no transaction on the MMC interface The autogating of interface and functional clocks stops when the following conditions are met A register access occurs through the L3 or L4 interconnect A wake up event occurs an interrupt from a SDIO card A transaction on the MMC SD SDIO interface starts Then the MMC SD SDIO ho...

Page 3359: ...de if the associated enable bit is set in the SD_ISE register Interrupts and wake up events have independent enable disable controls accessible through the SD_HCTL and SD_ISE registers The overall consistency must be ensured by software The interrupt status register SD_STAT is updated with the event that caused the wake up in the CIRQ bit when the SD_IE 8 CIRQ_ENABLE associated bit is enabled Then...

Page 3360: ...mart idle modes Clock Activity SD_SYSCONFIG CLOCKACTIVITY bit Please see Table 18 10 for configuration details Global Wake Up SD_SYSCONFIG ENAWAKEUP bit This bit enables the wake up feature at module level Enable Wake Up Sources SD_HCTL register This register holds one active high enable bit per event source Enable able to generate wake up signal Table 18 10 Clock Activity Settings Clock State Whe...

Page 3361: ...the service of the interrupt without updating the status SD_STAT or transmitting an interrupt request Table 18 11 lists the event flags and their mask that can cause module interrupts Table 18 11 Events Event Flag Event Mask Map To Description SD_STAT 29 BADA SD_IE 29 MMC_IRQ Bad Access to Data space This bit is set automatically to indicate a bad BADA_ENABLE access to buffer when not allowed This...

Page 3362: ...urce is sampled during the interrupt cycle In CE ATA mode interrupt source is detected when the card drive CMD line to zero during one cycle after data transmission end SD_STAT 5 BRR SD_IE 5 MMC_IRQ Buffer Read ready This bit is set automatically during a read operation to BRR_ENABLE the card when one block specified by SD_BLK 10 0 BLEN is completely written in the buffer It indicates that the mem...

Page 3363: ...egister to detect when the corresponding event occurs Writing 1 into the corresponding bit of the SD_STAT register clears the interrupt status and does not affect the interrupt line state NOTE Please see the note in Section 18 3 4 1 concerning CIRQ and ERRI bits clearing 18 3 5 DMA Modes The device supports DMA slave mode only In this case the controller is slave on DMA transaction managed by two ...

Page 3364: ...level when the sDMA has read one single word from the buffer Only one request is sent per block the DMA controller can make a 1 shot read access or several DMA bursts in which case the DMA controller must manage the number of burst accesses according to block size BLEN field New DMA requests are internally masked if the sDMA has not read exactly BLEN bytes and a new complete block is not ready As ...

Page 3365: ... buffer The block size transfer is specified in the SD_BLK 10 0 BLEN field The SDMAWREQN signal is deasserted to its inactive level when the sDMA has written one single word to the buffer Only one request is sent per block the DMA controller can make a 1 shot write access or multiple write DMA bursts in which case the DMA controller must manage the number of burst accesses according to block size ...

Page 3366: ...f 32 bit accesses to the SD_DATA register that are needed to read or write a data block with a size of SD_BLK 10 0 BLEN and equals the rounded up result of BLEN divided by 4 The maximum block size supported by the host controller is hard coded in the register SD_CAPA 17 16 MBL field and cannot be changed A read access to the SD_DATA register is allowed only when the buffer read enable status is se...

Page 3367: ...me and Write to the card SD_CMD DDIR 0 Interconnect bus Interconnect bus Card bus Card bus MEM_SIZE 8 www ti com Functional Description CAUTION The SD_CMD 4 DDIR bit must be configured before a transfer to indicate the direction of the transfer Figure 18 19 shows the buffer management for writing and Figure 18 20 shows the buffer management for reading Figure 18 19 Buffer Management for a Write 33...

Page 3368: ...e 18 20 Buffer Management for a Read 18 3 7 1 1 Memory Size Block Length and Buffer Management Relationship The maximum block length and buffer management that can be targeted by system depend on memory depth setting Table 18 12 Memory Size BLEN and Buffer Relationship Memory Size 5 2 MEMSIZE in bytes 512 1024 2048 4096 Maximum block length supported 512 1024 2048 2048 Double buffering for maximum...

Page 3369: ...d Specifications the SDIO Card Specification Part E1 or the SD Card Specification Part A2 SD Host Controller Standard Specification for more details Table 18 13 shows how the MMC SD and SDIO responses are stored in the SD_RSPxx registers Table 18 13 MMC SD SDIO Responses in the SD_RSPxx Registers Kind of Response Response Field Response Register R1 R1b normal response R3 R4 R5 R5b R6 R7 RESP 39 8 ...

Page 3370: ... is set upon DEB 21 DCRC 1 TC is set upon DCRC 20 DTO DTO and TC are mutually exclusive DCRC and DEB cannot occur with DTO 19 CIE 1 CC is set upon CIE 18 CEB 1 CC is set upon CEB 17 CCRC 1 CC can be set upon CCRC See CTO comment 16 CTO CTO and CC are mutually exclusive CIE CEB and CERR cannot occur with CTO CTO can occur at the same time as CCRC it indicates a command abort due to a contention on ...

Page 3371: ...r R1b or R5b responses Figure 18 21 Busy Timeout for R1b R5b Responses t1 Data timeout counter is loaded and starts after R1b R5b response type t2 Data timeout counter stops and if it is 0 SD_STAT 21 DCRC is generated 18 3 9 2 Busy Timeout After Write CRC Status Figure 18 22 shows DCRC event condition asserted when there is busy timeout after write CRC status Figure 18 22 Busy Timeout After Write ...

Page 3372: ...t1 Data timeout counter is loaded and starts after Data block CRC t2 Data timeout counter stops and if it is 0 SD_STAT 21 DCRC is generated 18 3 9 4 Read Data Timeout Figure 18 24 shows DCRC event condition asserted when there is read data timeout Figure 18 24 Read Data Timeout t1 Data timeout counter is loaded and starts after Command transmission t2 Data timeout counter stops and if it is 0 SD_S...

Page 3373: ...counter stops and if it is 0 SD_STAT 21 DCRC is generated t3 Data timeout counter is loaded and starts t4 Data timeout counter stops and if it is 0 SD_STAT 21 DCRC is generated t5 Data timeout counter is loaded and starts after Data CRC transmission t6 Data timeout counter stops and if it is 0 SD_STAT 21 DCRC is generated Figure 18 26 shows DCRC event condition asserted when there is boot acknowle...

Page 3374: ... ti com t6 Data timeout counter stops and if it is 0 SD_STAT 21 DCRC is generated 3374 Multimedia Card MMC SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3375: ...as been defined for SDR50 and SDR104 card components for write data transfers as auto command 12 end bit shall arrive after the CRC status end bit Figure 18 27 shows auto CMD12 timings during write transfer Figure 18 27 Auto CMD12 Timing During Write Transfer The Host controller has a margin of 18 clock cycles to make sure that auto CMD12 end bit arrives after the CRC status This margin does not d...

Page 3376: ...al in order to receive the last complete and reliable block SD controller only follows the Left Border Case defined by SD UHS specification Figure 18 28 shows ACMD12 timings during read transfer Figure 18 28 Auto Command 12 Timings During Read Transfer The Auto CMD12 arrival sent by the Host controller is not sensitive to the MMC bus configuration whether it is DDR or standard transfer and whether...

Page 3377: ...ed by setting the SD_HCTL 16 SBGR bit to 1 When enabled this capability holds the transfer on until the end of a block boundary If a stop transmission is needed software can use this pause to send a CMD12 to the card Table 18 15 shows the common ways to stop a transfer indicating command to send and features to enable Table 18 15 MMC SD SDIO Controller Transfer Stop Command Summary WRITE Transfer ...

Page 3378: ...s cleared to 0 Figure 18 29 shows the output signals of the module when generating from the falling edge of the MMC clock Figure 18 29 Output Driven on Falling Edge 18 3 12 2 Generation on Rising Edge of MMC Clock This mode increases setup timings and allows reaching higher bus frequency This feature is activated by setting SD_HCTL 2 HSPE bit to 1 The controller shall be set in this mode to suppor...

Page 3379: ...tMOH Valid OUT tMIS tCP tC2 tC1 tMiH Valid IN www ti com Functional Description Figure 18 30 Output Driven on Rising Edge 3379 SPRUH73H October 2011 Revised April 2013 Multimedia Card MMC Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3380: ...iagram of a boot sequence using CMD0 Figure 18 31 Boot Mode With CMD0 Configure MMCHS_CON BOOT_CF0 to 0 MMCHS_CON BOOT_ACK if an acknowledge will be received to 0x1 MMCHS_BLK with the correct block length and number of block MMCHS_SYSCTL DTO for timeout If transfer is done in DDR mode also set MMCHS_CON DDR to 1 Write register MMCHS_ARG with correct argument see MMC Specification Write in MMCHS_CM...

Page 3381: ...also set MMCHS_CON DDR to 1 Write in MMCHS_CMD register to start boot sequence with DP set to 1 DDIR set to 1 MSBS set to 1 BCE set to 1 This leads the controller to force CMD line to 0 If the boot status is not received within the timing defined the MMCHS_STAT DTO will be generated Otherwise the MMCHS_STAT BSR is arisen After the transfer is complete the controller will generate the MMCHS_STAT TC...

Page 3382: ...CS token sent by the card Three cases can be met CCS is receive just before CCSD is emitted An interrupt CIRQ is generated with CCS detection CCSD is transmitted to card then an interrupt CC is generated when CCSD ends In this case card consider the CCSD sequence CCS is not generated or generated during the CCSD transfer The CCS bit cannot be detected conflict is not possible as they drive the sam...

Page 3383: ...er write enable Status 10 BWE Indicates whether there is enough space in the buffer to write BLEN bytes of data Read transfer active Status 9 RTA This status is used for detecting completion of a read transfer Write transfer active Status 8 WTA This status indicates a write transfer active Data line active Status 2 DLA Indicates whether the data lines are active Command Inhibit data lines Status 1...

Page 3384: ...e SD module See Chapter 6 Interrupts optional EDMA DMA configuration must be done to enable the module DMA channel requests See Chapter 11 EDMA optional Interconnect For more information about the interconnect configuration see Chapter 10 Interconnects NOTE The MPU interrupt controller and the EDMA configurations are necessary if the interrupt and DMA based communication modes are used 18 4 2 MMC ...

Page 3385: ...A 26 24 and SD_CUR_CAPA 23 0 registers before the MMC SD SDIO host driver is started 18 4 2 4 Wake Up Configuration Table 18 18 details SD controller wake up configuration Table 18 18 MMC SD SDIO Controller Wake Up Configuration Step Access Type Register Bit Field Programming Model Configure wake up bit if necessary W SD_SYSCONFIG 2 ENAWAKEUP Enable wake up events on SD card interrupt if W SD_HCTL...

Page 3386: ...nternal clock Configure the SD_SYSCTL 15 6 CLKD bit field Read the SD_SYSCTL 1 ICS bit ICS 0x1 YES Clock is stable Write the SD_SYSCONFIG CLOCKACTIVITY SIDLEMODE and AUTOIDLE fields to configure the behavior of the module in idle mode NO Write SD_CON register to configure specific data and command transfer OD DW8 CEATA Low Level Programming Models www ti com 18 4 2 5 MMC Host and Bus Configuration...

Page 3387: ...Clear SD_STAT register write 0xFFFF FFFF Change clock frequency to fit protocol Send a CMD0 command www ti com Low Level Programming Models 18 4 3 Operational Modes Configuration 18 4 3 1 Basic Operations for MMC SD SDIO Host Controller The MMC SD SDIO controller performs data transfers data to card referred to as write transfers and data from card referred to as read transfers The host controller...

Page 3388: ...and to get information on how to access the card content MMC cards YES and all cards are not identified NO or all cards are identified Is there more than one MMC connected to the same bus and are they all indentified End unknown type of card YES Send an CMD55 command YES It is a MMC card YES The card is not busy NO The card is busy YES It is a MMC card NO The card is busy YES The card is not busy ...

Page 3389: ...h SD_PWCNT Section 18 5 1 6 200h SD_SDMASA Section 18 5 1 7 204h SD_BLK Section 18 5 1 8 208h SD_ARG Section 18 5 1 9 20Ch SD_CMD Section 18 5 1 10 210h SD_RSP10 Section 18 5 1 11 214h SD_RSP32 Section 18 5 1 12 218h SD_RSP54 Section 18 5 1 13 21Ch SD_RSP76 Section 18 5 1 14 220h SD_DATA Section 18 5 1 15 224h SD_PSTATE Section 18 5 1 16 228h SD_HCTL Section 18 5 1 17 22Ch SD_SYSCTL Section 18 5 1...

Page 3390: ...k may be switched off 0x2 Functional clock is maintained Interface clock may be switched off 0x3 Interface and Functional clocks are maintained 7 5 Reserved R 0h 4 3 SIDLEMODE R W 0h Power management 0x0 If an idle request is detected the MMC SD SDIO host controller acknowledges it unconditionally and goes in Inactive mode Interrupt and DMA requests are unconditionally deasserted 0x1 If an idle re...

Page 3391: ...ion 0 AUTOIDLE R W 0h Internal Clock gating strategy 0x0 R Clocks are free running 0x1 W Automatic clock gating strategy is applied based on the interconnect and MMC interface activity 3391 SPRUH73H October 2011 Revised April 2013 Multimedia Card MMC Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3392: ...Reserved RESETDONE R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 18 21 SD_SYSSTATUS Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 RESETDONE R 0h Internal Reset Monitoring Notethe debounce clock the interface clock and the functional clock shall be provided to the MMC SD SDIO host controller to allow the interna...

Page 3393: ...tatus to avoid the host driver reading the response register SD_RSP10 No automatic card error detection for autoCMD12 is implemented the host system has to check autoCMD12 response register SD_RSP76 for possible card errors Figure 18 39 SD_CSRE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CSRE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1...

Page 3394: ...oCl Write 1 to clear bit n value after reset Table 18 23 SD_SYSTEST Register Field Descriptions Bit Field Type Reset Description 31 17 Reserved R 0h 16 OBI R W 0h Out of band interrupt OBI data value 0x0 The out of band interrupt pin is driven low 0x1 The out of band interrupt pin is driven high 15 SDCD R W 0h Card detect input signal SDCD data value 0x0 The card detect pin is driven low 0x1 The c...

Page 3395: ...ns the value on the DAT6 line high If SD_SYSTEST 3 DDIR bit 0 output mode direction returns 1 9 D5D R W 0h DAT5 input output signal data value 0x0 W If SD_SYSTEST 3 DDIR bit 0 output mode direction the DAT5 line is driven low If SD_SYSTEST 3 DDIR bit 1 input mode direction no effect 0x0 R If SD_SYSTEST 3 DDIR bit 1 input mode direction returns the value on the DAT5 line low If SD_SYSTEST 3 DDIR bi...

Page 3396: ...1D R W 0h DAT1 input output signal data value 0x0 W If SD_SYSTEST 3 DDIR bit 0 output mode direction the DAT1 line is driven low If SD_SYSTEST 3 DDIR bit 1 input mode direction no effect 0x0 R If SD_SYSTEST 3 DDIR bit 1 input mode direction returns the value on the DAT1 line low If SD_SYSTEST 3 DDIR bit 0 output mode direction returns 0 0x1 W If SD_SYSTEST 3 DDIR bit 0 output mode direction the DA...

Page 3397: ...ne is driven high If SD_SYSTEST 1 CDIR bit 1 input mode direction no effect 0x1 R If SD_SYSTEST 1 CDIR bit 1 input mode direction returns the value on the CMD line high If SD_SYSTEST 1 CDIR bit 0 output mode direction returns 1 1 CDIR R W 0h Control of the CMD pin direction 0x0 W The CMD line is an output host to card 0x0 R No action Returns 0 0x1 W The CMD line is an input card to host 0x1 R No a...

Page 3398: ...her edge sensitive with early de assertion on first access to SD_DATA register or late de assertion request remains active until last allowed data written into SD_DATA 0x0 Slave DMA edge sensitive 0x1 Slave DMA level sensitive 20 DMA_MnS R W 0h DMA Master or Slave selection When this bit is set and the controller is configured to use the DMA Ocp master interface is used to get datas from system us...

Page 3399: ... 2 CEN bit is set 15 PADEN R W 0h Control power for MMC lines This register is only useful when MMC PADs contain power saving mechanism to minimize its leakage power It works as a GPIO that directly control the ACTIVE pin of PADs Excepted for mmc_dat 1 the signal is also combine outside the module with the dedicated power control SD_CON 11 CTPL bit 0x0 ADPIDLE module pin is not forced it is automa...

Page 3400: ...mand MMC cards only This bit must be set to 1 when the next write access to the command register SD_CMD is for writing a MMC interrupt command CMD40 requiring the command timeout detection to be disabled for the command response 0x0 Command timeout enabled 0x1 Command timeout disabled 5 DW8 R W 0h 8 bit mode MMC select MMC cards only For SD SDIO cards this bit must be cleared to 0 For MMC card thi...

Page 3401: ...en 1 INIT R W 0h Send initialization stream all cards When this bit is set to 1 and the card is idle an initialization sequence is sent to the card An initialization sequence consists of setting the mmc_cmd line to 1 during 80 clock cycles The initialization sequence is mandatory but it is not required to do it through this bit this bit makes it easier Clock divider SD_SYSCTL 15 6 CLKD bits should...

Page 3402: ...CNT R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 18 25 SD_PWCNT Register Field Descriptions Bit Field Type Reset Description 31 16 Reserved R 0h 15 0 PWRCNT R W 0h Power counter register This register is used to introduce a delay between the PAD ACTIVE pin assertion and the command issued 0x0 No additional delay added 0x1 TCF delay card clock perio...

Page 3403: ...e after a transaction has stopped Read operations during transfers may return an invalid value The Host Driver shall initialize this register before starting a SDMA transaction After SDMA has stopped the next system address of the next contiguous data position can be read from this register The SDMA transfer waits at the every boundary specified by the Host SDMA Buffer Boundary in the Block Size r...

Page 3404: ...ction has stopped Read operations during transfers may return an invalid value and write operation will be ignored In suspend context the number of blocks yet to be transferred can be determined by reading this register When restoring transfer context prior to issuing a Resume command The local host shall restore the previously saved block count 0x0 Stop count 0x1 1 block 0x2 2 blocks 0xffff 65535...

Page 3405: ...tion is for a command index specifying stuff bits in arguments making a write unnecessary Figure 18 45 SD_ARG Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARG R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 18 28 SD_ARG Register Field Descriptions Bit Field Type Reset Description 31 0 ARG R W 0h Comman...

Page 3406: ... card In SYSTEST mode a write into SD_CMD register will not start a transfer Figure 18 46 SD_CMD Register 31 30 29 28 27 26 25 24 Reserved INDX R 0h R W 0h 23 22 21 20 19 18 17 16 CMD_TYPE DP CICE CCCE Reserved RSP_TYPE R W 0h R W 0h R W 0h R W 0h R 0h R W 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved MSBS DDIR Reserved ACEN BCE DE R 0h R W 0h R W 0h R 0h R W 0h R W 0h R W 0h LEG...

Page 3407: ...e 18 29 SD_CMD Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 3407 SPRUH73H October 2011 Revised April 2013 Multimedia Card MMC Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3408: ...D20 or ACMD20 0x15 CMD21 or ACMD21 0x16 CMD22 or ACMD22 0x17 CMD23 or ACMD23 0x18 CMD24 or ACMD24 0x19 CMD25 or ACMD25 0x1a CMD26 or ACMD26 0x1b CMD27 or ACMD27 0x1c CMD28 or ACMD28 0x1d CMD29 or ACMD29 0x1e CMD30 or ACMD30 0x1f CMD31 or ACMD31 0x20 CMD32 or ACMD32 0x21 CMD33 or ACMD33 0x22 CMD34 or ACMD34 0x23 CMD35 or ACMD35 0x24 CMD36 or ACMD36 0x25 CMD37 or ACMD37 0x26 CMD38 or ACMD38 0x27 CMD...

Page 3409: ...e set to 1 to enable index check on command response to compare the index field in the response against the index of the command If the index is not the same in the response as in the command it is reported as a command index error SD_STAT 19 CIE bit set to1 NoteThe CICE bit cannot be configured for an Auto CMD12 then index check is automatically checked when this command is issued 0x0 Index check...

Page 3410: ...t block The Host Driver shall not set this bit to issue commands that do not require CMD12 to stop data transfer In particular secure commands do not require CMD12 For CE ATA commands SD_CON 12 CEATA bit set to 1 auto CMD12 is useless therefore when this bit is set the mechanism to detect command completion signal named CCS interrupt is activated 0x0 Auto CMD12 disable 0x1 Auto CMD12 enable or CCS...

Page 3411: ...26 25 24 RSP1 R 0h 23 22 21 20 19 18 17 16 RSP1 R 0h 15 14 13 12 11 10 9 8 RSP0 R 0h 7 6 5 4 3 2 1 0 RSP0 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 18 30 SD_RSP10 Register Field Descriptions Bit Field Type Reset Description 31 16 RSP1 R 0h Command Response 31 16 15 0 RSP0 R 0h Command Response 15 0 3411 SPRUH73H October 2011 Revised April 2013 Mul...

Page 3412: ... R 0h 23 22 21 20 19 18 17 16 RSP3 R 0h 15 14 13 12 11 10 9 8 RSP2 R 0h 7 6 5 4 3 2 1 0 RSP2 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 18 31 SD_RSP32 Register Field Descriptions Bit Field Type Reset Description 31 16 RSP3 R 0h Command Response 63 48 15 0 RSP2 R 0h Command Response 47 32 3412 Multimedia Card MMC SPRUH73H October 2011 Revised April ...

Page 3413: ... R 0h 23 22 21 20 19 18 17 16 RSP5 R 0h 15 14 13 12 11 10 9 8 RSP4 R 0h 7 6 5 4 3 2 1 0 RSP4 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 18 32 SD_RSP54 Register Field Descriptions Bit Field Type Reset Description 31 16 RSP5 R 0h Command Response 95 80 15 0 RSP4 R 0h Command Response 79 64 3413 SPRUH73H October 2011 Revised April 2013 Multimedia Card...

Page 3414: ...R 0h 23 22 21 20 19 18 17 16 RSP7 R 0h 15 14 13 12 11 10 9 8 RSP6 R 0h 7 6 5 4 3 2 1 0 RSP6 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 18 33 SD_RSP76 Register Field Descriptions Bit Field Type Reset Description 31 16 RSP7 R 0h Command Response 127 112 15 0 RSP6 R 0h Command Response 111 96 3414 Multimedia Card MMC SPRUH73H October 2011 Revised Apri...

Page 3415: ...een 3 0 0001 1 byte Mbyteen 3 0 0010 1 byte Mbyteen 3 0 1100 2 bytes OK Mbyteen 3 0 0001 1 byte Mbyteen 3 0 0010 1 byte Mbyteen 3 0 0100 1 byte OK Mbyteen 3 0 0001 1 byte Mbyteen 3 0 0010 1 byte Mbyteen 3 0 1000 1 byte Bad Figure 18 51 SD_DATA Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 ...

Page 3416: ...time 0x0 The mmc_cmd line level is 0 0x1 The mmc_cmd line level is 1 23 20 DLEV R 0h mmc_dat 3 0 line signal level mmc_dat3 equal to or greater than bit 23 mmc_dat2 equal to or greater than bit 22 mmc_dat1 equal to or greater than bit 21 mmc_dat0 equal to or greater than bit 20 This status is used to check mmc_dat line level to recover from errors and for debugging This is especially useful in det...

Page 3417: ...m the card slot If SD_CON CDP is set to 1 the card has been inserted 0x1 If SD_CON CDP is cleared to 0 default the card has been inserted from the card slot If SD_CON CDP is set to 1 no card is detected The card may have been removed from the card slot 15 12 Reserved R 0h 11 BRE R 0h Buffer read enable This bit is used for non DMA read transfers It indicates that a complete block specified by SD_B...

Page 3418: ...as a result of a stop at gap request 0x0 mmc_dat line inactive 0x1 mmc_dat line active 1 DATI R 0h Command inhibit mmc_dat This status bit is generated if either mmc_dat line is active SD_PSTATE 2 DLA bit or Read transfer is active SD_PSTATE 9 RTA bit or when a command with busy is issued This bit prevents the local host to issue a command A change of this bit from 1 to 0 generates a transfer comp...

Page 3419: ...vents for out of band assertion Wake up is generated if the wake up feature is enabled SD_SYSCONFIG 2 ENAWAKEUP bit The write to this register is ignored when SD_CON 14 OBIE bit is not set 0x0 Disable wake up on out of band Interrupt 0x1 Enable wake up on out of band Interrupt 26 REM R W 0h Wake up event enable on SD card removal This bit enables wake up events for card removal assertion Wake up i...

Page 3420: ... has restarted that is mmc_dat line is active SD_PSTATE 2 DLA bit or transferring data SD_PSTATE 8 WTA bit The Stop at block gap request must be disabled SD_HCTL 16 SBGR bit 0 before setting this bit 0x0 No affect 0x1 Transfer restart 16 SBGR R W 0h Stop at block gap request This bit is used to stop executing a transaction at the next block gap The transfer can restart with a continue request SD_H...

Page 3421: ... 5 Reserved R 0h 4 3 DMAS R W 0h DMA Select One of the supported DMA modes can be selected The host driver shall check support of DMA modes by referencing the Capabilities register Use of selected DMA is determined by DMA Enable of the Transfer Mode register This register is only meaningful when MADMA_EN is set to 1 When MADMA_EN is cleared to 0 the bit field is read only and returned value is 0 0...

Page 3422: ...set and c Poll for 0 to identify reset is complete mmc_dat finite state machine in both clock domain are also reset These registers are cleared by the SD_SYSCTL 26 SRD bit SD_DATA SD_PSTATEBRE BWE RTA WTA DLA and DATI SD_HCTLSBGR and CR SD_STATBRR BWR BGE and TC Interconnect and MMC buffer data management is reinitialized Note If a soft reset is issued when an interrupt is asserted data may be los...

Page 3423: ...a reference clock frequency system dependant and the output clock frequency on the mmc_clk pin of either the memory card MMC SD or SDIO 0x0 Clock Ref bypass 0x1 Clock Ref bypass 0x2 Clock Ref 2 0x3 Clock Ref 3 0x3ff Clock Ref 1023 5 3 Reserved R 0h 2 CEN R W 0h Clock enable This bit controls if the clock is provided to the card or not 0x0 The clock is not provided to the card Clock frequency can b...

Page 3424: ...0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 18 38 SD_STAT Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 BADA R W 0h Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed During a read access to the data register SD_DATA ...

Page 3425: ...d bit position of read data on mmc_dat line or at the end position of the CRC status in write mode 0x0 W Status bit unchanged 0x0 R No error 0x1 W Status is cleared 0x1 R Data end bit error 21 DCRC R W 0h Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3 bit CRC status different of a position 010 to...

Page 3426: ...D_STAT 31 16 are set then this bit is set to 1 Therefore the host driver can efficiently test for an error by checking this bit first Writes to this bit are ignored 0x0 No interrupt 0x1 Error interrupt event s occurred 14 11 Reserved R 0h 10 BSR R W 0h Boot Status Received Interrupt This bit is set automatically when SD_CON BOOT is set 1 or 2 and a boot status is received on DAT 0 line This interr...

Page 3427: ... bit doesn t affect Card inserted present state SD_PSTATE CINS 0x0 W Status bit unchanged 0x0 R Card State stable or debouncing 0x1 W Status is cleared 0x1 R Card Removed 6 CINS R W 0h Card Insertion This bit is set automatically when SD_PSTATE CINS changes from 0 to 1 A clear of this bit doesn t affect Card inserted present state SD_PSTATE CINS 0x0 W Status bit unchanged 0x0 R Card State stable o...

Page 3428: ...W Status bit unchanged 0x0 R DMA Interrupt detected 0x1 W Status is cleared 0x1 R No DMA Interrupt 2 BGE R W 0h Block gap event When a stop at block gap is requested SD_HCTL 16 SBGR bit this bit is automatically set when transaction is stopped at the block gap during a read or write operation 0x0 W Status bit unchanged 0x0 R No block gap event 0x1 W Status is cleared 0x1 R Transaction stopped at b...

Page 3429: ... R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 18 39 SD_IE Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 BADA_ENABLE R W 0h Bad access to data space interrupt enable 0x0 Masked 0x1 Enabled 28 CERR_ENABLE R W 0h Card error interrupt enable 0x0 Masked 0x1 Enabled 27...

Page 3430: ...he interrupt routine does not remove the source of a card interrupt in the SDIO card the status bit is reasserted when this bit is set to 1 This bit must be set to 1 when entering in smart idle mode to enable system to identity wake up event and to allow controller to clear internal wake up source 0x0 Masked 0x1 Enabled 7 CREM_ENABLE R W 0h Card Removal interrupt Enable This bit must be set to 1 w...

Page 3431: ... gap event interrupt enable 0x0 Masked 0x1 Enabled 1 TC_ENABLE R W 0h Transfer completed interrupt enable 0x0 Masked 0x1 Enabled 0 CC_ENABLE R W 0h Command completed interrupt enable 0x0 Masked 0x1 Enabled 3431 SPRUH73H October 2011 Revised April 2013 Multimedia Card MMC Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3432: ...te R Read only W1toCl Write 1 to clear bit n value after reset Table 18 40 SD_ISE Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 BADA_SIGEN R W 0h Bad access to data space interrupt enable 0x0 Masked 0x1 Enabled 28 CERR_SIGEN R W 0h Card error interrupt signal status enable 0x0 Masked 0x1 Enabled 27 26 Reserved R 0h 25 ADMA_SIGEN R W 0h ADMA error signal status...

Page 3433: ...it mode if the interrupt routine does not remove the source of a card interrupt in the SDIO card the status bit is reasserted when this bit is set to 1 This bit must be set to 1 when entering in smart idle mode to enable system to identity wake up event and to allow controller to clear internal wake up source 0x0 Masked 0x1 Enabled 7 CREM_SIGEN R W 0h Card Removal signal status enable This bit mus...

Page 3434: ...event signal status enable 0x0 Masked 0x1 Enabled 1 TC_SIGEN R W 0h Transfer completed signal status enable 0x0 Masked 0x1 Enabled 0 CC_SIGEN R W 0h Command completed signal status enable 0x0 Masked 0x1 Enabled 3434 Multimedia Card MMC SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3435: ...D12 error If this bit is set to 1 it means that pending command is not executed due to auto CMD12 error ACEB ACCE ACTO or ACNE 0x0 Not error 0x1 Command not issued 6 5 Reserved R 0h 4 ACIE R 0h Auto CMD12 index error This bit is a set to 1 when response index differs from corresponding command auto CMD12 index previously emitted This bit depends on the command index check enable SD_CMD 20 CICE bit...

Page 3436: ...MD12 not executed This bit is set to 1 if multiple block data transfer command has started and if an error occurs in command before auto CMD12 starts 0x0 Auto CMD12 executed 0x1 Auto CMD12 not executed 3436 Multimedia Card MMC SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3437: ...ss descriptor mode and is connected to 64 bit address system bus 0x0 R 32 bit System bus address 0x1 R 64 bit System bus address 27 Reserved R 0h 26 VS18 R W 0h Voltage support 1 8 V Initialization of this register via a write access to this register depends on the system capabilities The host driver shall not modify this register after the initialization This register is only reinitialized by a h...

Page 3438: ...and can supply an up to 52 MHz clock to the card 0x0 DMA not supported 0x1 DMA supported 20 Reserved R 0h 19 AD2S R 0h This bit indicates whether the Host Controller is capable of using ADMA2 It depends on setting of generic parameter MADMA_EN 0x0 ADMA2 supported 0x1 ADMA2 not supported 18 Reserved R 0h 17 16 MBL R 0h Maximum block length This value indicates the maximum block size that the host d...

Page 3439: ...19 18 17 16 CUR_1V8 R W 0h 15 14 13 12 11 10 9 8 CUR_3V0 R W 0h 7 6 5 4 3 2 1 0 CUR_3V3 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 18 43 SD_CUR_CAPA Register Field Descriptions Bit Field Type Reset Description 31 24 Reserved R 0h 23 16 CUR_1V8 R W 0h Maximum current for 1 8 V 0x0 R The maximum current capability for this voltage is not available ...

Page 3440: ...R Read only W1toCl Write 1 to clear bit n value after reset Table 18 44 SD_FE Register Field Descriptions Bit Field Type Reset Description 31 30 Reserved R 0h 29 FE_BADA W 0h Force Event Bad access to data space 0x0 No effect no interrupt 0x1 Interrupt forced 28 FE_CERR W 0h Force Event Card error 0x0 No effect no interrupt 0x1 Interrupt forced 27 26 Reserved R 0h 25 FE_ADMAE W 0h Force Event ADMA...

Page 3441: ... No effect no interrupt 0x1 Interrupt forced 6 5 Reserved R 0h 4 FE_ACIE W 0h Force Event Auto CMD12 index error 0x0 No effect no interrupt 0x1 Interrupt forced 3 FE_ACEB W 0h Force Event Auto CMD12 end bit error 0x0 No effect no interrupt 0x1 Interrupt forced 2 FE_ACCE W 0h Force Event Auto CMD12 CRC error 0x0 No effect no interrupt 0x1 Interrupt forced 1 FE_ACTO W 0h Force Event Auto CMD12 timeo...

Page 3442: ...e ADMA Error State indicates that an error occurs at ST_FDS state The Host Driver may find that the Valid bit is not set in the error descriptor Figure 18 62 SD_ADMAES Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved LME AES R 0h W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit...

Page 3443: ...ead Write R Read only W1toCl Write 1 to clear bit n value after reset Table 18 46 SD_ADMASAL Register Field Descriptions Bit Field Type Reset Description 31 0 ADMA_A32B R W 0h The ADMA increments this register address which points to the next line whenever fetching a Descriptor line When the ADMA Error Interrupt is generated this register holds the valid Descriptor address depending on the ADMA st...

Page 3444: ...21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADMA_A32B R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 18 47 SD_ADMASAH Register Field Descriptions Bit Field Type Reset Description 31 0 ADMA_A32B R W 0h ADMA_A32B 3444 Multimedia Card MMC SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instrum...

Page 3445: ..._REV Register Field Descriptions Bit Field Type Reset Description 31 24 VREV R 31h Vendor Version Number Bits 7 4 is the major revision bits 3 0 is the minor revision Examples 10h for 1 0 21h for 2 1 23 16 SREV R 01h Specification Version Number This status indicates the Standard SD Host Controller Specification Version The upper and lower 4 bits indicate the version 0x0 SD Host Specification Vers...

Page 3446: ...evice Topic Page 19 1 Introduction 3447 19 2 Integration 3449 19 3 Functional Description 3453 19 4 UART IrDA CIR Basic Programming Model 3496 19 5 UART Registers 3505 3446 Universal Asynchronous Receiver Transmitter UART SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3447: ...um infrared MIR and fast infrared FIR communications very fast infrared VFIR is not supported Frame formatting addition of variable xBOF characters and EOF characters Uplink downlink CRC generation detection Asynchronous transparency automatic insertion of break character 8 entry status FIFO with selectable trigger levels available to monitor frame length and frame errors Framing error cyclic redu...

Page 3448: ... not pinned out Full modem control on UART2 5 DCD DSR DTR RI not pinned out Device wake up on UART1 5 Wake up not supported no SWake connection 3448 Universal Asynchronous Receiver Transmitter UART SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3449: ...5 UART0 provides wakeup capability Only UART 1 provides full modem control signals All UARTs support IrDA and CIR modes and RTS CTS flow control subject to pin muxing configuration Figure 19 1 shows an example of system connectivity using UART communication with hardware handshake Figure 19 1 UART IrDA Module UART Application Figure 19 2 shows an example of system connectivity using infrared commu...

Page 3450: ...URXEVTx Physical Address L4 Peripheral slave port 19 2 2 UART Clock and Reset Management The UART modules use separate functional and bus interface clocks Table 19 4 UART0 Clock Signals Clock Signal Max Freq Reference Source Comments CLK 100 MHz CORE_CLKOUTM4 2 pd_wkup_l4_wkup_gclk Interface clock From PRCM FCLK 48 MHz PER_CLKOUTM2 4 pd_wkup_uart0_gfclk Functional clock From PRCM Table 19 5 UART1 ...

Page 3451: ...13 1 0 16 For IrDA operation the internal functional clock divisor allows generation of SIR MIR or FIR baud rates as shown in Table 19 7 Table 19 7 IrDA Mode Baud and Error Rates Baud rate IR mode Encoding Divisor Error 2400 SIR 3 16 1250 0 9600 SIR 3 16 312 0 16 19200 SIR 3 16 156 0 16 38400 SIR 3 16 78 0 16 57600 SIR 3 16 52 0 16 115200 SIR 3 16 26 0 16 576000 MIR 1 4 2 0 1152000 MIR 1 4 1 0 400...

Page 3452: ... Data Set Ready UARTx_DCDn 1 I UART Data Carrier Detect UARTx_RIN 1 1 UART Ring Indicator 1 UART1 only The UART module can operate in three different modes based on the MODE_SELECT bits The signal muxing based on these mode bits is shown in Table 19 9 Table 19 9 UART Muxing Control UARTx_TXD IRTX UARTx_RXD IRRX RCRX UARTx_RTSn SD UARTx_CTSn Mode RCTX Function Function Function Function TXD RXD RTS...

Page 3453: ... clocks Data formatting Each function uses its own state machine that is responsible for the transition between FIFO data and frame data associated with it Interrupt management Different interrupt types are generated depending on the chosen function UART mode interrupts Seven interrupts prioritized in six different levels IrDA mode interrupts Eight interrupts The interrupt line is activated when a...

Page 3454: ...re information see Clock Domain Module Attributes in Chapter 8 Power Reset and Clock Management The idle and wake up processes use a handshake protocol between the PRCM and the UART for a description of the protocol see Module Level Clock Management in Chapter 8 Power Reset and Clock Management The UARTi UART_SYSC 4 3 IDLEMODE bit field controls UART idle mode 19 3 3 Software Reset The UARTi UART_...

Page 3455: ...vice The UART supports an idle req idle ack handshaking protocol used at the system level to shut down the UART clocks in a clean and controlled manner and to switch the UART from interrupt generation mode to wake up generation mode for unmasked events see the UARTi UART_SYSC 2 ENAWAKEUP bit and the UARTi UART_WER register For more information see Module Level Clock Management in Chapter 8 Power R...

Page 3456: ...entification register UARTi UART_IIR sets the UARTi UART_IIR 0 IT_PENDING bit to 0 to indicate that an interrupt is pending and indicates the type of interrupt through the UARTi UART_IIR 5 1 bit field Table 19 11 summarizes the interrupt control functions Table 19 11 UART Mode Interrupts UART_IIR 5 0 Priority Level Interrupt Type Interrupt Source Interrupt Reset Method 000001 None None None None 0...

Page 3457: ...N Wake Up interface implementation in IrDA mode is based on the UARTi_SIDLEACK low to high transition instead of the UARTi_SIDLEACK state This does not ensure wake up event generation as expected when configured in smart idle mode and the system wakes up for a short period 19 3 5 3 IrDA Mode Interrupt Management 19 3 5 3 1 IrDA Interrupts The IrDA function generates interrupts All interrupts can b...

Page 3458: ...entification register UARTi UART_IIR UART IrDA and CIR modes have different interrupts in the UART IrDA CIR module and therefore different UARTi UART_IER and UARTi UART_IIR mappings depending on the selected mode Table 19 13 lists the interrupt modes to be maintained In CIR mode the sole purpose of the UARTi UART_IIR 5 bit is to indicate that the last bit of infrared data was passed to the uart_ct...

Page 3459: ...eading the UARTi UART_SSR 0 TX_FIFO_FULL bit at 1 means the FIFO is full The UARTi UART_TLR register controls the FIFO trigger level which enables DMA and interrupt generation After reset transmit TX and receive RX FIFOs are disabled thus the trigger level is the default value of 1 byte Figure 19 4 shows the FIFO management registers NOTE Data in the UARTi UART_RHR register is not overwritten when...

Page 3460: ...rom 1 to 63 characters with a granularity of 1 character Note The combination of RX_FIFO_TRIG_DMA 0x0 and RX_FIFO_TRIG 0x0 all zeros is not supported minimum of one character required All zeros result in unpredictable behavior The receive threshold is programmed using the UARTi UART_TCR 7 4 RX_FIFO_TRIG_START and UARTi UART_TCR 3 0 RX_FIFO_TRIG_HALT bit fields Trigger levels from 0 to 60 bytes are...

Page 3461: ...is reached The interrupt signals instruct the MPU to transfer data to the destination from the UART in receive mode and or from any source to the UART FIFO in transmit mode When UART flow control is enabled with interrupt capabilities the UART flow control FIFO threshold the UARTi UART_TCR 3 0 RX_FIFO_TRIG_HALT bit field must be greater than or equal to the RX FIFO threshold Figure 19 5 shows the ...

Page 3462: ...cked by polling the line status register UARTi UART_LSR This mode is an alternative to the FIFO interrupt mode of operation in which the status of the receiver and transmitter is automatically determined by sending interrupts to the MPU 19 3 6 4 FIFO DMA Mode Operation Although DMA operation includes four modes DMA modes 0 through 3 assume that mode 1 is used Mode 2 and mode 3 are legacy modes tha...

Page 3463: ...ignals associated with DMA operation are not active Depending on UART_MDR3 2 SET_DMA_TX_THRESHOLD the threshold can be programmed different ways SET_TX_DMA_THRESHOLD 1 The threshold value will be the value of the UART_TX_DMA_THRESHOLD register If SET_TX_DMA_THRESHOLD TX trigger spaces 64 then the default method of threshold is used threshold value TX FIFO size SET_TX_DMA_THRESHOLD 0 The threshold ...

Page 3464: ...reshold can be programmed in a number of ways Figure 19 8 shows a DMA transfer operating with a space setting of 56 that can arise from using the auto settings in the UARTi UART_FCR 5 4 TX_FIFO_TRIG bit field or the UARTi UART_TLR 3 0 TX_FIFO_TRIG_DMA bit field concatenated with the TX_FIFO_TRIG bit field The setting of 56 spaces in the UART IrDA CIR module must correlate with the settings of the ...

Page 3465: ...t buffer see Figure 19 10 The buffer is filled faster than the baud rate at which data is transmitted to the TX pin Eventually the buffer is completely full and the DMA operations stop transferring data to the transmit buffer On two occasions the buffer holds the maximum amount of data words shortly after this the DMA is disabled to show the slower transmission of the data words to the TX pin Even...

Page 3466: ...rations stop transferring data to the transmit buffer When the buffer is emptied to the threshold level by transmission the DMA operation activates again to fill the buffer with 8 bytes Eventually the buffer is emptied at the rate specified by the baud rate settings of the UART_DLL and UART_DLH registers If the selected threshold level plus the trigger level exceed the maximum buffer size the orig...

Page 3467: ...e 19 13 shows DMA reception Figure 19 13 DMA Reception 1 Enable the reception 2 Received data are put in the RX FIFO 3 Data are transferred from the RX FIFO to the device memory by the DMA a At each received byte the RX FIFO trigger level one character is reached and a DMA request is generated b An element 1 byte is transferred from the RX FIFO to the SDRAM at each DMA request DMA element synchron...

Page 3468: ...or UART_MCR 6 0x0 TCR_TLR UART_EFR 4 0x1 and UART_MCR 6 0x1 Table 19 18 Subconfiguration Mode B Summary Mode Condition TCR_TLR UART_EFR 4 0x1 and UART_MCR 6 0x1 XOFF UART_EFR 4 0x0 or UART_MCR 6 0x0 Table 19 19 Suboperational Mode Summary Mode Condition MSR_SPR UART_EFR 4 0x0 or UART_MCR 6 0x0 TCR_TLR UART_EFR 4 0x1 and UART_MCR 6 0x1 19 3 7 1 3 Registers Available for the Register Access Modes Ta...

Page 3469: ...54 UART_SYSC UART_SYSC UART_SYSC UART_SYSC UART_SYSC UART_SYSC 0x058 UART_SYSS UART_SYSS UART_SYSS 0x05C UART_WER UART_WER UART_WER UART_WER UART_WER UART_WER 0x060 UART_CFPS UART_CFPS UART_CFPS UART_CFPS UART_CFPS UART_CFPS 0x064 UART_RXFIFO UART_RXFIFO_ UART_RXFIFO_LVL UART_RXFIFO_L UART_RXFIFO_LV UART_RXFIFO _LVL LVL VL L _LVL 0x068 UART_TXFIFO UART_TXFIFO_ UART_TXFIFO_LVL UART_TXFIFO_L UART_TX...

Page 3470: ...ON2_ADD UART_XON2_AD UART_LSR UART RT R2 DR2 0x018 UART_MSR U UART_TCR UART_XOFF1 UAR UART_XOFF1 U UART_MSR UART UART_TCR ART_TCR T_TCR ART_TCR _TCR 0x01C UART_TLR UA UART_TLR UA UART_TLR UART_ UART_TLR UAR UART_TLR UART_ UART_TLR UA RT_SPR RT_SPR XOFF2 T_XOFF2 SPR RT_SPR 0x020 UART_MDR1 UART_MDR1 2 UART_MDR1 2 0 UART_MDR1 2 0 UART_MDR1 2 0 UART_MDR1 2 0 0 0x024 UART_MDR2 UART_MDR2 UART_MDR2 UART_...

Page 3471: ...DLL UART_DLL UART_DLL UART_DLL UART_RHR UART_THR 0x004 UART_DLH UART_DLH UART_DLH UART_DLH UART_IER IrDA UART_IER IrD A 0x008 UART_IIR UART_FCR UART_EFR 4 UART_EFR 4 UART_IIR IrDA UART_FCR Ir DA 0x00C UART_LCR 7 UART_LCR 7 UART_LCR 7 UART_LCR 7 UART_LCR 7 UART_LCR 7 0x010 UART_XON1_ADD UART_XON1_AD R1 DR1 0x014 UART_LSR IrD UART_XON2_ADD UART_XON2_AD UART_LSR IrDA A R2 DR2 0x018 UART_MSR U UART_TC...

Page 3472: ... UART_TX_DMA UART_TX_DMA_TH UART_TX_DMA_ UART_TX_DMA_T UART_TX_DM A_THRESHOL _THRESHOLD RESHOLD THRESHOLD HRESHOLD A_THRESHOL D D 19 3 7 2 3 Registers Available for the CIR Function Only the registers listed in Table 19 24 are used for the CIR function Table 19 24 CIR Mode Register Overview 1 2 Address Registers Offset Configuration Mode A Configuration Mode B Operational Mode Read Write Read Writ...

Page 3473: ...R2 UART_ISR2 UART_ISR2 0x074 UART_FREQ_ UART_FREQ_S UART_FREQ_SEL UART_FREQ_SE UART_FREQ_SEL UART_FREQ_ SEL EL L SEL 0x080 UART_MDR3 UART_MDR3 UART_MDR3 UART_MDR3 UART_MDR3 UART_MDR3 0x084 UART_TX_DM UART_TX_DMA UART_TX_DMA_TH UART_TX_DMA_ UART_TX_DMA_T UART_TX_DM A_THRESHOL _THRESHOLD RESHOLD THRESHOLD HRESHOLD A_THRESHOL D D 19 3 8 Protocol Formatting The UART IRDA module can operate in seven di...

Page 3474: ...ntrol to manage transmission and reception Hardware flow control significantly reduces software overhead and increases system efficiency by automatically controlling serial data flow using the RTS output and CTS input signals Software flow control automatically controls data flow by using programmable XON XOFF characters The UART modem module is enhanced with an autobauding functionality which in ...

Page 3475: ...46 Mbps 0 16 3 6884 Mbps 13x 1 0x00 0x01 3 6923 Mbps 0 16 19 3 8 1 3 UART Data Formatting The UART can use hardware flow control to manage transmission and reception Hardware flow control significantly reduces software overhead and increases system efficiency by automatically controlling serial data flow using the RTS output and CTS input signals The UART is enhanced with the autobauding function ...

Page 3476: ...signal Auto CTS The transmitter circuitry checks uarti_cts before sending the next data byte When uarti_cts is active the transmitter sends the next byte To stop the transmitter from sending the next byte uarti_cts must be deasserted before the middle of the last stop bit currently sent The auto CTS function reduces interrupts to the host system When auto CTS flow control is enabled the uarti_cts ...

Page 3477: ...occurs while receiving a software flow control character this character is treated as normal data and is written to the RX FIFO When XON any and special character detect are disabled and software flow control is enabled no valid XON or XOFF characters are written to the RX FIFO For example when UARTi UART_EFR 1 0 0x2 if XON1 and XOFF1 characters are received they are not written to the RX FIFO Whe...

Page 3478: ...r or lower case sequence is detected The UARTi UART_UASR register reflects the correct settings for the baud rate detected Interrupt activity can continue in this fashion when a subsequent character is received Therefore it is recommended that the software enable the RHR interrupt when using the autobaud mode The following settings are detected in autobaud mode with a module clock of 48 MHz Speed ...

Page 3479: ...ng receive occurs if the RX state machine tries to write data into the RX FIFO when it is already full When overrun occurs the device interrupts the MPU with the UARTi UART_IIR 5 1 IT_TYPE bit field set to 0x3 receiver line status error and discards the remaining portion of the frame Overrun also causes an internal flag to be set which disables further reception Before the next frame can be receiv...

Page 3480: ...ter the 0x7D character The SIR receive state machine recovers the receive clock removes the start flags removes any transparency from the incoming data and determines frame boundary with reception of the stop flag It also checks for errors such as frame abort 0x7D character followed immediately by a 0xC1 stop flag without transparency CRC error and frame length error At the end of a frame receptio...

Page 3481: ...ding flag It is possible to abort a transmission frame by programming the ABORTEN bit of the Auxiliary Control Register ACREG 1 When this bit is set to 1 0x7D and 0xC1 are transmitted and the frame is not terminated with CRC or stop flags The receiver treats a frame as an aborted frame when a 0x7D character followed immediately by a 0xC1 character has been received without transparency 19 3 8 2 1 ...

Page 3482: ...cting address1 checking is done by setting EFR 0 to 1 address2 checking is done by setting EFR 1 to 1 Setting EFR 1 0 to 0 disables all address checking operations If both bits are set then the incoming frame is checked for both private and public addresses If address checking is disabled then all received frames are written into the reception FIFO 19 3 8 2 1 8 SIR Free Format Mode To allow comple...

Page 3483: ... also looks for five consecutive values of 1 in the frame data and automatically inserts a zero after five consecutive values of one this is called bit stuffing On receive the MIR receive state machine recovers the receive clock removes the start flags de stuffs the incoming data and determines frame boundary with reception of the stop flag It also checks for errors such as frame abort CRC error o...

Page 3484: ...But when MDR1 6 0 the transmission of the SIP depends on the SENDSIP bit of the Auxiliary Control Register ACREG 3 The system LH can set ACREG 3 at least once every 500ms The advantage of this approach over the default approach is that the TX state machine does not need to send the SIP at the end of each frame which may reduce the overhead required 19 3 8 2 3 FIR Mode In fast infrared mode FIR dat...

Page 3485: ...IR RX circuitry is automatically disabled by hardware See bit 5 in Section 19 5 1 26 Auxiliary Control Register for a description of the logical operation Note This applies to all three modes of SIR MIR and FIR 19 3 8 2 4 IrDA Clock Generation Baud Generator The IrDA function contains a programmable baud generator and a set of fixed dividers that divide the 48 MHz clock input down to the expected ...

Page 3486: ...the output of the transceiver has the same polarity at module level By default the uarti_rx_irrx pin is inverted because most transceivers invert the IR receive pin 19 3 8 2 6 2 IrDA Reception Control The module can transmit and receive data but when the device is transmitting the IR RX circuitry is automatically disabled by hardware Operation of the uarti_rx_irrx input can be disabled by the UART...

Page 3487: ...a maximum of eight reads is required 19 3 8 2 6 7 Underrun During Transmission Underrun during transmission occurs when the TX FIFO is empty before the end of the frame is transmitted When underrun occurs the device closes the frame with end flags but attaches an incorrect CRC value The receiving device detects a CRC error and discards the frame it can then ask for a retransmission Underrun also c...

Page 3488: ...transmit mode 19 3 8 2 7 3 SIR Free Format Programming The SIR FF mode is selected by setting the module in the UART mode UARTi UART_MDR1 2 0 MODE_SELECT 0x0 and the UARTi UART_MDR2 3 UART_PULSE bit to 1 to allow pulse shaping Because the bit format stays the same some UART mode configuration registers must be set at specific values UARTi UART_LCR 1 0 CHAR_LENGTH bit field 0x3 8 data bits UARTi UA...

Page 3489: ...ation encoding whereas European manufacturers favor the use of bi phase encoding The CIR mode is designed to use a completely flexible free format encoding where a digit 1 from the TX RX FIFO is to be transmitted received as a modulated pulse with duration T Equally a 0 is to be transmitted received as a blank duration T The protocol of the data is to be constructed and deciphered by the host CPU ...

Page 3490: ...elay in the transmission of the same command would be detected by the use of the toggle bit The address bits define the machine or device that the Infrared transmission is intended for and the command defines the operation To accommodate an extended RC5 format the S2 bit is replaced by a further command bit C6 that allows the command range to increase to 7 bits This format is known as the extended...

Page 3491: ...was provided to illustrate the consideration required to employ different encoding methods for different industry standard protocols The user should refer to industry standard documentation for specific methods of encoding and protocol usage 19 3 8 3 2 CIR Mode Operation Depending on the encoding method variable pulse distance bi phase the LH should develop a data structure that combines the 1 and...

Page 3492: ...stopping the reception If the value set in the EBLR register is different than 0 this features is enabled and count a number of bit received at 0 When the counter achieves the value defined in the EBLR register the reception is automatically stopped and RX_STOP_IT IIR 2 is set When a 1 is detected on the RCRX pin the reception is automatically enabled Note There s a limitation when receiving data ...

Page 3493: ...MHz 12 real value of BAUD multiple MODfreq Effective frequency of the modulation MHz Example For a targeted modulation frequency of 36 kHz the CFPS value must be set to 111 in decimal which provide an modulation frequency of 36 04 kHz Note The CFPS register is to start with a reset value of 105 decimal which translates to a frequency of 38 1 kHz The duty cycle of these pulses is user defined by th...

Page 3494: ...itting continuous bytes back to back no delay is inserted between two transmitted bytes Note The CIR RX demodulation can be bypassed by setting the MDR3 0 register bit This bit will not affect the transmission modulation 3494 Universal Asynchronous Receiver Transmitter UART SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3495: ...m clock frequency 48 MHz 16 real value of BAUD multiple Tfreq Effective frequency of the T pulse MHz In an example case using a variable pulse duration definitions Figure 19 33 Variable Pulse Duration Definitions For a logical 1 the pulse duration is equal to 2T and for a logical 0 it s equal to 4T If T 0 56 ms the value coded into the DLH and DLL register must be 1680 in decimal 3495 SPRUH73H Oct...

Page 3496: ...ET bit to 1 2 Wait for the end of the reset operation Poll the UARTi UART_SYSS 0 RESETDONE bit until it equals 1 19 4 1 1 2 FIFOs and DMA Settings To enable and configure the receive and transmit FIFOs and program the DMA mode perform the following steps 1 Switch to register configuration mode B to access the UARTi UART_EFR register a Save the current UARTi UART_LCR register value b Set the UARTi ...

Page 3497: ... 3 0 TX_FIFO_TRIG_DMA UARTi UART_SCR 6 TX_TRIG_GRANU1 Triggers are used to generate interrupt and DMA requests See Section 19 3 6 1 2 Receive FIFO Trigger to choose the following values UARTi UART_FCR 7 6 RX_FIFO_TRIG UARTi UART_TLR 7 4 RX_FIFO_TRIG_DMA UARTi UART_SCR 7 RX_TRIG_GRANU1 DMA mode enables DMA requests See Section 19 3 6 4 FIFO DMA Mode Operation to choose the following values UARTi UA...

Page 3498: ...mode B to access the UARTi UART_EFR register Set the UARTi UART_LCR register value to 0x00BF 11 Restore the UARTi UART_EFR 4 ENHANCED_EN value saved in Step 3a 12 Load the new protocol formatting parity stop bit character length and switch to register operational mode Set the UARTi UART_LCR 7 DIV_EN bit to 0 Set the UARTi UART_LCR 6 BREAK_EN bit to 0 Set the following bits to the desired values UA...

Page 3499: ... the UARTi UART_TCR register part 2 of 2 a Save the UARTi UART_EFR 4 ENHANCED_EN value b Set the UARTi UART_EFR 4 ENHANCED_EN bit to 1 5 Load the new start and halt trigger values for hardware flow control Set the following bits to the desired values UARTi UART_TCR 7 4 AUTO_RTS_START UARTi UART_TCR 3 0 AUTO_RTS_HALT 6 Enable or disable receive and transmit hardware flow control mode and restore th...

Page 3500: ...ister configuration mode B to access the UARTi UART_EFR register Set the UARTi UART_LCR register value to 0x00BF 8 Load the new start and halt trigger values for software flow control Set the following bits to the desired values UARTi UART_TCR 7 4 AUTO_RTS_START UARTi UART_TCR 3 0 AUTO_RTS_HALT 9 Enable or disable special character function and load the new software flow control mode and restore t...

Page 3501: ...sic Programming Model UARTi UART_XOFF2 7 0 XOFF_WORD2 3501 SPRUH73H October 2011 Revised April 2013 Universal Asynchronous Receiver Transmitter UART Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3502: ...nd 7 bit word length 1 Disable the UART before accessing the UARTi UART_DLL and UARTi UART_DLH registers Set the UART_MDR1 2 0 MODE_SELECT bit field to 0x7 2 Grant access to the UART_EFR register UARTi UART_LCR 0xBF 3 Enable the enhanced features the UART_EFR 4 ENAHNCED_EN bit 1 Set the UARTi UART_EFR register value to 0x10 4 Grant access to the UART_DLL and UART_DLH registers the UART_LCR 7 DIV_E...

Page 3503: ...ram the module to transmit an IrDA 60 byte frame with no parity baud rate 1 152 Mpbs and FIFOs disabled 1 Disable the UART before accessing the UARTi UART_DLL and UARTi UART_DLH registers Set the UARTi UART_MDR1 2 0 MODE_SELECT bit field to 0x7 2 Grant access to the UART_DLL and UART_DLH registers UART_LCR 7 DIV_EN bit 1 UARTi UART_LCR 0x80 Data format is unaffected by the use and settings of the ...

Page 3504: ...rogramming model explains how to program the module to transmit an IrDA 4 byte frame with no parity baud rate 4 Mbps FIFOs enabled and 8 bit word length 1 Disable the UART before accessing the UARTi UART_DLL and UARTi UART_DLH registers Set the UARTi UART_MDR1 2 0 MODE_SELECT bit field to 0x7 2 Grant access to EFR_REG UARTi UART_LCR 0xBF 3 Enable the enhanced features EFR_REG 4 ENAHNCED_EN 0x1 UAR...

Page 3505: ...SR TXFLL 2Ch RESUME TXFLH RESUME TXFLH RESUME TXFLH 30h SFREGL RXFLL SFREGL RXFLL SFREGL RXFLL 34h SFREGH RXFLH SFREGH RXFLH SFREGH RXFLH 38h BLR BLR UASR UASR 3Ch ACREG ACREG 40h SCR SCR SCR SCR SCR SCR 44h SSR SSR 2 SSR SSR 2 SSR SSR 2 48h EBLR EBLR 50h MVR MVR MVR 54h SYSC SYSC SYSC SYSC SYSC SYSC 58h SYSS SYSS SYSS 5Ch WER WER WER WER WER WER 60h CFPS CFPS CFPS CFPS CFPS CFPS 64h RXFIFO_LVL RX...

Page 3506: ...UART Registers www ti com 3506 Universal Asynchronous Receiver Transmitter UART SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3507: ...Reserved 0 Reserved 7 0 RHR 0 FFh Receive holding register 19 5 1 2 Transmit Holding Register THR The transmitter section consists of the transmit holding register and the transmit shift register The transmit holding register is a 64 byte FIFO The MPU writes data to the THR The data is placed in the transmit shift register where it is shifted out serially on the TX output If the FIFO is disabled l...

Page 3508: ...iption 15 8 Reserved 0 Reserved 7 CTSIT Can be written only when EFR 4 1 0 Disables the CTS interrupt 1 Enables the CTS interrupt 6 RTSIT Can be written only when EFR 4 1 0 Disables the RTS interrupt 1 Enables the RTS interrupt 5 XOFFIT Can be written only when EFR 4 1 0 Disables the XOFF interrupt 1 Enables the XOFF interrupt 4 SLEEPMODE Can be only written when EFR 4 1 0 Disables sleep mode 1 En...

Page 3509: ...d Write R Read only n value after reset Table 19 33 IrDA Interrupt Enable Register IER Field Descriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 EOFIT 0 Disables the received EOF interrupt 1 Enables the received EOF interrupt 6 LINESTSIT 0 Disables the receiver line status interrupt 1 Enables the receiver line status interrupt 5 TXSTATUSIT 0 Disables the TX status interrupt 1 Enabl...

Page 3510: ...ed R 0 7 6 5 4 3 2 1 0 Reserved TXSTATUSIT Reserved RXOVERRUNIT RXSTOPIT THRIT RHRIT R 0 R W 0 R 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 19 34 CIR Interrupt Enable Register IER Field Descriptions Bit Field Value Description 15 6 Reserved 0 Reserved 5 TXSTATUSIT 0 Disables the TX status interrupt 1 Enables the TX status interrupt 4 Reserved 0 Reserved 3...

Page 3511: ...ld Descriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 6 FCR_MIRROR 0 3h Mirror the contents of FCR 0 on both bits 5 1 IT_TYPE 0 1Fh Seven possible interrupts in UART mode other combinations never occur 0 Modem interrupt Priority 4 1h THR interrupt Priority 3 2h RHR interrupt Priority 2 3h Receiver line status error Priority 1 4h 5h Reserved 6h Rx timeout Priority 2 7h Reserved 8h ...

Page 3512: ...scriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 EOF_IT 0 Received EOF interrupt inactive 1 Received EOF interrupt active 6 LINE_STS_IT 0 Receiver line status interrupt inactive 1 Receiver line status interrupt active 5 TX_STATUS_IT 0 TX status interrupt inactive 1 TX status interrupt active 4 STS_FIFO_IT 0 Status FIFO trigger level interrupt inactive 1 Status FIFO trigger level i...

Page 3513: ... 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 19 37 CIR Interrupt Identification Register IIR Field Descriptions Bit Field Value Description 15 6 Reserved 0 Reserved 5 TXSTATUSIT 0 TX status interrupt inactive 1 TX status interrupt active 4 Reserved 0 Reserved 3 RXOEIT 0 RX overrun interrupt inactive 1 RX overrun interrupt active 2 RXSTOPIT 0 Receive stop interrupt is ...

Page 3514: ...RIG is not considered If SCR 6 1 TX_FIFO_TRIG is 2 LSB of the trigger space 1 to 63 on 6 bits with a granularity of 1 If SCR 6 0 and TLR 3 0 0000 0 8 spaces 1h 16 spaces 2h 32 spaces 3h 56 spaces 3 DMA_MODE Can be changed only when the baud clock is not running DLL and DLH cleared to 0 If SCR 0 0 this register is considered 0 DMA_MODE 0 No DMA 1 DMA_MODE 1 UART_NDMA_REQ 0 in TX UART_NDMA_REQ 1 in ...

Page 3515: ... as long as LCR 6 1 0 Normal operating condition 1 Forces the transmitter output to go low to alert the communication terminal 5 PARITY_TYPE2 If LCR 3 1 0 If LCR 5 0 LCR 4 selects the forced parity format 1 If LCR 5 1 and LCR 4 0 the parity bit is forced to 1 in the transmitted and received data 1 If LCR 5 1 and LCR 4 1 the parity bit is forced to 0 in the transmitted and received data 4 PARITY_TY...

Page 3516: ...y function 4 LOOPBACKEN Loopback mode enable 0 Normal operating mode 1 Enable local loopback mode internal In this mode the MCR 3 0 signals are looped back into MSR 7 4 The transmit output is looped back to the receive input internally 3 CDSTSCH 0 In loopback mode forces DCD input high and IRQ outputs to INACTIVE state 1 In loopback mode forces DCD input low and IRQ outputs to INACTIVE state 2 RIS...

Page 3517: ...ion 1 At least one parity error framing error or break indication in the RX FIFO Bit 7 is cleared when no errors are present in the RX FIFO 6 TXSRE 0 Transmitter hold TX FIFO and shift registers are not empty 1 Transmitter hold TX FIFO and shift registers are empty 5 TXFIFOE 0 Transmit hold register TX FIFO is not empty 1 Transmit hold register TX FIFO is empty The transmission is not necessarily ...

Page 3518: ...o be read 1 The RX FIFO RHR contains the last byte of the frame to be read This bit is set to 1 only when the last byte of a frame is available to be read It is used to determine the frame boundary It is cleared on a single read of the LSR register 4 FRAME_TOO_LONG 0 No frame too long error in frame 1 Frame too long error in the frame at the top of the status FIFO next character to be read This bi...

Page 3519: ...EMPTY 0 Transmit holding register TX FIFO is not empty 1 Transmit hold register TX FIFO is empty The transmission is not necessarily completed 6 Reserved 0 Reserved 5 RXSTOP The RXSTOP is generated based on the value set in the BOF Length register EBLR 0 Reception is on going or waiting for a new frame 1 Reception is completed It is cleared on a single read of the LSR register 4 1 Reserved 0 Reser...

Page 3520: ... of the DCD input In loopback mode it is equivalent to MCR 3 6 NRI_STS This bit is the complement of the RI input In loopback mode it is equivalent to MCR 2 5 NDSR_STS This bit is the complement of the DSR input In loopback mode it is equivalent to MCR 0 4 NCTS_STS This bit is the complement of the CTS input In loopback mode it is equivalent to MCR 1 3 DCD_STS 0 No change 1 Indicates that DCD inpu...

Page 3521: ...gister TCR 15 8 7 4 3 0 Reserved RXFIFOTRIGSTART RXFIFOTRIGHALT R 0 R W 0 R W Fh LEGEND R W Read Write R Read only n value after reset Table 19 45 Transmission Control Register TCR Field Descriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 4 RXFIFOTRIGSTART 0 Fh RX FIFO trigger level to RESTORE transmission 0 to 60 3 0 RXFIFOTRIGHALT 0 Fh RX FIFO trigger level to HALT transmission 0...

Page 3522: ...0 Defined by TLR 7 4 from 4 to 60 characters with a granularity of 4 characters 1 any value Defined by the concatenated value of TLR 7 4 and FCR 7 6 from 1 to 63 characters with a granularity of 1 character Note the combination of TLR 7 4 0000 and FCR 7 6 00 all zeros is not supported minimum of 1 character is required All zeros results in unpredictable behavior Table 19 49 TX FIFO Trigger Space S...

Page 3523: ...ter 1 MDR1 Field Descriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 FRAMEENDMODE IrDA mode only 0 Frame length method 1 Set EOT bit method 6 SIPMODE MIR FIR modes only 0 Manual SIP mode SIP is generated with the control of ACREG 3 1 Automatic SIP mode SIP is generated after each transmission 5 SCT Store and control the transmission 0 Starts the infrared transmission when a value i...

Page 3524: ...lity for MDR1 4 0 Normal mode 1 Alternate mode for SETTXIR 6 IRRXINVERT Only for IR mode IrDA and CIR Invert RX pin in the module before the voting or sampling system logic of the infrared block This does not affect the RX path in UART modem modes 0 Inversion is performed 1 No inversion is performed 5 4 CIRPULSEMODE 0 3h CIR pulse modulation definition Defines high level of the pulse width associa...

Page 3525: ... error in RX FIFO when frame at top of RX FIFO was received 3 FRAME_TOO_LONG_ERROR 0 No error 1 Frame length too long error in frame at top of RX FIFO 2 ABORT_DETECT 0 No error 1 Abort pattern detected in frame at top of RX FIFO 1 CRC_ERROR 0 No error 1 CRC error in frame at top of RX FIFO 0 Reserved 0 Reserved 19 5 1 22 RESUME Register The RESUME register is used to clear internal flags which hal...

Page 3526: ...part of the frame length 19 5 1 24 Status FIFO Register High SFREGH The frame lengths of received frames are written into the status FIFO This information can be read by reading the status FIFO register low SFREGL and the status FIFO register high SFREGH These registers do not physically exist The LSBs are read from SFREGL and the MSBs are read from SFREGH Reading these registers does not alter th...

Page 3527: ...8 and described in Table 19 56 Figure 19 58 BOF Control Register BLR 15 8 7 6 5 0 Reserved STSFIFORESET XBOFTYPE Reserved R 0 R W 0 R W 1 R 0 LEGEND R W Read Write R Read only n value after reset Table 19 56 BOF Control Register BLR Field Descriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 STSFIFORESET Status FIFO reset This bit is self clearing 6 XBOFTYPE SIR xBOF select 0 FFh sta...

Page 3528: ...pin is set to low 5 DISIRRX Disable RX input 0 Normal operation RX input automatically disabled during transmit but enabled outside of transmit operation 1 Disables RX input permanent state independent of transmit 4 DISTXUNDERRUN Disable TX underrun 0 Long stop bits cannot be transmitted TX underrun is enabled 1 Long stop bits can be transmitted 3 SENDSIP MIR FIR modes only Send serial infrared in...

Page 3529: ...RANU1 0 Disables the granularity of 1 for trigger RX level 1 Enables the granularity of 1 for trigger RX level 6 TXTRIGGRANU1 0 Disables the granularity of 1 for trigger TX level 1 Enables the granularity of 1 for trigger TX level 5 DSRIT 0 Disables DSR interrupt 1 Enables DSR interrupt 4 RXCTSDSRWAKEUPENABLE RX CTS wake up enable 0 Disables the WAKE UP interrupt and clears SSR 1 1 Waits for a fal...

Page 3530: ...ield Descriptions Bit Field Value Description 15 3 Reserved 0 Reserved 2 DMACOUNTERRST 0 The DMA counter will not be reset if the corresponding FIFO is reset via FCR 1 or FCR 2 1 The DMA counter will be reset if the corresponding FIFO is reset via FCR 1 or FCR 2 1 RXCTSDSRWAKEUPSTS Pin falling edge detection Reset only when SCR 4 is reset to 0 0 No falling edge event on RX CTS and DSR 1 A falling ...

Page 3531: ...led by setting the ACREG 5 bit to 1 The BOF length register EBLR is shown in Figure 19 62 and described in Table 19 60 NOTE If the RX_STOP interrupt occurs before a byte boundary the remaining bits of the last byte are filled with zeros and then passed into the RX FIFO Figure 19 62 BOF Length Register EBLR 15 8 7 0 Reserved EBLR R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table...

Page 3532: ...r MVR 15 8 7 4 3 0 Reserved MAJORREV MINORREV R 0 R unknown R unknown LEGEND R W Read Write R Read only n value after reset Table 19 61 Module Version Register MVR Field Descriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 4 MAJORREV 0 Fh Major revision number of the module 3 0 MINORREV 0 Fh Minor revision number of the module 3532 Universal Asynchronous Receiver Transmitter UART SP...

Page 3533: ... in the internal activity of the module 3h Smart idle Wakeup Acknowledgement to an idle request is given based in the internal activity of the module The module is allowed to generate wakeup request Only available on UART0 2 ENAWAKEUP Wakeup control 0 Wakeup is disabled 1 Wakeup capability is enabled 1 SOFTRESET Software reset Set this bit to 1 to trigger a module reset This bit is automatically r...

Page 3534: ...ield Value Description 15 8 Reserved 0 Reserved 7 TXWAKEUPEN Wake up interrupt 0 Event is not allowed to wake up the system 1 Event can wake up the system Event can be THRIT or TXDMA request and or TXSATUSIT 6 RLS_ INTERRUPT Receiver line status interrupt 0 Event is not allowed to wake up the system 1 Event can wake up the system 5 RHR_ INTERRUPT RHR interrupt 0 Event is not allowed to wake up the...

Page 3535: ...quency prescaler register CFPS is shown in Figure 19 67 and described in Table 19 65 Figure 19 67 Carrier Frequency Prescaler Register CFPS 15 8 7 0 Reserved CFPS R 0 R W 69h LEGEND R W Read Write R Read only n value after reset Table 19 65 Carrier Frequency Prescaler Register CFPS Field Descriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 0 CFPS 0 FFh System clock frequency prescal...

Page 3536: ...the 8 LSB divisor value 19 5 1 36 Divisor Latches High Register DLH The divisor latches high register DLH with the DLL register stores the 14 bit divisor for generation of the baud clock in the baud rate generator DLH stores the most significant part of the divisor DLL stores the least significant part of the divisor The DLH register is shown in Figure 19 69 and described in Table 19 67 NOTE DLL a...

Page 3537: ...peration 1 Auto RTS flow control is enabled RTS pin goes high inactive when the receiver FIFO HALT trigger level TCR 3 0 is reached and goes low active when the receiver FIFO RESTORE transmission trigger level is reached 5 SPECIALCHARDETECT Special character detect UART mode only 0 Normal operation 1 Special character detect enable Received data is compared with XOFF2 data If a match occurs the re...

Page 3538: ...er 15 8 7 0 Reserved XONWORD1 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 19 70 XON1 ADDR1 Register Field Descriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 0 XONWORD1 0 FFh Stores the 8 bit XON1 character in UART modes and ADDR1 address 1 in IrDA modes 19 5 1 39 XON2 ADDR2 Register In UART mode XON2 character in IrDA mode ADDR2 address 2 The XON2 ADDR2 r...

Page 3539: ...1 character in UART modes 19 5 1 41 XOFF2 Register In UART mode XOFF2 character The XOFF2 register is shown in Figure 19 74 and described in Table 19 73 Figure 19 74 XOFF2 Register 15 8 7 0 Reserved XOFFWORD2 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 19 73 XOFF2 Register Field Descriptions Bit Field Value Description 15 8 Reserved 0 Reserved 7 0 XOFFWORD2 0 FFh Stores t...

Page 3540: ...pecify the frame length 19 5 1 43 Transmit Frame Length High Register TXFLH The transmit frame length high register TXFLH and the TXFLL register hold the 13 bit transmit frame length expressed in bytes TXFLL holds the LSBs and TXFLH holds the MSBs The frame length value is used if the frame length method of frame closing is used The transmit frame length high register TXFLH is shown in Figure 19 7...

Page 3541: ...rame length in reception 19 5 1 45 Received Frame Length High Register RXFLH The received frame length high register RXFLH and the RXFLL register hold the 12 bit receive maximum frame length RXFLL holds the LSBs and RXFLH holds the MSBs If the intended maximum receive frame length is n bytes program RXFLL and RXFLH to be n 3 in SIR or MIR modes and n 6 in FIR mode 3 and 6 are the result of frame f...

Page 3542: ...mitation Only 7 and 8 bits character 5 and 6 bits not supported 7 bits character with space parity not supported Baud rate between 1200 and 115 200 bp s 10 possibilities Figure 19 79 UART Autobauding Status Register UASR 15 8 7 6 5 4 0 Reserved PARITYTYPE BITBYCHAR SPEED R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 19 78 UART Autobauding Status Register UASR Field De...

Page 3543: ...31 8 7 0 Reserved RXFIFO_LVL R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 19 79 RXFIFO_LVL Register Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 RXFIFO_LVL 0 Level of the RX FIFO 3543 SPRUH73H October 2011 Revised April 2013 Universal Asynchronous Receiver Transmitter UART Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Inco...

Page 3544: ...31 8 7 0 Reserved TXFIFO_LVL R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 19 80 TXFIFO_LVL Register Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 TXFIFO_LVL 0 Level of the TX FIFO 3544 Universal Asynchronous Receiver Transmitter UART SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Inco...

Page 3545: ...Read only n value after reset Table 19 81 IER2 Register Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 EN_TXFIFO_EM 0 Disables EN_TXFIFO_EMPTY interrupt PTY 1 Enables EN_TXFIFO_EMPTY interrupt 0 EN_RXFIFO_EM Number of bits by characters PTY 0 Disables EN_RXFIFO_EMPTY interrupt 1 Enables EN_RXFIFO_EMPTY interrupt 3545 SPRUH73H October 2011 Revised April 2013 Universal Asy...

Page 3546: ...LEGEND R W Read Write R Read only n value after reset Table 19 82 ISR2 Register Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 TXFIFO_EMPTY_ 0 TXFIFO_EMPTY interrupt not pending STS 1 TXFIFO_EMPTY interrupt pending 0 RXFIFO_EMPTY 0 RXFIFO_EMPTY interrupt not pending _STS 1 RXFIFO_EMPTY interrupt pending 3546 Universal Asynchronous Receiver Transmitter UART SPRUH73H Octob...

Page 3547: ...alue after reset Table 19 83 FREQ_SEL Register Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 FREQ_SEL 1A Sets the sample per bit if non default frequency is used MDR3 1 must be set to 1 after this value is set Must be equal or higher then 6 3547 SPRUH73H October 2011 Revised April 2013 Universal Asynchronous Receiver Transmitter UART Submit Documentation Feedback Copy...

Page 3548: ...3 Register 31 3 2 1 0 Reserved SET_DMA_TX_ NONDEFAULT DISABLE_CIR_ THRESHOLD _FREQ RX_DEMOD R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 19 84 Mode Definition Register 3 MDR3 Register Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 SET_DMA_TX_T 0 Disable use of TX DMA Threshold register Use 64 TX trigger as DMA threshold HRESHOLD 1 Enable to...

Page 3549: ..._DMA_THRESHOLD Register Field Descriptions Bit Field Value Description 31 6 Reserved 0 Reserved 5 0 TX_DMA_THRES 0 Used to manually set the TX DMA threshold level UART_MDR3 2 SET_TX_DMA_THRESHOLD HOLD must be 1 and must be value tx_trigger_level 64 TX FIFO size If not 64 tx_trigger_level will be used without modifying the value of this register 3549 SPRUH73H October 2011 Revised April 2013 Univers...

Page 3550: ... chapter describes the timers for the device Topic Page 20 1 DMTimer 3551 20 2 DMTimer 1ms 3585 20 3 RTC_SS 3621 20 4 WATCHDOG 3670 3550 Timers SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3551: ...imer clock A drawback of this mode is that full resynchronization path is used with access latency performance impact in terms of OCP clock cycles In order to improve module access latency and under restricted conditions on clocks ratios write posted mode can be used by setting the POSTED bit of the System Control Register TSCR Under this mode write posted mode is enabled meaning that OCP write co...

Page 3552: ...IRQSTATUS IRQWAKEEN IRQSTATUS_RAW DMTimer www ti com Table 20 1 Timer Resolution and Maximum Range Clock Prescaler Resolution Interrupt Period Range 32 768 KHz 1 min 31 25 us 31 25 us to 36h 35m 256 max 8 ms 8 ms to 391d 22h 48m 25 MHz 1 min 40 ns 40 ns to 171 8s 256 max 10 24 us 20 5 us to 24h 32m 20 1 1 3 Functional Block Diagram Figure 20 1 shows a block diagram of the timer Figure 20 1 Timer B...

Page 3553: ... 3 MPU Subsystem WakeM3 L4 Wakeup Interconnect DMTIMER_DMC Timer0 www ti com DMTimer 20 1 2 Integration The integration of Timer0 and Timer2 7 is shown in Figure 20 2 and Figure 20 3 Figure 20 2 Timer0 Integration 3553 SPRUH73H October 2011 Revised April 2013 Timers Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3554: ... 4 7 only DMTimer www ti com Figure 20 3 Timer2 7 Integration 20 1 2 1 Timer Connectivity Attributes Table 20 2 Timer 0 Connectivity Attributes Attributes Type Power domain Wakeup domain Clock Domain PD_WKUP_L4_WKUP_GCLK Interface OCP PD_WKUP_TIMER0_GCLK Func Reset Signals WKUP_DOM_RST_N Idle Wakeup Signals Idle Slave Wakeup Interrupt Requests 1 to MPU Subsystem TINT0 1 to WakeM3 DMA Requests None...

Page 3555: ...3 possible sources The 24 MHz typ system clock CLK_M_OSC The PER PLL generated 32 768 KHz clock CLK_32KHZ The TCLKIN external timer input clock The DMTimer 0 functional clock is fixed to use the internal 32KHz RC Clock CLK_RC32K 20 1 2 3 Timer Clock Signals Table 20 4 Timer Clock Signals Clock Signal Max Freq Reference Source Comments Timer 0 Clock Signals PICLKOCP 100 MHz CORE_CLKOUTM4 2 pd_wkup_...

Page 3556: ...PORGPOCFG signal as an output enable Table 20 5 Timer Pin List Pin Type Description TCLKIN I External timer clock source TIMER4 I O Timer 4 trigger input or PWM output TIMER5 I O Timer 5 trigger input or PWM output TIMER6 I O Timer 6 trigger input or PWM output TIMER7 I O Timer 7 trigger input or PWM output 3556 Timers SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyrigh...

Page 3557: ...r reset is released When the timer is stopped TCRR is frozen and it can be restarted from the frozen value unless TCRR has been reloaded with a new value In the one shot mode TCLR AR bit 0 the counter is stopped after counting overflow counter value remains at zero When the auto reload mode is enabled TCLR AR bit 1 the TCRR is reloaded with the Timer Load Register TLDR value after a counting overf...

Page 3558: ...nts are ignored no update on TCAR1 2 and no interrupt triggering until the detection logic is reset or the interrupt status register is cleared on TCAR s position writing a 1 in it This mechanism is useful for period calculation of a clock if that clock is connected to the PIEVENTCAPT input pin The edge detection logic is reset a new capture is enabled when the active capture interrupt is served T...

Page 3559: ...e setting TCLR CE bit to avoid any unwanted interrupt due to a reset value matching effect The dedicated output pin PORTIMERPWM can be programmed through TCLR TRG and PT bits to generate one positive pulse TIMER clock duration or to invert the current value toggle mode when an overflow and a match occur 20 1 3 1 4 Prescaler Functionality A prescaler counter can be used to divide the timer counter ...

Page 3560: ...nistic state of the output pin when modulation is stopped The modulation is synchronously stopped when TRG bit is cleared and overflow occurred In the following timing diagram the internal overflow pulse is set each time FFFF FFFFFh TLDR 1 value is reached and the internal match pulse is set when the counter reaches TMAR register value According to TCLR TRG and PT bits programming value the timer ...

Page 3561: ...er_pwm TRG 10 PT 1 timer_pwm TRG 01 PT 1 Set up mode sequence First match event ignored www ti com DMTimer Figure 20 8 Timing Diagram of Pulse Width Modulation with SCPWM 1 3561 SPRUH73H October 2011 Revised April 2013 Timers Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3562: ...f we consider a timer clock input of 32 kHz with a PRE field equal to 0 the timer output period is Table 20 8 Value and Corresponding Interrupt Period TLDR Interrupt period 0000 0000h 37 h FFFF 0000h 2 s FFFF FFF0h 500 us FFFF FFFEh 62 5 us 20 1 3 1 7 Dual Mode Timer Under Emulation During emulation mode when PINSUSPENDN signal is active the timer can cannot continue running according to the value...

Page 3563: ...mer module responds with error indication in the following cases Error on write transactions Assert the PORSRESP ERR signal in the same cycle as PORSCMDACCEPTED Use the ERR code for PORSRESP during the response phase Error on read transactions Assert the PORSRESP ERR signal in the same cycle as PORSCMDACCEPTED Use the ERR code for PORSRESP during the response phase PORSDATA in this case is not val...

Page 3564: ...action For each register a status bit is provided that is set if there is a pending write access to this register In this mode it is mandatory that the CPU checks the status bit prior to any write access In case a write is attempted to a register with a previous access pending the previous access is discarded without notice this can lead to unexpected results also There is one status bit per regis...

Page 3565: ...This mode uses a posted read scheme for reading any internal register The read transaction is immediately acknowledged on the OCP interface and the value to be read has been previously resynchronised This has the advantage of not stalling either the interconnect system or the CPU that requested the read transaction 20 1 3 5 2 Read Non Posted This mode is functional whatever the ratio between the O...

Page 3566: ... 5 2Ch IRQENABLE_SET Timer Interrupt Enable Set Register Section 20 1 5 6 30h IRQENABLE_CLR Timer Interrupt Enable Clear Register Section 20 1 5 7 34h IRQWAKEEN Timer IRQ Wakeup Enable Register Section 20 1 5 8 38h TCLR Timer Control Register Section 20 1 5 9 3Ch TCRR Timer Counter Register Section 20 1 5 10 40h TLDR Timer Load Register Section 20 1 5 11 44h TTGR Timer Trigger Register Section 20 ...

Page 3567: ... 1h 7 6 5 4 3 2 1 0 CUSTOM Y_MINOR R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 11 TIDR Register Field Descriptions Bit Field Type Reset Description 31 30 SCHEME R W 1h Used to distinguish between old scheme and current 29 28 Reserved R 0h 27 16 FUNC R W 0h Function indicates a software compatible module family 15 11 R_RTL R W 0h RTL Vers...

Page 3568: ... only 0x1 No idle mode local target never enters idle state Backup mode for debug only 0x2 Smart idle mode local target s idle state eventually follows acknowledges the system s idle requests depending on the IP module s internal requirements IP module shall not generate IRQ or DMA request related wakeup events 0x3 Smart idle wakeup capable mode local target s idle state eventually follows acknowl...

Page 3569: ...15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved DMAEvent_Ack R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 13 IRQ_EOI Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 DMAEvent_Ack R W 0h Write 0 to acknowledge DMA event has been completed Module will be able to generate another DMA event only whe...

Page 3570: ...W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 14 IRQSTATUS_RAW Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 TCAR_IT_FLAG R W 0h IRQ status for Capture 0x0x0 W No action 0x0x0 R No event pending 0x0x1 W Trigger IRQ event by software 0x0x1 R IRQ event pending 1 OVF_IT_FLAG R W 0h IRQ status for Overflow 0x0x0 W No action 0x0x0 ...

Page 3571: ...R 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 15 IRQSTATUS Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 TCAR_IT_FLAG R W 0h IRQ status for Capture 0x0x0 W No action 0x0x0 R No event pending 0x0x1 W Clear pending event if any 0x0x1 R IRQ event pending 1 OVF_IT_FLAG R W 0h IRQ status for Overf...

Page 3572: ...y W1toCl Write 1 to clear bit n value after reset Table 20 16 IRQENABLE_SET Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 TCAR_EN_FLAG R W 0h IRQ enable for Capture 0x0x0 W No action 0x0x0 R IRQ event is disabled 0x0x1 W Set IRQ enable 0x0x1 R IRQ event is enabled 1 OVF_EN_FLAG R W 0h IRQ enable for Overflow 0x0x0 W No action 0x0x0 R IRQ event is disabled 0x0x1 ...

Page 3573: ...W1toCl Write 1 to clear bit n value after reset Table 20 17 IRQENABLE_CLR Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 TCAR_EN_FLAG R W 0h IRQ enable for Capture 0x0x0 W No action 0x0x0 R IRQ event is disabled 0x0x1 W Clear IRQ enable 0x0x1 R IRQ event is enabled 1 OVF_EN_FLAG R W 0h IRQ enable for Overflow 0x0x0 W No action 0x0x0 R IRQ event is disabled 0x0x1 ...

Page 3574: ..._WUP_ENA R 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 18 IRQWAKEEN Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 TCAR_WUP_ENA R W 0h Wakeup generation for Capture 0x0 Wakeup disabled 0x1 Wakeup enabled 1 OVF_WUP_ENA R W 0h Wakeup generation for Overflow 0x0 Wakeup disabled 0x1 Wakeup enabled...

Page 3575: ...ral purpose output this register drives directly the PORGPOCFG output pin 0x0 PORGPOCFG drives 0 0x1 PORGPOCFG drives 1 13 CAPT_MODE R W 0h Capture mode 0x0 Single capture 0x1 Capture on second event 12 PT R W 0h Pulse or toggle mode on PORTIMERPWM output pin 0x0 Pulse 0x1 Toggle 11 10 TRG R W 0h Trigger output mode on PORTIMERPWM output pin 0x0 No trigger 0x1 Trigger on overflow 0x2 Trigger on ov...

Page 3576: ...er 4 2 PTV R W 0h Pre scale clock Timer value 1 AR R W 0h 0x0 One shot timer 0x1 Auto reload timer 0 ST R W 0h In the case of one shot mode selected AR 0 this bit is automatically reset by internal logic when the counter is overflowed 0x0 READ Stop timeOnly the counter is frozen 0x1 Start timer 3576 Timers SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 T...

Page 3577: ...et 2Ah During this Read the value of the upper 16 bit MSBs that has been temporary register is forwarded onto the output OCP data bus So to read the value of TCRR correctly the first OCP read access has to be to the lower 16 bit offset 28h followed by OCP read access to the upper 16 bit offset 2Ah As the TCRR is updated using more sources shadow_in_tcrr incremented value of tcrr TLDR and 0 a prior...

Page 3578: ... 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LOAD_VALUE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 21 TLDR Register Field Descriptions Bit Field Type Reset Description 31 0 LOAD_VALUE R W 0h Timer counter value loaded on overflow in auto reload mode or on TTGR write access 3578 Timers SPRUH73H October 2011 Revised April 2013 Submit Documentati...

Page 3579: ...E R W FFFFFFFFh LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 22 TTGR Register Field Descriptions Bit Field Type Reset Description 31 0 TTGR_VALUE R W FFFFFFFFh Writing in the TTGR register TCRR will be loaded from TLDR and prescaler counter will be cleared Reload will be done regardless of the AR field value of TCLR register 3579 SPRUH73H October 2011 ...

Page 3580: ... 0 Reserved W_PEND_TMAR W_PEND_TTGR W_PEND_TLDR W_PEND_TCRR W_PEND_TCLR R 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 23 TWPS Register Field Descriptions Bit Field Type Reset Description 31 5 Reserved R 0h 4 W_PEND_TMAR R W 0h When equal to 1 a write is pending to the TMAR register 3 W_PEND_TTGR R W 0h When equal ...

Page 3581: ...e 20 22 TMAR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COMPARE_VALUE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 24 TMAR Register Field Descriptions Bit Field Type Reset Description 31 0 COMPARE_VALUE R W 0h Value to be compared to the timer counter 3581 SPRUH73H October 2011 Revised April 20...

Page 3582: ...is being updated due to some capture event In 16 bit mode the following sequence must be followed to read the TCAR1 register properly Figure 20 23 TCAR1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPTURED_VALUE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 25 TCAR1 Register Field Descriptions Bi...

Page 3583: ...19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved POSTED SFT Reserved R 0h R W 0h R W 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 26 TSICR Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 POSTED R W 0h PIFREQRATIO 0x0 Posted mode inactive will delay the command accept output...

Page 3584: ... bit mode the following sequence must be followed to read the TCAR2 register properly First perform an OCP Read Transaction to Read the lower 16 bits of the TCAR2 register Second perform an OCP Read Transaction to read the upper 16 bits of the TCAR2 register Figure 20 25 TCAR2 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPTURED_VALUE R W 0h LEGEN...

Page 3585: ...e clock divider prescaler allows reduction of the timer input clock frequency All internal timer interrupt sources are merged in one module interrupt line and one wake up line Each internal interrupt sources can be independently enabled disabled with a dedicated bit of TIER register for the interrupt features and a dedicated bit of TWER for the wake up This module is controllable through the OCP p...

Page 3586: ...pocfg pieventcapt piclktimer Prescaler TCAR 1 2 Pulse Pwm Logic COMP TISR TIER TWER Wakeup Logic Interrupt Logic porocpsinterrupt portimerpwm timerwakeup piocpmidlereq porocpsidleack DMTimer 1ms www ti com Figure 20 26 Block Diagram 3586 Timers SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3587: ... WKUP_DOM_RST_N Idle Wakeup Signals Smart Idle Slave Wakeup Interrupt Requests 1 to MPU Subsystem TINT1_1MS and WakeM3 DMA Requests None Physical Address L4 Wakeup slave port 20 2 2 2 Timer Clock and Reset Manangement The DMTimer1 1ms timer functional clock can be selected from one of five sources using the CLKSEL_TIMER1MS_CLK register in the PRCM The 24 MHz typ system clock CLK_M_OSC The PER PLL ...

Page 3588: ...CORE_CLKOUTM4 2 pd_wkup_l4_wkup_gclk Interface clock from PRCM PICLKTIMER 25 MHz 1 pd_wkup_timer1_gclk CLK_M_OSC Functional clock from PRCM CLK_32KHZ PER_CLKOUTM2 5859 375 TCLKIN CLK_RC32K CLK_32K_RTC 1 PICLKTIMER must be less than PICLKOCP 4 3588 Timers SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3589: ...a new value In the one shot mode TCLR AR bit 0 the counter is stopped after counting overflow counter value remains at zero When the auto reload mode is enabled TCLR AR bit 1 the TCRR is reloaded with the Timer Load Register TLDR value after a counting overflow It is not recommended to put the overflow value 0xFFFFFFFF in TLDR because it can lead to undesired results An interrupt can be issued on ...

Page 3590: ...ows the value loaded in TCRR according to the sign of the result of Add1 Add2 and Add3 MSB 0 means a positive value MSB 1 means a negative value Table 20 30 Value Loaded in TCRR to Generate 1ms Tick Add1 MSB Add2 MSB Add3 MSB TCRR 0 0 0 TLDR 0 0 1 TLDR 0 1 0 TLDR 0 1 1 TLDR 1 1 0 0 N A 1 0 1 N A 1 1 0 TLDR 1 1 1 1 TLDR 1 The values of TPIR and TNIR registers are calculated with formula Positive In...

Page 3591: ... first enabled capture event the value of the counter register is saved in TCAR1 register and all the next events are ignored no update on TCAR1 and no interrupt triggering until the detection logic is reset or the interrupt status register is cleared on TCAR s position writing a 1 in it If TCLR s CAPT_MODE field is 1 then on the first enabled captured event the counter value is saved in TCAR1 reg...

Page 3592: ...ising edge of the PIEVENTCAPT will trigger a capture in TCAR1 on first enabled event and TCAR2 will update on the second enabled event Figure 20 31 Capture Wave Example for CAPT_MODE 1 20 2 3 3 Compare Mode Functionality When Compare Enable TCLR CE bit is set to 1 the timer value TCRR is permanently compared to the value held in timer match register TMAR TMAR value can be loaded at any time timer ...

Page 3593: ...when a compare condition occurs In case of overflow and match mode the match event will be ignored from the moment the mode was set up until the first overflow event occurs The TCLR SCPWM bit can be programmed to set or clear the PORTIMERPWM output signal while the counter is stopped or the triggering is off only This allows fixing a deterministic state of the output pin when modulation is stopped...

Page 3594: ...idth Modulation SCPWM Bit 1 20 2 3 6 Timer Interrupt Control The timer can issue an overflow interrupt a timer match interrupt and a timer capture interrupt Each internal interrupt sources can be independently enabled disabled in the Interrupt Enable Register TIER When the interrupt event has been issued the associated interrupt status bit is set in the Timer Status Register TISR The pending inter...

Page 3595: ...luates the internal activity and asserts the Idle acknowledge signal POROCPSIDLEACK entering in Sleep mode ready to issue a wake up request The following table describes the Smart Idle behavior according to the clock activity setting Table 20 32 SmartIdle Clock Activity Field Configuration Clock Activity Functional Clock OCP Clock Module Behavior 11 ON ON The Idle acknowledge signal is asserted wh...

Page 3596: ...nal and then the host can read the corresponding bit in TISR to find out which interrupt source has trigged wake up request After acknowledging the wake up request the processor resets the status bit and releases the interrupt line by writing a 1 in the corresponding bit of the TISR register 20 2 3 8 Timer Counting Rate The dmtimer s counter is composed of a prescaler stage and a timer counter Rat...

Page 3597: ... asynchronous input pin is internally synchronized on 2 TIMER clock rising edges 20 2 4 Use Cases 20 2 5 DMTIMER_1MS Registers Table 20 35 lists the memory mapped registers for the DMTIMER_1MS All register offset addresses not listed in Table 20 35 should be considered as reserved locations and the register contents should not be modified Table 20 35 DMTIMER_1MS REGISTERS Offset Acronym Register N...

Page 3598: ...or 1ms tick generation Section 20 2 5 16 The TPIR register holds the value of the positive increment The value of this register is added with the value of the TCVR to define whether next value loaded in TCRR will be the sub period value or the over period value 4Ch TNIR This register is used for 1ms tick generation Section 20 2 5 17 The TNIR register holds the value of the negative increment The v...

Page 3599: ... 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 TID_REV R 15h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 36 TIDR Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h Reads return 0 7 0 TID_REV R 15h IP revision 7 4 Major revision 3 0 Minor revision Examples 0x10 for 1 0 0x21 for 2 1 3599 SPRUH73H October 2011 Revised April 2013 Ti...

Page 3600: ...lation 4 3 IdleMode R W 0h Power Management req ack control 0 fidle Force idle An idle request is acknowledged unconditionally 1 nidle No idle An idle request is never acknowledged 2 sidle Smart idle Acknowledgment to an idle request is given based on the internal activity of the module 3 Smart idle wakeup capable Acknowledgment to an idle request is given based on the internal activity of the mod...

Page 3601: ...0 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved ResetDone R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 38 TISTAT Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h Reads return 0 Reserved for OCP socket status information 0 ResetDone R 0h Internal reset monitoring 0 rstongoing Internal module reset in on going 1 rstc...

Page 3602: ...ble 20 39 TISR Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h Reads return 0 2 TCAR_IT_FLAG R W1toCl 0h indicates when an external pulse transition of the correct polarity is detected on the external pin PIEVENTCAPT 0 TCAR_IT_FLAG_0 no capture interrupt request 1 TACR_IT_FLAG_1 capture interrupt request 1 OVF_IT_FLAG R W1toCl 0h TCRR overflow 0 OVF_IT_FLAG_0 no ove...

Page 3603: ...1toCl Write 1 to clear bit n value after reset Table 20 40 TIER Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h Reads return 0 2 TCAR_IT_ENA R W 0h Enable capture interrupt 0 Dsb_capt Disable capture interrupt 1 Enb_capt Enable capture interrupt 1 OVF_IT_ENA R W 0h Enable overflow interrupt 0 Dsb_ovf Disable overflow interrupt 1 Enb_ovf Enable overflow interrupt 0 M...

Page 3604: ...Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 41 TWER Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h Reads return 0 2 TCAR_WUP_ENA R W 0h Enable capture wake up 0 DsbWupCap Disable capture wake up 1 EnbWupCapt Enable capture wake up 1 OVF_WUP_ENA R W 0h Enable overflow wake up 0 DsbWupOvf Disable overflow wake up 1 EnbWupOvf Enable over...

Page 3605: ... event in TCAR1 1 Sec_capt Capture the second enabled capture event in TCAR2 12 PT R W 0h Pulse or Toggle select bit 0 pulse pulse modulation 1 toggle toggle modulation 11 10 TRG R W 0h Trigger Output Mode 0 no_trg No trigger 1 ovf_trg Overflow trigger 2 ovf_mat_trg Overflow and match trigger 3 reserved Reserved 9 8 TCM R W 0h Transition Capture Mode 0 no_edge No capture 1 rise_edge Capture on ris...

Page 3606: ... W 0h Auto reload mode 0 one_shot One shot mode overflow 1 auto_rel Auto reload mode overflow 0 ST R W 0h Start Stop timer control 0 cnt_stop Stop the timer 1 cnt_start Start the timer 3606 Timers SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3607: ... 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIMER_COUNTER R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 43 TCRR Register Field Descriptions Bit Field Type Reset Description 31 0 TIMER_COUNTER R W 0h The value of the timer counter register 3607 SPRUH73H October 2011 Revised April 2013 Timers Submit Documentation Feedback Copyright 201...

Page 3608: ...21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LOAD_VALUE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 44 TLDR Register Field Descriptions Bit Field Type Reset Description 31 0 LOAD_VALUE R W 0h The value of the timer load register 3608 Timers SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Tex...

Page 3609: ...19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TTGR_VALUE R W FFFFFFFFh LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 45 TTGR Register Field Descriptions Bit Field Type Reset Description 31 0 TTGR_VALUE R W FFFFFFFFh The value of the trigger register During reads it always returns 0xFFFFFFFF 3609 SPRUH73H October 2011 Revised April 2013 Timers Submit...

Page 3610: ...ing 1 OCR_Pend Overflow Counter Register write pending 7 W_PEND_TCVR R 0h Write pending for register TCVR 0 CVR_nPend No Counter Register write pending 1 CVR_Pend Counter Register write pending 6 W_PEND_TNIR R 0h Write pending for register TNIR 0 NIR_nPend No Negativ Increment Register write pending 1 NIR_Pend Negativ Increment Register write pending 5 W_PEND_TPIR R 0h Write pending for register T...

Page 3611: ...e Reset Description 0 W_PEND_TCLR R 0h Write pending for register TCLR 0 CLR_nPend No Control Register write pending 1 CLR_Pend Control Register write pending 3611 SPRUH73H October 2011 Revised April 2013 Timers Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3612: ... 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COMPARE_VALUE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 47 TMAR Register Field Descriptions Bit Field Type Reset Description 31 0 COMPARE_VALUE R W 0h The value of the match register 3612 Timers SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyri...

Page 3613: ...4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPTURE_VALUE1 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 48 TCAR1 Register Field Descriptions Bit Field Type Reset Description 31 0 CAPTURE_VALUE1 R 0h The value of first captured counter register 3613 SPRUH73H October 2011 Revised April 2013 Timers Submit Documentation Feedback Co...

Page 3614: ...t Table 20 49 TSICR Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h Reads return 0 2 POSTED R W 1h PIFREQRATIO 0x0 Posted mode inactive will delay the command accept output signal NOTE This mode is not recommended on this device 0x1 Posted mode active clocks ratio needs to fit freq timer less than freq OCP 4 frequency requirement 1 SFT R W 0h This bit reset all the ...

Page 3615: ...4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPTURE_VALUE2 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 50 TCAR2 Register Field Descriptions Bit Field Type Reset Description 31 0 CAPTURE_VALUE2 R 0h The value of second captured counter register 3615 SPRUH73H October 2011 Revised April 2013 Timers Submit Documentation Feedback C...

Page 3616: ...e the sub period value or the over period value Figure 20 50 TPIR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POSITIVE_INC_VALUE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 51 TPIR Register Field Descriptions Bit Field Type Reset Description 31 0 POSITIVE_INC_VALUE R W 0h The value of the posit...

Page 3617: ...e the sub period value or the over period value Figure 20 51 TNIR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NEGATIVE_INV_VALUE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 52 TNIR Register Field Descriptions Bit Field Type Reset Description 31 0 NEGATIVE_INV_VALUE R W 0h The value of the negat...

Page 3618: ...alue Figure 20 52 TCVR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COUNTER_VALUE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 53 TCVR Register Field Descriptions Bit Field Type Reset Description 31 0 COUNTER_VALUE R W 0h The value of CVR counter 3618 Timers SPRUH73H October 2011 Revised April 20...

Page 3619: ...F_COUNTER_VALUE R W 0h 15 14 13 12 11 10 9 8 OVF_COUNTER_VALUE R W 0h 7 6 5 4 3 2 1 0 OVF_COUNTER_VALUE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 54 TOCR Register Field Descriptions Bit Field Type Reset Description 31 24 Reserved R 0h Reads return 0 23 0 OVF_COUNTER_VALUE R W 0h The number of overflow events 3619 SPRUH73H October 2011 Revised...

Page 3620: ...LUE R W 0h 15 14 13 12 11 10 9 8 OVF_WRAPPING_VALUE R W 0h 7 6 5 4 3 2 1 0 OVF_WRAPPING_VALUE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 55 TOWR Register Field Descriptions Bit Field Type Reset Description 31 24 Reserved R 0h Reads return 0 23 0 OVF_WRAPPING_VALU R W 0h The number of masked interrupts E 3620 Timers SPRUH73H October 2011 Revise...

Page 3621: ...tate Alarms are available to interrupt the CPU at a particular time or at periodic time intervals such as once per minute or once per day In addition the RTC can interrupt the CPU every time the calendar and time registers are updated or at programmable periodic intervals 20 3 1 1 Features The real time clock RTC provides the following features 100 year calendar xx00 to xx99 Counts seconds minutes...

Page 3622: ...generation of real time alarms The integration of the RTC is shown in Figure 20 55 Figure 20 55 RTC Integration 20 3 2 1 RTC Connectivity Attributes The general connectivity for the RTC module in the device is shown in Table 20 56 Table 20 56 RTC Module Connectivity Attributes Attributes Type Power Domain RTC Clock Domain PD_RTC_L4_RTC_GCLK Interface OCP PD_RTC_RTC32KCLK Func CLK_32K_RTC Func Rese...

Page 3623: ... clock From OSC1_IN rtc_32k_clk_rtc_32k_aux_clk 32 768 KHz PER_CLKOUTM2 5859 3752 pd_rtc_rtc_32kclk Internal functional clock From PRCM 20 3 2 3 RTC Pin List The RTC module does not include any external interface pins Table 20 58 RTC Pin List Pin Type Description RTC_PORz I RTC Power On Reset EXT_WAKEUP I External wakeup PMIC_POWER_EN O Power enable control for external power management IC Analog ...

Page 3624: ...d between pins RTC_XTALIN and RTC_XTALOUT RTC_XTALIN is the input to the on chip oscillator and RTC_XTALOUT is the output from the oscillator back to the crystal The oscillator can be enabled or disabled by using the RTC_OSC_REG register For more information about the RTC crystal connection see your device specific data manual An external 32 768 kHz clock oscillator may be used instead of a crysta...

Page 3625: ...ter enables this interrupt The timer interrupt is active low The RTC_STATUS_REG 5 2 are only updated at each new interrupt and occur according to Table 20 60 For example bit 2 SEC will always be set when one second has passed It will also be set when one minute has passed since the completion of one minute also marks the completion of one second from 59 seconds to 60 seconds The same holds true fo...

Page 3626: ... RTC_STATUS_REG 6 indicates that IRQ_ALARM_CHIP has occurred This interrupt is disabled by writing 1 into the RTC_STATUS_REG 6 To set up an alarm Modify the ALARM_SECONDS ALARM_MINUTES ALARM_HOURS ALARM_DAY ALARM_WEEK ALARM_MONTH and ALARM_YEAR registers to the exact time you want an alarm to generate Set the IT_ALARM bit in the RTC_INTERRUPTS register to enable the alarm interrupt 3626 Timers SPR...

Page 3627: ... the names above also share the same BCD formatting SECOND Second Count 00 59 MINUTE Minute Count 00 59 HOUR Hour Count 12HR 01 12 24HR 00 23 DAY Day of the Month Count 01 31 WEEK Day of the Week 0 6 SUN 0 MONTH Month Count 01 12 JAN 1 YEAR Year Count 00 99 20 3 3 5 2 Register Access The three register types are as follows and each has its own access constraints TC and TC alarm registers General r...

Page 3628: ...s to the nearest minute with zero seconds This feature is enabled by setting the ROUND_30S bit in the control register CTRL the RTC automatically rounds the time values to the nearest minute upon the next read of the SECONDS register NOTE Software should always read the Seconds register first However the software does not have to poll any status bit to determine when to read the TC registers Table...

Page 3629: ...t 1 needs to be checked to verify the RTC has in fact stopped Once this is confirmed the TC values can be updated After the values have been updated the RTC can be re started by resetting the STOP_RTC bit NOTE After writing to a TC register the user must wait 4 OCP clock cycles before reading the value from the register If this wait time is not observed and the TC register is accessed then old dat...

Page 3630: ...ensation versus one hour period and load the compensation registers with the drift compensation value Auto compensation is enabled by AUTO_COMP_EN bit in the RTC_CTRL register If the COMP_REG value is positive compensation occurs after the second change event COMP_REG cycles are removed from the next second If the COMP_REG value is negative compensation occurs before the second change event COMP_R...

Page 3631: ...one for a timer event When the RTC is in IDLE mode the OCP clock is turned off and the 32 kHz clock remains on The time and calendar continue to count in IDLE mode When the RTC is placed back in FUNCTIONAL mode the TC registers can be read The Alarm SWakeup event can be used to wakeup the RTC when it is in IDLE state In order to do so the alarm needs to be set and enabled before RTC enters the IDL...

Page 3632: ...m Months Register Section 20 3 5 12 34h ALARM_YEARS_REG Alarm Years Register Section 20 3 5 13 40h RTC_CTRL_REG Control Register Section 20 3 5 14 44h RTC_STATUS_REG Status Register Section 20 3 5 15 48h RTC_INTERRUPTS_REG Interrupt Enable Register Section 20 3 5 16 4Ch RTC_COMP_LSB_REG Compensation LSB Register Section 20 3 5 17 50h RTC_COMP_MSB_REG Compensation MSB Register Section 20 3 5 18 54h...

Page 3633: ...ERS continued Offset Acronym Register Name Section 9Ch RTC_DEBOUNCE RTC Debounce Register Section 20 3 5 35 3633 SPRUH73H October 2011 Revised April 2013 Timers Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3634: ...e 20 61 SECONDS_REG Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved SEC1 SEC0 R 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 64 SECONDS_REG Register Field Descriptions Bit Field Type Reset Description 31 7 Reserved R 0h 6 4 SEC1 R W 0h 2nd...

Page 3635: ...62 MINUTES_REG Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved MIN1 MIN0 R 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 65 MINUTES_REG Register Field Descriptions Bit Field Type Reset Description 31 7 Reserved R 0h 6 4 MIN1 R W 0h 2nd digi...

Page 3636: ...5 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 PM_nAM Reserved HOUR1 HOUR0 R W 0h R 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 66 HOURS_REG Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 PM_nAM R W 0h Only used in PM_AM mode otherwise 0 0...

Page 3637: ...0 64 DAYS_REG Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved DAY1 DAY0 R 0h R W 0h R W 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 67 DAYS_REG Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 4 DAY1 R W 0h 2nd digit of...

Page 3638: ...ure 20 65 MONTHS_REG Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved MONTH1 MONTH0 R 0h R W 0h R W 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 68 MONTHS_REG Register Field Descriptions Bit Field Type Reset Description 31 5 Reserved R 0h 4 MONTH1 R W 0h...

Page 3639: ...nd YEAR1 set as 7 Figure 20 66 YEARS_REG Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 YEAR1 YEAR0 R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 69 YEARS_REG Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 4 YEAR1 R ...

Page 3640: ...day with 6 Figure 20 67 WEEKS_REG Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved WEEK R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 70 WEEKS_REG Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 0 WEEK R W 0h 1st...

Page 3641: ... 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved ALARMSEC1 ALARMSEC0 R 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 71 ALARM_SECONDS_REG Register Field Descriptions Bit Field Type Reset Description 31 7 Reserved R 0h 6 4 ALARMSEC1 R W 0h 2nd digit of seconds Rang...

Page 3642: ...6 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved ALARM_MIN1 ALARM_MIN0 R 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 72 ALARM_MINUTES_REG Register Field Descriptions Bit Field Type Reset Description 31 7 Reserved R 0h 6 4 ALARM_MIN1 R W 0h 2nd digit of minutes Ran...

Page 3643: ...h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 ALARM_PM_nAM Reserved ALARM_HOUR1 ALARM_HOUR0 R W 0h R 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 73 ALARM_HOURS_REG Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 ALARM_PM_nAM R W 0h Only used in PM_AM mode otherwise 0 0x0 AM 0x1 PM 6 Reserved R...

Page 3644: ...6 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved ALARM_DAY1 ALARM_DAY0 R 0h R W 0h R W 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 74 ALARM_DAYS_REG Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 4 ALARM_DAY1 R W 0h 2nd digit for days Range fr...

Page 3645: ...26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved ALARM_MONTH1 ALARM_MONTH0 R 0h R W 0h R W 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 75 ALARM_MONTHS_REG Register Field Descriptions Bit Field Type Reset Description 31 5 Reserved R 0h 4 ALARM_MONTH1 R W 0h 2nd digit of months ...

Page 3646: ...egister 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 ALARM_YEAR1 ALARM_YEAR0 R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 76 ALARM_YEARS_REG Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 4 ALARM_YEAR1 R W 0h 2nd digit of ...

Page 3647: ...e RTC clears it If the ARM sets the ROUND_30S bit and then reads it the ARM reads 1 until the round to the closest minute is performed at the next second The ARM can stop the RTC by clearing the STOP_RTC bit owing to internal resynchronization the RUN bit of the status register STATUS_REG must be checked to ensure that the RTC is frozen then update TC values and re start the RTC by resetting the S...

Page 3648: ...e oscillator compensation mode 0x0 No auto compensation 0x1 Auto compensation enabled 1 ROUND_30S R W 0h Enable one time rounding to nearest minute on next time register read 0x0 No update 0x1 Time is rounded to the nearest minute 0 STOP_RTC R W 0h Stop the RTC 32 kHz counter 0x0 RTC is frozen 0x1 RTC is running 3648 Timers SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Cop...

Page 3649: ...t is running The RUN bit shows the real state of the RTC Indeed because the STOP_RTC signal is resynchronized on 32 kHz clock the action of this bit is delayed BUSY This bit will give the status of RTC module The Time and alarm registers can be modified only when this bit is 0 The timer interrupt is a negative edge sensitive low level pulse 1 OCP cycle duration Figure 20 75 RTC_STATUS_REG Register...

Page 3650: ...REG Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved IT_ALARM2 IT_ALARM IT_TIMER EVERY R 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 79 RTC_INTERRUPTS_REG Register Field Descriptions Bit Field Type Reset Description 31 5 Rese...

Page 3651: ...ite FFFFh into RTC_COMP_MSB_REG and RTC_COMP_LSB_REG To remove one 32 kHz oscillator period every hour the ARM must write 0001h into RTC_COMP_MSB_REG and RTC_COMP_LSB_REG The 7FFFh value is forbidden Figure 20 77 RTC_COMP_LSB_REG Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 RTC_COMP_LSB R W 0h LEGEND R W Re...

Page 3652: ...ery hour the ARM must write FFFFh into RTC_COMP_MSB_REG and RTC_COMP_LSB_REG To remove one 32 kHz oscillator period every hour the ARM must write 0001h into RTC_COMP_MSB_REG and RTC_COMP_LSB_REG The 7FFFh value is forbidden Figure 20 78 RTC_COMP_MSB_REG Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 RTC_COMP_...

Page 3653: ...7 Reserved R 0h 6 EN_32KCLK R W 0h 32 kHz clock enable post clock mux of rtc_32k_clk_rtc_32k_aux_clk and rtc_32k_clk_rtc_32k_clk 0x0 Disable 0x1 Enable 5 Reserved R 0h 4 OSC32K_GZ R W 1h Disable the oscillator and apply high impedance to the output 0x0 Enable 0x1 Disabled and high impedance 3 SEL_32KCLK_SRC R W 0h 32 kHz clock source select 0x0 Selects internal clock source namely rtc_32k_clk_rtc_...

Page 3654: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCSCRATCH0 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 83 RTC_SCRATCH0_REG Register Field Descriptions Bit Field Type Reset Description 31 0 RTCSCRATCH0 R W 0h Scratch registers available to program 3654 Timers SPRUH73H October 2011 Revised April 2013 Submit Docu...

Page 3655: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCSCRATCH1 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 84 RTC_SCRATCH1_REG Register Field Descriptions Bit Field Type Reset Description 31 0 RTCSCRATCH1 R W 0h Scratch registers available to program 3655 SPRUH73H October 2011 Revised April 2013 Timers Submit Docu...

Page 3656: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCSCRATCH2 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 85 RTC_SCRATCH2_REG Register Field Descriptions Bit Field Type Reset Description 31 0 RTCSCRATCH2 R W 0h Scratch registers available to program 3656 Timers SPRUH73H October 2011 Revised April 2013 Submit Docu...

Page 3657: ...protection the value of 83E7 0B13h must be written to KICK0R followed by the value of 95A4 F1E0h written to KICK1R RTC register write protection is enabled when any value is written to KICK0R Figure 20 83 KICK0R Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KICK0_ W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset...

Page 3658: ... mechanism to write to other MMRs To disable RTC register write protection the value of 83E7 0B13h must be written to KICK0R followed by the value of 95A4 F1E0h written to KICK1R Figure 20 84 KICK1R Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KICK1 W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 87 K...

Page 3659: ...y W1toCl Write 1 to clear bit n value after reset Table 20 88 RTC_REVISION Register Field Descriptions Bit Field Type Reset Description 31 30 SCHEME R 1h Used to distinguish between old scheme and current 29 28 Reserved R 0h 27 16 FUNC R EB0h Function indicates a software compatible module family 15 11 R_RTL R 1h RTL Version R 10 8 X_MAJOR R 1h Major Revision 7 6 CUSTOM R 0h Indicates a special ve...

Page 3660: ...te 0x0 Force idle mode local target s idle state follows acknowledges the system s idle requests unconditionally i e regardless of the IP module s internal requirements Backup mode for debug only 0x1 No idle mode local target never enters idle state Backup mode for debug only 0x2 Smart idle mode local target s state eventually follows acknowledges the system s idle requests depending on the IP mod...

Page 3661: ...KEEN R 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 90 RTC_IRQWAKEEN Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 ALARM_WAKEEN R W 0h Wakeup generation for event Alarm 0x0 Wakeup disabled 0x1 Wakeup enabled 0 TIMER_WAKEEN R W 0h Wakeup generation for event Timer 0x0 Wakeup disabled 0x1 Wakeup enable...

Page 3662: ...25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved ALARM2_SEC1 ALARM2_SEC0 R 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 91 ALARM2_SECONDS_REG Register Field Descriptions Bit Field Type Reset Description 31 7 Reserved R 0h 6 4 ALARM2_SEC1 R W 0h 2nd digit of seconds R...

Page 3663: ...25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved ALARM2_MIN1 ALARM2_MIN0 R 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 92 ALARM2_MINUTES_REG Register Field Descriptions Bit Field Type Reset Description 31 7 Reserved R 0h 6 4 ALARM2_MIN1 R W 0h 2nd digit of minutes R...

Page 3664: ... 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 ALARM2_PM_nAM Reserved ALARM2_HOUR1 ALARM2_HOUR0 R W 0h R 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 93 ALARM2_HOURS_REG Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 ALARM2_PM_nAM R W 0h Only used in PM_AM mode otherwise 0 0x0 AM 0x1 PM 6 Reserved ...

Page 3665: ...5 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved ALARM2_DAY1 ALARM2_DAY0 R 0h R W 0h R W 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 94 ALARM2_DAYS_REG Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 4 ALARM2_DAY1 R W 0h 2nd digit for days Range f...

Page 3666: ... 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved ALARM2_MONTH1 ALARM2_MONTH0 R 0h R W 0h R W 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 95 ALARM2_MONTHS_REG Register Field Descriptions Bit Field Type Reset Description 31 5 Reserved R 0h 4 ALARM2_MONTH1 R W 0h 2nd digit of month...

Page 3667: ...ter 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 ALARM2_YEAR1 ALARM2_YEAR0 R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 96 ALARM2_YEARS_REG Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 4 ALARM2_YEAR1 R W 0h 2nd digit of ...

Page 3668: ...R W 0h Enable for PMIC_POWER_EN signal 0b Disable When Disabled pmic_power_en signal will always be driven as 1 ON state 1b Enable When Enabled pmic_power_en signal will be controlled by ext_wakeup alarm and alarm2 ON OFF Turn OFF only by ALARM2 event OFF ON TURN ON only by ALARM event OR ext_wakeup event 15 12 EXT_WAKEUP_STATUS R W 0h External wakeup status Write 1 to clear EXT_WAKEUP_STATUS n st...

Page 3669: ...stay the same value defined in DEBOUNCE_REG for a defined time Figure 20 95 RTC_DEBOUNCE Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 DEBOUNCE_REG R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 98 RTC_DEBOUNCE Register Field Descriptions Bit Field Type Rese...

Page 3670: ... 1 Features The main features of the watchdog timer controllers are L4 slave interface support 32 bit data bus width 32 16 bit access supported 8 bit access not supported 11 bit address bus width Burst mode not supported Write nonposted transaction mode only Free running 32 bit upward counter Programmable divider clock source 2n where n 0 7 On the fly read write register while counting Subset prog...

Page 3671: ...WD Timer Module Connectivity Attributes Attributes Type Power Domain Wakeup Domain Clock Domain PD_WKUP_L4_WKUP_GCLK OCP PD_WKUP_WDT1_GCLK Func Reset Signals WKUP_DOM_RST_N Idle Wakeup Signals Smart Idle Slave Wakeup Interrupt Requests 1 Interrupt to MPU Subsystem WDT1INT and WakeM3 DMA Requests None Physical Address L4 Wakeup slave port 20 4 2 2 Public WD Timer Clock and Reset Management The Watc...

Page 3672: ..._CLK 100 MHz CORE_CLKOUTM4 2 pd_wkup_l4_wkup_gclk Interface clock from PRCM PI_SYS_CLK 32768 Hz CLK_RC32K or pd_wkup_wdt1_gclk Functional clock CLK_32KHZ from PRCM PER_CLKOUTM2 5859 375 3672 Timers SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3673: ...CLR 1 WDTINT Watchdog delay value DLY_IT_ENA reached 20 4 3 3 General Watchdog Timer Operation The watchdog timers are based on an upward 32 bit counter coupled with a prescaler The counter overflow is signaled through two independent signals a simple reset signal and an interrupt signal both active low Figure 20 97 is a functional block diagram of the watchdog timer The interrupt generation mecha...

Page 3674: ...lse is one prescaled timer clock cycle wide and occurs at the same time as the timer counter overflow After reset generation the counter is automatically reloaded with the value stored in the watchdog load register WDT_WLDR and the prescaler is reset the prescaler ratio remains unchanged When the reset pulse output is generated the timer counter begins incrementing again Figure 20 98 shows a gener...

Page 3675: ... by 2 and WDT_WCLR 5 PRE 1 clock divider enabled the reset period is as listed in Table 20 104 Table 20 104 Reset Period Examples WDT_WLDR Value Reset Period 0000 0000h 74 h 56 min FFFF 0000h 4 s FFFF FFF0h 1 ms FFFF FFFFh 62 5 us CAUTION Ensure that the reloaded value allows the correct operation of the application When a watchdog timer is enabled software must periodically trigger a reload befor...

Page 3676: ...WWPS W_PEND_WSPR To enable the timer follow this sequence 1 Write XXXX BBBBh in WDT_WSPR 2 Poll for posted write to complete using WDT_WWPS W_PEND_WSPR 3 Write XXXX 4444h in WDT_WSPR 4 Poll for posted write to complete using WDT_WWPS W_PEND_WSPR All other write sequences on the WDT_WSPR register have no effect on the start stop feature of the module 20 4 3 9 Modifying Timer Count Load Values and P...

Page 3677: ...nterrupt can be disabled by setting the WDT_WIRQENCLR 0 OVF_IT_ENA bit to 1 The watchdog can issue the delay interrupt if this interrupt is enabled in the interrupt enable register WDT_WIRQENSET 1 DLY_IT_ENA 1 When the counter is running and the counter value matches the value stored in the delay configuration register WDT_WDLY the corresponding interrupt status bit is set in the watchdog status r...

Page 3678: ...counters prescaler timer are frozen and incrementation restarts after exiting from emulation mode 20 4 3 13 Accessing Watchdog Timer Registers Posted nonposted selection applies only to functional registers that require synchronization on from the timer functional clock domain WDTi_FCLK For write read operation the following registers are affected WDT_WCLR WDT_WCRR WDT_WLDR WDT_WTGR WDT_WDLY WDT_W...

Page 3679: ... Global Initialization Table 20 107 lists the steps for initializing the watchdog timer module when the module is to be used for the first time Table 20 107 Watchdog Timer Module Global Initialization Step Register Bit Field Programming Model Value Execute software reset WDT_WDSC 1 SOFTRESET 1 Wait until reset release WDT_WDSC 1 SOFTRESET 0 Enable delay interrupt WDT_WIRQENSET 1 ENABLE_DLY 1 Enabl...

Page 3680: ...rs have the same functionality The WDT_WIER register is used for software backward compatibility The WDT_WIRQSTATRAW and WDT_WIRQSTAT registers give the same information when read The WDT_WIRQSTATRAW register is used for debug 20 4 4 1 WATCHDOG_TIMER Registers Table 20 111 lists the memory mapped registers for the WATCHDOG_TIMER All register offset addresses not listed in Table 20 111 should be co...

Page 3681: ...1 48h WDT_WSPR Watchdog Start Stop Register Section 20 4 4 1 12 54h WDT_WIRQSTATRAW Watchdog Raw Interrupt Status Register Section 20 4 4 1 13 58h WDT_WIRQSTAT Watchdog Interrupt Status Register Section 20 4 4 1 14 5Ch WDT_WIRQENSET Watchdog Interrupt Enable Set Register Section 20 4 4 1 15 60h WDT_WIRQENCLR Watchdog Interrupt Enable Clear Register Section 20 4 4 1 16 3681 SPRUH73H October 2011 Re...

Page 3682: ...6 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REVISION R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 112 WDT_WIDR Register Field Descriptions Bit Field Type Reset Description 31 0 REVISION R 0h IP Revision 3682 Timers SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments...

Page 3683: ... it is out of IDLE state 0x0 Force idle mode local target s idle state follows acknowledges the system s idle requests unconditionally i e regardless of the IP module s internal requirements Backup mode for debug only 0x1 No idle mode local target never enters idle state Backup mode for debug only 0x2 Smart idle mode local target s idle state eventually follows acknowledges the system s idle reque...

Page 3684: ... R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved RESETDONE R 0h R 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 114 WDT_WDST Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 RESETDONE R 1h Internal module reset monitoring 0x0 Internal module reset is ongoing 0x1 Reset completed 3684 Timers SPRUH73H O...

Page 3685: ...Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 115 WDT_WISR Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 DLY_IT_FLAG R W 0h Pending delay interrupt status 0x0x0 W Status unchanged 0x0x0 R No delay interrupt pending 0x0x1 W Status bit cleared 0x0x1 R Delay interrupt pending 0 OVF_IT_FLAG R W 0h Pending overflow interrupt status 0...

Page 3686: ...rved DLY_IT_ENA OVF_IT_ENA R 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 116 WDT_WIER Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 DLY_IT_ENA R W 0h Delay interrupt enable disable 0x0 Disable delay interrupt 0x1 Enable delay interrupt 0 OVF_IT_ENA R W 0h Overflow interrupt enable disable 0x0 Disabl...

Page 3687: ...te R Read only W1toCl Write 1 to clear bit n value after reset Table 20 117 WDT_WCLR Register Field Descriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 PRE R W 1h Prescaler enable disable configuration 0x0 Prescaler disabled 0x1 Prescaler enabled 4 2 PTV R W 0h Prescaler value The timer counter is prescaled with the value 2 PTV Example PTV 3 then counter increases value if started a...

Page 3688: ...26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIMER_COUNTER R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 118 WDT_WCRR Register Field Descriptions Bit Field Type Reset Description 31 0 TIMER_COUNTER R W 0h Value of the timer counter register 3688 Timers SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedbac...

Page 3689: ...25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIMER_LOAD R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 119 WDT_WLDR Register Field Descriptions Bit Field Type Reset Description 31 0 TIMER_LOAD R W 0h Value of the timer load register 3689 SPRUH73H October 2011 Revised April 2013 Timers Submit Documentation Feedback Copyright ...

Page 3690: ...T_WTGR Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TTGR_VALUE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 120 WDT_WTGR Register Field Descriptions Bit Field Type Reset Description 31 0 TTGR_VALUE R W 0h Value of the trigger register 3690 Timers SPRUH73H October 2011 Revised April 2013 Submit Do...

Page 3691: ...escriptions Bit Field Type Reset Description 31 6 Reserved R 0h 5 W_PEND_WDLY R 0h Write pending for register WDLY 0x0 No register write pending 0x1 Register write pending 4 W_PEND_WSPR R 0h Write pending for register WSPR 0x0 No register write pending 0x1 Register write pending 3 W_PEND_WTGR R 0h Write pending for register WTGR 0x0 No register write pending 0x1 Register write pending 2 W_PEND_WLD...

Page 3692: ...WDT_WDLY Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDLY_VALUE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 122 WDT_WDLY Register Field Descriptions Bit Field Type Reset Description 31 0 WDLY_VALUE R W 0h Value of the delay register 3692 Timers SPRUH73H October 2011 Revised April 2013 Submit Do...

Page 3693: ...ister 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WSPR_VALUE R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 123 WDT_WSPR Register Field Descriptions Bit Field Type Reset Description 31 0 WSPR_VALUE R W 0h Value of the start stop register 3693 SPRUH73H October 2011 Revised April 2013 Timers Submit Documenta...

Page 3694: ... Reserved R 0h 7 6 5 4 3 2 1 0 Reserved EVENT_DLY EVENT_OVF R 0h R W1S 0h R W1S 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 124 WDT_WIRQSTATRAW Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 EVENT_DLY R W1S 0h Settable raw status for delay event 0x0x0 W No action 0x0x0 R No event pending 0x0x1 W Set event debug 0x...

Page 3695: ... 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved EVENT_DLY EVENT_OVF R 0h R W1C 0h R W1C 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 125 WDT_WIRQSTAT Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 EVENT_DLY R W1C 0h Clearable enabled status for delay event 0x0x0 W No action 0x0x0 R No enabled event pendi...

Page 3696: ...4 3 2 1 0 Reserved ENABLE_DLY ENABLE_OVF R 0h R W1S 0h R W1S 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 126 WDT_WIRQENSET Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 ENABLE_DLY R W1S 0h Enable for delay event 0x0x0 W No action 0x0x0 R Interrupt disabled masked 0x0x1 W Enable interrupt 0x0x1 R Interrupt enabled...

Page 3697: ...5 4 3 2 1 0 Reserved ENABLE_DLY ENABLE_OVF R 0h R W1C 0h R W1C 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 20 127 WDT_WIRQENCLR Register Field Descriptions Bit Field Type Reset Description 31 2 Reserved R 0h 1 ENABLE_DLY R W1C 0h Enable for delay event 0x0x0 W No action 0x0x0 R Interrupt disabled masked 0x0x1 W Disable interrupt 0x0x1 R Interrupt enab...

Page 3698: ...scribes the I2C of the device Topic Page 21 1 Introduction 3699 21 2 Integration 3700 21 3 Functional Description 3702 21 4 I2C Registers 3716 3698 I2C SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3699: ...and generates the clock signals to permit that transfer During this transfer any device addressed by this master is considered a slave 21 1 1 I2C Features The general features of the I2C controller are Compliant with Philips I2C specification version 2 1 Supports OmniVision Serial Camera Control Bus Protocol SCCB Supports standard mode up to 100K bits s and fast mode up to 400K bits s Multimaster ...

Page 3700: ...heral implements the multi master I2C bus which allows serial transfer of 8 bit data to from other I2C master slave devices through a two wire interface There are three I2C modules instantiations called I2C0 I2C1 and I2C2 The I2C0 module is located in the Wake up power domain Figure 21 1 and Figure 21 2 show examples of a system with multiple I2C compatible devices Figure 21 1 I2C0 Integration and...

Page 3701: ...ck From PRCM PISYSCLK 48 MHz PER_CLKOUTM2 4 pd_wkup_i2c0_gfclk Functional clock From PRCM I2C 1 2 Clock Signals PIOCPCLK 100 MHz CORE_CLKOUTM4 2 pd_per_l4ls_gclk Interface clock From PRCM PISYSCLK 48 MHz PER_CLKOUTM2 4 pd_per_ic2_fclk Functional clock From PRCM 21 2 3 I2C Pin List The external signals I2Cx_SDA I2Cx_SCL on the device use standard LVCMOS I Os and may not meet full compliance with th...

Page 3702: ...clock generator and the clock on the I2C_SCL pin and to synchronize data transfers with masters of different clock speeds A prescaler to divide down the input clock that is driven to the I2C peripheral A noise filter on each of the two pins I2C_SDA and I2C_SCL An arbitrator to handle arbitration between the I2C peripheral when it is a master and another master Interrupt generation logic so that an...

Page 3703: ...he same action on the module logic as the system bus reset All registers are reset to power up reset values The I2C_EN bit in the I2C_CON register can be used to hold the I2C module in reset When the system bus reset is removed PIRSTNA 1 I2C_EN 0 keeps the functional part of I2C module in reset state and all configuration registers can be accessed I2C_EN 0 does not reset the registers to power up ...

Page 3704: ...ata allowed I2Cx_SDA I2Cx_SCL Functional Description www ti com Figure 21 5 Bit Transfer on the I2C Bus 3704 I2C SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3705: ...e number of bytes that can be transmitted or received is restricted by the value programmed in the DCOUNT register The data is transferred with the most significant bit MSB first Each byte is followed by an acknowledge bit from the I2C module if it is in receiver mode Figure 21 7 I2C Data Transfer The I2C module supports two data formats as shown in Figure 21 8 7 bit 10 bit addressing format 7 bit...

Page 3706: ...e master receiver is entered after the slave address byte and bit R W_ has been transmitted if R W_ is high Serial data bits received on bus line SDA are shifted in synch with the self generated clock pulses on SCL The clock pulses are inhibited and SCL held low when the intervention of the processor is required ROVR after a byte has been transmitted At the end of a transfer it generates the stop ...

Page 3707: ... overrules the other devices At this high low transition the clock generators of the other devices are forced to start generation of their own low period The clock line is then held low by the device with the longest low period while the other devices that finish their low periods must wait for the clock line to be released before starting their high periods A synchronized signal on the clock line...

Page 3708: ...These 12 interrupts are accompanied with 12 interrupt masks and flags defined in the I2C_IRQENABLE_SET and respectively I2C_IRQSTATUS_RAW registers Note that all these 12 interrupt events are sharing the same hardware interrupt line Addressed As Slave interrupt AAS is generated to inform the Local Host that an external master addressed the module as a slave When this interrupt occurs the CPU can c...

Page 3709: ... the correct value to clear the interrupt flag 21 3 12 DMA Events The I2C module can generate two DMA requests events read I2C_DMA_RX and write I2C_DMA_TX that can be used by the DMA controller to synchronously read received data from the I2C_DATA or write transmitted data to the I2C_DATA register The DMA read and write requests are generated in a similar manner as RRDY and XRDY respectively The I...

Page 3710: ...igured to read an amount of bytes equal with the value of the RX FIFO threshold 1 Figure 21 12 Transmit FIFO Interrupt Request Generation Note that in the figure above the XRDY Condition illustrates that the condition for generating a XRDY interrupt is achieved The interrupt request is generated when this condition is achieved when TX FIFO is empty or the TX FIFO threshold is not reached and there...

Page 3711: ...AW RDR and XDR can also be polled if draining feature must be used The XRDY and RRDY flags are accurately reflecting the interrupt conditions mentioned in Interrupt Mode This mode is an alternative to the FIFO interrupt mode of operation where the status of the receiver and transmitter is automatically known by means of interrupts sent to the CPU 21 3 14 3 FIFO DMA Mode Operation In receive mode a...

Page 3712: ... Feature subsection for additional details According to the desired operation mode the programmer must set the FIFO thresholds according to the following table note that only the interface OCP side thresholds can be programmed the I2C side thresholds are default equals to 1 Note that the thresholds must be set consistent with the DMA channel length In I2C Slave RX Mode the Local Host can program t...

Page 3713: ...al master requests a byte and the FIFO is empty However in this case the TX FIFO will require to be cleared at the end of the transfer The I2C module offers the possibility to the user to clear the RX or TX FIFO This is achieved through I2C_BUF RXFIFO_CLR and I2C_BUF TXFIFO_CLR registers which act like software reset for the FIFOs In DMA mode these bits will also reset the DMA state machines The F...

Page 3714: ...XTRSH the transmit draining interrupt I2C_IRQSTATUS_RAW XDR will be asserted to inform the local host that it can read the amount of data remained to be written in the TX FIFO I2C_BUFSTAT TXSTAT The CPU will need to write the required number of data bytes specified by TXSTAT value or re configure the DMA controller with the required value in order to transfer the last bytes to the FIFO Note that i...

Page 3715: ...ceived data in the data receive register I2C_DATA Use draining feature I2C_IRQSTATUS_RAW RDR enabled by I2C_IRQENABLE_SET RDR_IE if the transfer length is not equal with FIFO threshold 21 3 15 6 Transmit Data Poll the transmit data ready interrupt flag bit XRDY in the I2C status register I2C_IRQSTATUS_RAW use the XRDY interrupt I2C_IRQENABLE_SET XRDY_IE set or use the DMA TX I2C_BUF XDMA_EN set to...

Page 3716: ...QENABLE_SET Section 21 4 1 6 30h I2C_IRQENABLE_CLR Section 21 4 1 7 34h I2C_WE Section 21 4 1 8 38h I2C_DMARXENABLE_SET Section 21 4 1 9 3Ch I2C_DMATXENABLE_SET Section 21 4 1 10 40h I2C_DMARXENABLE_CLR Section 21 4 1 11 44h I2C_DMATXENABLE_CLR Section 21 4 1 12 48h I2C_DMARXWAKE_EN Section 21 4 1 13 4Ch I2C_DMATXWAKE_EN Section 21 4 1 14 90h I2C_SYSS Section 21 4 1 15 94h I2C_BUF Section 21 4 1 1...

Page 3717: ... 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 21 9 I2C_REVNB_LO Register Field Descriptions Bit Field Type Reset Description 31 16 Reserved R 0h 15 11 RTL R 0h RTL version 10 8 MAJOR R 0h Major Revision This field changes when there is a major feature change This field does not change due to bug fix or minor feature change 7 6 CUSTOM R 0h Indicate...

Page 3718: ...R 0h R 0h 7 6 5 4 3 2 1 0 FUNC R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 21 10 I2C_REVNB_HI Register Field Descriptions Bit Field Type Reset Description 31 16 Reserved R 0h 15 14 SCHEME R 0h Used to distinguish between old Scheme and current Spare bit to encode future schemes 13 12 Reserved R 0h 11 0 FUNC R 0h Function Indicates a software compati...

Page 3719: ...s Note If the System functional Clock is cut off the module will assert a WakeUp event when it asynchronously detects a Start Condition on the I2C Bus Note that in this case the first transfer will not be taken into account by the module NACK will be detected by the external master 0x0 Both clocks can be cut off 0x1 Only Interface OCP clock must be kept active system clock can be cut off 0x2 Only ...

Page 3720: ... 0 Value after reset is low 0x0 Normal mode 0x1 The module is reset 0 AUTOIDLE R W 0h Autoidle bit When this bit is set to 1 the module activates its own idle mode mechanism By evaluating its internal state the module can decide to gate part of his internal clock tree in order to improve the overall power consumption Value after reset is high 0x0 Auto Idle mechanism is disabled 0x1 Auto Idle mecha...

Page 3721: ...s I2C Master Transmit mode only This read clear only bit is set to 1 when the module is configured as a master transmitter the TX FIFO level is below the configured threshold TXTRSH and the amount of data still to be transferred is less than TXTRSH When this bit is set to 1 by the core CPU must read the I2C_BUFSTAT TXSTAT register in order to check the amount of data that need to be written in the...

Page 3722: ... register A write 0 has no effect Value after reset is low 0x0 Receive draining inactive 0x1 Receive draining enabled 12 BB R 0h This read only bit indicates the state of the serial bus In slave mode on reception of a start condition the device sets BB to 1 BB is cleared to 0 after reception of a stop condition In master mode the software controls BB To start a transmission with a start condition ...

Page 3723: ...to this register writing 0 has no effect The other way is if the interrupt was not enabled the AAS bit is reset to 0 by restart or stop Value after reset is low 0x0 No action 0x1 Address recognized 8 BF R W 0h I2C mode only This read only bit is set to 1 by the device when the I2C bus became free after a transfer is ended on the bus stop condition detected This interrupt informs the Local Host tha...

Page 3724: ...the WakeUp enable for restoring the Active Mode of the module On the I2C line the external master which generated the transfer will detect this behavior as a not acknowledge to the address phase and will possibly restart the transfer The CPU can only clear this bit by writing a 1 into this register Writing 0 has no effect Value after reset is low 0x0 No action 0x1 Start Condition detected 5 GC R W...

Page 3725: ...riting a 1 into this register Writing 0 has no effect Note If the DMA transmit mode is enabled I2C_BUF XDMA_EN is set together with I2C_DMATXENABLE_SET this bit is forced to 0 and no interrupt will be generated instead a DMA TX request to the main DMA controller of the system is generated Value after reset is low 0x0 Transmission ongoing 0x1 Transmit data ready 3 RRDY R W 0h Receive mode only I2C ...

Page 3726: ...ear only No Acknowledge flag bit is set when the hardware detects No Acknowledge has been received When a NACK event occurs on the bus this bit is set to 1 the core automatically ends the transfer and clears the MST STP bits in the I2C_CON register and the I2C becomes a slave Clearing the FIFOs from remaining data might be required The CPU can only clear this bit by writing a 1 into this register ...

Page 3727: ... NACK AL R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 21 13 I2C_IRQSTATUS Register Field Descriptions Bit Field Type Reset Description 31 15 Reserved R 0h 14 XDR R W 0h Transmit draining IRQ enabled status 0x0 Transmit draining inactive 0x1 Transmit draining enabled 13 RDR R W 0h Receive draining IRQ...

Page 3728: ...ver mode a new data is able to be read When set to 1 by core an interrupt is signaled to MPUSS Write 1 to clear 0x0 No data available 0x1 Receive data available 2 ARDY R W 0h Register access ready IRQ enabled status When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write 1 to clear 0x0 Module busy 0x1 A...

Page 3729: ...rupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT XDR 0x0 Transmit draining interrupt disabled 0x1 Transmit draining interrupt enabled 13 RDR_IE R W 0h Receive draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT RDR 0x0 Receive draining interrupt disabled 0x1 Receive draining interrupt enabled 12 Reserved R 0h 11 ROVR R W 0h Receive overrun...

Page 3730: ... 0h Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT RRDY 0x0 Receive data ready interrupt disabled 0x1 Receive data ready interrupt enabled 2 ARDY_IE R W 0h Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT ARDY 0x0 Register access ready interrupt disabled 0x1 Register access ready interrupt enabled ...

Page 3731: ...Mask or unmask the interrupt signaled by bit in I2C_STAT XDR 0x0 Transmit draining interrupt disabled 0x1 Transmit draining interrupt enabled 13 RDR_IE R W 0h Receive draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT RDR 0x0 Receive draining interrupt disabled 0x1 Receive draining interrupt enabled 12 Reserved R 0h 11 ROVR R W 0h Receive overrun enable clear ...

Page 3732: ... 0h Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT RRDY 0x0 Receive data ready interrupt disabled 0x1 Receive data ready interrupt enabled 2 ARDY_IE R W 0h Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT ARDY 0x0 Register access ready interrupt disabled 0x1 Register access ready interrupt enable...

Page 3733: ...1toCl Write 1 to clear bit n value after reset Table 21 16 I2C_WE Register Field Descriptions Bit Field Type Reset Description 31 15 Reserved R 0h 14 XDR_WE R W 0h Transmit draining wakeup enable This read write bit is used to enable or disable wakeup signal generation when I2C module is in idle mode the TX FIFO level is below the threshold and the amount of data left to be transferred is less tha...

Page 3734: ... not enable this wakeup since the module has other synchronously detected WakeUp event that might be used to exit from idle mode only if the detected transfer is accessing the I2C module 0x0 Start condition wakeup disabled 0x1 Start condition wakeup enabled 5 GC_WE R W 0h General call IRQ wakeup enable This read write bit is used to enable or disable wakeup signal generation when I2C module is in ...

Page 3735: ...it is used to enable or disable wakeup signal generation when I2C module is configured as a master and it loses the arbitration This wake up is very useful when the module is configured as a master transmitter all the necessary data is provided in the FIFO Tx STT is enabled and the module enters in Idle Mode If the module loses the arbitration an Arbitration Lost event is raised and the module nee...

Page 3736: ...ld should also be set to 1 to enable a receive DMA request Figure 21 24 I2C_DMARXENABLE_SET Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved DMARX_ENABLE_SE T R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 21 17 I2C_DMARXENABLE_SET Register Field Des...

Page 3737: ... should also be set to 1 to enable a transmit DMA request Figure 21 25 I2C_DMATXENABLE_SET Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved DMATX_TRANSMIT_ SET R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 21 18 I2C_DMATXENABLE_SET Register Field De...

Page 3738: ...e is not modified Figure 21 26 I2C_DMARXENABLE_CLR Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved DMARX_ENABLE_CL EAR R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 21 19 I2C_DMARXENABLE_CLR Register Field Descriptions Bit Field Type Reset Descript...

Page 3739: ...ue is not modified Figure 21 27 I2C_DMATXENABLE_CLR Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved DMARX_ENABLE_CL EAR R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 21 20 I2C_DMATXENABLE_CLR Register Field Descriptions Bit Field Type Reset Descrip...

Page 3740: ...15 Reserved R 0h 14 XDR R W 0h Transmit draining wakeup set 0x0 Transmit draining interrupt disabled 0x1 Transmit draining interrupt enabled 13 RDR R W 0h Receive draining wakeup set 0x0 Receive draining interrupt disabled 0x1 Receive draining interrupt enabled 12 Reserved R 0h 11 ROVR R W 0h Receive overrun wakeup set 0x0 Receive overrun interrupt disabled 0x1 Receive draining interrupt enabled 1...

Page 3741: ...ARDY R W 0h Register access ready IRQ wakeup set 0x0 Register access ready wakeup disabled 0x1 Register access ready wakeup enabled 1 NACK R W 0h No acknowledgment IRQ wakeup set 0x0 Not Acknowledge wakeup disabled 0x1 Not Acknowledge wakeup enabled 0 AL R W 0h Arbitration lost IRQ wakeup set 0x0 Arbitration lost wakeup disabled 0x1 Arbitration lost wakeup enabled 3741 SPRUH73H October 2011 Revise...

Page 3742: ...15 Reserved R 0h 14 XDR R W 0h Transmit draining wakeup set 0x0 Transmit draining interrupt disabled 0x1 Transmit draining interrupt enabled 13 RDR R W 0h Receive draining wakeup set 0x0 Receive draining interrupt disabled 0x1 Receive draining interrupt enabled 12 Reserved R 0h 11 ROVR R W 0h Receive overrun wakeup set 0x0 Receive overrun interrupt disabled 0x1 Receive draining interrupt enabled 1...

Page 3743: ...ARDY R W 0h Register access ready IRQ wakeup set 0x0 Register access ready wakeup disabled 0x1 Register access ready wakeup enabled 1 NACK R W 0h No acknowledgment IRQ wakeup set 0x0 Not Acknowledge wakeup disabled 0x1 Not Acknowledge wakeup enabled 0 AL R W 0h Arbitration lost IRQ wakeup set 0x0 Arbitration lost wakeup disabled 0x1 Arbitration lost wakeup enabled 3743 SPRUH73H October 2011 Revise...

Page 3744: ...after reset Table 21 23 I2C_SYSS Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 RDONE R W 0h Reset done bit This read only bit indicates the state of the reset in case of hardware reset global software reset I2C_SYSC SRST or partial software reset I2C_CON I2C_EN The module must receive all its clocks before it can grant a reset completed status Value after reset ...

Page 3745: ...he core Value after reset is low 0x0 Receive DMA channel disabled 0x1 Receive DMA channel enabled 14 RXFIFO_CLR R W 0h Receive FIFO clear When set receive FIFO is cleared hardware reset for RX FIFO generated This bit is automatically reset by the hardware During reads it always returns 0 Value after reset is low 0x0 Normal mode 0x1 Rx FIFO is reset 13 8 RXTRSH R W 0h Threshold value for FIFO buffe...

Page 3746: ...During reads it always returns 0 Value after reset is low 0x0 Normal mode 0x1 Tx FIFO is reset 5 0 TXTRSH R W 0h Threshold value for FIFO buffer in TX mode The Transmit Threshold value is used to specify the trigger level for data transfers The value is specified from the OCP point of view Value after reset is 00h Note 1 programmed threshold cannot exceed the actual depth of the FIFO Note 2 the th...

Page 3747: ...the number of bytes that are yet to be received or sent A read into DCOUNT returns the initial value only before a start condition and after a stop condition When DCOUNT reaches 0 the core generates a stop condition if a stop condition was specified I2C_CON STP 1 and the ARDY status flag is set to 1 in the I2C_IRQSTATUS_RAW register Note that DCOUNT must not be reconfigured after I2C_CON STT was e...

Page 3748: ...t Field Type Reset Description 31 8 Reserved R 0h 7 0 DATA R W 0h Transmit Receive data FIFO endpoint When read this register contains the received I2C data When written this register contains the byte value to transmit over the I2C data In SYSTEST loop back mode I2C_SYSTEST TMODE 11 this register is also the entry receive point for the data Values after reset are unknown all 8 bits Note A read ac...

Page 3749: ... I2C controller is not enabled and reset When 0 receive and transmit FIFOs are cleared and all status bits are set to their default values All configuration registers I2C_IRQENABLE_SET I2C_IRQWAKE_SET I2C_BUF I2C_CNT I2C_CON I2C_OA I2C_SA I2C_PSC I2C_SCLL and I2C_SCLH are not reset they keep their initial values and can be accessed The CPU must set this bit to 1 for normal operation Value after re...

Page 3750: ...follows MST 0 TRX x Operating Mode Slave receiver MST 0 TRX x Operating Mode Slave transmitter MST 1 TRX 0 Operating Modes Master receiver MST 1 TRX 0 Operating Modes Master transmitter 0x0 Receiver mode 0x1 Transmitter mode 8 XSA R W 0h Expand slave address I2C mode only When set this bit expands the slave address to 10 bit Value after reset is low 0x0 7 bit address mode 0x1 10 bit address mode 7...

Page 3751: ...or stop condition detected 0x1 Stop condition queried 0 STT R W 0h Start condition I2C master mode only This bit can be set to a 1 by the CPU to generate a start condition It is reset to 0 by the hardware after the start condition has been generated The start stop bits can be configured to generate different transfer formats Value after reset is low Note DCOUNT is data count value in I2C_CNT regis...

Page 3752: ... 0h 15 14 13 12 11 10 9 8 Reserved OA R 0h R W 0h 7 6 5 4 3 2 1 0 OA R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 21 28 I2C_OA Register Field Descriptions Bit Field Type Reset Description 31 10 Reserved R 0h 9 0 OA R W 0h Own address This field specifies either A 10 bit address coded on OA 9 0 when XOA Expand Own Address I2C_CON 7 is set to 1 or A ...

Page 3753: ... 15 14 13 12 11 10 9 8 Reserved SA R 0h R W 0h 7 6 5 4 3 2 1 0 SA R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 21 29 I2C_SA Register Field Descriptions Bit Field Type Reset Description 31 10 Reserved R 0h 9 0 SA R W 0h Slave address This field specifies either A 10 bit address coded on SA 9 0 when XSA Expand Slave Address I2C_CON 8 is set to 1 or A...

Page 3754: ...3 2 1 0 PSC R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 21 30 I2C_PSC Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 PSC R W 0h Fast Standard mode prescale sampling clock divider value The core uses this 8 bit value to divide the system clock SCLK and generates its own internal sampling clock ICLK for Fast and ...

Page 3755: ... 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 SCLL R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 21 31 I2C_SCLL Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 SCLL R W 0h Fast Standard mode SCL low time I2C master mode only FS This 8 bit value is used to generate the SCL low ti...

Page 3756: ...20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 SCLH R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 21 32 I2C_SCLH Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R 0h 7 0 SCLH R W 0h Fast Standard mode SCL low time I2C master mode only FS This 8 bit value is used to generate the SCL high ti...

Page 3757: ... 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 ST_EN FREE TMODE SSB Reserved SCL_I_FUNC R W 0h R W 0h R W 0h R W 0h R 0h R 0h 7 6 5 4 3 2 1 0 SCL_O_FUNC SDA_I_FUNC SDA_O_FUNC Reserved SCL_I SCL_O SDA_I SDA_O R 0h R 0h R 0h R 0h R 0h R 0h R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 21 33 I2C_SYSTEST Register Field Descriptions Bit ...

Page 3758: ...0h Test mode select In normal functional mode ST_EN 0 these bits are don t care They are always read as 00 and a write is ignored In system test mode ST_EN 1 these bits can be set according to the following table to permit various system tests Values after reset are low 2 bits SCL counter test mode in this mode the SCL pin is driven with a permanent clock as if mastered with the parameters set in ...

Page 3759: ...ive both in functional and test mode Value after reset is low 0x0 Driven 0 to SDA line 0x1 Driven 1 to SDA line 4 Reserved R 0h 3 SCL_I R 0h SCL line sense input value In normal functional mode ST_EN 0 this read only bit always reads 0 In system test mode ST_EN 1 and TMODE 11 this read only bit returns the logical state taken by the SCL line either 1 or 0 Value after reset is low 0x0 Read 0 from S...

Page 3760: ... bit is don t care It reads as 0 and a write is ignored In system test mode ST_EN 1 and TMODE 11 a 0 forces a low level on the SDA line and a 1 puts the I2C output driver to a high impedance state Value after reset is low 0x0 Write 0 to SDA line 0x1 Write 1 to SDA line 3760 I2C SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated...

Page 3761: ...d only bit indicates the internal FIFO buffer depth Value after reset is given by the boundary module generic parameter 0x0 8 bytes FIFO 0x1 16 bytes FIFO 0x2 32 bytes FIFO 0x3 64 bytes FIFO 13 8 RXSTAT R 0h RX buffer status This read only field indicates the number of bytes to be transferred from the FIFO at the end of the I2C transfer when RDR is asserted It corresponds to the level indication o...

Page 3762: ...4 13 12 11 10 9 8 Reserved OA1 R 0h R W 0h 7 6 5 4 3 2 1 0 OA1 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 21 35 I2C_OA1 Register Field Descriptions Bit Field Type Reset Description 31 10 Reserved R 0h 9 0 OA1 R W 0h Own address 1 This field specifies either A 10 bit address coded on OA1 9 0 when XOA1 Expand Own Address 1 XOA1 I2C_CON 6 is set to ...

Page 3763: ...4 13 12 11 10 9 8 Reserved OA2 R 0h R W 0h 7 6 5 4 3 2 1 0 OA2 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 21 36 I2C_OA2 Register Field Descriptions Bit Field Type Reset Description 31 10 Reserved R 0h 9 0 OA2 R W 0h Own address 2 This field specifies either A 10 bit address coded on OA2 9 0 when XOA1 Expand Own Address 2 XOA2 I2C_CON 5 is set to ...

Page 3764: ...4 13 12 11 10 9 8 Reserved OA3 R 0h R W 0h 7 6 5 4 3 2 1 0 OA3 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 21 37 I2C_OA3 Register Field Descriptions Bit Field Type Reset Description 31 10 Reserved R 0h 9 0 OA3 R W 0h Own address 2 This field specifies either A 10 bit address coded on OA3 9 0 when XOA3 Expand Own Address 3 XOA3 I2C_CON 4 is set to ...

Page 3765: ...es to the Local Host that an external master using the corresponding own address addressed the module Value after reset is low 0x0 Own address inactive 0x1 Own address active 2 OA2_ACT R 0h Own address 2 active When a bit location is set to 1 by the core it signalizes to the Local Host that an external master using the corresponding own address addressed the module Value after reset is low 0x0 Own...

Page 3766: ...ng the corresponding own address addresses the core the core will block the I2C clock right after the address phase For releasing the I2C clock the CPU must write 0 in the corresponding field Value after reset is low 0x0 I2C clock released 0x1 I2C clock blocked 2 OA2_EN R W 0h Enable I2C clock blocking for own address 2 When the CPU sets a bit location to 1 if an external master using the correspo...

Page 3767: ... if an external master using the corresponding own address addresses the core the core will block the I2C clock right after the address phase For releasing the I2C clock the CPU must write 0 in the corresponding field Value after reset is low 0x0 I2C clock released 0x1 I2C clock blocked 3767 SPRUH73H October 2011 Revised April 2013 I2C Submit Documentation Feedback Copyright 2011 2013 Texas Instru...

Page 3768: ...ribes the McASP of the device Topic Page 22 1 Introduction 3769 22 2 Integration 3771 22 3 Functional Description 3773 22 4 McASP Registers 3826 3768 Multichannel Audio Serial Port McASP SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3769: ...onnection to audio analog to digital converters ADC digital to analog converters DAC codec digital audio interface receiver DIR and S PDIF transmit physical layer components Wide variety of I2S and similar bit stream format Integrated digital audio interface transmitter DIT supports up to 10 transmit pins S PDIF IEC60958 1 AES 3 formats Enhanced channel status user data RAM 384 slot TDM with exter...

Page 3770: ...ode for McASP additional features of the transmitter are Transmit only mode 384 time slots subframe per frame Bi phase encoded 3 3 V output Support for consumer and professional applications Channel status RAM 384 bits User data RAM 384 bits Separate valid bit V for subframe A B In I2S mode the transmit and receive sections can support simultaneous transfers on up to all serial data pins operating...

Page 3771: ...gure 22 1 McASP0 1 Integration 22 2 1 McASP Connectivity Attributes The general connectivity attributes for the McASP modules are summarized in Table 22 1 Table 22 1 McASP Connectivity Attributes Attributes Type Power Domain Peripheral Domain Clock Domain PD_PER_L3S_GCLK OCP Clock PD_PER_MCASP_FCLK Aux Clock Reset Signals PER_DOM_RST_N Idle Wakeup Signals Smart Idle Interrupt Requests 1 Transmit I...

Page 3772: ...nals are shown in Table 22 3 Table 22 3 McASP Pin List Pin Type Description McASPx_AXR 3 0 I O Audio transmit receive pin McASPx_ACLKX 1 I O Transmit clock McASPx_FSX 1 I O Frame synch for transmit McASPx_AHCLKX 1 I O High speed transmit clock McASPx_ACLKR 1 I O Receive clock McASPx_FSR 1 I O Frame synch for receive McASPx_AHCLKR 1 I O High speed receive clock 1 These signals are also used as inpu...

Page 3773: ...udes the following pins Serializers Data pins AXRn Up to four pins Transmit clock generator AHCLKX McASP transmit high frequency master clock ACLKX McASP transmit bit clock Transmit Frame Sync Generator AFSX McASP transmit frame sync or left right clock LRCLK Receive clock generator AHCLKR McASP receive high frequency master clock ACLKR McASP receive bit clock Receive Frame Sync Generator AFSR McA...

Page 3774: ...ntrol Clock check circuit format unit Data port DAT Configuration bus CFG L3 Slow Interconnect L4 Standard Interconnect AXR15 Serializer 15 Functional Description www ti com 22 3 2 Functional Block Diagram Figure 22 2 shows the major blocks of the McASP The McASP has independent receive transmit clock generators and frame sync generators Figure 22 2 McASP Block Diagram A McASP has 6 serial data pi...

Page 3775: ... ti com Functional Description 22 3 2 1 System Level Connections Figure 22 3 through Figure 22 7 show examples of McASP usage in digital audio encoder decoder systems Figure 22 3 McASP to Parallel 2 Channel DACs Figure 22 4 McASP to 6 Channel DAC and 2 Channel DAC 3775 SPRUH73H October 2011 Revised April 2013 Multichannel Audio Serial Port McASP Submit Documentation Feedback Copyright 2011 2013 Te...

Page 3776: ...coded I2S PWM generator Stereo I2S Digital amp Digital amp Digital Digital amp amp generator PWM generator generator PWM PWM Functional Description www ti com Figure 22 5 McASP to Digital Amplifier Figure 22 6 McASP as Digital Audio Encoder Figure 22 7 McASP as 16 Channel Digital Processor 3776 Multichannel Audio Serial Port McASP SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedb...

Page 3777: ...e data bits are grouped into words and slots as defined in Section 22 3 4 The slots are also commonly referred to as time slots or channels in TDM terminology A frame consists of multiple slots or channels Each TDM frame is defined by the frame sync signal AFSX or AFSR Data transfer is continuous and periodic since the TDM format is most commonly used to communicate with data converters that opera...

Page 3778: ...total of 6 channels within each frame period Alternatively a similar six channel DAC may be designed to use three serial data pins AXR 0 1 2 transferring two channels of data on each pin during each sample period In the latter case if the sample period remains the same the serial clock can run three times slower than the former case The McASP is flexible enough to support either type of DAC 22 3 3...

Page 3779: ...by two transitions of the signal within a time interval which corresponds to a cell with logical states 01 or 10 A logical 0 is represented by one transition within a time interval which corresponds to a cell with logical states 00 or 11 In addition the logical level at the start of a cell is inverted from the level at the end of the previous cell Figure 22 11 and Table 22 4 show how data is encod...

Page 3780: ... the user data channel U associated with the main data field in the subframe Time interval 30 carries the channel status information C associated with the main data field in the subframe The channel status indicates if the data in the subframe is digital audio or some other type of data Time interval 31 carries a parity bit P such that time intervals 4 31 carry an even number of 1s and an even num...

Page 3781: ...rial interface consists of three important components clock frame sync and data Figure 22 14 shows two of the three basic components the clock ACLK and the data AXRn Figure 22 14 does not specify whether the clock is for transmit ACLKX or receive ACLKR because the definitions of terms apply to both receive and transmit interfaces In operation the transmitter uses ACLKX as the serial clock and the ...

Page 3782: ...first pad zeros 87h as 8 bit word 12 bit slot d 87h as 8 bit word 12 bit slot left align MSB first pad with bit 7 e 87h as 8 bit word 12 bit slot right align MSB first pad with bit 4 f 87h as 8 bit word 12 bit slot left align LSB first pad with bit 7 g 87h as 8 bit word 12 bit slot right align LSB first pad with bit 4 h left align LSB first pad with bit 7 07h as 8 bit word 12 bit slot i right alig...

Page 3783: ... all data pins configured as outputs I2S Inter Integrated Sound protocol commonly used on audio interfaces The McASP supports the I2S protocol as part of the TDM mode when configured as a 2 slot frame Slot or For TDM format the term time slot is interchangeable with the term slot defined in this section For DIT format a Time Slot McASP time slot corresponds to a DIT subframe 22 3 5 Clock and Frame...

Page 3784: ...0 the CLKXP mux directly passes ACLKX to XCLK As a result the McASP shifts transmit data at the rising edge of ACLKX If CLKXP 1 the CLKX mux passes the inverted version of ACLKX to XCLK As a result the McASP shifts transmit data at the falling edge of ACLKX The transmit high frequency master clock AHCLKX may be either externally sourced from the AHCLKX pin or internally generated as selected by th...

Page 3785: ...erate synchronously from the ACLKX and AFSX signals This is achieved when the ASYNC bit in the transmit clock control register ACLKXCTL is cleared to 0 see Figure 22 18 The receiver may be configured with different polarity CLKRP and frame sync data delay options from those options of the transmitter The receive clock configuration is controlled by the following registers ACLKRCTL AHCLKRCTL Figure...

Page 3786: ... are Internally generated or externally generated Frame sync polarity rising edge or falling edge Frame sync width single bit or single word Bit delay 0 1 or 2 cycles before the first data bit The transmit frame sync pin is AFSX and the receive frame sync pin is AFSR A typical usage for these pins is to carry the left right clock LRCLK signal when transmitting and receiving stereo data Regardless ...

Page 3787: ... 22 6 Table 22 6 McASP Interface Signals Device Reset Pin I O Z RESET 0 Description Transmitter Control AHCLKX I O Z Input Transmit high frequency master clock AFSX I O Z Input Transmit frame sync or left right clock LRCLK ACLKX I O Z Input Transmit bit clock Receiver Control AHCLKR I O Z Input Receive high frequency master clock AFSR I O Z Input Receive frame sync or left right clock LRCLK ACLKR ...

Page 3788: ...ata For receive when generating the receive frame sync internally frame sync begins when the previous transmission has completed and when all the RBUF n for every serializer set to operate as a receiver has been read Figure 22 20 Burst Frame Sync Mode The control registers must be configured as follows for the burst transfer mode The burst mode specific bit fields are in bold face PFUNC The clock ...

Page 3789: ...r generate AHCLKR internally or receive AHCLKR as an input See Section 22 3 5 2 and Section 22 3 5 3 The control registers must be configured as follows for the TDM mode The TDM mode specific bit fields are in bold face PFUNC The clock frame data pins must be configured for McASP function PDIR The clock frame data pins must be configured to the direction desired PDOUT PDIN PDSET PDCLR Not applicab...

Page 3790: ...nsmit pins are automatically set to a high impedance state 0 or 1 during that slot as determined by bit DISMOD in SRCTL n Figure 22 21 shows when the transmit DMA event AXEVT is generated See Section 22 3 10 1 1 for details on data ready and the initialization period indication The transmit DMA event for an active time slot slot N is generated during the previous time slot slot N 1 regardless if t...

Page 3791: ...tems through an optical or coaxial cable The DIT mode only applies to serializers configured as transmitters not receivers See Section 22 3 3 2 for a description of the S PDIF format 22 3 8 3 1 Transmit DIT Encoding The McASP operation in DIT mode is basically identical to the 2 time slot TDM mode but the data transmitted is output as a biphase mark encoded bit stream with preamble channel status ...

Page 3792: ...r configurations required for DIT mode The DIT mode specific bit fields are in bold face PFUNC The data pins must be configured for McASP function If AHCLKX is used it must also be configured for McASP function PDIR The data pins must be configured as outputs If AHCLKX is used as an input reference it should be configured as input If internal clock source AUXCLK is used as the reference clock it m...

Page 3793: ...e CPU reads the transmit TDM slot counter to determine which word of the register is being used It is a requirement that the software avoid writing to the word of user data and channel status that are being used to encode the current time slot otherwise it will be indeterminate whether the old or new data is used to encode the bitstream The DIT subframe format is defined in Section 22 3 3 2 2 The ...

Page 3794: ...DITCSRB2 DITUDRA2 DITUDRB2 64 1 L M DITCSRA2 0 DITUDRA2 0 64 2 R W DITCSRB2 0 DITUDRB2 0 95 1 L M DITCSRA2 31 DITUDRA2 31 95 2 R W DITCSRB2 31 DITUDRB2 31 Defined by DITCSRA3 DITCSRB3 DITUDRA3 DITUDRB3 96 1 L M DITCSRA3 0 DITUDRA3 0 96 2 R W DITCSRB3 0 DITUDRB3 0 127 1 L M DITCSRA3 31 DITUDRA3 31 127 2 R W DITCSRB3 31 DITUDRB3 31 Defined by DITCSRA4 DITCSRB4 DITUDRA4 DITUDRB4 128 1 L M DITCSRA4 0 ...

Page 3795: ...ch is an alias of the XRBUF for receive When the processor reads from the RBUF the McASP passes the data from RBUF through the receive format unit and returns the formatted data to the processor For transmit the processor services the McASP by writing data into the XBUF register which is an alias of the XRBUF for transmit The data automatically passes through the transmit format unit before actual...

Page 3796: ...Bit mask and pad masks off bits performs sign extension Rotate right aligns data within word Bit reversal selects between MSB first or LSB first Figure 22 23 shows a block diagram of the receive formatting unit and Figure 22 24 shows the transmit formatting unit Note that the order in which data flows through the three stages is different between the transmit and receive formatting units Figure 22...

Page 3797: ...can occur until the respective state machine is released from reset See initialization sequence for details Section 22 3 12 The receive state machine is controlled by the RFMT register and it reports the McASP status and error conditions in the RSTAT register Similarly the transmit state machine is controlled by the XFMT register and it reports the McASP status and error conditions in the XSTAT re...

Page 3798: ...n to 0 Writing a 0 has no effect Applicable only when the pin is configured as GPIO output PFUNC n 1 and PDIR n 1 See the register descriptions in Section 22 4 for details on the mapping of each McASP pin to the register bits Figure 22 25 shows the pin control block diagram Figure 22 25 McASP I O Pin Control Block Diagram 22 3 9 6 1 McASP Pin Control Transmit and Receive You must correctly set the...

Page 3799: ...tion 22 3 10 1 4 and Section 22 3 14 2 22 3 10 1 1 Data Ready Status and Event Interrupt Generation 22 3 10 1 1 1 Transmit Data Ready The transmit data ready flag XDATA bit in the XSTAT register reflects the status of the XBUF register The XDATA flag is set when data is transferred from the XRBUF n buffers to the XRSR n shift registers indicating that the XBUF is empty and ready to accept new data...

Page 3800: ... 32 bit With the above setup we obtain the following parameters corresponding to Figure 22 26 Calculation of McASP system clock cycle System functional clock 26 MHz Therefore McASP system clock cycle 1 26MHz 38 5 ns Calculation of ACLKX clock cycle This example has two 32 bit slots per frame for a total of 64 bits per frame ACLKX clock cycle is 1 192 kHz 64 81 4 ns Time Slot between AXEVT events F...

Page 3801: ...STAT already has the RDATA flag set to 1 from a previous request the next transfer triggers another DMA request Since all serializers act in lockstep only one DMA event is generated to indicate that all active receive serializers are ready to receive new data Figure 22 27 shows the timing details of when AREVT is generated at the McASP boundary In this example as soon as the last bit bit A0 of Wor...

Page 3802: ...active and receive within each time slot Failure to do results in a buffer overrun condition Section 22 3 10 4 3 To perform internal transfers through the data port clear XBUSEL RBUSEL bit to 0 in the respective XFMT RFMT registers 22 3 10 1 3 Transfers Through the Configuration Bus CFG NOTE To perform internal transfers through the configuration bus set XBUSEL RBUSEL bit to 1 in the respective XF...

Page 3803: ...Transmission When the Write FIFO is disabled transmit DMA requests pass through directly from the McASP to the host DMA controller Whether the WFIFO is enabled or disabled the McASP generates transmit DMA requests as needed the AFIFO is invisible to the McASP When the Write FIFO is enabled transmit DMA requests from the McASP are sent to the AFIFO which in turn generates transmit DMA requests to t...

Page 3804: ... the host CPU reads the Read FIFO independent of a receive DMA request and the RFIFO at that time contains less than RNUMEVT words those words will be read correctly emptying the FIFO 22 3 10 2 2 1 Receive DMA Event Pacer The AFIFO may be configured to delay making a receive DMA request to the host until the Read FIFO contains a specified number of words In this situation the number of receive DMA...

Page 3805: ...d unit does allow for any number of significant digits For example a Q31 number may have 19 significant digits word and be transmitted in a 24 bit slot this would be formatted as a word size of 20 bits and a slot size of 24 bits However it is possible to set the bit mask unit to only pass the 19 most significant digits program the mask value to FFFF E000h The digits that are not significant can be...

Page 3806: ... Out MSB first LEFT aligned M M 1 L P P XRVRS 1 reverse P P L M 1 M REP Integer P L M P M 1 Data flow P P P P M M 1 L XROT SLOT P P f Out MSB first RIGHT aligned XRVRS 1 reverse P P M M 1 L P P L M 1 M REP Integer P L P M M 1 Data flow XROT 0 P L M P M 1 XRVRS 0 no reverse P L P M M 1 g Out LSB first LEFT aligned L M 1 M P P REP Integer P L M P M 1 Data flow P P P P M M 1 L XROT 32 SLOT WORD 32 XR...

Page 3807: ...of significant digits For example a Q31 number may have 19 significant digits word and be transmitted in a 24 bit slot this would be formatted as a word size of 20 bits and a slot size of 24 bits However it is possible to set the bit mask unit to only pass the 19 most significant digits program the mask value to FFFF E000h The digits that are not significant can be set to a selected pad value whic...

Page 3808: ...L M 1 P P RROT 0 M M 1 L P P M M 1 L P P RRVRS 0 no reverse RROT 0 M 1 P P M L RRVRS 1 reverse f In MSB first RIGHT aligned P P M M 1 L L M 1 M P P Data flow Data flow Data flow Data flow Data flow M 1 P P M L Data flow M 1 P P M RROT 32 SLOT L L M 1 M P P g In LSB first LEFT aligned RRVRS 0 no reverse M 1 P P M P P L RROT 32 WORD M 1 M 1 REP Integer P P M P P M L L Data flow P P L M 1 M h In LSB ...

Page 3809: ...rame sync occurs Current frame is not resynchronized The number of bits in the current frame is completed The next frame sync which occurs after the current frame is completed will be resynchronized 2 Late A late unexpected frame sync occurs when there is a gap or delay between the last bit of the previous frame and the first bit of the next frame When a late unexpected frame sync occurs as soon a...

Page 3810: ...e exactly as many words as there are serializers enabled as transmitters XDMAERR indicates that the DMA or CPU wrote too many words to the McASP for a given transmit DMA event Writing too few words results in a transmit underrun error setting XUNDRN in XSTAT While XDMAERR occurs infrequently an occurrence indicates a serious loss of synchronization between the McASP and the DMA or CPU You should r...

Page 3811: ...e enabled i transmit clock failure interrupt enable bit XCKFAIL in the transmitter interrupt control register XINTCTL ii transmit clock failure detect autoswitch enable bit XCKFAILSW in the transmit clock check control register XCLKCHK iii mute option XCKFAIL in the mute control register AMUTE 2 For the receive clock failure check a Configure receive clock failure detect logic RMIN RMAX RPS in the...

Page 3812: ...T when an out of range condition occurs An out of range minimum condition occurs when the count is smaller than XMIN The logic continually compares the current count from the running system clock counter against the maximum allowable boundary XMAX This is in case the external clock completely stops so that the counter value is not copied to XCNT An out of range maximum condition occurs when the co...

Page 3813: ... a full period However the transmit clock divide ratio bits HCLKXDIV in AHCLKXCTL are not affected so the internal clock divider generates clocks at the rate configured 3 The transmit section is reset for a single serial clock period 4 The transmit section is released from reset and attempts to begin transmitting If data is available it begins transmitting immediately otherwise it enters the under...

Page 3814: ...n occurs when the count is smaller than RMIN The logic continually compares the current count from the running system clock counter against the maximum allowable boundary RMAX This is in case the external clock completely stops so that the counter value is not copied to RCNT An out of range maximum condition occurs when the count is greater than RMAX Note that the RMIN and RMAX fields are 8 bit un...

Page 3815: ... logical connection of the serializers in loopback mode Two types of loopback connections are possible selected by the ORD bit in the digital loopback control register DLBCTL as follows ORD 0 Outputs of odd serializers are connected to inputs of even serializers If this mode is selected you should configure odd serializers to be transmitters and even serializers to be receivers ORD 1 Outputs of ev...

Page 3816: ...n order to assert the software reset bits in GBLCTL see Section 22 3 12 2for details on how to ensure reset has occurred The entire McASP module may also be reset through the Power and Sleep Controller PSC Note that from the McASP perspective this reset appears as a hardware reset to the entire module 22 3 11 2 Hardware Reset Considerations When the McASP is reset due to device reset the entire se...

Page 3817: ...gisters PFUNC PDIR DITCTL DLBCTL AMUTE Note that PDIR should only be programmed after the clocks and frames are set up in the steps above This is because the moment a clock pin is configured as an output in PDIR the clock pin starts toggling at the rate defined in the corresponding clock control register Therefore you must ensure that the clock control register is configured appropriately before y...

Page 3818: ...VT Before proceeding in this step you should verify that the XDATA bit in the XSTAT is cleared to 0 indicating that all transmit buffers are already serviced by the DMA b If CPU interrupt is used to service the McASP interrupt service routine is entered upon the AXINT interrupt The interrupt service routine should service the XBUF registers Before proceeding in this step you should verify that the...

Page 3819: ...l Description machine and frame sync generators from reset 3819 SPRUH73H October 2011 Revised April 2013 Multichannel Audio Serial Port McASP Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3820: ...me out and the bit clock stops the changes written to GBLCTL will not be reflected until the bit clock restarts Finally please note that while RGBLCTL and XGBLCTL allow separate changing of the receive and transmit halves of GBLCTL they also immediately reflect the updated value useful for debug purposes Only GBLCTL can be used for the read back step 22 3 12 5 Synchronous Transmit and Receive Oper...

Page 3821: ...ync A transmit last slot interrupt XLAST is a qualified version of the data ready interrupt XDATA It has the same behavior as the data ready interrupt but is further qualified by having the data requested belonging to the last slot the slot that just ended was next to last TDM slot current slot is last slot 22 3 13 3 Receive Data Ready Interrupt The receive data ready interrupt RDATA is generated ...

Page 3822: ...in to a preprogrammed output state as selected by the MUTEN bit in the audio mute control register AMUTE The AMUTE pin is asserted when one of the interrupt flags is set or an external device issues an error signal on the AMUTEIN input Typically the AMUTEIN input is shared with a device interrupt pin for example EXT_INT4 The AMUTEIN input allows the on chip logic to consider a mute input from othe...

Page 3823: ...equest is allowed on each port so a transmit and a receive interrupt request may both be outstanding at the same time 22 3 14 EDMA Event Support 22 3 14 1 EDMA Events There are 6 EDMA events 22 3 14 2 Using the DMA for McASP Servicing The most typical scenario is to use the DMA to service the McASP through the data port although the DMA can also service the McASP through the configuration bus Two ...

Page 3824: ...or channels RF RS LFE Similarly AREVT is triggered for each of the receive audio channel time slot Scenario 1 allows for the use of a single DMA to transmit all audio channels and a single DMA to receive all audio channels In scenario 2 Figure 22 37 two alternating DMA events are triggered for each time slot In the example AXEVTE even is triggered for the time slot for the even audio channels LF L...

Page 3825: ...ach receive DMA request is for data in the previous time slot For example Figure 22 38 shows a circled AXEVTE event for an even time slot transmit DMA request The transmitter always requests a DMA transfer for data it will need to transmit during the next time slot So in this example the circled event AXEVTE is a request for data for samples LF2 LS2 and C2 On the other hand the circled AREVTE even...

Page 3826: ...t independently from transmitter 64h RMASK Receive format unit bit mask register Section 22 4 1 14 68h RFMT Receive bit stream format register Section 22 4 1 15 6Ch AFSRCTL Receive frame sync control register Section 22 4 1 16 70h ACLKRCTL Receive clock control register Section 22 4 1 17 74h AHCLKRCTL Receive high frequency clock control register Section 22 4 1 18 78h RTDM Receive TDM time slot 0 ...

Page 3827: ...5 Left even TDM time slot channel user data register DIT mode 5 Section 22 4 1 40 148h DITUDRB0 Right odd TDM time slot channel user data register DIT mode 0 Section 22 4 1 41 14Ch DITUDRB1 Right odd TDM time slot channel user data register DIT mode 1 Section 22 4 1 41 150h DITUDRB2 Right odd TDM time slot channel user data register DIT mode 2 Section 22 4 1 41 154h DITUDRB3 Right odd TDM time slo...

Page 3828: ...ntification data for the peripheral The REV is shown in Figure 22 39 and described in Table 22 12 Figure 22 39 Revision Identification Register REV 31 0 REV R 4430 0A02h LEGEND R Read only n value after reset Table 22 12 Revision Identification Register REV Field Descriptions Bit Field Value Description 31 0 REV 4430 0A02h Identifies revision of peripheral 3828 Multichannel Audio Serial Port McASP...

Page 3829: ...of the local target state management mode By definition target can handle read write transaction as long as it is out of IDLE state 0x0 Force idle mode local target s idle state follows acknowledges the system s idle requests unconditionally i e regardless of the IP module s internal requirements Backup mode for debug only 0x1 No idle mode local target never enters idle state Backup mode for debug...

Page 3830: ... to reserved bits in this register may cause improper device operation Figure 22 41 Pin Function Register PFUNC 31 30 29 28 27 26 25 24 AFSR AHCLKR ACLKR AFSX AHCLKX ACLKX AMUTE Reserved R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R 0 23 8 Reserved R 0 7 6 5 4 3 2 1 0 Reserved AXR5 AXR4 AXR3 AXR2 AXR1 AXR0 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset ...

Page 3831: ...functions as McASP or GPIO 0 Pin functions as McASP pin 1 Pin functions as GPIO pin 26 ACLKX Determines if ACLKX pin functions as McASP or GPIO 0 Pin functions as McASP pin 1 Pin functions as GPIO pin 25 AMUTE Determines if AMUTE pin functions as McASP or GPIO 0 Pin functions as McASP pin 1 Pin functions as GPIO pin 24 6 Reserved 0 Reserved The reserved bit location always returns the default valu...

Page 3832: ...tput When AXRn is configured to transmit the PFUNC bit must be cleared to 0 McASP function and the PDIR bit must be set to 1 an output Similarly when AXRn is configured to receive the PFUNC bit must be cleared to 0 McASP function and the PDIR bit must be cleared to 0 an input CAUTION Writing to Reserved Bits Writing a value other than 0 to reserved bits in this register may cause improper device o...

Page 3833: ...functions as an input or output 0 Pin functions as input 1 Pin functions as output 26 ACLKX Determines if ACLKX pin functions as an input or output 0 Pin functions as input 1 Pin functions as output 25 AMUTE Determines if AMUTE pin functions as an input or output 0 Pin functions as input 1 Pin functions as output 24 6 Reserved 0 Reserved The reserved bit location always returns the default value A...

Page 3834: ...effect and keeps the bits in PDOUT unchanged PDCLR when written to at this address writing a 1 to a bit in PDCLR clears the corresponding bit in PDOUT to 0 writing a 0 has no effect and keeps the bits in PDOUT unchanged There is only one set of data out bits PDOUT 31 0 The other registers PDSET and PDCLR are just different addresses for the same control bits with different behaviors during writes ...

Page 3835: ...LKX output pin when the corresponding PFUNC 27 and PDIR 27 bits are set to 1 0 Pin drives low 1 Pin drives high 26 ACLKX Determines drive on ACLKX output pin when the corresponding PFUNC 26 and PDIR 26 bits are set to 1 0 Pin drives low 1 Pin drives high 25 AMUTE Determines drive on AMUTE output pin when the corresponding PFUNC 25 and PDIR 25 bits are set to 1 0 Pin drives low 1 Pin drives high 24...

Page 3836: ...N Writing to Reserved Bits Writing a value other than 0 to reserved bits in this register may cause improper device operation Figure 22 44 Pin Data Input Register PDIN 31 30 29 28 27 26 25 24 AFSR AHCLKR ACLKR AFSX AHCLKX ACLKX AMUTE Reserved R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R 0 23 8 Reserved R 0 7 6 5 4 3 2 1 0 Reserved AXR5 AXR4 AXR3 AXR2 AXR1 AXR0 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W ...

Page 3837: ... 0 Pin is logic low 1 Pin is logic high 26 ACLKX Logic level on ACLKX pin 0 Pin is logic low 1 Pin is logic high 25 AMUTE Logic level on AMUTE pin 0 Pin is logic low 1 Pin is logic high 24 6 Reserved 0 Reserved The reserved bit location always returns the default value A value written to this field has no effect If writing to this field always write the default value for future device compatibilit...

Page 3838: ...SP The PDSET is shown in Figure 22 45 and described in Table 22 18 CAUTION Writing to Reserved Bits Writing a value other than 0 to reserved bits in this register may cause improper device operation Figure 22 45 Pin Data Set Register PDSET 31 30 29 28 27 26 25 24 AFSR AHCLKR ACLKR AFSX AHCLKX ACLKX AMUTE Reserved R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R 0 23 8 Reserved R 0 7 6 5 4 3 2 1 0 Reser...

Page 3839: ...AHCLKX bit in PDOUT to be set to a logic high without affecting other I O pins controlled by the same port 0 No effect 1 PDOUT 27 bit is set to 1 26 ACLKX Allows the corresponding ACLKX bit in PDOUT to be set to a logic high without affecting other I O pins controlled by the same port 0 No effect 1 PDOUT 26 bit is set to 1 25 AMUTE Allows the corresponding AMUTE bit in PDOUT to be set to a logic h...

Page 3840: ...cASP The PDCLR is shown in Figure 22 46 and described in Table 22 19 CAUTION Writing to Reserved Bits Writing a value other than 0 to reserved bits in this register may cause improper device operation Figure 22 46 Pin Data Clear Register PDCLR 31 30 29 28 27 26 25 24 AFSR AHCLKR ACLKR AFSX AHCLKX ACLKX AMUTE Reserved R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R 0 23 8 Reserved R 0 7 6 5 4 3 2 1 0 R...

Page 3841: ... AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I O pins controlled by the same port 0 No effect 1 PDOUT 27 bit is cleared to 0 26 ACLKX Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I O pins controlled by the same port 0 No effect 1 PDOUT 26 bit is cleared to 0 25 AMUTE Allows the corresponding AMUTE bit in PDOUT to be c...

Page 3842: ...ing frame sync as programmed 11 XSMRST Transmit state machine reset enable bit 0 Transmit state machine is held in reset AXRn pin state If PFUNC n 0 and PDIR n 1 then the serializer drives the AXRn pin to the state specified for inactive time slot as determined by DISMOD bits in SRCTL 1 Transmit state machine is released from reset When released from reset the transmit state machine immediately tr...

Page 3843: ...released from reset the receive state machine immediately begins detecting frame sync and is ready to receive Receive TDM time slot begins at slot 0 after reset is released 2 RSRCLR Receive serializer clear enable bit By clearing then setting this bit the receive buffer is flushed 0 Receive serializers are cleared 1 Receive serializers are active 1 RHCLKRST Receive high frequency clock divider res...

Page 3844: ...en according to MUTEN bit 10 XCKFAIL If transmit clock failure XCKFAIL drive AMUTE active enable bit 0 Drive is disabled Detection of transmit clock failure is ignored by AMUTE 1 Drive is enabled active Upon detection of transmit clock failure AMUTE is active and is driven according to MUTEN bit 9 RCKFAIL If receive clock failure RCKFAIL drive AMUTE active enable bit 0 Drive is disabled Detection ...

Page 3845: ...s detected 3 INEN Drive AMUTE active when AMUTEIN error is active INSTAT 1 0 Drive is disabled AMUTEIN is ignored by AMUTE 1 Drive is enabled active INSTAT 1 drives AMUTE active 2 INPOL Audio mute in AMUTEIN polarity select bit 0 Polarity is active high A high on AMUTEIN sets INSTAT to 1 1 Polarity is active low A low on AM UTEIN sets INSTAT to 1 1 0 MUTEN 0 3h AMUTE pin enable bit unless overridd...

Page 3846: ...back generator mode bits Applies only when loopback mode is enabled DLBEN 1 0 Default and reserved on loopback mode DLBEN 1 When in non loopback mode DLBEN 0 MODE should be left at default 00 When in loopback mode DLBEN 1 MODE 00 is reserved and is not applicable 1h Transmit clock and frame sync generators used by both transmit and receive sections When in loopback mode DLBEN 1 MODE must be 01 2h ...

Page 3847: ...ight subframe 0 V bit is 0 during odd DIT subframes 1 V bit is 1 during odd DIT subframes 2 VA Valid bit for even time slots DIT left subframe 0 V bit is 0 during even DIT subframes 1 V bit is 1 during even DIT subframes 1 Reserved 0 Reserved The reserved bit location always returns the default value A value written to this field has no effect If writing to this field always write the default valu...

Page 3848: ...L Writes have no effect 9 XHCLKRST x Transmit high frequency clock divider reset enable bit A read of this bit returns the XHCLKRST bit value of GBLCTL Writes have no effect 8 XCLKRST x Transmit clock divider reset enable bit A read of this bit returns the XCLKRST bit value of GBLCTL Writes have no effect 7 5 Reserved 0 Reserved The reserved bit location always returns the default value A value wr...

Page 3849: ... n value after reset Table 22 25 Receive Format Unit Bit Mask Register RMASK Field Descriptions Bit Field Value Description 31 0 RMASK 31 0 Receive data mask n enable bit 0 Corresponding bit of receive data after passing through reverse and rotate units is masked out and then padded with the selected bit pad value RPAD and RPBIT bits in RFMT 1 Corresponding bit of receive data after passing throug...

Page 3850: ...ive frame sync AFSR 1h 1 bit delay The first receive data bit AXRn occurs one ACLKR cycle after the receive frame sync AFSR 2h 2 bit delay The first receive data bit AXRn occurs two ACLKR cycles after the receive frame sync AFSR 3h Reserved 15 RRVRS Receive serial bitstream order 0 Bitstream is LSB first No bit reversal is performed in receive format bit reverse unit 1 Bitstream is MSB first Bit r...

Page 3851: ... the data DAT port 0 Reads from XRBUF n originate on data port Reads from XRBUF n on configuration bus are ignored 1 Reads from XRBUF n originate on configuration bus Reads from XRBUF n on data port are ignored 2 0 RROT 0 7h Right rotation value for receive rotate right format unit 0 Rotate right by 0 no rotation 1h Rotate right by 4 bit positions 2h Rotate right by 8 bit positions 3h Rotate right...

Page 3852: ...putting 384 slot DIR frames to McASP over I2S interface 181h 1FFh Reserved 6 5 Reserved 0 Reserved The reserved bit location always returns the default value A value written to this field has no effect If writing to this field always write the default value for future device compatibility 4 FRWID Receive frame sync width select bit indicates the width of the receive frame sync AFSR during its acti...

Page 3853: ...al transmitter driving this receiver must shift data out on the rising edge of the serial clock 1 Rising edge Receiver samples data on the rising edge of the serial clock so the external transmitter driving this receiver must shift data out on the falling edge of the serial clock 6 Reserved 0 Reserved The reserved bit location always returns the default value A value written to this field has no e...

Page 3854: ...utput of programmable high clock divider 14 HCLKRP Receive bitstream high frequency clock polarity select bit 0 AHCLKR is not inverted before programmable bit clock divider In the special case where the receive bit clock ACLKR is internally generated and the programmable bit clock divider is set to divide by 1 CLKRDIV 0 in ACLKRCTL AHCLKR is directly passed through to the ACLKR pin 1 AHCLKR is inv...

Page 3855: ... value after reset Table 22 30 Receive TDM Time Slot Register RTDM Field Descriptions Bit Field Value Description 31 0 RTDMS 31 0 Receiver mode during TDM time slot n 0 Receive TDM time slot n is inactive The receive serializer does not shift in data during this slot 1 Receive TDM time slot n is active The receive serializer shifts in data during this slot 3855 SPRUH73H October 2011 Revised April ...

Page 3856: ...ceive data ready interrupt enable bit 0 Interrupt is disabled A receive data ready interrupt does not generate a McASP receive interrupt RINT 1 Interrupt is enabled A receive data ready interrupt generates a McASP receive interrupt RINT 4 RLAST Receive last slot interrupt enable bit 0 Interrupt is disabled A receive last slot interrupt does not generate a McASP receive interrupt RINT 1 Interrupt i...

Page 3857: ...ct 0 Receive DMA error did not occur 1 Receive DMA error did occur 6 RSTAFRM Receive start of frame flag Causes a receive interrupt RINT if this bit is set and RSTAFRM in RINTCTL is set This bit is cleared by writing a 1 to this bit Writing a 0 to this bit has no effect 0 No new receive frame sync AFSR is detected 1 A new receive frame sync AFSR is detected 5 RDATA Receive data ready flag Causes a...

Page 3858: ...n did occur 22 4 1 22 Current Receive TDM Time Slot Registers RSLOT The current receive TDM time slot register RSLOT indicates the current time slot for the receive data frame The RSLOT is shown in Figure 22 60 and described in Table 22 33 Figure 22 60 Current Receive TDM Time Slot Registers RSLOT 31 16 Reserved R 0 15 9 8 0 Reserved RSLOTCNT R 0 R 0 LEGEND R Read only n value after reset Table 22...

Page 3859: ...alue is greater than RMAX after counting 32 AHCLKR signals RCKFAIL in RSTAT is set The comparison is performed using unsigned arithmetic 15 8 RMIN 0 FFh Receive clock minimum boundary This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high frequency master clock AHCLKR signals have been received If RCNT is less than RMIN after counting 32 AHCLK...

Page 3860: ... R W Read Write R Read only n value after reset Table 22 35 Receiver DMA Event Control Register REVTCTL Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit location always returns the default value A value written to this field has no effect If writing to this field always write the default value for future device compatibility 0 RDATDMA Receive data DMA reques...

Page 3861: ...ate machine is released from reset 10 XSRCLR Transmit serializer clear enable bit A write to this bit affects the XSRCLR bit of GBLCTL 0 Transmit serializers are cleared 1 Transmit serializers are active 9 XHCLKRST Transmit high frequency clock divider reset enable bit A write to this bit affects the XHCLKRST bit of GBLCTL 0 Transmit high frequency clock divider is held in reset 1 Transmit high fr...

Page 3862: ...ransmit Format Unit Bit Mask Register XMASK Field Descriptions Bit Field Value Description 31 0 XMASK 31 0 Transmit data mask n enable bit 0 Corresponding bit of transmit data before passing through reverse and rotate units is masked out and then padded with the selected bit pad value XPAD and XPBIT bits in XFMT which is transmitted out the McASP in place of the original bit 1 Corresponding bit of...

Page 3863: ...nc AFSX 1h 1 bit delay The first transmit data bit AXRn occurs one ACLKX cycle after the transmit frame sync AFSX 2h 2 bit delay The first transmit data bit AXRn occurs two ACLKX cycles after the transmit frame sync AFSX 3h Reserved 15 XRVRS Transmit serial bitstream order 0 Bitstream is LSB first No bit reversal is performed in transmit format bit reverse unit 1 Bitstream is MSB first Bit reversa...

Page 3864: ... originate from the data port Writes to XRBUF n from the configuration bus are ignored with no effect to the McASP 1 Writes to XRBUF n originate from the configuration bus Writes to XRBUF n from the data port are ignored with no effect to the McASP 2 0 XROT 0 7h Right rotation value for transmit rotate right format unit 0 Rotate right by 0 no rotation 1h Rotate right by 4 bit positions 2h Rotate r...

Page 3865: ...h 384 slot DIT mode 181h 1FFh Reserved 6 5 Reserved 0 Reserved The reserved bit location always returns the default value A value written to this field has no effect If writing to this field always write the default value for future device compatibility 4 FXWID Transmit frame sync width select bit indicates the width of the transmit frame sync AFSX during its active period 0 Single bit 1 Single wo...

Page 3866: ...nal receiver samples data on the falling edge of the serial clock so the transmitter must shift data out on the rising edge of the serial clock 1 Falling edge External receiver samples data on the rising edge of the serial clock so the transmitter must shift data out on the falling edge of the serial clock 6 ASYNC Transmit receive operation asynchronous enable bit 0 Synchronous Transmit clock and ...

Page 3867: ...m output of programmable high clock divider 14 HCLKXP Transmit bitstream high frequency clock polarity select bit 0 AHCLKX is not inverted before programmable bit clock divider In the special case where the transmit bit clock ACLKX is internally generated and the programmable bit clock divider is set to divide by 1 CLKXDIV 0 in ACLKXCTL AHCLKX is directly passed through to the ACLKX pin 1 AHCLKX i...

Page 3868: ...TDM Time Slot Register XTDM 31 0 XTDMS n R W 0 LEGEND R W Read Write n value after reset Table 22 42 Transmit TDM Time Slot Register XTDM Field Descriptions Bit Field Value Description 31 0 XTDMS 31 0 Transmitter mode during TDM time slot n 0 Transmit TDM time slot n is inactive The transmit serializer does not shift out data during this slot 1 Transmit TDM time slot n is active The transmit seria...

Page 3869: ... ready interrupt enable bit 0 Interrupt is disabled A transmit data ready interrupt does not generate a McASP transmit interrupt XINT 1 Interrupt is enabled A transmit data ready interrupt generates a McASP transmit interrupt XINT 4 XLAST Transmit last slot interrupt enable bit 0 Interrupt is disabled A transmit last slot interrupt does not generate a McASP transmit interrupt XINT 1 Interrupt is e...

Page 3870: ...it DMA error did not occur 1 Transmit DMA error did occur 6 XSTAFRM Transmit start of frame flag Causes a transmit interrupt XINT if this bit is set and XSTAFRM in XINTCTL is set This bit is cleared by writing a 1 to this bit Writing a 0 has no effect 0 No new transmit frame sync AFSX is detected 1 A new transmit frame sync AFSX is detected 5 XDATA Transmit data ready flag Causes a transmit interr...

Page 3871: ... 34 Current Transmit TDM Time Slot Register XSLOT The current transmit TDM time slot register XSLOT indicates the current time slot for the transmit data frame The XSLOT is shown in Figure 22 72 and described in Table 22 45 Figure 22 72 Current Transmit TDM Time Slot Register XSLOT 31 16 Reserved R 0 15 10 9 0 Reserved XSLOTCNT R 0 R 17Fh LEGEND R Read only n value after reset Table 22 45 Current ...

Page 3872: ...value is greater than XMAX after counting 32 AHCLKX signals XCKFAIL in XSTAT is set The comparison is performed using unsigned arithmetic 15 8 XMIN 0 FFh Transmit clock minimum boundary This 8 bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high frequency master clock AHCLKX signals have been received If XCNT is less than XMIN after counting 32 AH...

Page 3873: ...ND R W Read Write R Read only n value after reset Table 22 47 Transmitter DMA Event Control Register XEVTCTL Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit location always returns the default value A value written to this field has no effect If writing to this field always write the default value for future device compatibility 0 XDATDMA Transmit data DMA ...

Page 3874: ... buffer RBUF is empty 1 Receive buffer RBUF contains data and needs to be read before the start of the next time slot or a receiver overrun occurs 4 XRDY Transmit buffer ready bit XRDY indicates the current transmit buffer state Always reads 0 when programmed as a receiver or as inactive If SRMOD bit is set to transmit 1h XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to i...

Page 3875: ...R W Read Write n value after reset 22 4 1 40 DIT Left Channel User Data Registers DITUDRA0 DITUDRA5 The DIT left channel user data registers DITUDRA provides the user data of each left channel even TDM time slot Each of the six 32 bit registers Figure 22 78 can store 192 bits of user data for a complete block of transmission The DIT reuses the same data for the next block It is your responsibility...

Page 3876: ...lue after reset 22 4 1 43 Receive Buffer Registers RBUFn The receive buffers for the serializers RBUF hold data from the serializer before the data goes to the receive format unit For receive operations the RBUF Figure 22 81 is an alias of the XRBUF in the serializer NOTE Device specific registers Accessing XBUF registers not implemented on a specific device may cause improper device operation Fig...

Page 3877: ...enabled If Write FIFO is to be enabled it must be enabled prior to taking McASP out of reset 15 8 WNUMEVT 0 FFh Write word count per DMA event 32 bit When the Write FIFO has space for at least WNUMEVT words of data then an AXEVT transmit DMA event is generated to the host DMA controller This value should be set to a non zero integer multiple of the number of serializers enabled as transmitters Thi...

Page 3878: ...te FIFO Status Register WFIFOSTS Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 WLVL 0 FFh Write level read only Number of 32 bit words currently in the Write FIFO 0 0 words currently in Write FIFO 1h 1 word currently in Write FIFO 2h 2 words currently in Write FIFO 3h 40h 3 to 64 words currently in Write FIFO 41h FFh Reserved 3878 Multichannel Audio Serial Port McASP ...

Page 3879: ...ead FIFO is enabled If Read FIFO is to be enabled it must be enabled prior to taking McASP out of reset 15 8 RNUMEVT 0 FFh Read word count per DMA event 32 bit When the Read FIFO contains at least RNUMEVT words of data then an AREVT receive DMA event is generated to the host DMA controller This value should be set to a non zero integer multiple of the number of serializers enabled as receivers Thi...

Page 3880: ...to 64 words currently in Read FIFO 41h FFh Reserved 22 4 2 McASP Data Port Registers Table 22 53 McASP Registers Accessed Through Data Port Hex Address Register Name Register Description Read Accesses RBUF Receive buffer data port address Cycles through receive serializers skipping over transmit serializers and inactive serializers Starts at the lowest serializer at the beginning of each time slot...

Page 3881: ... controller area network for the device Topic Page 23 1 Introduction 3882 23 2 Integration 3883 23 3 Functional Description 3885 23 4 DCAN Registers 3922 3881 SPRUH73H October 2011 Revised April 2013 Controller Area Network CAN Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3882: ...c bus on after Bus Off state by a programmable 32 bit timer Message RAM parity check mechanism Direct access to Message RAM during test mode CAN Rx Tx pins configurable as general purpose IO pins Two interrupt lines plus additional parity error interrupt line RAM initialization DMA support 23 1 2 Unsupported DCAN Features The DCAN module in this device does not support GPIO pin mode All GPIO funct...

Page 3883: ... shows the DCAN module integration Figure 23 1 DCAN Integration 23 2 1 DCAN Connectivity Attributes The general connectivity attributes for the DCAN module are shown in Table 23 1 Table 23 1 DCAN Connectivity Attributes Attributes Type Power Domain Peripheral Domain Clock Domain PD_PER_L4LS_GCLK OCP PD_PER_CAN_CLK Func Reset Signals PER_DOM_RST_N Idle Wakeup Signals Smart Idle Interrupt Requests 3...

Page 3884: ...ls_gclk Interface clock from PRCM DCAN_io_clk 26 MHz CLK_M_OSC pd_per_can_clk Functional clock from PRCM 23 2 3 DCAN Pin List The external signals for the DCAN module are shown in the following table Table 23 3 DCAN Pin List Pin Type Description DCANx_TX O DCAN transmit line DCANx_RX I DCAN receive line 3884 Controller Area Network CAN SPRUH73H October 2011 Revised April 2013 Submit Documentation ...

Page 3885: ...erning the handling of messages are implemented in the message handler Those functions are acceptance filtering the transfer of messages between the CAN core and the message RAM and the handling of transmission requests as well as the generation of interrupts or DMA requests The register set of the DCAN module can be accessed directly by the CPU via the module interface These registers are used to...

Page 3886: ... 23 3 15 12 The interface registers have the same word length as the message RAM 23 3 5 Registers and Message Object Access Data consistency is ensured by indirect accesses to the message objects During normal operation all CPU and DMA accesses to the message RAM are done through interface registers In a dedicated test mode the message RAM is memory mapped and can be directly accessed by either CP...

Page 3887: ... for CAN communication Message objects that are not needed can be deactivated Figure 23 3 CAN Module General Initialization Flow 23 3 8 1 1 Configuration of CAN Bit Timing The CAN module must be in initialization mode to configure the CAN bit timing For CAN bit timing software configuration flow see Figure 23 4 Step 1 Enter initialization mode by setting the Init Initialization bit in the CAN cont...

Page 3888: ... 3 16 2 for the BTR value calculation for a given bit timing Step 5 Clear the CCE and Init bit Step 6 Wait for the Init bit to clear This would ensure that the module has come out of initialization mode Following these steps the module comes to operation by synchronizing itself to the CAN bus provided the BTR is configured as per the CAN bus baud rate although the message objects have to be config...

Page 3889: ...ints to those message objects with IntPnd 1 It is updated even if the interrupt lines to the CPU are disabled IE0 IE1 are zero The CPU may poll all MessageObject s NewDat and TxRqst bits in parallel from the NewData X registers and the Transmission Request X Registers DCAN TXRQ X Polling can be made easier if all transmit objects are grouped at the low numbers and all receive objects are grouped a...

Page 3890: ... of CAN bus errors it stops all bus activities and automatically sets the Init bit Once the Init bit has been reset by the CPU or due to the Auto Bus On feature the device will wait for 129 occurrences of bus Idle equal to 129 11 consecutive recessive bits before resuming normal operation At the end of the Bus Off recovery sequence the error counters will be reset 23 3 8 3 Test Modes The DCAN modu...

Page 3891: ...er to be independent from external stimulation the CAN core ignores acknowledge sampled in the acknowledge slot of a data remote frame Figure 23 6 shows the connection of signals CAN_TX and CAN_RX to the CAN core in loopback mode Loopback mode can be activated by setting bit LBack in the test register to one NOTE In loopback mode the signal path from CAN core to Tx pin the Tx pin itself and the si...

Page 3892: ...n external loopback mode NOTE When loopback mode is active LBack bit set the ExL bit will be ignored Figure 23 7 CAN Core in External Loopback Mode 23 3 8 3 4 Loopback Mode Combined With Silent Mode It is also possible to combine loopback mode and silent mode by setting bits LBack and Silent at the same time This mode can be used for a Hot Selftest i e the DCAN hardware can be tested without affec...

Page 3893: ...o clock domains are provided to the DCAN module the peripheral synchronous clock domain L3_SLOW_GCLK as the general module clock source and the peripheral asynchronous clock source domain CLK_M_OSC provided to the CAN core as clock source CAN_CLK for generating the CAN bit timing Both clock domains can be derived from the same clock source so that L3_SLOW_GCLK CLK_M_OSC For more information on how...

Page 3894: ...t1ID will point to the pending message interrupt with the highest priority The Message Object 1 has the highest priority the last message object has the lowest priority An interrupt service routine that reads the message that is the source of the interrupt may read the message and reset the message object s IntPnd at the same time ClrIntPnd bit in the IF1 IF2 command register When IntPnd is cleare...

Page 3895: ...errupts IE0 DCAN0INT Fig 10 7 See Error and Status Change Interrupts are Routed to DCAN0INT line L www ti com Functional Description 23 3 10 3 Error Interrupts The events PER BOff and EWarn monitored in the Error and Status register DCAN ES belong to the error interrupts The error interrupt group can be enabled by setting bit EIE in the CAN Control register Error interrupts can only be routed to i...

Page 3896: ... to wake up the DCAN from local power down mode The application could wake up the DCAN module manually by clearing the PDR bit and then clearing the Init bit in CAN Control register Alternatively a CAN bus activity detection circuit can be activated by setting the wakeup on bus activity bit WUBA in the CAN control register If this circuit is active on occurrence of a dominant CAN bus level the DCA...

Page 3897: ... PDA Bit 0 Application Set Init 0 Wait for 11 Recessive Bits END D_CAN Set PDA Bit 0 Set PDR Bit 0 Set WakeUpPnd Bit 1 CAN_INTR 1 if Enabled Set Init Bit 0 www ti com Functional Description Figure 23 11 Local Power Down Mode Flow Diagram 3897 SPRUH73H October 2011 Revised April 2013 Controller Area Network CAN Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3898: ...r of 1 bits in the data is odd NOTE The parity scheme is tied to even parity at the device level 23 3 12 1 Behavior on Parity Error On any read access to message RAM e g during start of a CAN frame transmission the parity of the message object will be checked If a parity error is detected the PER bit in the error and status register will be set If error interrupts are enabled an interrupt would al...

Page 3899: ...ever it is also possible to change the configuration of message objects during CAN communication The CAN software driver library should offer subroutines that Transfer a complete message structure into a message object Configuration Transfer the data bytes of a message into a message object and set TxRqst and NewDat Start a new transmission Get the data bytes of a message from a message object and...

Page 3900: ...Single Receive Object for Data Frames Table 23 5 shows how a receive object for data frames can be initialized Table 23 5 Initialization of a single Receive Object for Data Frames MsgVal Arb Data Mask EoB Dir NewDat MsgLst RxIE TxIE IntPnd RmtEn TxRqst 1 appl appl appl 1 0 0 0 appl 0 0 0 0 The arbitration bits ID 28 0 and Xtd bit are given by the application They define the identifier and type of ...

Page 3901: ...1 bit Identifier standard frame is used Xtd 0 it is programmed to ID 28 18 In this case ID 17 0 can be ignored When a remote frame with an 11 bit Identifier is received ID 17 0 will be set to 0 The data length code DLC 3 0 may be given by the application When the message handler stores a remote frame in the message object it will store the received data length code The data bytes of the message ob...

Page 3902: ... message object via IFx registers separately these message handler registers provides a fast and easy way to get an overview for example about all pending transmission requests All message handler registers are read only 23 3 15 2 Receive Transmit Priority The receive transmit priority for the message objects is attached to the message number not to the CAN identifier Message object 1 has the high...

Page 3903: ...nsferred to the message object Either the CPU has to write all four bytes into the IF1 IF2 data register or the message object is transferred to the IF1 IF2 data register before the CPU writes the new data bytes When only the data bytes are updated first 0x87 can be written to bits 23 16 of the IF1 IF2 Command register DCAN IF1CMD DCAN IF2CMD and then the number of the message object is written to...

Page 3904: ...of Remote Frames When a remote frame is received three different configurations of the matching message object have to be considered Dir 1 direction transmit RmtEn 1 UMask 1 or 0 The TxRqst bit of this message object is set at the reception of a matching remote frame The rest of the message object remains unchanged Dir 1 direction transmit RmtEn 0 UMask 0 The remote frame is ignored this message o...

Page 3905: ...he message object is locked for further write accesses by the message handler until the CPU has cleared the NewDat bit Messages are stored into a FIFO buffer until the last message object of this FIFO buffer is reached If none of the preceding message objects is released by writing NewDat to 0 all further messages for this FIFO buffer will be written into the last message object of the FIFO buffer...

Page 3906: ...age Control NewDat 1 Read Data From IF1 IF2 Data A B EoB 1 Next Message Number in This FIFO Buffer Yes No Yes No Message Interrupt Interrupt Handling Message Number Interrupt Identifier Else 0x0000 Functional Description www ti com Figure 23 12 CPU Handling of a FIFO Buffer Interrupt Driven 3906 Controller Area Network CAN SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copy...

Page 3907: ...tters to become error passive The analysis of such sporadic errors requires a detailed knowledge of the CAN bit synchronization inside a CAN node and of the CAN nodes interaction on the CAN bus Even if minor errors in the configuration of the CAN bit timing do not result in immediate failure the performance of a CAN network can be reduced significantly 23 3 16 1 Bit Time and Bit Rate According to ...

Page 3908: ... CAN bus level are expected to occur If an edge occurs outside of Sync_Seg its distance to the Sync_Seg is called the phase error of this edge 23 3 16 1 2 Propagation Time Segment This part of the bit time is used to compensate physical delay times within the CAN network These delay times consist of the signal propagation time on the bus and the internal delay time of the CAN nodes Any CAN node sy...

Page 3909: ...lerance The phase buffer segments surround the sample point and may be lengthened or shortened by synchronization The synchronization jump width SJW defines how far the resynchronizing mechanism may move the sample point inside the limits defined by the phase buffer segments to compensate for edge phase errors Synchronizations occur on edges from recessive to dominant Their purpose is to control t...

Page 3910: ...r tolerance when the differences in the oscillator s clock periods of transmitter and receivers sum up during the time between synchronizations at most ten bits These summarized differences may not be longer than the SJW limiting the oscillator s tolerance range Figure 23 15 shows how the phase buffer segments are used to compensate for phase errors There are three drawings of each two consecutive...

Page 3911: ...rror of the spike s edge from recessive to dominant Therefore the sample point is shifted after the end of the spike a recessive bus level is sampled In the second example SJW is shorter than the phase error so the sample point cannot be shifted far enough the dominant spike is sampled as actual bus level Figure 23 16 Filtering of Short Dominant Spikes 23 3 16 1 4 Oscillator Tolerance Range With t...

Page 3912: ...fore the length of the bit time is programmed values TSEG1 TSEG2 3 tq or functional values Sync_Seg Prop_Seg Phase_Seg1 Phase_Seg2 tq The data in the bit timing register BTR is the configuration input of the CAN protocol controller The baud rate prescaler configured by BRPE BRP defines the length of the time quantum the basic time unit of the bit time the bit timing logic configured by TSEG1 TSEG2...

Page 3913: ... 1 The minimum nominal length of Phase_Seg2 has to be regarded as well Phase_Seg2 may not be shorter than any CAN controller s Information Processing Time in the network which is device dependent and can be in the range of 0 2 tq The length of the synchronization jump width is set to its maximum value which is the minimum of four 4 and Phase_Seg1 The oscillator tolerance range necessary for the re...

Page 3914: ... 1 2 1 1 6 so the bit timing register is programmed to 00000700 23 3 16 2 3 Example for Bit Timing at Low Baud Rate In this example the frequency of CAN_CLK is 2 MHz BRP is 1 the bit rate is 100 KBit s tq 1 µs tCAN_CLK Delay of bus driver 200 ns Delay of receiver circuit 80 ns Delay of bus line 40 m 220 ns tProp 1 µs 1 tq tSJW 4 µs 4 tq tTSeg1 5 µs tProp tSJW tTSeg2 3 µs Information Processing Tim...

Page 3915: ...t selected in the command register will be left unchanged By buffering the data to be transferred the interface register sets avoid conflicts between concurrent CPU accesses to the message RAM and CAN message reception and transmission A complete message object see Section 23 3 18 1 or parts of the message object may be transferred between the message RAM and the IF1 IF2 register set see in one si...

Page 3916: ...r active NewDat flags If such a message object is found it will be transferred to the IF3 register if no previous DMA transfers are ongoing controlled by IF3 Observation register If more than one NewDat flag is active the message object with the lowest number has the highest priority for automatic IF3 update The NewDat bit in the message object will be reset by a transfer to IF3 If DCAN internal I...

Page 3917: ...e message objects The third interface register set IF3 can be configured to automatically receive control and user data from the message RAM when a message object has been updated after reception of a CAN message The CPU does not need to initiate the transfer from message RAM to IF3 register set The message handler avoids potential conflicts between concurrent accesses to message RAM and CAN frame...

Page 3918: ... is not used for acceptance filtering don t care 1 The corresponding bit in the message identifier is used for acceptance filtering Xtd Mask extended identifier 0 The extended identifier bit IDE has no effect on the acceptance filtering 1 The extended identifier bit IDE is used for acceptance filtering Note When 11 bit standard Identifiers are used for a message object the identifiers of received ...

Page 3919: ...ity RmtEn Remote enable 0 At the reception of a remote frame TxRqst is not changed 1 At the reception of a remote frame TxRqst is set TxRqst Transmit request 0 This message object is not waiting for a transmission 1 The transmission of this message object is requested and is not yet done DLC 3 0 Data length code 0 Data frame has 0 to 8 data bytes 1 Data frame has 8 data bytes Note The data length ...

Page 3920: ...Xtd Dir ID ID 27 0 DLC 1 0x002C 4 Ctrl Mask Xtd Dir ID 28 0x0030 5 Data Bytes 3 0 Parity Ctrl MXtd MDir 0x0034 6 Data Bytes 7 4 0x03E0 1 Parity Data Bytes 4 7 0x03E4 2 MXtd MDir Mask Data Bytes 0 3 0x03E8 3 Xtd Dir ID ID 27 0 DLC 31 0x03EC 4 Ctrl Mask Xtd Dir ID 28 0x03F0 5 Data Bytes 3 0 Parity Ctrl MXtd MDir 0x03F4 6 Data Bytes 7 4 0x07E0 1 Parity Data Bytes 4 7 0x07E4 2 MXtd MDir Mask Data Byte...

Page 3921: ...N module is in test mode test bit in the CAN control register is set the CPU has direct access to the message RAM Due to the 32 bit bus structure the RAM is split into word lines to support this feature The CPU has access to one word line at a time only In RAM direct access mode the RAM is represented by a continuous memory space within the address frame of the DCAN module starting at the message ...

Page 3922: ...h TEST Test Register Section 23 4 6 1Ch PERR Parity Error Code Register Section 23 4 7 80h ABOTR Auto Bus On Time Register Section 23 4 8 84h TXRQ_X Transmission Request X Register Section 23 4 9 88h TXRQ12 Transmission Request Register 12 Section 23 4 10 8Ch TXRQ34 Transmission Request Register 34 Section 23 4 11 90h TXRQ56 Transmission Request Register 56 Section 23 4 12 94h TXRQ78 Transmission ...

Page 3923: ... IF2ARB IF2 Arbitration Register Section 23 4 41 12Ch IF2MCTL IF2 Message Control Register Section 23 4 42 130h IF2DATA IF2 Data A Register Section 23 4 43 134h IF2DATB IF2 Data B Register Section 23 4 44 140h IF3OBS IF3 Observation Register Section 23 4 45 144h IF3MSK IF3 Mask Register Section 23 4 46 148h IF3ARB IF3 Arbitration Register Section 23 4 47 14Ch IF3MCTL IF3 Message Control Register S...

Page 3924: ...h R W 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 14 CTL Register Field Descriptions Bit Field Type Reset Description 31 26 Reserved R 0h 25 WUBA R W 0h Automatic wake up on bus activity when in local power down mode Note The CAN message which initiates the bus activity cannot be received This means that the first message received in power down and...

Page 3925: ...al Operation 0x1 Module is forced to reset state This bit will automatically get cleared after execution of SW reset after one OCP clock cycle 14 Reserved R 0h 13 10 PMD R W 5h Parity on off 5 Parity function disabled Others Parity function enabled 9 ABO R W 0h Auto Bus On enable 0x0 The Auto Bus On feature is disabled 0x1 The Auto Bus On feature is enabled 8 IDS R W 0h Interruption debug support ...

Page 3926: ...k and LEC bits can not generate an interrupt 0x1 Enabled WakeUpPnd RxOk TxOk and LEC can generate an interrupt at DCAN0INT line and affect the interrupt register 1 IE0 R W 0h Interrupt line 0 enable 0x0 Disabled Module interrupt DCAN0INT is always low 0x1 Enabled interrupts will assert line DCAN0INT to one line remains active until pending interrupts are processed 0 Init R W 1h Initialization 0x0 ...

Page 3927: ...W1toCl Write 1 to clear bit n value after reset Table 23 15 ES Register Field Descriptions Bit Field Type Reset Description 31 11 Reserved R 0h 10 PDA R 0h Local power down mode acknowledge 0x0 DCAN is not in local power down mode 0x1 Application request for setting DCAN to local power down mode was successful DCAN is in local power down mode 9 WakeUp_Pnd R C 0h Wake up pending This bit can be use...

Page 3928: ... reception or transmission without error 0x0 No error 0x1 Stuff error More than five equal bits in a row have been detected in a part of a received message where this is not allowed 0x2 Form error A fixed format part of a received frame has the wrong format 0x3 Ack error The message this CAN core transmitted was not acknowledged by another node 0x4 Bit1 error During the transmission of a message w...

Page 3929: ...riptions Bit Field Type Reset Description 31 16 Reserved R 0h 15 RP R 0h Receive error passive 0x0 The receive error counter is below the error passive level 0x1 The receive error counter has reached the error passive level as defined in the CAN specification 14 8 REC 6 0 R 0h Receive error counter Actual state of the receive error counter values from 0 to 255 7 0 TEC 7 0 R 0h Transmit error count...

Page 3930: ...id programmed values are 0 to 15 By programming BRPE the baud rate prescaler can be extended to values up to 1024 15 Reserved R 0h 14 12 TSeg2 R WP 2h Time segment after the sample point Valid programmed values are 0 to 7 The actual TSeg2 value which is interpreted for the bit timing will be the programmed TSeg2 value 1 11 8 TSeg1 R WP 3h Time segment before the sample point Valid programmed value...

Page 3931: ...ge object s IntPnd bit Among the message interrupts the message object s interrupt priority decreases with increasing message number 0x00 No interrupt is pending 0x01 to 0x80 Number of message object which caused the interrupt 0xff Unused 15 0 Int0ID 15 0 R 0h Interrupt Identifier the number here indicates the source of the interrupt If several interrupts are pending the CAN interrupt register wil...

Page 3932: ... Reserved R 0h R WP 0h R WP 0h R WP 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 19 TEST Register Field Descriptions Bit Field Type Reset Description 31 10 Reserved R 0h 9 RDA R WP 0h RAM direct access enable 0x0 Normal operation 0x1 Direct access to the RAM is enabled while in test mode 8 EXL R WP 0h External loopback mode 0x0 Disabled 0x1 Ena...

Page 3933: ...the last error code until power is removed Figure 23 25 PERR Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved Word_Number R 0h R 0h 7 6 5 4 3 2 1 0 Message_Number R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 20 PERR Register Field Descriptions Bit Field Type Reset Description 31 11...

Page 3934: ...toCl Write 1 to clear bit n value after reset Table 23 21 ABOTR Register Field Descriptions Bit Field Type Reset Description 31 0 ABO_Time R W 0h Number of OCP clock cycles before a Bus Off recovery sequence is started by clearing the Init bit This function has to be enabled by setting bit ABO in CAN control register The Auto Bus On timer is realized by a 32 bit counter that starts to count down t...

Page 3935: ...TxRqstReg5 R 0h R 0h R 0h R 0h 7 6 5 4 3 2 1 0 TxRqstReg4 TxRqstReg3 TxRqstReg2 TxRqstReg1 R 0h R 0h R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 22 TXRQ_X Register Field Descriptions Bit Field Type Reset Description 31 16 Reserved R 0h 15 14 TxRqstReg8 R 0h TxRqstReg8 13 12 TxRqstReg7 R 0h TxRqstReg7 11 10 TxRqstReg6 R 0h TxRqstReg6 9 8 TxRq...

Page 3936: ...R 0h 15 14 13 12 11 10 9 8 TxRqs 16 1 R 0h 7 6 5 4 3 2 1 0 TxRqs 16 1 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 23 TXRQ12 Register Field Descriptions Bit Field Type Reset Description 31 16 TxRqs 32 17 R 0h Transmission request bits for all message objects 0x0 No transmission has been requested for this message object 0x1 The transmission of thi...

Page 3937: ...0h 15 14 13 12 11 10 9 8 TxRqs 48 33 R 0h 7 6 5 4 3 2 1 0 TxRqs 48 33 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 24 TXRQ34 Register Field Descriptions Bit Field Type Reset Description 31 16 TxRqs 64 49 R 0h Transmission request bits for all message objects 0x0 No transmission has been requested for this message object 0x1 The transmission of thi...

Page 3938: ...0h 15 14 13 12 11 10 9 8 TxRqs 80 65 R 0h 7 6 5 4 3 2 1 0 TxRqs 80 65 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 25 TXRQ56 Register Field Descriptions Bit Field Type Reset Description 31 16 TxRqs 96 81 R 0h Transmission request bits for all message objects 0x0 No transmission has been requested for this message object 0x1 The transmission of thi...

Page 3939: ...0h 15 14 13 12 11 10 9 8 TxRqs 112 97 R 0h 7 6 5 4 3 2 1 0 TxRqs 112 97 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 26 TXRQ78 Register Field Descriptions Bit Field Type Reset Description 31 16 TxRqs 128 113 R 0h Transmission request bits for all message objects 0x0 No transmission has been requested for this message object 0x1 The transmission of...

Page 3940: ...ter 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 NewDatReg8 NewDatReg7 NewDatReg6 NewDatReg5 R 0h R 0h R 0h R 0h 7 6 5 4 3 2 1 0 NewDatReg4 NewDatReg3 NewDatReg2 NewDatReg1 R 0h R 0h R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 27 NWDAT_X Register Field Descriptions Bit Field Type Reset Des...

Page 3941: ...Write 1 to clear bit n value after reset Table 23 28 NWDAT12 Register Field Descriptions Bit Field Type Reset Description 31 16 NewDat 32 17 R 0h New Data Bits for all message objects 0x0 No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the CPU 0x1 The message handler or the CPU has written new data i...

Page 3942: ... Write 1 to clear bit n value after reset Table 23 29 NWDAT34 Register Field Descriptions Bit Field Type Reset Description 31 16 NewDat 64 49 R 0h New Data Bits for all message objects 0x0 No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the CPU 0x1 The message handler or the CPU has written new data ...

Page 3943: ... Write 1 to clear bit n value after reset Table 23 30 NWDAT56 Register Field Descriptions Bit Field Type Reset Description 31 16 NewDat 96 81 R 0h New Data Bits for all message objects 0x0 No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the CPU 0x1 The message handler or the CPU has written new data ...

Page 3944: ...l Write 1 to clear bit n value after reset Table 23 31 NWDAT78 Register Field Descriptions Bit Field Type Reset Description 31 16 NewDat 128 113 R 0h New Data Bits for all message objects 0x0 No new data has been written into the data portion of this message object by the message handler since the last time when this flag was cleared by the CPU 0x1 The message handler or the CPU has written new da...

Page 3945: ... set Figure 23 37 INTPND_X Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 IntPndReg8 IntPndReg7 IntPndReg6 IntPndReg5 R 0h R 0h R 0h R 0h 7 6 5 4 3 2 1 0 IntPndReg4 IntPndReg3 IntPndReg2 IntPndReg1 R 0h R 0h R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 32 INTPND_X Register Field Desc...

Page 3946: ... 16 IntPnd 32 17 R 0h 15 14 13 12 11 10 9 8 IntPnd 16 1 R 0h 7 6 5 4 3 2 1 0 IntPnd 16 1 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 33 INTPND12 Register Field Descriptions Bit Field Type Reset Description 31 16 IntPnd 32 17 R 0h Interrupt Pending Bits for all message objects 0x0 This message object is not the source of an interrupt 0x1 This mess...

Page 3947: ...16 IntPnd 64 49 R 0h 15 14 13 12 11 10 9 8 IntPnd 48 33 R 0h 7 6 5 4 3 2 1 0 IntPnd 48 33 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 34 INTPND34 Register Field Descriptions Bit Field Type Reset Description 31 16 IntPnd 64 49 R 0h Interrupt Pending Bits for all message objects 0x0 This message object is not the source of an interrupt 0x1 This mes...

Page 3948: ...16 IntPnd 96 81 R 0h 15 14 13 12 11 10 9 8 IntPnd 80 65 R 0h 7 6 5 4 3 2 1 0 IntPnd 80 65 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 35 INTPND56 Register Field Descriptions Bit Field Type Reset Description 31 16 IntPnd 96 81 R 0h Interrupt Pending Bits for all message objects 0x0 This message object is not the source of an interrupt 0x1 This mes...

Page 3949: ...IntPnd 128 113 R 0h 15 14 13 12 11 10 9 8 IntPnd 112 97 R 0h 7 6 5 4 3 2 1 0 IntPnd 112 97 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 36 INTPND78 Register Field Descriptions Bit Field Type Reset Description 31 16 IntPnd 128 113 R 0h Interrupt Pending Bits for all message objects 0x0 This message object is not the source of an interrupt 0x1 This ...

Page 3950: ...23 42 MSGVAL_X Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 MsgValReg8 MsgValReg7 MsgValReg6 MsgValReg5 R 0h R 0h R 0h R 0h 7 6 5 4 3 2 1 0 MsgValReg4 MsgValReg3 MsgValReg2 MsgValReg1 R 0h R 0h R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 37 MSGVAL_X Register Field Descriptions Bit...

Page 3951: ... 11 10 9 8 MsgVal 16 1 R 0h 7 6 5 4 3 2 1 0 MsgVal 16 1 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 38 MSGVAL12 Register Field Descriptions Bit Field Type Reset Description 31 16 MsgVal 32 17 R 0h Message valid bits for all message objects 0x0 This message object is ignored by the message handler 0x1 This message object is configured and will be ...

Page 3952: ...11 10 9 8 MsgVal 48 33 R 0h 7 6 5 4 3 2 1 0 MsgVal 48 33 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 39 MSGVAL34 Register Field Descriptions Bit Field Type Reset Description 31 16 MsgVal 64 49 R 0h Message valid bits for all message objects 0x0 This message object is ignored by the message handler 0x1 This message object is configured and will be...

Page 3953: ...11 10 9 8 MsgVal 80 65 R 0h 7 6 5 4 3 2 1 0 MsgVal 80 65 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 40 MSGVAL56 Register Field Descriptions Bit Field Type Reset Description 31 16 MsgVal 96 81 R 0h Message valid bits for all message objects 0x0 This message object is ignored by the message handler 0x1 This message object is configured and will be...

Page 3954: ...1 10 9 8 MsgVal 112 97 R 0h 7 6 5 4 3 2 1 0 MsgVal 112 97 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 41 MSGVAL78 Register Field Descriptions Bit Field Type Reset Description 31 16 MsgVal 128 113 R 0h Message valid bits for all message objects 0x0 This message object is ignored by the message handler 0x1 This message object is configured and will...

Page 3955: ...4 IntMux 32 17 R 0h 23 22 21 20 19 18 17 16 IntMux 32 17 R 0h 15 14 13 12 11 10 9 8 IntMux 16 1 R 0h 7 6 5 4 3 2 1 0 IntMux 16 1 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 42 INTMUX12 Register Field Descriptions Bit Field Type Reset Description 31 16 IntMux 32 17 R 0h Multiplexes IntPnd value to either DCAN0INT or DCAN1INT interrupt lines for al...

Page 3956: ...IntMux 64 49 R 0h 23 22 21 20 19 18 17 16 IntMux 64 49 R 0h 15 14 13 12 11 10 9 8 IntMux 48 33 R 0h 7 6 5 4 3 2 1 0 IntMux 48 33 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 43 INTMUX34 Register Field Descriptions Bit Field Type Reset Description 31 16 IntMux 64 49 R 0h Multiplexes IntPnd value to either DCAN0INT or DCAN1INT interrupt lines for al...

Page 3957: ...IntMux 96 81 R 0h 23 22 21 20 19 18 17 16 IntMux 96 81 R 0h 15 14 13 12 11 10 9 8 IntMux 80 65 R 0h 7 6 5 4 3 2 1 0 IntMux 80 65 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 44 INTMUX56 Register Field Descriptions Bit Field Type Reset Description 31 16 IntMux 96 81 R 0h Multiplexes IntPnd value to either DCAN0INT or DCAN1INT interrupt lines for al...

Page 3958: ...ux 128 113 R 0h 23 22 21 20 19 18 17 16 IntMux 128 113 R 0h 15 14 13 12 11 10 9 8 IntMux 112 97 R 0h 7 6 5 4 3 2 1 0 IntMux 112 97 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 45 INTMUX78 Register Field Descriptions Bit Field Type Reset Description 31 16 IntMux 128 113 R 0h Multiplexes IntPnd value to either DCAN0INT or DCAN1INT interrupt lines fo...

Page 3959: ... 16 WR RD Mask Arb Control ClrIntPnd TxRqst NewDat Data_A Data_B R WP 0h R WP 0h R WP 0h R WP 0h R WP 0h R WP 0h R WP 0h R WP 0h 15 14 13 12 11 10 9 8 Busy DMAactive Reserved R WP 0h R WP 0h R 0h 7 6 5 4 3 2 1 0 Message_Number R WP 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 46 IF1CMD Register Field Descriptions Bit Field Type Reset Description 31 ...

Page 3960: ...ion Write TxRqst NewDat bit will be handled according to the control bit 0x1 Direction Read Clears NewDat bit in the message object Direction Write Sets TxRqst NewDat in message object 17 Data_A R WP 0h Access Data Bytes 0 to 3 0x0 Data Bytes 0 3 will not be changed 0x1 Direction Read The data bytes 0 3 will be transferred from the message object addressed by the Message Number Bits 7 0 to the cor...

Page 3961: ...register set and message RAM The DMA request remains active until the first read or write to one of the IF1 registers an exception is a write to Message Number Bits 7 0 when DMAactive is one 13 8 Reserved R 0h 7 0 Message_Number R WP 0h Number of message object in message RAM which is used for data transfer 0x00 Invalid message number 0x01 Valid message numbers value 01 to 80 0x80 Valid message nu...

Page 3962: ...rs are used for a message object the identifiers of received data frames are written into bits ID28 to ID18 For acceptance filtering only these bits together with mask bits Msk28 to Msk18 are considered 0x0 The extended identifier bit IDE has no effect on the acceptance filtering 0x1 The extended identifier bit IDE is used for acceptance filtering 30 MDir R WP 1h Mask Message Direction 0x0 The mes...

Page 3963: ...he control bits Xtd Dir or DLC3 to DLC0 are modified or if the messages object is no longer required 0x0 The message object is ignored by the message handler 0x1 The message object is to be used by the message handler 30 Xtd R WP 0h Extended identifier 0x0 The 11 bit standard Identifier is used for this message object 0x1 The 29 bit extended Identifier is used for this message object 29 Dir R WP 0...

Page 3964: ...into the data portion of this message object 14 MsgLst R WP 0h Message lost only valid for message objects with direction receive 0x0 No message lost since the last time when this bit was reset by the CPU 0x1 The message handler stored a new message into this object when NewDat was still set so the previous message has been overwritten 13 IntPnd R WP 0h Interrupt pending 0x0 This message object is...

Page 3965: ...Buffer For single message objects not belonging to a FIFO Buffer this bit must always be set to one 0x0 Data frame has 8 data bytes 0x1 Note The data length code of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes When the message handler stores a data frame it will write the DLC to the value given by the received message 6 4 Res...

Page 3966: ...gure 23 55 IF1DATA Register 31 30 29 28 27 26 25 24 Data_3 R WP 0h 23 22 21 20 19 18 17 16 Data_2 R WP 0h 15 14 13 12 11 10 9 8 Data_1 R WP 0h 7 6 5 4 3 2 1 0 Data_0 R WP 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 50 IF1DATA Register Field Descriptions Bit Field Type Reset Description 31 24 Data_3 R WP 0h Data 3 23 16 Data_2 R WP 0h Data 2 15 8 Da...

Page 3967: ...gure 23 56 IF1DATB Register 31 30 29 28 27 26 25 24 Data_7 R WP 0h 23 22 21 20 19 18 17 16 Data_6 R WP 0h 15 14 13 12 11 10 9 8 Data_5 R WP 0h 7 6 5 4 3 2 1 0 Data_4 R WP 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 51 IF1DATB Register Field Descriptions Bit Field Type Reset Description 31 24 Data_7 R WP 0h Data 7 23 16 Data_6 R WP 0h Data 6 15 8 Da...

Page 3968: ... 16 WR RD Mask Arb Control ClrIntPnd TxRqst NewDat Data_A Data_B R WP 0h R WP 0h R WP 0h R WP 0h R WP 0h R WP 0h R WP 0h R WP 0h 15 14 13 12 11 10 9 8 Busy DMAactive Reserved R WP 0h R WP 0h R 0h 7 6 5 4 3 2 1 0 Message_Number R WP 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 52 IF2CMD Register Field Descriptions Bit Field Type Reset Description 31 ...

Page 3969: ...ion Write TxRqst NewDat bit will be handled according to the control bit 0x1 Direction Read Clears NewDat bit in the message object Direction Write Sets TxRqst NewDat in message object 17 Data_A R WP 0h Access Data Bytes 0 to 3 0x0 Data Bytes 0 3 will not be changed 0x1 Direction Read The data bytes 0 3 will be transferred from the message object addressed by the Message Number Bits 7 0 to the cor...

Page 3970: ...egister set and message RAM The DMA request remains active until the first read or write to one of the IF2 registers an exception is a write to Message Number Bits 7 0 when DMAactive is one 13 8 Reserved R 0h 7 0 Message_Number R WP 0h Number of message object in message RAM which is used for data transfer 0x00 Invalid message number 0x01 Valid message numbers values 01 to 80 0x80 Valid message nu...

Page 3971: ...rs are used for a message object the identifiers of received data frames are written into bits ID28 to ID18 For acceptance filtering only these bits together with mask bits Msk28 to Msk18 are considered 0x0 The extended identifier bit IDE has no effect on the acceptance filtering 0x1 The extended identifier bit IDE is used for acceptance filtering 30 MDir R WP 1h Mask Message Direction 0x0 The mes...

Page 3972: ...he control bits Xtd Dir or DLC3 to DLC0 are modified or if the messages object is no longer required 0x0 The message object is ignored by the message handler 0x1 The message object is to be used by the message handler 30 Xtd R WP 0h Extended identifier 0x0 The 11 bit standard Identifier is used for this message object 0x1 The 29 bit extended Identifier is used for this message object 29 Dir R WP 0...

Page 3973: ...into the data portion of this message object 14 MsgLst R WP 0h Message lost only valid for message objects with direction receive 0x0 No message lost since the last time when this bit was reset by the CPU 0x1 The message handler stored a new message into this object when NewDat was still set so the previous message has been overwritten 13 IntPnd R WP 0h Interrupt pending 0x0 This message object is...

Page 3974: ...Buffer For single message objects not belonging to a FIFO Buffer this bit must always be set to one 0x0 Data frame has 8 data bytes 0x1 Note The data length code of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes When the message handler stores a data frame it will write the DLC to the value given by the received message 6 4 Res...

Page 3975: ...gure 23 61 IF2DATA Register 31 30 29 28 27 26 25 24 Data_3 R WP 0h 23 22 21 20 19 18 17 16 Data_2 R WP 0h 15 14 13 12 11 10 9 8 Data_1 R WP 0h 7 6 5 4 3 2 1 0 Data_0 R WP 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 56 IF2DATA Register Field Descriptions Bit Field Type Reset Description 31 24 Data_3 R WP 0h Data 3 23 16 Data_2 R WP 0h Data 2 15 8 Da...

Page 3976: ...gure 23 62 IF2DATB Register 31 30 29 28 27 26 25 24 Data_7 R WP 0h 23 22 21 20 19 18 17 16 Data_6 R WP 0h 15 14 13 12 11 10 9 8 Data_5 R WP 0h 7 6 5 4 3 2 1 0 Data_4 R WP 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 57 IF2DATB Register Field Descriptions Bit Field Type Reset Description 31 24 Data_7 R WP 0h Data 7 23 16 Data_6 R WP 0h Data 6 15 8 Da...

Page 3977: ...See the device specific data sheet for the availability of this interrupt source With this interrupt the observation status bits and the IF3Upd bit could be used by the application to realize the notification about new IF3 content in polling or interrupt mode Figure 23 63 IF3OBS Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 IF3_Upd Reser...

Page 3978: ...be read 0x1 Data B section has to be read to enable next IF3 update 3 DataA R W 0h Data A read observation 0x0 Data A section has not to be read 0x1 Data A section has to be read to enable next IF3 update 2 Ctrl R W 0h Ctrl read observation 0x0 Ctrl section has not to be read 0x1 Ctrl section has to be read to enable next IF3 update 1 Arb R W 0h Arbitration data read observation 0x0 Arbitration da...

Page 3979: ...en into bits ID28 to ID18 For acceptance filtering only these bits together with mask bits Msk28 to Msk18 are considered 0x0 The extended identifier bit IDE has no effect on the acceptance filtering 0x1 The extended identifier bit IDE is used for acceptance filtering 30 MDir R 1h Mask Message Direction 0x0 The message direction bit Dir has no effect on the acceptance filtering 0x1 The message dire...

Page 3980: ...quired 0x0 The message object is ignored by the message handler 0x1 The message object is to be used by the message handler 30 Xtd R 0h Extended Identifier 0x0 The 11 bit standard Identifier is used for this message object 0x1 The 29 bit extended Identifier is used for this message object 29 Dir R 0h Message Direction 0x0 Direction receive On TxRqst a remote frame with the identifier of this messa...

Page 3981: ...PU 0x1 The message handler stored a new message into this object when NewDat was still set so the previous message has been overwritten 13 IntPnd R 0h Interrupt Pending 0x0 This message object is not the source of an interrupt 0x1 This message object is the source of an interrupt The Interrupt Identifier in the interrupt register will point to this message object if there is no other interrupt sou...

Page 3982: ... one 0x0 Data frame has 8 data bytes 0x1 Note The data length code of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes When the message handler stores a data frame it will write the DLC to the value given by the received message 6 4 Reserved R 0h 3 0 DLC R 0h Data Length Code Note The data length code of a message object must be ...

Page 3983: ...d first Figure 23 67 IF3DATA Register 31 30 29 28 27 26 25 24 Data_3 R 0h 23 22 21 20 19 18 17 16 Data_2 R 0h 15 14 13 12 11 10 9 8 Data_1 R 0h 7 6 5 4 3 2 1 0 Data_0 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 62 IF3DATA Register Field Descriptions Bit Field Type Reset Description 31 24 Data_3 R 0h Data 3 23 16 Data_2 R 0h Data 2 15 8 Data_1 R 0...

Page 3984: ...d first Figure 23 68 IF3DATB Register 31 30 29 28 27 26 25 24 Data_7 R 0h 23 22 21 20 19 18 17 16 Data_6 R 0h 15 14 13 12 11 10 9 8 Data_5 R 0h 7 6 5 4 3 2 1 0 Data_4 R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 63 IF3DATB Register Field Descriptions Bit Field Type Reset Description 31 24 Data_7 R 0h Data 7 23 16 Data_6 R 0h Data 6 15 8 Data_5 R 0...

Page 3985: ...0 IF3UpdEn 16 1 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 64 IF3UPD12 Register Field Descriptions Bit Field Type Reset Description 31 16 IF3UpdEn 32 17 R W 0h IF3 Update Enabled for all message objects 0x0 Automatic IF3 update is disabled for this message object 0x1 Automatic IF3 update is enabled for this message object A message object is s...

Page 3986: ... IF3UpdEn 48 33 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 65 IF3UPD34 Register Field Descriptions Bit Field Type Reset Description 31 16 IF3UpdEn 64 49 R W 0h IF3 Update Enabled for all message objects 0x0 Automatic IF3 update is disabled for this message object 0x1 Automatic IF3 update is enabled for this message object A message object is s...

Page 3987: ... IF3UpdEn 80 65 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 66 IF3UPD56 Register Field Descriptions Bit Field Type Reset Description 31 16 IF3UpdEn 96 81 R W 0h IF3 Update Enabled for all message objects 0x0 Automatic IF3 update is disabled for this message object 0x1 Automatic IF3 update is enabled for this message object A message object is s...

Page 3988: ...0 IF3UpdEn 112 97 R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 23 67 IF3UPD78 Register Field Descriptions Bit Field Type Reset Description 31 16 IF3UpdEn 128 113 R W 0h IF3 Update Enabled for all message objects 0x0 Automatic IF3 update is disabled for this message object 0x1 Automatic IF3 update is enabled for this message object A message object ...

Page 3989: ...0x0 CAN_TX pull down is selected when pull logic is active PD 0 0x1 CAN_TX pull up is selected when pull logic is active PD 0 17 PD R W 0h CAN_TX pull disable This bit is only active when CAN_TX is configured to be an input 0x0 CAN_TX pull is active 0x1 CAN_TX pull is disabled 16 OD R WP 0h CAN_TX open drain enable This bit is only active when CAN_TX is configured to be in GIO mode TIOC Func 0 For...

Page 3990: ... the CAN core if Init bit of CAN control register is reset 0x0 The CAN_TX pin is driven to logic low 0x1 The CAN_TX pin is driven to logic high 0 In R 0h CAN_TX data in Note When CAN_TX pin is connected to a CAN transceiver an external pullup resistor has to be used to ensure that the CAN bus will not be disturbed e g while reset of the DCAN module 0x0 The CAN_TX pin is at logic low 0x1 The CAN_TX...

Page 3991: ... CAN_RX pull down is selected when pull logic is active PD 0 0x1 CAN_T RX pull up is selected when pull logic is active PD 0 17 PD R W 0h CAN_RX pull disable This bit is only active when CAN_TX is configured to be an input 0x0 CAN_RX pull is active 0x1 CAN_RX pull is disabled 16 OD R WP 0h CAN_RX open drain enable This bit is only active when CAN_RX is configured to be in GIO mode TIOC Func 0 Forc...

Page 3992: ... CAN core if Init bit of CAN control register is reset 0x0 The CAN_RX pin is driven to logic low 0x1 The CAN_RX pin is driven to logic high 0 In R 0h CAN_RX data in Note When CAN_RX pin is connected to a CAN transceiver an external pullup resistor has to be used to ensure that the CAN bus will not be disturbed for example while reset of the DCAN module 0x0 The CAN_RX pin is at logic low 0x1 The CA...

Page 3993: ...ribes the McSPI of the device Topic Page 24 1 Introduction 3994 24 2 Integration 3995 24 3 Functional Description 3997 24 4 McSPI Registers 4032 3993 SPRUH73H October 2011 Revised April 2013 Multichannel Serial Port Interface McSPI Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 3994: ...ex Multi channel master or single channel slave operations Programmable 1 32 bit transmit receive shift operations Wide selection of SPI word lengths continuous from 4 to 32 bits Up to four SPI channels SPI word Transmit Receive slot assignment based on round robin arbitration SPI configuration per channel clock definition enable polarity and word width Clock generation supports Programmable maste...

Page 3995: ...e SPI Devices McSPI Pads PIRFFRET PER_CLKOUTM2 192 MHz PRCM SPI_GCLK 4 CH 3 2 SDMARREQN CH 3 2 SDMAWREQN www ti com Integration 24 2 Integration This device includes two instantiations of McSPI SPI0 and SPI1 The McSPI module is a general purpose receive transmit master slave controller that can interface with either up to four slave external devices or one single external master Figure 24 1 shows ...

Page 3996: ...select input pin CS0n using a GPIO attached to that device pin Neither of these methods is supported on the device Table 24 3 McSPI Clock Signals Clock Signal Max Freq Reference Source Comments CLK 100 MHz CORE_CLKOUTM4 2 pd_per_l4ls_gclk Interface clock From PRCM CLKSPIREF 48 MHz PER_CLKOUTM2 4 pd_per_spi_gclk Functional clock From PRCM 24 2 3 McSPI Pin List The McSPI interface pins are summarize...

Page 3997: ...t are not selected do not interfere with SPI bus activities Connected to multiple external devices McSPI exchanges data with a single SPI device at a time through two main modes Two data pins interface mode See Section 24 3 1 1 Single data pin interface mode recommended for half duplex transmission See Section 24 3 1 2 The flexibility of McSPI allows exchanging data with several formats through pr...

Page 3998: ...a bit is transferred out from the Master one bit is transferred in from Slave Figure 24 3 shows an example of a full duplex system with a Master device on the left and a Slave device on the right After 8 cycles of the serial clock SPICLK the WordA has been transferred from the master to the slave At the same time the 8 bit WordB has been transferred from the slave to the master When referring to t...

Page 3999: ...and a receive only Slave device on the right Each time a bit is transferred out from the Master one bit is transferred in the Slave After 8 cycles of the serial clock SPICLK the 8 bit WordA has been transferred from the master to the slave Figure 24 4 SPI Half Duplex Transmission Receive only Slave 24 3 1 2 2 Example With a Transmit Only Slave Figure 24 5 shows a half duplex system with a Master d...

Page 4000: ...e master of slave device can be connected to the SPI bus 24 3 1 3 3 Programmable SPI Enable SPIEN The polarity of the SPIEN signals is programmable SPIEN signals can be active high or low The assertion of the SPIEN signals is programmable SPIEN signals can be manually asserted or can be automatically asserted Two consecutive words for two different slave devices may go along with active SPIEN sign...

Page 4001: ... slave devices may go along with active SPICLK signal with different phase and polarity Table 24 5 Phase and Polarity Combinations Polarity POL Phase PHA SPI Mode Comments 0 0 mode0 SPICLK active high and sampling occurs on the rising edge 0 1 mode1 SPICLK active high and sampling occurs on the falling edge 1 0 mode2 SPICLK active low and sampling occurs on the falling edge 1 1 mode3 SPICLK active...

Page 4002: ...data line This process continues for a total of pulses on the SPICLK line defined by the SPI word length programmed in the master device with data being latched on odd numbered edges and shifted on even numbered edges Figure 24 7 is a timing diagram of a SPI transfer for the SPI mode0 and the SPI mode2 when McSPI is master or slave with the frequency of SPICLK equals to the frequency of CLKSPIREF ...

Page 4003: ... received data bit is shifted into the shift register The next data bit of the master is provided to the serial input pin of the slave This process continues for a total of pulses on the SPICLK line defined by the word length programmed in the master device with data being latched on even numbered edges and shifted on odd numbered edges Figure 24 8 is a timing diagram of a SPI transfer for the SPI...

Page 4004: ...bits IS and DPE SPI word length programmable with the bits WL SPIEN polarity programmable with the bit EPOL SPIEN kept active between words programmable with the bit FORCE Turbo mode programmable with the bit TURBO SPICLK frequency programmable with the bit CLKD the granularity of clock division can be changed using CLKG bit the clock ratio is then concatenated with MCSPI_CHCTRL EXTCLK value SPICL...

Page 4005: ... Transmit Register MCSPI_TX i should be loaded as infrequently as possible TX_underflow interrupt status bit must be cleared for interrupt line de assertion if event enable as interrupt source Note When more than one channel has an FIFO enable bit field FFER or FFEW set the FIFO will not be used on any channel Software must ensure that only one enabled channel is configured to use the FIFO buffer ...

Page 4006: ...serialization transmit and receive starts according to the channel communication configuration On serialization completion the received data is transferred to the channel receive register The built in FIFO is available in this mode and if configured in one data direction transmit or receive then the FIFO is seen as a unique 64 byte buffer If configured in both data directions transmit and receive ...

Page 4007: ...as transmit register or FIFO is not empty In 4 pin mode MCSPI_MODULCTRL 1 PIN34 bit is cleared to 0 and MCSPI_MODULCTRL 0 SINGLE bit is set to 1 SPIEN assertion deassertion controlled by Software See Section 24 3 2 6 1 using the MCSPI_CHxCONF 20 FORCE bit 24 3 2 6 1 Programming Tips When Switching to Another Channel When a single channel is enabled and data transfer is ongoing Wait for completion ...

Page 4008: ...he SPIEN signal is activated The Transmit Receive mode programmable with the bit TRM can be modified only when the channel is disabled The channel can be disabled and enabled while the SPIEN signal is activated The delay between SPI words that requires the connected SPI slave device to switch from one configuration Transmit only for instance to another receive only for instance must be handled und...

Page 4009: ...led if its receive register is full bit RXS of the register MCSPI_CH I STAT at the time of shift register assignment until the shift register is full The receiver register cannot be overwritten in turbo mode In consequence the RX_overflow bit in MCSPI_IRQSTATUS register is never set in this mode 24 3 2 7 Start Bit Mode The purpose of the start bit mode is to add an extended bit before the SPI word...

Page 4010: ...14 15 16 17 18 D CX MSB Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 LSB D CX MSB Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 LSB Transfer Functional Description www ti com Figure 24 11 Extended SPI Transfer With Start Bit PHA 1 4010 Multichannel Serial Port Interface McSPI SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 4011: ...which occurs when granularity is one clock cycle that means that MCSPI_CH I CONF CLKG is set to 1 and MCSPI_CH I CONF CLKD has an even value the clock duty cycle is not 50 then one of the high level or low level duration is selected to be added to TCS delay Table 24 6 summarizes all delays between chip select and first setup or last hold clock edge In 3 pin mode this option is useless the chip sel...

Page 4012: ...ti com Fratio MCSPI_CH I CNTRL EXTCLK MCSPI_CH I CONF CLKD 1 4012 Multichannel Serial Port Interface McSPI SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 4013: ...KSPIREF period in ns Thigh_ref CLKSPIREF high Time period in ns Tlow_ref CLKSPIREF low Time period in ns Fratio SPI clock division ratio Fratio MCSPI_CH I CTRL EXTCLK MCSPI_CH I CONF CLKD 1 For odd ratio value the duty cycle is calculated as below Duty_cycle Granularity examples With a clock source frequency of 48 MHz Table 24 8 Clock Granularity Examples MCSPI_CH MCSPI_CH MCSPI_CH MCSPI_CH MCSPI_...

Page 4014: ... and AFL located in MCSPI_XFERLEVEL register rule the buffer management The granularity of these levels is one byte then it is not aligned with SPI word length It is the responsibility of the driver to set these values as a multiple of SPI word length defined in MCSPI_CH I CONF WL The number of byte written in the FIFO depends on word length see Table 24 9 Table 24 9 FIFO Writes Word Length Relati...

Page 4015: ... RX Shift Register TX Shift Clock RX Shift Clock SPI Domain OCP Domain Configuration MCSPI_CH i CONF TRM 0x0 Transmit receive mode MCSPI_CH i CONF FFRE 0x0 FIFO disabled on receive path MCSPI_CH i CONF FFWE 0x0 FIFO disabled on transmit path OCP Bus SPIDATAO SPIDATAI www ti com Functional Description Figure 24 13 Transmit Receive Mode With No FIFO Used Figure 24 14 Transmit Receive Mode With Only ...

Page 4016: ...ister RX Shift Register TX Shift Clock RX Shift Clock SPI Domain OCP Domain Configuration MCSPI_CH i CONF TRM 0x0 Transmit receive mode MCSPI_CH i CONF FFRE 0x0 FIFO disabled on receive path MCSPI_CH i CONF FFWE 0x1 FIFO enabled on transmit path OCP Bus SPIDATAO SPIDATAI Functional Description www ti com Figure 24 15 Transmit Receive Mode With Only Transmit FIFO Used Figure 24 16 Transmit Receive ...

Page 4017: ...hift Register RX Shift Register TX Shift Clock RX Shift Clock SPI Domain OCP Domain Configuration MCSPI_CH i CONF TRM 0x2 Transmit only mode MCSPI_CH i CONF FFRE 0x1 FIFO enabled on transmit path MCSPI_CH i CONF FFWE not applicable OCP Bus SPIDATAO SPIDATAI www ti com Functional Description Figure 24 17 Transmit Only Mode With FIFO Used Figure 24 18 Receive Only Mode With FIFO Used 4017 SPRUH73H O...

Page 4018: ...he CPU to enable system to read AFL 1 bytes from receive register Be careful AFL 1 must correspond to a multiple value of MCSPI_CH I CONF WL When DMA is used the request is de asserted after the first receive register read No new request will be asserted until the system has performed the correct number of read operations from the buffer Figure 24 19 Buffer Almost Full Level AFL NOTE SPI_IRQSTATUS...

Page 4019: ...10 4 End of Transfer Management When the FIFO buffer is enabled for a channel the user should configure the MCSPI_XFERLEVEL register the AEL and AFL levels and especially the WCNT bit field to define the number of SPI word to be transferred using the FIFO This should be done before enabling the channel This counter allows the controller to stop the transfer correctly after a defined number of SPI ...

Page 4020: ...access depending on SPI word length 3 WL 7 SPI word length smaller or equal to byte length four SPI words accessed per 32 bit OCP read write If word count is used MCSPI_XFERLEVEL WCNT set the bit field to WCNT 0 WCNT 1 0 8 WL 15 SPI word length greater than byte or equal to 16 bit length two SPI words accessed per 32 bit OCP read write If word count is used MCSPI_XFERLEVEL WCNT set the bit field t...

Page 4021: ...value the controller is in 4 pin mode using the SPI pins CLKSPI SOMI SIMO and chip enable CS If MCSPI_MODULCTRL PIN34 is set to 1 the controller is in 3 pin mode using the SPI pins CLKSPI SOMI and SIMO In 3 pin mode it is mandatory to put the controller in single channel master mode MCSPI_MODULECTRL SINGLE asserted and to connect only one SPI device on the bus Figure 24 22 3 Pin Mode System Overvi...

Page 4022: ...r whether it has been updated or not The transmitter register should be loaded before McSPI is selected by a master Its own receiver register MCSPI_RX on top of the common shift register If the receiver register is full the status bit RXS of the register MCSPI_CH0STAT is set NOTE The transmitter register and receiver registers of the other channels are not used Read from or Write in the registers ...

Page 4023: ...nd its transmitter register becomes empty Enabling channel automatically raises this event When FIFO buffer is enabled MCSPI_CH I CONF FFEW set to 1 the TX_empty is asserted as soon as there is enough space in buffer to write a number of byte defined by MCSPI_XFERLEVEL AEL Transmitter register must be load to remove source of interrupt and TX_empty interrupt status bit must be cleared for interrup...

Page 4024: ...W event is activated in slave mode in either transmit and receive or receive only mode when a channel is enabled and the SPI_RXn register or FIFO is full when a new SPI word is received The SPI_RXn register is always overwritten with the new SPI word If the FIFO is enabled data within the FIFO is overwritten it must be considered as corrupted The RX0_OVERFLOW event should not appear in slave mode ...

Page 4025: ...evice Transmitter register or FIFO if enabled content is always loaded into the shift register whether it has been updated or not The event TX_underflow is activated accordingly and does not prevent transmission When an SPI word transfer completes the MCSPI_CH I STAT EOT bit with I 0 is set to 1 the received data is transferred to the channel receive register To use McSPI as a slave receive only d...

Page 4026: ...FIFO is seen as a unique 64 byte buffer Figure 24 25 shows a half duplex system with a master device on the left and a transmit only slave device on the right Each time a bit transfers out from the slave device one bit transfers in the master If WordB is 8 bits then after eight cycles of the serial clock spim_clk WordB transfers from the slave to the master Figure 24 25 SPI Half Duplex Transmissio...

Page 4027: ... remove the source of the events TX_underflow and RX_overflow Writing a 1 into the corresponding bit of MCSPI_IRQSTATUS register clears the interrupt status and does not affect the interrupt line state 24 3 5 DMA Requests McSPI can be interfaced with a DMA controller At system level the advantage is to free the local host of the data transfers According to its transmitter register state its receiv...

Page 4028: ...FO to be compliant the a DMA handler providing only 256 bit aligned addresses This features is activated when the bit field MCSPI_MODULCTRL FDDA is set to 1 and only one enabled channel have its bit field MCSPI_CH I CONF FFEW or MCSPI_CH I CONF FFER enabled In this case the registers MCSPI_TX I and MCSPI_RX I are not used and data is managed through registers MCSPI_DAFTX and MCSPI_DAFRX 24 3 6 Emu...

Page 4029: ...ger request and behaves normally as if the request was not asserted When programmed for smart idle mode the bit SIdleMode of the register MCSPI_SYSCONFIG is set to 10 the module acknowledges the system power manager request according to its internal state When programmed for force idle mode the bit SIdleMode of the register MCSPI_SYSCONFIG is set to 00 the module acknowledges the system power mana...

Page 4030: ... responsibility Any access to the module in force idle mode will generate an error as long as the OCP clock is alive and IdleReq is asserted The module exits the force idle mode when The idle request signal IdleReq is de asserted Upon IdleReq de assertion the module switches back to normal mode and de asserts SIdleAck signal The module is fully operational The interrupt and DMA request lines are o...

Page 4031: ... and the content of the data registers is not reset between the SPI data transfers The coherence between the number of bits of the SPI Word the number of bits of the access and the enabled byte remains under the user s responsibility Only aligned accesses are supported In Master mode data should not be written in the transmit register when the channel is disbaled 24 3 11 Programming Aid 24 3 11 1 ...

Page 4032: ...RL McSPI module control register Section 24 4 1 7 12Ch MCSPI_CH0CONF McSPI channel i configuration register Section 24 4 1 8 130h MCSPI_CH0STAT McSPI channel i status register Section 24 4 1 9 134h MCSPI_CH0CTRL McSPI channel i control register Section 24 4 1 10 138h MCSPI_TX0 McSPI channel i FIFO transmit buffer register Section 24 4 1 11 13Ch MCSPI_RX0 McSPI channel i FIFO receive buffer registe...

Page 4033: ...ive buffer register Section 24 4 1 12 17Ch MCSPI_XFERLEVEL McSPI transfer levels register Section 24 4 1 13 180h MCSPI_DAFTX McSPI DMA address aligned FIFO transmitter register 1A0h MCSPI_DAFRX McSPI DMA address aligned FIFO receiver register Section 24 4 1 15 4033 SPRUH73H October 2011 Revised April 2013 Multichannel Serial Port Interface McSPI Submit Documentation Feedback Copyright 2011 2013 Te...

Page 4034: ... 0 R W 2h LEGEND R W Read Write n value after reset Table 24 11 McSPI Revision Register MCSPI_REVISION Field Descriptions Bit Field Value Description 31 30 SCHEME Used to distinguish between old scheme and current 0 Legacy ASP or WTBU scheme 1 Revision 0 8 scheme 29 28 Reserved 0 Read returns 0 27 16 FUNC 030h Function indicates a software compatible module family If there is no level of software ...

Page 4035: ...ctional clock is maintained OCP clock may be switched off 3h OCP and Functional clocks are maintained 7 5 Reserved 0 Reads returns 0 4 3 SIDLEMODE Power management 0 If an idle request is detected the McSPI acknowledges it unconditionally and goes in Inactive mode Interrupt DMA requests are unconditionally de asserted 1h If an idle request is detected the request is ignored and keeps on behaving n...

Page 4036: ...YSSTATUS 31 16 Reserved R 0 15 1 0 Reserved RESETDONE R 0 R 0 LEGEND R Read only n value after reset Table 24 13 McSPI System Status Register MCSPI_SYSSTATUS Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved for module specific status information Read returns 0 0 RESETDONE Internal Reset Monitoring 0 Internal module reset is on going 1 Reset completed 4036 Multichannel Serial...

Page 4037: ...a channel is enabled using the FIFO buffer and the channel has sent the number of McSPI words defined by the MCSPI_XFERLEVEL WCNT Write 0 Event status bit is unchanged Read 0 Event false Write 1 Event status bit is reset Read 1 Event is pending 16 Reserved 0 Reserved 15 Reserved 0 Reads returns 0 14 RX3_FULL Receiver register is full or almost full Only when Channel 3 is enabled This bit indicate ...

Page 4038: ...FO is used for transmit register MCSPI_CH3CONF FFE2W is set Write 0 Event status bit is unchanged Read 0 Event false Write 1 Event status bit is reset Read 1 Event is pending 7 Reserved 0 Reads returns 0 6 RX1_FULL Receiver register full or almost full Channel 1 This bit indicate FIFO almost full status when built in FIFO is use for receive register MCSPI_CH3CONF FFE1R is set Write 0 Event status ...

Page 4039: ...er underflow Channel 0 Write 0 Event status bit is unchanged Read 0 Event false Write 1 Event status bit is reset Read 1 Event is pending 0 TX0_EMPTY Transmitter register empty or almost empty Channel 0 This bit indicate FIFO almost full status when built in FIFO is use for transmit register MCSPI_CH3CONF FFE0W is set Write 0 Event status bit is unchanged Read 0 Event false Write 1 Event status bi...

Page 4040: ...ord count interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled 16 Reserved Reserved 15 Reserved 0 Reads return 0 14 RX3_FULL_ ENABLE MCSPI_RX3 receiver register full or almost full interrupt enable channel 3 0 Interrupt is disabled 1 Interrupt is enabled 13 TX3_UNDERFLOW_ ENABLE MCSPI_TX3 transmitter register underflow interrupt enable channel 3 0 Interrupt is disabled 1 Interrupt is en...

Page 4041: ... Interrupt is enabled 3 RX0_OVERFLOW_ ENABLE MCSPI_RX0 receivier register overflow interrupt enable channel 0 0 Interrupt is disabled 1 Interrupt is enabled 2 RX0_FULL_ ENABLE MCSPI_RX0 receiver register full or almost full interrupt enable channel 0 0 Interrupt is disabled 1 Interrupt is enabled 1 TX0_UNDERFLOW_ ENABLE MCSPI_TX0 transmitter register underflow interrupt enable channel 0 0 Interrup...

Page 4042: ...I_IRQSTATUS register 10 SPIENDIR Sets the direction of the SPIEN 3 0 lines and SPICLK line 0 Output as in master mode 1 Input as in slave mode 9 SPIDATDIR1 Sets the direction of the SPIDAT 1 0 Output 1 Input 8 SPIDATDIR0 Sets the direction of the SPIDAT 0 0 Output 1 Input 7 Reserved 0 Reserved 6 SPICLK SPICLK line signal data value If MCSPI_SYST SPIENDIR 1 input mode direction this bit returns the...

Page 4043: ...the value on the SPIEN 2 line high or low and a write into this bit has no effect 1 SPIEN_1 SPIEN 1 line signal data value If MCSPI_SYST SPIENDIR 0 output mode direction the SPIENT 1 line is driven high or low according to the value written into this register If MCSPI_SYST SPIENDIR 1 input mode direction this bit returns the value on the SPIEN 1 line high or low and a write into this bit has no ef...

Page 4044: ...ple SPI word access for a single 32 bit OCP word access This is possible for WL 16 0 Multiple word access disabled 1 Multiple word access enabled with FIFO 6 4 INITDLY Initial SPI delay for first transfer This register is an option only available in SINGLE master mode The controller waits for a delay to transmit the first SPI word after channel enabled and corresponding TX register filled This Del...

Page 4045: ...Single channel Multi Channel master mode only 0 More than one channel will be used in master mode 1 Only one channel will be used in master mode This bit must be set in Force SPIEN mode 4045 SPRUH73H October 2011 Revised April 2013 Multichannel Serial Port Interface McSPI Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 4046: ...configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF CLKD and MCSPI_CHCTRL EXTCLK values 0 Clock granularity of power of 2 1 1 clock cycle granularity 28 FFER FIFO enabled for receive Only one channel can have this bit set 0 The buffer is not used to receive data 1 The buffer is used to receive data 27 FFEW FIFO enabled for trans...

Page 4047: ...ected for reception 17 DPE1 Transmission enable for data line 1 SPIDATAGZEN 1 0 Data line 1 SPIDAT 1 selected for transmission 1 No transmission on data line 1 SPIDAT 1 16 DPE0 Transmission enable for data line 0 SPIDATAGZEN 0 0 Data line 0 SPIDAT 0 selected for transmission 1 No transmission on data line 0 SPIDAT 0 15 DMAR DMA read request The DMA read request line is asserted when the channel is...

Page 4048: ...ts long 10h The SPI word is 17 bits long 11h The SPI word is 18 bits long 12h The SPI word is 19 bits long 13h The SPI word is 20 bits long 14h The SPI word is 21 bits long 15h The SPI word is 22 bits long 16h The SPI word is 23 bits long 17h The SPI word is 24 bits long 18h The SPI word is 25 bits long 19h The SPI word is 26 bits long 1Ah The SPI word is 27 bits long 1Bh The SPI word is 28 bits l...

Page 4049: ... 7h 128 8h 256 9h 512 Ah 1024 Bh 2048 Ch 4096 Dh 8192 Eh 16384 Fh 32768 1 POL SPICLK polarity 0 SPICLK is held high during the active state 1 SPICLK is held low during the active state 0 PHA SPICLK phase 0 Data are latched on odd numbered edges of SPICLK 1 Data are latched on even numbered edges of SPICLK Table 24 19 Data Lines Configurations TRMi ISi DPEi1 DPEi0 Transmit and Receive Receive Only ...

Page 4050: ...smit buffer empty status 0 FIFO transmit buffer is not empty 1 FIFO transmit buffer is empty 2 EOT Channel i end of transfer status The definitions of beginning and end of transfer vary with master versus slave and the transfer format transmit receive mode turbo mode 0 This flag is automatically cleared when the shift register is loaded with the data from the transmitter register beginning of tran...

Page 4051: ...CTRL Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 8 EXTCLK Clock ratio extension Used to concatenate with the CLKD bit field in MCSPI_CHnCONF for clock ratio only when granularity is 1 clock cycle CLKG bit in MCSPI_CHnCONF set to 1 Then the maximum value reached is a 4096 clock divider ratio 0 Clock ratio is CLKD 1 1h Clock ratio is CLKD 1 16 FFh Clock ratio is CLKD ...

Page 4052: ... 31 0 TDATA 0 FFFF FFFFh Channel i data to transmit 24 4 1 12 McSPI Channel i Receive Register MCSPI_RX i The McSPI channel i FIFO receive buffer register MCSPI_RX i contains a single McSPI word received through the serial link The MCSPI_RX i is shown in Figure 24 37 and described in Table 24 23 Little endian host access SPI 8 bit word on 0 big endian host accesses on 3h Figure 24 37 McSPI Channel...

Page 4053: ...SPI word transfer index 0 Counter not used 1 1 SPI word FFFEh 65534 SPI word FFFFh 65535 SPI word 15 14 Reserved 0 Reserved 13 8 AFL Buffer almost full Holds the programmable almost full level value used to determine almost full buffer condition If you want an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least n bytes then the buffer MCSPI_M...

Page 4054: ...words are transferred with MSB first Figure 24 39 McSPI DMA Address Aligned FIFO Transmitter Register MCSPI_DAFTX 31 16 DAFTDATA R W 0 15 0 DAFTDATA R W 0 LEGEND R W Read Write n value after reset Table 24 25 McSPI DMA Address Aligned FIFO Transmitter Register MCSPI_DAFTX Field Descriptions Bit Field Value Description 31 0 DAFTDATA FIFO Data to transmit with DMA 256 bit aligned address This regist...

Page 4055: ...ess Aligned FIFO Receiver Register MCSPI_DAFRX 31 16 DAFRDATA R 0 15 0 DAFRDATA R 0 LEGEND R W Read Write n value after reset Table 24 26 McSPI DMA Address Aligned FIFO Receiver Register MCSPI_DAFRX Field Descriptions Bit Field Value Description 31 0 DAFRDATA FIFO Received Data with DMA 256 bit aligned address This register is used only when MCSPI_MODULCTRL FDAA is set to 1 and only one of the MCS...

Page 4056: ...cribes the GPIO of the device Topic Page 25 1 Introduction 4057 25 2 Integration 4058 25 3 Functional Description 4061 25 4 GPIO Registers 4068 4056 General Purpose Input Output SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 4057: ... be configured to be used in the following applications Data input output Keyboard interface with a de bouncing cell Synchronous interrupt generation in active mode upon the detection of external events signal transition s and or signal level s Wake up request generation in Idle mode upon the detection of signal transition s Global features of the GPIO interface are Synchronous interrupt requests ...

Page 4058: ...ons and wake up signal Two Interrupt lines are available for bi processor operation Pins can be dedicated to be used as a keyboard controller With four GPIO modules the device allows for a maximum of 128 GPIO pins The exact number available varies as a function of the device configuration and pin muxing GPIO0 is in the Wakeup domain and may be used to wakeup the device via external sources GPIO 1 ...

Page 4059: ...request only for GPIO1 GPIOEVT1 and GPIO2 GPIOEVT2 Physical Address L4 Peripheral slave port 25 2 2 GPIO Clock and Reset Management The GPIO modules require two clocks The de bounce clock is used for the de bouncing cells The interface clock provided by the peripheral bus L4 interface is also the functional clock and is used through the entire GPIO module except within the de bouncing sub module I...

Page 4060: ... module includes 32 interface I Os These signals are designated as shown in Table 25 4 Note that for this device most of these signals will be multiplexed with functional signals from other interfaces Table 25 4 GPIO Pin List Pin Type Description GPIO0 GPIO0_ 31 0 I O General Purpose Input Output pins GPIO1 GPIO1_ 31 0 I O General Purpose Input Output pins GPIO2 GPIO2_ 31 0 I O General Purpose Inp...

Page 4061: ...eral bus OCP compatible system interface It is used through the entire GPIO module except within the debouncing sub module logic It clocks the OCP interface and the internal logic Clock gating features allow adapting the module power consumption to the activity 25 3 2 2 Clocks Gating and Active Edge Definitions The interface clock provided by the peripheral bus OCP compatible system interface is u...

Page 4062: ...r the GPIO module goes to the Idle mode only if there is no active bit in GPIO_IRQSTATUS_RAW_n registers 25 3 2 4 Reset The OCP hardware Reset signal has a global reset action on the GPIO All configuration registers all DFFs clocked with the Interface clock or Debouncing clock and all internal state machines are reset when the OCP hardware Reset is active low level The RESETDONE bit in the system ...

Page 4063: ...t GPIO to trigger a synchronous interrupt request is two times the internally gated interface clock period the internally gated interface clock period is equal to N times the interface clock period This minimum pulse width has to be met before and after any expected level transition detection Level detection requires the selected level to be stable for at least two times the internally gated inter...

Page 4064: ...then a single clock is active NOTE When the clocks are enabled by writing to the GPIO_LEVELDETECT0 GPIO_LEVELDETECT1 GPIO_RISINGDETECT and GPIO_FALLINGDETECT registers the detection starts after 5 clock cycles This period is required to clean the synchronization edge level detection pipeline The mechanism is independent of each clock group If the clock has been started before a new setting is perf...

Page 4065: ...ure write 0000 0000 0000 0001h at the address of the clear data output register or at the address of the clear interrupt enable register After this write operation a reading of the data output register or the interrupt enable register returns 0000 0001 0000 0000h bit 0 is cleared NOTE Although the general purpose interface registers are 32 bits wide only the 16 least significant bits are represent...

Page 4066: ...ite access to the set data output register GPIO_SETDATAOUT or to the clear data output register GPIO_CLEARDATAOUT address If the application uses a pin as an output and does not want interrupt generation from this pin the application must properly configure the interrupt enable registers When configured as an input the desired bit set to 1 in GPIO_OE the state of the input can be read from the cor...

Page 4067: ...d matrix key is pressed the corresponding row and column lines are shorted together and a low level is driven on the corresponding row channel This generates an interrupt based on the proper configuration see Section 25 3 3 When the keyboard interrupt is received the processor can disable the keyboard interrupt and scan the column channels for the key coordinates The scanning sequence has as many ...

Page 4068: ...QSTATUS_SET_1 Section 25 4 1 9 3Ch GPIO_IRQSTATUS_CLR_0 Section 25 4 1 10 40h GPIO_IRQSTATUS_CLR_1 Section 25 4 1 11 44h GPIO_IRQWAKEN_0 Section 25 4 1 12 48h GPIO_IRQWAKEN_1 Section 25 4 1 13 114h GPIO_SYSSTATUS Section 25 4 1 14 130h GPIO_CTRL Section 25 4 1 15 134h GPIO_OE Section 25 4 1 16 138h GPIO_DATAIN Section 25 4 1 17 13Ch GPIO_DATAOUT Section 25 4 1 18 140h GPIO_LEVELDETECT0 Section 25 ...

Page 4069: ...1h R 0h 7 6 5 4 3 2 1 0 CUSTOM MINOR R 0h R 1h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 6 GPIO_REVISION Register Field Descriptions Bit Field Type Reset Description 31 30 SCHEME R 1h Used to distinguish between old Scheme and current 29 28 Reserved R 1h 27 16 FUNC R 60h Indicates a software compatible module family 15 11 RTL R 1h RTL version 10 8 M...

Page 4070: ...ster Field Descriptions Bit Field Type Reset Description 31 5 Reserved R 0h 4 3 IDLEMODE R W 0h Power Management Req Ack control 0x0 Force idle An idle request is acknowledged unconditionally 0x1 No idle An idle request is never acknowledged 0x2 Smart idle Acknowledgment to an idle request is given based on the internal activity of the module 0x3 Smart Idle Wakeup GPIO0 only 2 ENAWAKEUP R W 0h 0x0...

Page 4071: ...3 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved DMAEvent_Ack R 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 8 GPIO_EOI Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 DMAEvent_Ack R W 0h Write 0 to acknowledge DMA event has been completed Module will be able to generate another DMA event only when the p...

Page 4072: ... is not be modified Only enabled active events trigger an actual interrupt request on the IRQ output line Figure 25 10 GPIO_IRQSTATUS_RAW_0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTLINE n R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 9 GPIO_IRQSTATUS_RAW_0 Register Field Descriptions Bit Fi...

Page 4073: ... is not be modified Only enabled active events trigger an actual interrupt request on the IRQ output line Figure 25 11 GPIO_IRQSTATUS_RAW_1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTLINE n R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 10 GPIO_IRQSTATUS_RAW_1 Register Field Descriptions Bit F...

Page 4074: ...ve events trigger an actual interrupt request on the IRQ output line Figure 25 12 GPIO_IRQSTATUS_0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTLINE n R W1C 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 11 GPIO_IRQSTATUS_0 Register Field Descriptions Bit Field Type Reset Description 31 0 INTLINE n ...

Page 4075: ...ve events trigger an actual interrupt request on the IRQ output line Figure 25 13 GPIO_IRQSTATUS_1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTLINE n R W1C 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 12 GPIO_IRQSTATUS_1 Register Field Descriptions Bit Field Type Reset Description 31 0 INTLINE n ...

Page 4076: ...alue is not modified Figure 25 14 GPIO_IRQSTATUS_SET_0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTLINE n R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 13 GPIO_IRQSTATUS_SET_0 Register Field Descriptions Bit Field Type Reset Description 31 0 INTLINE n R W 0h Interrupt n enable 0x0 No effect 0x...

Page 4077: ...alue is not modified Figure 25 15 GPIO_IRQSTATUS_SET_1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTLINE n R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 14 GPIO_IRQSTATUS_SET_1 Register Field Descriptions Bit Field Type Reset Description 31 0 INTLINE n R W 0h Interrupt n enable 0x0 No effect 0x...

Page 4078: ...fied Figure 25 16 GPIO_IRQSTATUS_CLR_0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTLINE n R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 15 GPIO_IRQSTATUS_CLR_0 Register Field Descriptions Bit Field Type Reset Description 31 0 INTLINE n R W 0h Interrupt n enable 0x0 No effect 0x1 Disable IRQ ge...

Page 4079: ...fied Figure 25 17 GPIO_IRQSTATUS_CLR_1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTLINE n R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 16 GPIO_IRQSTATUS_CLR_1 Register Field Descriptions Bit Field Type Reset Description 31 0 INTLINE n R W 0h Interrupt n enable 0x0 No effect 0x1 Disable IRQ ge...

Page 4080: ...quest coming from the host processor Note In Force Idle mode the module wake up feature is totally inhibited The wake up generation can also be gated at module level using the EnaWakeUp bit from GPIO_SYSCONFIG register Figure 25 18 GPIO_IRQWAKEN_0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTLINE R W 0h LEGEND R W Read Write R Read only W1toCl W...

Page 4081: ...equest coming from the host processor Note In Force Idle mode the module wake up feature is totally inhibited The wake up generation can also be gated at module level using the EnaWakeUp bit from GPIO_SYSCONFIG register Figure 25 19 GPIO_IRQWAKEN_1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTLINE R W 0h LEGEND R W Read Write R Read only W1toCl ...

Page 4082: ...served R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved RESETDONE R 0h R 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 19 GPIO_SYSSTATUS Register Field Descriptions Bit Field Type Reset Description 31 1 Reserved R 0h 0 RESETDONE R 0h Reset status information 0x0 Internal Reset is on going 0x1 Res...

Page 4083: ...e 25 21 GPIO_CTRL Register 31 30 29 28 27 26 25 24 Reserved R 0h 23 22 21 20 19 18 17 16 Reserved R 0h 15 14 13 12 11 10 9 8 Reserved R 0h 7 6 5 4 3 2 1 0 Reserved GATINGRATIO DISABLEMODULE R 0h R W 0h R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 20 GPIO_CTRL Register Field Descriptions Bit Field Type Reset Description 31 3 Reserved R 0h 2 1 GAT...

Page 4084: ...in the application can has to properly configure the Interrupt Enable registers Figure 25 22 GPIO_OE Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OUTPUTEN n R W FFFFFFFFh LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 21 GPIO_OE Register Field Descriptions Bit Field Type Reset Description 31 0 OUTPUTEN n ...

Page 4085: ...write the data When the AUTOIDLE bit in the system configuration register GPIO_SYSCONFIG is set the GPIO_DATAIN read command has a 3 OCP cycle latency due to the data in sample gating mechanism When the AUTOIDLE bit is not set the GPIO_DATAIN read command has a 2 OCP cycle latency Figure 25 23 GPIO_DATAIN Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ...

Page 4086: ...ts of this register with a single write access to the set data output register GPIO_SETDATAOUT or to the clear data output register GPIO_CLEARDATAOUT address Figure 25 24 GPIO_DATAOUT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATAOUT R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 23 GPIO_DATAOUT...

Page 4087: ...or Figure 25 25 GPIO_LEVELDETECT0 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LEVELDETECT0 n R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 24 GPIO_LEVELDETECT0 Register Field Descriptions Bit Field Type Reset Description 31 0 LEVELDETECT0 n R W 0h Low Level Interrupt Enable 0x0 Disable the IRQ as...

Page 4088: ...r Figure 25 26 GPIO_LEVELDETECT1 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LEVELDETECT1 n R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 25 GPIO_LEVELDETECT1 Register Field Descriptions Bit Field Type Reset Description 31 0 LEVELDETECT1 n R W 0h High Level Interrupt Enable 0x0 Disable the IRQ as...

Page 4089: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RISINGDETECT n R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 26 GPIO_RISINGDETECT Register Field Descriptions Bit Field Type Reset Description 31 0 RISINGDETECT n R W 0h Rising Edge Interrupt Enable 0x0 Disable IRQ on rising edge detect 0x1 Enable IRQ on rising ...

Page 4090: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FALLINGDETECT n R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 27 GPIO_FALLINGDETECT Register Field Descriptions Bit Field Type Reset Description 31 0 FALLINGDETECT n R W 0h Falling Edge Interrupt Enable 0x0 Disable IRQ on falling edge detect 0x1 Enable IRQ on fa...

Page 4091: ...12 11 10 9 8 7 6 5 4 3 2 1 0 DEBOUNCEENABLE n R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 28 GPIO_DEBOUNCENABLE Register Field Descriptions Bit Field Type Reset Description 31 0 DEBOUNCEENABLE n R W 0h Input Debounce Enable 0x0 Disable debouncing feature on the corresponding input port 0x1 Enable debouncing feature on the corresponding input po...

Page 4092: ...gister 31 30 29 28 27 26 25 24 Reserved R W 0h 23 22 21 20 19 18 17 16 Reserved R W 0h 15 14 13 12 11 10 9 8 Reserved R W 0h 7 6 5 4 3 2 1 0 DEBOUNCETIME R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 29 GPIO_DEBOUNCINGTIME Register Field Descriptions Bit Field Type Reset Description 31 8 Reserved R W 0h 7 0 DEBOUNCETIME R W 0h Input Debouncing Va...

Page 4093: ...UT Figure 25 31 GPIO_CLEARDATAOUT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTLINE n R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 30 GPIO_CLEARDATAOUT Register Field Descriptions Bit Field Type Reset Description 31 0 INTLINE n R W 0h Clear Data Output Register 0x0 No effect 0x1 Clear the corr...

Page 4094: ...T Figure 25 32 GPIO_SETDATAOUT Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTLINE n R W 0h LEGEND R W Read Write R Read only W1toCl Write 1 to clear bit n value after reset Table 25 31 GPIO_SETDATAOUT Register Field Descriptions Bit Field Type Reset Description 31 0 INTLINE n R W 0h Set Data Output Register 0x0 No effect 0x1 Set the corresponding...

Page 4095: ...nitialization This chapter describes the initialization of the device Topic Page 26 1 Functional Description 4096 4095 SPRUH73H October 2011 Revised April 2013 Initialization Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 4096: ...s the device into public mode Hence the Public ROM Code provides run time services for cache maintenance 26 1 1 Architecture The architecture of the Public ROM Code is shown in Figure 26 1 It is split into three main layers with a top down approach high level drivers and hardware abstraction layer HAL One layer communicates with a lower level layer through a unified interface The high level layer ...

Page 4097: ... loop of the booting procedure goes through the booting device list and tries to search for an image from the currently selected booting device This loop is exited if a valid booting image is found and successfully executed or upon watchdog expiration Figure 26 2 Public ROM Code Boot Procedure 26 1 3 Memory Map 26 1 3 1 Public ROM Memory Map The on chip ROM memory map is shown in Figure 26 3 The P...

Page 4098: ...Exception Vectors Table 26 1 lists the Public ROM exception vectors The reset exception is redirected to the Public ROM Code startup Other exceptions are redirected to their RAM handlers by loading appropriate addresses into the PC register 4098Initialization SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 4099: ... dead loop address from R0 register The main purpose of the function is to go in a dead loop until the watchdog expires and resets the device The function is located at address 200C0h In addition the function clears global cold reset status upon issuing the global SW reset Table 26 2 Dead Loops Address Purpose 20080h Undefined exception default handler 20084h SWI exception default handler 20088h P...

Page 4100: ... in the subsequent seven addresses into the PC register Theses instructions are executed when an exception occurs since they are called from the ROM exception vectors Undefined SWI Unused and FIQ exceptions are redirected to a hardcoded dead loop Pre fetch abort data abort and IRQ exception are redirected to pre defined ROM handlers User code can redirect any exception to a custom handler either b...

Page 4101: ... abort dead loop 2008Ch Tracing Data This area contains trace vectors reflecting the execution path of the public boot Section 26 1 12 describes the usage of the different trace vectors and lists all the possible trace codes Table 26 4 Tracing Data Address Size bytes Description 4030CE40h 4 Current tracing vector word 1 4030CE44h 4 Current tracing vector word 2 4030CE48h 4 Current tracing vector w...

Page 4102: ...ic vector base address is configured to the reset vector of Public ROM Code 20000h MMU is left switched off during the public boot hence L1 data cache off 26 1 4 3 Clocking Configuration The device supports the following frequencies based on SYSBOOT 15 14 Table 26 5 Crystal Frequencies Supported SYSBOOT 15 14 Crystal Frequency 00b 19 2 MHz 01b 24 MHz 10b 25 MHz 11b 26 MHz The ROM Code configures t...

Page 4103: ...O The DPLLs and PRCM clock dividers are configured with the ROM Code default values after cold or warm reset in order to give the same working conditions to the Public ROM Code sequence 26 1 5 Booting 26 1 5 1 Overview Figure 26 6 shows the booting procedure First a booting device list is created The list consists of all devices which will be searched for a booting image The list is filled in base...

Page 4104: ...inks The ROM Code uses a host slave logical protocol for synchronization Upon successful UART USB or Ethernet connection the host sends the image binary contents The peripheral booting procedure is described in detail in Section 26 1 8 If the memory or peripheral booting fails for all devices enumerated in the device list then the ROM Code gets into a loop waiting for the watchdog to reset the sys...

Page 4105: ... pins sensed in the control module The pins are used to index the device table from which the list of devices is extracted 26 1 5 2 1 SYSBOOT Configuration Pins Table 26 7 contains the SYSBOOT configuration pins 4105 SPRUH73H October 2011 Revised April 2013 Initialization Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 4106: ...it reserved MUX2 2 device device 1 CLKOUT1 10b 25MHz enabled 10b muxed 11b 26MHz device x1b reserved 00b For NAND boot Don t care for Don t care for 00010b UART0 SPI0 NAND NANDI2C 00b 19 2MHz 0 ECC done 0 CLKOUT1 all other values must be 00b ROM code ROM code by ROM disabled 01b 24MHz reserved 1 ECC 1 CLKOUT1 10b 25MHz handled by enabled 11b 26MHz NAND 00b Don t care for Don t care for 00011b UART...

Page 4107: ...s WAIT 1 by ROM disabled 01b 24MHz 00b non muxed 1 16 bit 01b RMII reserved MUX2 2 device 1 ECC device 1 CLKOUT1 10b 25MHz 10b handled by enabled 10b muxed Reserved 11b 26MHz NAND device 11b RGMII x1b reserved w o internal delay For NAND boot must be 00b 00b 01000b EMAC1 MMC0 XIP NANDI2C 00b 19 2MHz For XIP boot 0 ECC done 0 8 bit device 00b MII 0 CLKOUT1 all other values MUX2 2 by ROM disabled 01...

Page 4108: ... NANDI2C 00b 19 2MHz For XIP boot 0 ECC done 0 8 bit device 0 CLKOUT1 all other values ROM code MUX2 2 by ROM disabled 01b 24MHz 00b non muxed 1 16 bit reserved device 1 ECC device 1 CLKOUT1 10b 25MHz handled by enabled 10b muxed 11b 26MHz NAND device x1b reserved For NAND boot must be 00b 00b Don t care for 01101b USB0 NAND XIP SPI0 00b 19 2MHz For XIP boot 0 ECC done 0 8 bit device 0 CLKOUT1 all...

Page 4109: ... CLKOUT1 all other values must be 00b ROM code ROM code by ROM disabled 01b 24MHz reserved 1 ECC 1 CLKOUT1 10b 25MHz handled by enabled 11b 26MHz NAND 00b For NAND boot Don t care for Don t care for 10011b NAND NANDI2C MMC0 UART0 00b 19 2MHz 0 ECC done 0 CLKOUT1 all other values must be 00b ROM code ROM code by ROM disabled 01b 24MHz reserved 1 ECC 1 CLKOUT1 10b 25MHz handled by enabled 11b 26MHz ...

Page 4110: ...or 11001b SPI0 MMC0 EMAC1 UART0 00b 19 2MHz 00b MII 0 CLKOUT1 all other values ROM code ROM code ROM code disabled 01b 24MHz 01b RMII reserved 1 CLKOUT1 10b 25MHz 10b enabled Reserved 11b 26MHz 11b RGMII w o internal delay 00b Don t care for Don t care for 11010b XIP UART0 SPI0 MMC0 00b 19 2MHz For XIP boot 0 8 bit device 0 CLKOUT1 all other values ROM code ROM code MUX2 2 disabled 01b 24MHz 00b n...

Page 4111: ...ice enabled Reserved 11b 26MHz 10b muxed 11b RGMII device w o internal x1b reserved delay SYSBOOT Configuration Pins Notes 1 WAIT is monitored on GPMC_WAIT0 2 MUX1 and MUX2 designate which group of XIP signals are used Each group is defined in Table 26 9 3 Note that even though some bits may be a don t care for ROM code all SYSBOOT values are latched into the CONTROL_STATUS register and may be use...

Page 4112: ... device later in this chapter To extend the boot flow to boot from devices that are not natively supported by the ROM SPI boot can be used For example to be able to boot from a USB stick the system can be configured to boot from a SPI flash and the code for configuring the USB and booting from a USB stick can be loaded into the SPI flash This is known as a secondary boot The values corresponding t...

Page 4113: ...re and enable GPMC Jump to address 0x08000000in ARM mode Yes Yes No No Jump to external SW www ti com Functional Description Figure 26 7 Fast External Boot 4113 SPRUH73H October 2011 Revised April 2013 Initialization Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 4114: ...r each supported device type A sector is a logical unit of 512 bytes The detection of whether an image is present or not on a selected device depends on the first few bytes On a GP Device type a booting image is considered to be present when the first four bytes of the sector is not equal to 0000 0000h or FFFF FFFFh During the first read sector call sectors are copied to a temporary RAM buffer Onc...

Page 4115: ...AIT signal connected on the WAIT0 pin or not Wait pin polarity is set to stall accessing memory when the WAIT0 pin is low The wait monitoring is intended to be used with memories which require long time for initialization after reset or need to pause while reading data The boot procedure from XIP device can be described as such Configure GPMC for XIP device access Set the image location to 0x08000...

Page 4116: ...ue clock cycles twr write cycle period 17 trd read cycle period 17 tCEon CE low time 1 tCEoff CE high time 16 tADVon ADV low time 1 tADVoff ADV high time 2 tOEon OE low time 3 tWEon WE low time 3 trddata data latch time 15 tOEoff OE high time 16 tWEoff WE high time 15 4116 Initialization SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments In...

Page 4117: ...ed NOR Boot Signal name Pin used in XIP_MUX1 1 mode Pin used in XIP_MUX2 1 mode CS0 GPMC_CSN0 GPMC_CSN0 ADVN_ALE GPMC_ADVN_ALE GPMC_ADVN_ALE OEN_REN GPMC_OEN_REN GPMC_OEN_REN BE0N_CLE GPMC_BEN0_CLE GPMC_BEN0_CLE WEN GPMC_WEN GPMC_WEN WAIT GPMC_WAIT0 GPMC_WAIT0 AD0 AD15 GPMC_AD0 GPMC_AD15 GPMC_AD0 GPMC_AD15 A0 GPMC_A0 LCD_DATA0 A1 GPMC_A1 LCD_DATA1 A2 GPMC_A2 LCD_DATA2 A3 GPMC_A3 LCD_DATA3 A4 GPMC_...

Page 4118: ...it device 8 1 16 bit device 00b Non muxed device 11 10 10b Muxed device x1b Reserved 26 1 7 3 Image Shadowing for Non XIP Memories 26 1 7 3 1 Shadowing on GP Device The GP Device shadowing uses the following approach Figure 26 10 Image Shadowing on GP Device 26 1 7 4 NAND The NAND flash memory is not XIP and requires shadowing before the code can be executed 26 1 7 4 1 Features Uses GPMC as the co...

Page 4119: ...detection with parameters determination and finally bad block detection ONFI Support The NAND identification starts with ONFI detection For more information on ONFI standard see the Open NAND Flash Interface Specification http www onfi org GPMC Initialization The GPMC interface is configured as such it can be used for accessing NAND devices The address bus is released since a NAND device does not ...

Page 4120: ...ize spare area size number of pages per block and the addressing mode The remaining data bytes from the parameters page stream are simply ignored Table 26 13 ONFI Parameters Page Description Offset Description Size bytes 6 Features supported 2 80 Number of data bytes per page 4 84 Number of spare bytes per page 2 92 Number of pages per block 4 101 Number of address cycles 1 If the ONFI Read ID com...

Page 4121: ...32 Gb 87 x8 2048 32 Gb 97 x16 2048 64 Gb DE x8 2048 4096 64 Gb CE x16 2048 4096 64 Gb AE x8 2048 4096 64 Gb BE x16 2048 4096 When the parameters are retrieved from the ROM table page size and block size is updated based on 4th byte of NAND ID data Due to inconsistency amongst different manufacturers only devices which has been recognized to be at least 2Gb included have these parameters updated Th...

Page 4122: ...escribed in the previous sections Table 26 16 Pins Used for NANDI2C Boot for I2C EEPROM Access Signal name Pin Used in Device I2C SCL i2c0_scl I2C SDA i2c0_sda ROM accesses the I2C EEPROM at I2C slave address 0x50 and reads 7 bytes starting from address offset 0x80 The format of this NAND geometry information is as follows Table 26 17 NAND Geometry Information on I2C EEPROM Byte address Informatio...

Page 4123: ...s equal to 10b then the ECC correction applied is BCH 16b sector In addition ECC computation done by the ROM can be turned off completely by using SYSBOOT 9 This is particularly useful when interfacing with NAND devices that have built in ECC engines Table 26 18 ECC Configuration for NAND Boot SYSBOOT 9 ECC Computation 0 ECC done by ROM 1 ECC handled by NAND 4123 SPRUH73H October 2011 Revised Apri...

Page 4124: ...ND parameters from device parameters page Update page size block size ECC correction for devices 1 Gb Wait for device initialization max timeout 250ms Device ready No Yes Timeout reached Functional Description www ti com Figure 26 12 NAND Device Detection The detection procedure is described in Figure 26 12 Once the device has been successfully detected the ROM Code changes GPMC to 16 bit bus widt...

Page 4125: ...n Blocks validity status is coded in the spare areas of the first two pages of a block first byte equal to FFh in 1st and 2nd pages for an 8 bits device first word equal to FFFFh in 1st and 2nd page for a 16bits device Figure 26 13 depicts the invalid block detection routine The routine consists in reading spare areas and checking validity data pattern Figure 26 13 NAND Invalid Blocks Detection 26...

Page 4126: ...nst ECC stored in the spare area for the corresponding page Depending on the page size the amount of ECC data bytes stored in the corresponding spare area is different Figure 26 15 and Figure 26 16 show the mapping of ECC data inside the spare area for respectively 2KB page and 4KB page devices If both ECC data are equal then the Read Sector function returns the read 512 bytes sector without error...

Page 4127: ...byte x8 word x16 MSB LSB ECC D 12 53 ECC B 11 ECC B 12 13 ECC C 0 ECC C 1 ECC C 12 ECC D 0 ECC D 1 ECC D 2 20 21 26 ECC D 11 ECC D 12 14 1 www ti com Functional Description Figure 26 15 ECC Data Mapping for 2 KB Page and 8b BCH Encoding 4127 SPRUH73H October 2011 Revised April 2013 Initialization Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 4128: ...ase note that all the pins might not be driven at boot time NOTE Caution must be taken when using an 8 bit NAND The ROM initially configures all address and data signals AD0 AD15 the GPMC uses when attempting to read configuration values from the NAND If you use an 8 bit NAND and connect AD15 AD8 to other functions GPIOs for example there may be contention on these signals during the boot phase AD...

Page 4129: ...ile 26 1 7 5 2 System Interconnection Each interface has booting restrictions on which type of memory it supports MMC0 supports booting from the MMC SD card cage and also supports booting from eMMC eSD managed NAND memory devices with less than 4GB capacity MMC1 supports booting from eMMC eSD managed NAND memory device with 4GB capacity or greater The restriction is a result of many eMMC devices n...

Page 4130: ... Relative Card Address RCA assignment are used However the ROM Code assumes that only one memory or card is present on the bus This first sequence is done using the CMD signal which is common to SD and MMC devices MMC and SD standards detail this phase as initialization phase Both standards differ in the first commands involved CMD1 and ACMD41 The ROM Code uses this difference in command set to di...

Page 4131: ... ROM Code reads out raw sectors from image or the booting file within the file system and boots from it 26 1 7 5 5 MMC SD Read Sector Procedure in Raw Mode In raw mode the booting image can be located at one of the four consecutive locations in the main area offset 0x0 0x20000 128 KB 0x40000 256 KB 0x60000 384 KB For this reason a booting image shall not exceed 128KB in size However it is possible...

Page 4132: ...o 0xe0 to 0x00 0xe0 26 1 7 5 6 MMC SD Read Sector Procedure in FAT Mode MMC SD Cards may hold a FAT file system which ROM Code is able to read and process The image used by the booting procedure is taken from a specific booting file named MLO This file has to be located in the root directory on an active primary partition of type FAT12 16 or FAT32 An MMC SD card can be configured either as floppy ...

Page 4133: ... FAIL The Extended partitions are not checked the booting file must reside in a primary partition If a partition is found then its first sector is read and used further on If no MBR is present in case of a floppy like system the first sector of the device is read and used further on The read sector is checked to be a valid FAT12 16 or FAT32 partition If this fails in case another partition type is...

Page 4134: ... The aim of such a structure is to be able to divide the hard disk in partitions mostly used to boot different systems i e Microsoft Windows Linux Its structure is described in Table 26 22 and Table 26 23 The valid partition types searched by the ROM Code are described in Table 26 24 Table 26 22 Master Boot Record Structure Offset Length bytes Entry Description Value 0000h 446 Optional Code 01BEh ...

Page 4135: ...n relative to 0008h 4 LBAs Cs H S Hs S Ss 1 the beginning of media LBAe Ce H S He S Se 1Nbs 000Ch 4 Number of sectors in partition LBAe LBAs 1 Table 26 24 Partition Types Partition Type Description 01h FAT12 04h 06h 0Eh FAT16 0Bh 0Ch 0Fh FAT32 The way the ROM Code detects whether a sector is the 1st sector of an MBR or not is described in Figure 26 20 The ROM Code first checks if the signature is ...

Page 4136: ...ds the Files Directories and Root Directory for FAT12 16 the Root Directory has a specific fixed location The Boot Sector is described in Table 26 25 Note In the following description all the fields whose names start with BPB_ are part of the BPB All the fields whose names start with BS_ are part of the Boot Sector and not really part of the BPB not mandatory they are not used at all by the ROM Co...

Page 4137: ...SD MMC 001Ah 2 BPB_NumHeads Number of heads 255 for SD MMC Number of sectors preceeding the 001Ch 4 BPB_HiddSec partition Total Count of sectors on the volume If the size is smaller than 10000h for 0020h 4 BPB_TotSec32 FAT12 16 this field is 0 and BPB_TotSec16 is valid 0024h 1 BS_DrvNum Drive Number 0025h 1 BS_Reserved1 00h Extended Boot Signature 29h Indicates 0026h 1 BS_BootSig that the followin...

Page 4138: ...d FAT12 16 32 partition only fields starting with BPB can be checked as they are mandatory The fields starting from offset 0024h to 01FDh cannot be used for the check as they will differ if using FAT12 16 or FAT32 The procedure is described in Figure 30 First the ROM Code checks if the BPB_Signature is equal to AA55h Then it checks some fields which must have some specific values BPB_BytsPerSec BP...

Page 4139: ...en by Clustersector BPB_RsvdSecCnt BPB_NumFATs x BPB_FATSz Cluster x BPB_SecPerClus Note BPB_FatSz is BPB_FatSz16 for FAT12 16 or BPB_FatSz32 for FAT32 Note the BPB_HiddSec field can contain 0 even though the FAT file system is located somewhere other than on sector 0 floppy like The ROM Code actually uses the partition offset taken from the MBR instead of this field which can be wrong If no MBR w...

Page 4140: ...7 5 7 4 FAT12 16 32 File Allocation Table The ROM Code needs to read the FAT in order to retrieve sectors either for the booting file or for the Root Directory in case the file system is FAT32 There can be multiple copies of the FAT inside the file system ROM Code supports only 2 located after the Boot Sector FATnsector BPB_HiddSec BPB_RsvdSecCnt BPB_FatSz x n Its size is given by BPB_FATSz16 or B...

Page 4141: ...e list of device pins that are configured by the ROM in the case of MMC boot mode are as follows Please note that all the pins might not be driven at boot time Table 26 28 Pins Used for MMC0 Boot Signal name Pin Used in Device clk mmc0_clk cmd mmc0_cmd dat0 mmc0_dat0 dat1 mmc0_dat1 dat2 mmc0_dat2 dat3 mmc0_dat3 Table 26 29 Pins Used for MMC1 Boot Signal name Pin Used in Device clk gpmc_csn1 cmd gp...

Page 4142: ...bove should contain the image size If the value of the addresses mentioned above is neither 0x0 nor 0xFFFFFFFF then the boot will proceed else it will move to the next sector If no image is found after checking four sectors the ROM bootloader will move to the next device From the next iteration onwards a dummy value is transmitted on the master out line and the data is received on the master in li...

Page 4143: ... boot from three different peripheral interfaces EMAC 1000 100 10 Mbps Ethernet using standard TCP IP network boot protocols BOOTP and TFTP USB Full speed client mode UART 115 2Kbps 8 bits no parity 1 stop bit no flow control The purpose of booting from a peripheral interface is to download a boot image from an external host typically a PC This booting method is mostly used for programming flash m...

Page 4144: ...reference clock requirement when using RMII 26 1 8 4 2 BOOTP RFC 951 The device then proceeds to obtain the IP and Boot information using BOOTP protocol The device prepares and broadcasts the BOOTP message that has the following information Device MAC address in chaddr field to uniquely identify the device to the server vender class identifier option number 60 RFC 1497 RFC 1533 Servers could use t...

Page 4145: ...meout of 1s to receive a response for the READ request 5 retries for the READ request Retries are managed by server once data transfer starts server re sends a data packet if the ACK was not received within a timeout value Device has a 60s timeout to complete the data transfer to handle the scenario if the server dies in the middle of a data transfer 4145 SPRUH73H October 2011 Revised April 2013 I...

Page 4146: ...o_clk MDC 0 Table 26 33 Pins Used for EMAC Boot in RGMII Mode Signal Name Pin Used in Device Pin Mux Mode rgmii1_tctl MII1_TX_EN 2 rgmii1_rctl MII1_RX_DV 2 rgmii1_td 3 0 MII1_TXD 3 0 2 rgmii1_tclk MII1_TX_CLK 2 rgmii1_rclk MII1_RX_CLK 2 rgmii1_rd 3 0 MII1_RXD 3 0 2 mdio_data MDIO 0 mdio_clk MDC 0 Table 26 34 Pins Used for EMAC Boot in RMII Mode Signal Name Pin Used in Device Pin Mux Mode rmii1_crs...

Page 4147: ...cket for 3s UART boot will time out If the delay between two consecutive bytes of the same packet is more than 2ms the host is requested to re transmit the entire packet again Error checking using the CRC 16 support in x modem If an error is detected the host is requested to re transmit the packet again 26 1 8 5 3 Pins Used The list of device pins that are configured by the ROM in the case of UART...

Page 4148: ...e implements the RNDIS class driver From a user s perspective USB boot is indistinguishable from Ethernet boot The USB initialization procedure is shown in Figure 26 24 Figure 26 24 USB Initialization Procedure 26 1 8 6 1 2 Enumeration Descriptors The device descriptor parameters which are used during enumeration are listed in Table 26 37 The default Vendor ID and Product ID can be automatically o...

Page 4149: ...iven at boot time Table 26 38 Pins Used for USB Boot Signal Name Pin Used in Device USB0_DM USB0_DM USB0_DP USB0_DP USB0_ID USB0_ID USB0_VBUS USB0_VBUS 26 1 8 7 ASIC ID structure The ASIC ID size is 58 bytes for UART and 81 bytes for others The fields of this structure are unused This structure is included purely for legacy purposes 26 1 9 Image Format 26 1 9 1 Overview All preceding sections desc...

Page 4150: ...ry booting image starts directly with executable code Table 26 39 GP Device Image Format Field Non XIP Device Offset XIP Device Offset Size bytes Description Size 0000h 4 Size of the image Address where to store Destination 0004h 4 the image code entry point Image 0008h 0000h x Executable code Note The Destination address field stands for both Target address for the image copy from the non XIP sto...

Page 4151: ...sed 04h 4 descriptor address during the memory booting process 1 Code of device used for booting 00h void no device 01h XIP MUX1 memory 02h XIPWAIT MUX 1 wait monitoring on 03h XIP MUX2 memory 04h XIPWAIT MUX 2 wait monitoring on 08h Current Booting Device 1 05h NAND 06h NAND with I2C 08h MMC SD port 0 09h MMC SD port 1 15h SPI 41h UART0 44h USB 46h CPGMAC0 Current reset reason bit mask bit 1 even...

Page 4152: ...t in the device in all the modes other than RTC only the A8 internal SRAM and the L3 OCMC RAM are held in retention This is a fundamental assumption of the ROM code As the contents of these RAMs are not lost in the Deep Sleep modes it is possible to return to a location in these memories This does away with the need of the ROM having to restore PLL and EMIF settings which would have been needed if...

Page 4153: ...d set holds a copy of trace vectors collected at the first ROM Code run after cold reset As a consequence after a warm reset it is possible to have visibility on the boot scenario that occurred during cold reset Table 26 41 Tracing Vectors Trace vector Bit No Group Meaning 1 0 General Passed the public reset vector 1 1 General Entered main function 1 2 General Running after the cold reset 1 3 Boot...

Page 4154: ...nion chip Reserved 2 4 USB USB connect 2 5 USB USB configured state 2 6 USB USB VBUS valid 2 7 USB USB session valid 2 8 Reserved Reserved 2 9 Reserved Reserved 2 10 Reserved Reserved 2 11 Reserved Reserved 2 12 Memory Boot Memory booting trial 0 2 13 Memory Boot Memory booting trial 1 2 14 Memory Boot Memory booting trial 2 2 15 Memory Boot Memory booting trial 3 2 16 Memory Boot Execute GP image...

Page 4155: ...ed 3 10 Memory Boot Reserved 3 11 Reserved Reserved 3 12 Reserved Memory booting device SPI 3 13 Reserved Reserved 3 14 Reserved Reserved 3 15 Reserved Reserved Peripheral booting device 3 16 Reserved UART0 3 17 Reserved Reserved 3 18 Peripheral Boot Reserved 3 19 Reserved Reserved 3 20 Peripheral Boot Peripheral booting device USB 3 21 Peripheral Boot Reserved Peripheral booting device 3 22 Perip...

Page 4156: ...the debug subsystem of the device More information will be available in future revisions of this document Topic Page 27 1 Functional Description 4157 4156 Debug Subsystem SPRUH73H October 2011 Revised April 2013 Submit Documentation Feedback Copyright 2011 2013 Texas Instruments Incorporated ...

Page 4157: ... Suspend peripheral during debug halt 0x9 27 1 1 1 Debug Subsystem Registers Table 27 1 Debug Subsystem Registers Offset Peripheral Register Name 200h Watchdog Timer Watchdog_Timer_Suspend_Control 204h DMTimer 0 DMTimer_0_Suspend_Control 208h DMTimer 1 DMTimer_1_Suspend_Control 20Ch DMTimer 2 DMTimer_2_Suspend_Control 210h DMTimer 3 DMTimer_3_Suspend_Control 214h DMTimer 4 DMTimer_4_Suspend_Contro...

Page 4158: ...signal All other values are reserved 3 Suspend_Default 0 Enable Disable the override value in Suspend_Sel _Override 0 Suspend_Sel field will select which suspend signal reaches the peripheral 1 Suspend_Sel field ignored Default suspend signal will reach the peripheral 2 1 Reserved 0 0 SensCtrl 0 Sensitivity Control for suspend signals When Suspend_Default_Override 1 this bit is ignored and read as...

Page 4159: ... Interface Configuration Register Updated maximum frequency in Table 7 95 EMIF Clock Signals Added note to Section 7 3 6 DDR2 3 mDDR PHY Registers that the registers are write only due to a silicon bug Chapter 9 Updated Section 9 3 CONTROL_MODULE Registers Control Module Chapter 10 Updated Table 10 1 L3 Master Slave Connectivity and Table 10 2 MConnID Assignment Interconnects Chapter 11 Updated Se...

Page 4160: ...6 5 1 2 SYSCONFIG Register Chapter 18 Updated Section 18 2 Integration Multimedia Card Updated Section 18 3 Functional Description MMC Updated Section 18 5 1 1 SD_SYSCONFIG and Section 18 5 1 29 SD_REV registers Chapter 20 DMTimer Timers Added Figure 20 2 Timer0 Integration and Figure 20 3 Timer2 7 Integration Added note to Section 20 1 3 4 2 Write Non Posted that this mode is not recommended Adde...

Page 4161: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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