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4.6 Memory Interface

4.6.1 QSPI Interface

The AM243x LaunchPad board has 512 Mbit QSPI memory device (S25HL512TFAMHI010 from Cypress),
which is connected to the OSPI0 interface of the AM243x SoC. The QSPI interface supports memory speed up
to 166 MHz. External loopback is provided between OSPI0_LBCLKO and OSPI0_DQS.

Reset:

The reset for the flash is connected to a circuit that performs an AND operation to MCU_RESETSTATz

and a GPIO from the SoC.

Power:

The QSPI flash is powered by the 3.3 V IO supply. The 3.3 V supply is provided to both the VCC and

VCCQ pins of the flash memory. The OSPI0 interface of the SoC is powered by the VDDSHV_3V3 supply.

Figure 4-7. QSPI Interface

Hardware Description

SPRUJ12B – AUGUST 2021 – REVISED OCTOBER 2022

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AM243x LaunchPad™ Development Kit User's Guide

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Summary of Contents for AM243 Series

Page 1: ...d Setup 7 3 1 Power Requirements 7 3 1 1 Power Input Using USB Type C Connector 7 3 1 2 Power Status LED s 9 3 1 3 Power Tree 10 3 1 4 Power Sequence 11 3 2 Push Buttons 11 3 3 Boot Mode Selection 12 4 Hardware Description 13 4 1 Functional Block Diagram 13 4 2 BoosterPack Headers 14 4 2 1 Pinmux for BoosterPack 16 4 3 GPIO Mapping 25 4 4 Reset 27 4 5 Clock 28 4 6 Memory Interface 29 4 6 1 QSPI In...

Page 2: ...gure 4 19 eQEP2 Header 39 Figure 4 20 eQEP2 or MCAN0 Mux Selection Circuit 39 Figure 4 21 CAN Interface 40 Figure 4 22 MCAN Transceiver and Header 40 Figure 4 23 FSI Interface 41 Figure 4 24 FSI Header 42 Figure 4 25 FSI or BoosterPack Mux Selection Circuit 42 Figure 4 26 JTAG Interface 43 Figure 4 27 Micro B USB Connection for JTAG 43 Figure 4 28 Test Automation Header 44 Figure 4 29 SPI Connecti...

Page 3: ...st be ordered separately The Belkin USB C Wall Charger is known to work with the LaunchPad and the supplied type C cable For more information on power requirements go to Section 3 1 If there is an error in the power input then the red LED LD9 will glow continuously For more information about the power status LED s see Section 3 1 2 Note The JTAG connection through the micro B USB port needs to be ...

Page 4: ...igure 2 1 AM243x LaunchPad Board Kit Overview www ti com 4 AM243x LaunchPad Development Kit User s Guide SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 5: ...ed 3 meters 2 2 Key Features The AM243x LaunchPad has the following features AM2434 ALX MCU PCB dimensions 7 7 inch 195 58 mm x 2 3 inch 58 42 mm Powered through 5 V 3A USB type C input Two RJ45 Ethernet ports capable of 1Gb or 100Mb speeds On board XDS110 debug probe Four push buttons PORz Reset MCU warm reset SoC warm reset User interrupt www ti com Kit Overview SPRUJ12B AUGUST 2021 REVISED OCTO...

Page 6: ...tors featuring stackable headers to maximize expansion through the BoosterPack ecosystem Test automation header On Board Memory 512 Mb QSPI flash 1 Mb I2C EEPROM 2 3 Component Identification Figure 2 3 AM243x LaunchPad Top Component Identification Figure 2 4 AM243x LaunchPad Bottom Component Identification Kit Overview www ti com 6 AM243x LaunchPad Development Kit User s Guide SPRUJ12B AUGUST 2021...

Page 7: ...dvertise the current sourcing capability through CC1 and CC2 signals On AM243x LP the CC1 and CC2 from USB type C connector are interfaced to the port controller IC TUSB320LAIRWBR This device uses the CC pins to determine port attach and detach cable orientation role detection and port control for Type C current mode The CC logic detects the Type C current mode as default medium or high depending ...

Page 8: ...of the power supply 5 V supplied by the type C USB connector is used to generate all of the necessary voltages required by the LaunchPad Figure 3 2 USB Type C Power Input Discrete DC DC buck regulators and LDOs are used to generate the supplies required for the AM243x system on a chip SoC and other peripherals Two DC DC buck regulators TPS62822 are used to generate the 3 3 V main supply and VDD_CO...

Page 9: ... indication for voltage VUSB_5V0 LD7 ON VSYS_5V0 Power indicator for voltage VSYS_5V0 LD6 ON VSYS_3V3 Power indicator for voltage VSYS_3V3 LD8 ON VDD_CORE_0V85 Power indicator for voltage VDD_CORE_0V85 LD11 OFF XDS110_PROG_STAZ1 LED will glow after XDS configuration LD10 OFF XDS110_PROG_STAZ2 Figure 3 3 Power Status LED s www ti com Board Setup SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Docu...

Page 10: ... 4 Power Tree Diagram of AM243x LaunchPad Board Setup www ti com 10 AM243x LaunchPad Development Kit User s Guide SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 11: ...op side of the AM243x LaunchPad board Table 3 3 LaunchPad Push Buttons SL Push Button Signal Function 1 SW1 MCU_PORz PORz Reset input 2 SW2 MCU_RESETz MCU warm reset input 3 SW3 SoC_RESET_REQz SoC warm reset input 4 SW4 USER_INTn User interrupt input www ti com Board Setup SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feedback AM243x LaunchPad Development Kit User s Guide 11 Copyright ...

Page 12: ...odes are as follows QSPI MMC μSDCard no direct support Universal asynchronous receiver transmitter UART USB DFU No boot Table 3 4 Boot Mode Selection Table Boot Modes Supported SW4 1 SW4 2 SW4 3 SW4 4 SW4 5 SW4 6 SW4 7 QSPI Flash 0 1 0 0 0 1 0 MMC1 SD Card 0 0 0 1 0 0 1 UART 1 1 1 0 0 0 0 USB DFU 0 1 0 1 0 0 0 No Boot 1 1 1 1 0 0 0 Figure 3 6 Boot Mode DIP Switch Note SW4 8 of the DIP switch remai...

Page 13: ...ram Figure 4 1 AM243x LaunchPad Functional Block Diagram www ti com Hardware Description SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feedback AM243x LaunchPad Development Kit User s Guide 13 Copyright 2022 Texas Instruments Incorporated ...

Page 14: ...numbers as well as the the BoosterPack compliant features are listed in Figure 4 2 Each GPIO has multiple functions available through the GPIO mux The signals connected from the SoC to the BoosterPack headers include SPI0 and SPI3 UART0 and UART2 I2C0 and I2C1 MMC1 ADC0 EHRPWM0_A B and EHRPWM1_A B GPIO s 5 V and 3 3 V power supplies Hardware Description www ti com 14 AM243x LaunchPad Development K...

Page 15: ...erPack When left unpopulated the BoosterPack will be required to source its own power Note Sourcing power to the LaunchPad from the BoosterPack should not be attempted Table 4 1 BoosterPack Power Sourcing for BoosterPack Site 2 Function Mount R161 and R163 Default Unmount R161 and R163 Power to BoosterPack sourced from LaunchPad Power to BoosterPack sourced from the BoosterPack Figure 4 3 Site 2 B...

Page 16: ...Figure 4 4 80 Pin BoosterPack Pinout Hardware Description www ti com 16 AM243x LaunchPad Development Kit User s Guide SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 17: ..._AIN5 GPIO1_8 5 J1 7 PRG0_PRU0_GP O16 PRG0_PRU0_GPI1 6 PRG0_RGMII1_TXC PRG0_PWM0_A2 SPI3_CLK GPIO1_1 6 GPMC0_A4 J3 27 ADC0_AIN6 GPIO1_8 6 J1 8 PRG0_PRU0_GP O18 PRG0_PRU0_GPI1 8 PRG0_IEP0_EDC_LATCH _IN0 PRG0_PWM0_TZ _IN CPTS0_HW1TSPU SH CP_GEMAC_CPTS0_HW1TSP USH HRPWM8_A GPIO1_1 8 UART4_CT Sn GPMC0_A5 UART2_RX D J3 28 ADC0_AIN7 GPIO1_8 7 J1 9 I2C1_SCL CPTS0_HW1TSPU SH TIMER_IO0 SPI2_CS1 DDR0_IO_PLL...

Page 18: ...GPIO1_12 PRG0_PRU0_GPO12 J3 25 BP_ADC0_AIN4 ADC0_AIN4 J1 6 BP_ADC0_AIN1 ADC0_AIN1 J3 26 BP_ADC0_AIN5 ADC0_AIN5 J1 7 SPI3_CLK PRG0_PRU _GPO16 J3 27 BP_ADC0_AIN6 ADC0_AIN6 J1 8 GPIO1_18 PRG0_PRU0_GPO18 J3 28 BP_ADC0_AIN7 ADC0_AIN7 J1 9 SOC_I2C1_SCL I2C1_SCL J3 29 SYNC2_OUT MCAN0_TX J1 10 SOC_I2C1_SDA I2C1_SDA J3 30 SYNC3_OUT MCAN0_RX Hardware Description www ti com 18 AM243x LaunchPad Development Ki...

Page 19: ...RZ J4 35 EHRPWM2_B GPMC0_AD9 GPMC0_AD9 FSI_RX0_D0 UART3_CTSn EHRPWM2_B TRC_DATA7 GPIO0_24 PRG0_PWM2_ B2 J2 15 SPI3_D0 PRG0_PRU0_G PO13 PRG0_PRU0_G PO13 PRG0_PRU0_G PI13 PRG0_RGMII1_ TD2 PRG0_PWM0_ B0 SPI3_D0 GPIO1_13 GPMC0_A15 J4 34 EHRPWM0_TZ N_IN0 GPMC0_AD2 GPMC0_AD2 FSI_RX2_D1 UART2_RTSn EHRPWM_TZn _IN0 TRC_DATA0 GPIO0_17 PRG0_PWM2_ TZ_IN J2 14 SPI3_D1 PRG0_PRU0_G PO14 PRG0_PRU0_G PO14 PRG0_PRU...

Page 20: ...O4 J4 36 EHRPWM2_A GPMC0_AD8 J2 16 BP_CONN_1_PORZ J4 35 EHRPWM2_B GPMC0_AD9 J2 15 SPI3_D0 PRG0_PRU0_GPO13 J4 34 EHRPWM0_TZN_IN0 GPMC0_AD2 J2 14 SPI3_D1 PRG0_PRU0_GPO14 J4 33 GPIO1_0 PRG0_PRU0_GPO0 J2 13 GPIO1_5 PRG0_PRU0_GPO5 J4 32 GPIO1_1 PRG0_PRU0_GPO1 J2 12 SPI3_CS1 PRG0_PRU0_GPO15 J4 31 GPIO1_2 PRG0_PRU0_GPO2 J2 11 GPIO1_20 PRG0_PRU1_GPO0 Hardware Description www ti com 20 AM243x LaunchPad Dev...

Page 21: ...RT3_RXD J7 65 PRG1_PRU0_GPO1 7 PRG1_PRU0_GPI1 7 PRG1_IEP0_EDC_SYNC_OUT1 PRG1_PWM0_B2 CPTS0_TS_SYNC TIMER_IO7 GPIO0_62 GPMC0_A0 J5 46 PRG1_PRU0_GPO5 PRG1_PRU0_GPI5 PRG1_PWM3_B2 RGMII1_RX_CTL GPIO0_50 GPMC0_AD21 J7 66 PRG1_PRU0_GPO7 PRG1_PRU0_GPI7 PRG1_IEP0_EDC_LATCH_IN1 PRG1_PWM3_B1 CPTS0_HW2TSPUS H CLKOUT0 TIMER_IO10 GPIO0_52 GPMC0_AD23 J5 47 SPI0_CLK GPIO1_44 J7 67 PRG0_PRU1_GPO1 PRG0_PRU1_GPI1 P...

Page 22: ...PIO1_19 PRG0_PRU0_GPO19 J7 65 PRG1_IEP0_EDC_SYNC_OUT1 PRG1_PRU0_GPO17 J5 46 GPIO0_50 PRG1_PRU0_GPO5 J7 66 PRG1_IEP0_EDC_LATCH_IN1 PRG1_PRU0_GPO7 J5 47 SPI0_CLK SPI0_CLK J7 67 GPIO1_21 PRG0_PRU1_GPO1 J5 48 GPIO1_6 PRG0_PRU0_GPO6 J7 68 GPIO1_22 PRG0_PRU1_GPO2 J5 49 SOC_I2C0_SCL_BP I2C0_SCL J7 69 GPIO1_26 PRG0_PRU1_GPO6 J5 50 SOC_I2C0_SDA_BP I2C0_SDA J7 70 GPIO1_31 PRG0_PRU1_GPO11 Hardware Descriptio...

Page 23: ...PWM1_A 2 GPIO1_3 6 GPMC0_A1 1 PRG0_ECAP0_SYNC_OUT J8 76 MMC1_CLK UART2_CTSn TIMER_IO4 UART4_RXD GPIO1_7 5 J6 56 BP_CONN_2_POR Z J8 75 MMC1_CMD UART2_RTSn TIMER_IO5 UART4_TXD GPIO1_7 6 J6 55 SPI0_D0 GPIO1_4 5 J8 74 MMC1_SDCD UART3_CTSn TIMER_IO6 UART5_RXD GPIO1_7 7 J6 54 SPI0_D1 GPIO1_4 6 J8 73 MMC1_SDWP UART3_RTSn TIMER_IO7 UART5_TXD GPIO1_7 8 J6 53 PRG0_MDIO0_MDI O GPIO1_4 0 GPMC0_A1 2 J8 72 PRG0...

Page 24: ...G0_PRU1_GPO16 J8 76 TIMER_IO4 MMC1_CLK J6 56 BP_CONN_2_PORZ J8 75 TIMER_IO5 MMC1_CMD J6 55 SPI0_D0 SPI0_D0 J8 74 GPIO1_77 MMC1_SDCD J6 54 SPI0_D1 SPI0_D1 J8 73 GPIO1_78 MMC1_SDWP J6 53 GPIO1_40 PRG0_MDIO0_MDIO J8 72 GPIO1_32 PRG0_PRU1_GPO12 J6 52 GPIO1_41 PRG0_MDIO0_MDC J8 71 GPIO1_33 PRG0_PRU1_GPO13 J6 51 GPIO1_8 PRG0_PRU0_GPO8 Hardware Description www ti com 24 AM243x LaunchPad Development Kit U...

Page 25: ...eset the QSPI FLASH on OSPI0 interface MCAN eQEP_MUX_SEL PRG0_PRU1_GPO8 GPIO1_28 Output PD N A To select the functionality of MCAN0_RX pin as MCAN0_RX or eQEP_I FSI BP_MUX_SEL GPMC0_AD13 GPIO0_28 Output PD N A To select the functionality of GPMC0_AD8 and GPMC0_AD9 pins as FSI_RX or PWM MCAN0_STB PRG0_PRU1_GPO5 GPIO1_25 Output PU Active Low To put the CAN transceiver out of standby PRG_CPSW_RGMII1_...

Page 26: ...Function VPP_1V8_REG_EN PRG1_PRU0_GPO8 GPIO0_53 Output PD Active High To enable the VPP Regulator for eFUSE Programming Hardware Description www ti com 26 AM243x LaunchPad Development Kit User s Guide SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 27: ...ion 3 2 MCU_PORz signal is provided by the outputs of a voltage monitor IC TPS386000RGPR for the core and peripheral voltages where the enable of this voltage monitor is controlled by the PORz signal from the test automation header or push button switch SW1 MCU domain warm reset MCU_RESETz is provided from a push button switch SW2 Main domain warm reset SoC_RESET_REQz is provided by the Warm Reset...

Page 28: ... XDS110 is generated locally using a 16 MHz crystal Figure 4 6 Clock Architecture Table 4 11 Clock Frequency Table SI Signal Name Reference Expected Frequency 1 SOC_CLKIN U11 4 25 000 MHz 2 SOC_CLKIN_BUFF R46 25 000 MHz 3 PRG1_CPSW_RGMII1_CLK R25 25 000 MHz 4 PRG1_CPSW_RGMII2_CLK R50 25 000 MHz 5 OSC0 Y1 3 16 000 MHz Note The 16 MHz clock will only become active after power is supplied to the micr...

Page 29: ...r the flash is connected to a circuit that performs an AND operation to MCU_RESETSTATz and a GPIO from the SoC Power The QSPI flash is powered by the 3 3 V IO supply The 3 3 V supply is provided to both the VCC and VCCQ pins of the flash memory The OSPI0 interface of the SoC is powered by the VDDSHV_3V3 supply Figure 4 7 QSPI Interface www ti com Hardware Description SPRUJ12B AUGUST 2021 REVISED O...

Page 30: ... EE3355AA MAGIC 4 0000 0xEE3355AA HEX Magic Number TYPE 1 0004 0x01 HEX Fixed length and variable position board ID header 2 0005 F7 HEX Size of payload bytes following this field including end_list byte BRD_INFO TYPE 1 0007 0x10 HEX Board Info header identifier Length 2 0008 2E HEX offset to next header Board_Name 16 000A AM243 LPEVM CHAR Design_Rev 2 001A E2 CHAR PROC_Nbr 4 001C 109 CHAR PROC nu...

Page 31: ...ze of payload MAC control 2 003B 0x10 HEX MAC header control word MAC_adrs 192 003D xxxx HEX Will have three valid MAC addresses END_LIST TYPE 1 00FD 0xFE HEX End Marker 4 7 Ethernet Interface The LaunchPad supports two Ethernet PHYs that are terminated to RJ45 connectors with integrated magnetics for external communication Figure 4 9 Ethernet Connection www ti com Hardware Description SPRUJ12B AU...

Page 32: ...1614A from Wurth are used on the board for Ethernet 10Mb 100Mb 1Gb connectivity 4 7 1 Ethernet PHY Strapping The DP83869 uses many of the functional pins as strap options to place the device into specific modes of operation The values of these pins are sampled at power up or hard reset During software resets the strap options are internally reloaded from the values sampled at power up or hard rese...

Page 33: ... Figure 4 11 Ethernet PHY Strapping for RGMII1 PHY Figure 4 12 Ethernet PHY Strapping for RGMII2 PHY www ti com Hardware Description SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feedback AM243x LaunchPad Development Kit User s Guide 33 Copyright 2022 Texas Instruments Incorporated ...

Page 34: ...tput of the clock buffer to both Ethernet PHYs Alternatively RGMII2 PHY can be sourced by the OBSCLK0 output of the SoC as shown in the Clock Architecture Reset The reset signal for the PHYs is driven by an AND operation between PORz_OUT and an SoC GPIO Interrupt The interrupts from the two Ethernet PHYs are shorted and connect to a single GPIO of the AM243x SoC 4 7 3 LED indication in Ethernet RJ...

Page 35: ...he following I2C0 interface is used by the software to identify the LaunchPad through the Board ID memory device AT24CM01 XHD T which is configured to respond to the address 0x50 I2C0 on the LaunchPad is also used to control the 8 bit LED driver TPIC2810 configured to respond to address 0x60 which is used to conrol the Industrial LEDs I2C0 is also connected to the BoosterPack J5 9 J5 10 expansion ...

Page 36: ...C0 port These LEDs are to be toggled based on the Industrial application The other green LED as well as the red and two bi color LEDs are connected to SoC GPIO s such that they can be toggled based on the application Figure 4 15 Industrial Application LEDs Hardware Description www ti com 36 AM243x LaunchPad Development Kit User s Guide SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feed...

Page 37: ... main domain of the SoC MAIN_UART1 are terminated on two on board 1x6 headers There is a buffer SN74CB3Q3125PWR used to isolate between the connectors and the SoC One UART port from the main domain of the SoC Main_UART0 is connected to a buffer SN74AVC4T245PW isolated between the SoC and the on board emulator XDS110 TM4C1294NCPDTT3R Figure 4 16 UART Interface www ti com Hardware Description SPRUJ1...

Page 38: ... header J12 after voltage translation eQEP2_A eQEP2_B are directly connected to the eQEP header J21 after voltage translation eQEP2_I requires an external 1 2 mux TMUX154EDGSR since eQEP2_I and MCAN0_TX come from the same pin B13 Mux channel selection is done using SoC GPIO Figure 4 17 eQEP Interface Figure 4 18 eQEP1 Header Hardware Description www ti com 38 AM243x LaunchPad Development Kit User ...

Page 39: ... 20 eQEP2 or MCAN0 Mux Selection Circuit www ti com Hardware Description SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feedback AM243x LaunchPad Development Kit User s Guide 39 Copyright 2022 Texas Instruments Incorporated ...

Page 40: ...AN interface IC are connected to the MCAN0_RX and MCAN0_TX pins of the AM243x respectively The STB pin can be directly driven by the AM243x to enable standby mode When not directly driven by the AM243x the 10kΩ pulldown resistor puts the CAN interface IC into normal operation mode The output of signals for the CAN transceiver s high and low are connected to the 3 pin header J11 Figure 4 21 CAN Int...

Page 41: ...RPWM signals are internally muxed inside the SoC Figure 4 23 FSI Interface Table 4 14 FSI Header Pin Description Pin Number Signal J16 1 FSI_RX0_CLK J16 2 FSI_TX0_CLK J16 3 GND J16 4 GND J16 5 FSI_RX0_D0 J16 6 FSI_TX0_D0 J16 7 FSI_RX0_D1 J16 8 FSI_TX0_D1 J16 9 No connection J16 10 VSYS_3V3 www ti com Hardware Description SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feedback AM243x Lau...

Page 42: ... FSI or BoosterPack Mux Selection Circuit Hardware Description www ti com 42 AM243x LaunchPad Development Kit User s Guide SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 43: ...ation circuit such that the connection to the emulator is not lost when power to the LaunchPad is removed Voltage translation buffers are used to isolate the XDS110 circuit from the rest of the LaunchPad An ESD protection diode TPDE02B04DQAR is provided on the USB signals to steer ESD current pulses to VCC or GND The ESD protection diode protects against ESD pulses up to 2 5 kV Human Body Model HB...

Page 44: ...243x WARM_RESETn GPIO Creates a RESETz into the AM243x GPIO3 GPIO Disables the boot mode buffer GPIO4 GPIO Resets the bootmode IO expander Bootmode_I2C I2C communicates with bootmode I2C buffer I2C1 I2C For internal testing The test automation circuit has voltage translation circuits so that the controller is isolated from the IO voltages used by the AM243x Boot mode for the AM243x can be controll...

Page 45: ...d DGND 17 N A Reserved 18 N A Reserved 19 N A Reserved 20 N A Reserved 21 N A Reserved 22 N A Reserved 23 N A Reserved 24 N A Reserved 25 Ground DGND 26 Output TEST_POWERDOWN Used to power down the board 27 Output TEST_PORZn Used to reset the SoC PORz 28 Output TEST_WARMRESETn Used to reset the SoC Warm Reset 29 N A Reserved 30 Output TA_SOC_INTn Interrupt to SoC 31 Bidirectional TEST_GPIO2 32 Out...

Page 46: ...I interfaces SPI0 and SPI3 that are terminated to BoosterPack header connectors The SPI connections between the SoC and the BoosterPack connectors are show in Figure 4 29 Figure 4 29 SPI Connection From SoC to BoosterPack Connector Hardware Description www ti com 46 AM243x LaunchPad Development Kit User s Guide SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feedback Copyright 2022 Texas...

Page 47: ...numbers as well as the the BoosterPack compliant features are listed in Figure 4 2 Each GPIO has multiple functions available through the GPIO mux The signals connected from the SoC to the BoosterPack headers include SPI0 and SPI3 UART0 and UART2 I2C0 and I2C1 MMC1 ADC0 EHRPWM0_A B and EHRPWM1_A B GPIO s 5 V and 3 3 V power supplies www ti com Hardware Description SPRUJ12B AUGUST 2021 REVISED OCTO...

Page 48: ...erPack When left unpopulated the BoosterPack will be required to source its own power Note Sourcing power to the LaunchPad from the BoosterPack should not be attempted Table 4 1 BoosterPack Power Sourcing for BoosterPack Site 2 Function Mount R161 and R163 Default Unmount R161 and R163 Power to BoosterPack sourced from LaunchPad Power to BoosterPack sourced from the BoosterPack Figure 4 3 Site 2 B...

Page 49: ...Figure 4 4 80 Pin BoosterPack Pinout www ti com Hardware Description SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feedback AM243x LaunchPad Development Kit User s Guide 49 Copyright 2022 Texas Instruments Incorporated ...

Page 50: ..._AIN5 GPIO1_8 5 J1 7 PRG0_PRU0_GP O16 PRG0_PRU0_GPI1 6 PRG0_RGMII1_TXC PRG0_PWM0_A2 SPI3_CLK GPIO1_1 6 GPMC0_A4 J3 27 ADC0_AIN6 GPIO1_8 6 J1 8 PRG0_PRU0_GP O18 PRG0_PRU0_GPI1 8 PRG0_IEP0_EDC_LATCH _IN0 PRG0_PWM0_TZ _IN CPTS0_HW1TSPU SH CP_GEMAC_CPTS0_HW1TSP USH HRPWM8_A GPIO1_1 8 UART4_CT Sn GPMC0_A5 UART2_RX D J3 28 ADC0_AIN7 GPIO1_8 7 J1 9 I2C1_SCL CPTS0_HW1TSPU SH TIMER_IO0 SPI2_CS1 DDR0_IO_PLL...

Page 51: ...GPIO1_12 PRG0_PRU0_GPO12 J3 25 BP_ADC0_AIN4 ADC0_AIN4 J1 6 BP_ADC0_AIN1 ADC0_AIN1 J3 26 BP_ADC0_AIN5 ADC0_AIN5 J1 7 SPI3_CLK PRG0_PRU _GPO16 J3 27 BP_ADC0_AIN6 ADC0_AIN6 J1 8 GPIO1_18 PRG0_PRU0_GPO18 J3 28 BP_ADC0_AIN7 ADC0_AIN7 J1 9 SOC_I2C1_SCL I2C1_SCL J3 29 SYNC2_OUT MCAN0_TX J1 10 SOC_I2C1_SDA I2C1_SDA J3 30 SYNC3_OUT MCAN0_RX www ti com Hardware Description SPRUJ12B AUGUST 2021 REVISED OCTOB...

Page 52: ...RZ J4 35 EHRPWM2_B GPMC0_AD9 GPMC0_AD9 FSI_RX0_D0 UART3_CTSn EHRPWM2_B TRC_DATA7 GPIO0_24 PRG0_PWM2_ B2 J2 15 SPI3_D0 PRG0_PRU0_G PO13 PRG0_PRU0_G PO13 PRG0_PRU0_G PI13 PRG0_RGMII1_ TD2 PRG0_PWM0_ B0 SPI3_D0 GPIO1_13 GPMC0_A15 J4 34 EHRPWM0_TZ N_IN0 GPMC0_AD2 GPMC0_AD2 FSI_RX2_D1 UART2_RTSn EHRPWM_TZn _IN0 TRC_DATA0 GPIO0_17 PRG0_PWM2_ TZ_IN J2 14 SPI3_D1 PRG0_PRU0_G PO14 PRG0_PRU0_G PO14 PRG0_PRU...

Page 53: ...O4 J4 36 EHRPWM2_A GPMC0_AD8 J2 16 BP_CONN_1_PORZ J4 35 EHRPWM2_B GPMC0_AD9 J2 15 SPI3_D0 PRG0_PRU0_GPO13 J4 34 EHRPWM0_TZN_IN0 GPMC0_AD2 J2 14 SPI3_D1 PRG0_PRU0_GPO14 J4 33 GPIO1_0 PRG0_PRU0_GPO0 J2 13 GPIO1_5 PRG0_PRU0_GPO5 J4 32 GPIO1_1 PRG0_PRU0_GPO1 J2 12 SPI3_CS1 PRG0_PRU0_GPO15 J4 31 GPIO1_2 PRG0_PRU0_GPO2 J2 11 GPIO1_20 PRG0_PRU1_GPO0 www ti com Hardware Description SPRUJ12B AUGUST 2021 RE...

Page 54: ...RT3_RXD J7 65 PRG1_PRU0_GPO1 7 PRG1_PRU0_GPI1 7 PRG1_IEP0_EDC_SYNC_OUT1 PRG1_PWM0_B2 CPTS0_TS_SYNC TIMER_IO7 GPIO0_62 GPMC0_A0 J5 46 PRG1_PRU0_GPO5 PRG1_PRU0_GPI5 PRG1_PWM3_B2 RGMII1_RX_CTL GPIO0_50 GPMC0_AD21 J7 66 PRG1_PRU0_GPO7 PRG1_PRU0_GPI7 PRG1_IEP0_EDC_LATCH_IN1 PRG1_PWM3_B1 CPTS0_HW2TSPUS H CLKOUT0 TIMER_IO10 GPIO0_52 GPMC0_AD23 J5 47 SPI0_CLK GPIO1_44 J7 67 PRG0_PRU1_GPO1 PRG0_PRU1_GPI1 P...

Page 55: ...PIO1_19 PRG0_PRU0_GPO19 J7 65 PRG1_IEP0_EDC_SYNC_OUT1 PRG1_PRU0_GPO17 J5 46 GPIO0_50 PRG1_PRU0_GPO5 J7 66 PRG1_IEP0_EDC_LATCH_IN1 PRG1_PRU0_GPO7 J5 47 SPI0_CLK SPI0_CLK J7 67 GPIO1_21 PRG0_PRU1_GPO1 J5 48 GPIO1_6 PRG0_PRU0_GPO6 J7 68 GPIO1_22 PRG0_PRU1_GPO2 J5 49 SOC_I2C0_SCL_BP I2C0_SCL J7 69 GPIO1_26 PRG0_PRU1_GPO6 J5 50 SOC_I2C0_SDA_BP I2C0_SDA J7 70 GPIO1_31 PRG0_PRU1_GPO11 www ti com Hardware...

Page 56: ...PWM1_A 2 GPIO1_3 6 GPMC0_A1 1 PRG0_ECAP0_SYNC_OUT J8 76 MMC1_CLK UART2_CTSn TIMER_IO4 UART4_RXD GPIO1_7 5 J6 56 BP_CONN_2_POR Z J8 75 MMC1_CMD UART2_RTSn TIMER_IO5 UART4_TXD GPIO1_7 6 J6 55 SPI0_D0 GPIO1_4 5 J8 74 MMC1_SDCD UART3_CTSn TIMER_IO6 UART5_RXD GPIO1_7 7 J6 54 SPI0_D1 GPIO1_4 6 J8 73 MMC1_SDWP UART3_RTSn TIMER_IO7 UART5_TXD GPIO1_7 8 J6 53 PRG0_MDIO0_MDI O GPIO1_4 0 GPMC0_A1 2 J8 72 PRG0...

Page 57: ...G0_PRU1_GPO16 J8 76 TIMER_IO4 MMC1_CLK J6 56 BP_CONN_2_PORZ J8 75 TIMER_IO5 MMC1_CMD J6 55 SPI0_D0 SPI0_D0 J8 74 GPIO1_77 MMC1_SDCD J6 54 SPI0_D1 SPI0_D1 J8 73 GPIO1_78 MMC1_SDWP J6 53 GPIO1_40 PRG0_MDIO0_MDIO J8 72 GPIO1_32 PRG0_PRU1_GPO12 J6 52 GPIO1_41 PRG0_MDIO0_MDC J8 71 GPIO1_33 PRG0_PRU1_GPO13 J6 51 GPIO1_8 PRG0_PRU0_GPO8 www ti com Hardware Description SPRUJ12B AUGUST 2021 REVISED OCTOBER ...

Page 58: ...eset the QSPI FLASH on OSPI0 interface MCAN eQEP_MUX_SEL PRG0_PRU1_GPO8 GPIO1_28 Output PD N A To select the functionality of MCAN0_RX pin as MCAN0_RX or eQEP_I FSI BP_MUX_SEL GPMC0_AD13 GPIO0_28 Output PD N A To select the functionality of GPMC0_AD8 and GPMC0_AD9 pins as FSI_RX or PWM MCAN0_STB PRG0_PRU1_GPO5 GPIO1_25 Output PU Active Low To put the CAN transceiver out of standby PRG_CPSW_RGMII1_...

Page 59: ...Function VPP_1V8_REG_EN PRG1_PRU0_GPO8 GPIO0_53 Output PD Active High To enable the VPP Regulator for eFUSE Programming www ti com Hardware Description SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feedback AM243x LaunchPad Development Kit User s Guide 59 Copyright 2022 Texas Instruments Incorporated ...

Page 60: ...ion 3 2 MCU_PORz signal is provided by the outputs of a voltage monitor IC TPS386000RGPR for the core and peripheral voltages where the enable of this voltage monitor is controlled by the PORz signal from the test automation header or push button switch SW1 MCU domain warm reset MCU_RESETz is provided from a push button switch SW2 Main domain warm reset SoC_RESET_REQz is provided by the Warm Reset...

Page 61: ... XDS110 is generated locally using a 16 MHz crystal Figure 4 6 Clock Architecture Table 4 11 Clock Frequency Table SI Signal Name Reference Expected Frequency 1 SOC_CLKIN U11 4 25 000 MHz 2 SOC_CLKIN_BUFF R46 25 000 MHz 3 PRG1_CPSW_RGMII1_CLK R25 25 000 MHz 4 PRG1_CPSW_RGMII2_CLK R50 25 000 MHz 5 OSC0 Y1 3 16 000 MHz Note The 16 MHz clock will only become active after power is supplied to the micr...

Page 62: ...r the flash is connected to a circuit that performs an AND operation to MCU_RESETSTATz and a GPIO from the SoC Power The QSPI flash is powered by the 3 3 V IO supply The 3 3 V supply is provided to both the VCC and VCCQ pins of the flash memory The OSPI0 interface of the SoC is powered by the VDDSHV_3V3 supply Figure 4 7 QSPI Interface Hardware Description www ti com 62 AM243x LaunchPad Developmen...

Page 63: ... EE3355AA MAGIC 4 0000 0xEE3355AA HEX Magic Number TYPE 1 0004 0x01 HEX Fixed length and variable position board ID header 2 0005 F7 HEX Size of payload bytes following this field including end_list byte BRD_INFO TYPE 1 0007 0x10 HEX Board Info header identifier Length 2 0008 2E HEX offset to next header Board_Name 16 000A AM243 LPEVM CHAR Design_Rev 2 001A E2 CHAR PROC_Nbr 4 001C 109 CHAR PROC nu...

Page 64: ...ze of payload MAC control 2 003B 0x10 HEX MAC header control word MAC_adrs 192 003D xxxx HEX Will have three valid MAC addresses END_LIST TYPE 1 00FD 0xFE HEX End Marker 4 7 Ethernet Interface The LaunchPad supports two Ethernet PHYs that are terminated to RJ45 connectors with integrated magnetics for external communication Figure 4 9 Ethernet Connection Hardware Description www ti com 64 AM243x L...

Page 65: ...1614A from Wurth are used on the board for Ethernet 10Mb 100Mb 1Gb connectivity 4 7 1 Ethernet PHY Strapping The DP83869 uses many of the functional pins as strap options to place the device into specific modes of operation The values of these pins are sampled at power up or hard reset During software resets the strap options are internally reloaded from the values sampled at power up or hard rese...

Page 66: ... Figure 4 11 Ethernet PHY Strapping for RGMII1 PHY Figure 4 12 Ethernet PHY Strapping for RGMII2 PHY Hardware Description www ti com 66 AM243x LaunchPad Development Kit User s Guide SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 67: ...tput of the clock buffer to both Ethernet PHYs Alternatively RGMII2 PHY can be sourced by the OBSCLK0 output of the SoC as shown in the Clock Architecture Reset The reset signal for the PHYs is driven by an AND operation between PORz_OUT and an SoC GPIO Interrupt The interrupts from the two Ethernet PHYs are shorted and connect to a single GPIO of the AM243x SoC 4 7 3 LED indication in Ethernet RJ...

Page 68: ...he following I2C0 interface is used by the software to identify the LaunchPad through the Board ID memory device AT24CM01 XHD T which is configured to respond to the address 0x50 I2C0 on the LaunchPad is also used to control the 8 bit LED driver TPIC2810 configured to respond to address 0x60 which is used to conrol the Industrial LEDs I2C0 is also connected to the BoosterPack J5 9 J5 10 expansion ...

Page 69: ...C0 port These LEDs are to be toggled based on the Industrial application The other green LED as well as the red and two bi color LEDs are connected to SoC GPIO s such that they can be toggled based on the application Figure 4 15 Industrial Application LEDs www ti com Hardware Description SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feedback AM243x LaunchPad Development Kit User s Guid...

Page 70: ... main domain of the SoC MAIN_UART1 are terminated on two on board 1x6 headers There is a buffer SN74CB3Q3125PWR used to isolate between the connectors and the SoC One UART port from the main domain of the SoC Main_UART0 is connected to a buffer SN74AVC4T245PW isolated between the SoC and the on board emulator XDS110 TM4C1294NCPDTT3R Figure 4 16 UART Interface Hardware Description www ti com 70 AM2...

Page 71: ... header J12 after voltage translation eQEP2_A eQEP2_B are directly connected to the eQEP header J21 after voltage translation eQEP2_I requires an external 1 2 mux TMUX154EDGSR since eQEP2_I and MCAN0_TX come from the same pin B13 Mux channel selection is done using SoC GPIO Figure 4 17 eQEP Interface Figure 4 18 eQEP1 Header www ti com Hardware Description SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022...

Page 72: ... 20 eQEP2 or MCAN0 Mux Selection Circuit Hardware Description www ti com 72 AM243x LaunchPad Development Kit User s Guide SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments Incorporated ...

Page 73: ...AN interface IC are connected to the MCAN0_RX and MCAN0_TX pins of the AM243x respectively The STB pin can be directly driven by the AM243x to enable standby mode When not directly driven by the AM243x the 10kΩ pulldown resistor puts the CAN interface IC into normal operation mode The output of signals for the CAN transceiver s high and low are connected to the 3 pin header J11 Figure 4 21 CAN Int...

Page 74: ...RPWM signals are internally muxed inside the SoC Figure 4 23 FSI Interface Table 4 14 FSI Header Pin Description Pin Number Signal J16 1 FSI_RX0_CLK J16 2 FSI_TX0_CLK J16 3 GND J16 4 GND J16 5 FSI_RX0_D0 J16 6 FSI_TX0_D0 J16 7 FSI_RX0_D1 J16 8 FSI_TX0_D1 J16 9 No connection J16 10 VSYS_3V3 Hardware Description www ti com 74 AM243x LaunchPad Development Kit User s Guide SPRUJ12B AUGUST 2021 REVISED...

Page 75: ... FSI or BoosterPack Mux Selection Circuit www ti com Hardware Description SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feedback AM243x LaunchPad Development Kit User s Guide 75 Copyright 2022 Texas Instruments Incorporated ...

Page 76: ...ation circuit such that the connection to the emulator is not lost when power to the LaunchPad is removed Voltage translation buffers are used to isolate the XDS110 circuit from the rest of the LaunchPad An ESD protection diode TPDE02B04DQAR is provided on the USB signals to steer ESD current pulses to VCC or GND The ESD protection diode protects against ESD pulses up to 2 5 kV Human Body Model HB...

Page 77: ...243x WARM_RESETn GPIO Creates a RESETz into the AM243x GPIO3 GPIO Disables the boot mode buffer GPIO4 GPIO Resets the bootmode IO expander Bootmode_I2C I2C communicates with bootmode I2C buffer I2C1 I2C For internal testing The test automation circuit has voltage translation circuits so that the controller is isolated from the IO voltages used by the AM243x Boot mode for the AM243x can be controll...

Page 78: ...d DGND 17 N A Reserved 18 N A Reserved 19 N A Reserved 20 N A Reserved 21 N A Reserved 22 N A Reserved 23 N A Reserved 24 N A Reserved 25 Ground DGND 26 Output TEST_POWERDOWN Used to power down the board 27 Output TEST_PORZn Used to reset the SoC PORz 28 Output TEST_WARMRESETn Used to reset the SoC Warm Reset 29 N A Reserved 30 Output TA_SOC_INTn Interrupt to SoC 31 Bidirectional TEST_GPIO2 32 Out...

Page 79: ...I interfaces SPI0 and SPI3 that are terminated to BoosterPack header connectors The SPI connections between the SoC and the BoosterPack connectors are show in Figure 4 29 Figure 4 29 SPI Connection From SoC to BoosterPack Connector www ti com Hardware Description SPRUJ12B AUGUST 2021 REVISED OCTOBER 2022 Submit Document Feedback AM243x LaunchPad Development Kit User s Guide 79 Copyright 2022 Texas...

Page 80: ...6RGYR 6 bit Bidirectional Voltage Level Translator TMUX154E 2 Channel 2 1 Switch TPD4E02B04DQAR ESD Protection Diode for USB 3 0 XDS110 JTAG Debug Probe TUSB320LAI USB Type C Configuration Channel Port Controller LMK1C1103PWR 3 Channel Output LVCMOS 1 8V Buffer TS3DDR3812RUAR 12 Channel Switch for DDR3 Applications TCAN1044 Q1 Automotive High Speed CAN Tranceiver TPIC2810D 8 bit LED Driver with I2...

Page 81: ...PRG1_PRU0_GPO5 GPIO0_50 GPIO0_50 PRG1_CPSW_ETH1_LED_1000 RX_ER Ethernet PHY1 RX ER indication to SoC PRG1_PRU0_GPO8 GPIO0_53 VPP_1V8_REG_EN PRG1_CPSW_ETH1_LED_LINK Ethernet PHY1 RX link indication to SoC PRG1_PRU0_GPO9 GPIO0_54 CPSW_RGMII1_TX_CTL PRG1_CPSW_ETH1_LED_ACT Ethernet PHY1 MII COL indication to SoC PRG1_PRU1_GPO9 GPIO0_74 CPSW_RGMII1_TD1 PRG1_CPSW_ETH2_LED_ACT Ethernet PHY2 MII COL indic...

Page 82: ...1_CPSW_ETH1_LED_LINK Ethernet PHY1 RX link indication to SoC PRG1_PRU0_GPO9 GPIO0_54 PRG1_CPSW_ETH1_LED_ACT Ethernet PHY1 MII COL indication to SoC PRG1_PRU1_GPO9 GPIO0_74 PRG1_CPSW_ETH2_LED_ACT Ethernet PHY2 MII COL indication to SoC c The ETH n _LED_ACT signals are connected via a resistor mux with the following logic Table A 4 E3 LED ACT Signal Resistor Mounting Interface Mount DNI CPSW_RGMII1_...

Page 83: ...o change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you will fully indemn...

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