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Architecture

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SPRUH82C – April 2013 – Revised September 2016

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Copyright © 2013–2016, Texas Instruments Incorporated

Enhanced Direct Memory Access (EDMA3) Controller

17.2.11 EDMA3 Transfer Controller (EDMA3TC)

The EDMA3 channel controller is the user-interface of the EDMA3 and the EDMA3 transfer controller
(EDMA3TC) is the data movement engine of the EDMA3. The EDMA3CC submits transfer requests (TR)
to the EDMA3TC and the EDMA3TC performs the data transfers dictated by the TR.

17.2.11.1 Architecture Details

17.2.11.1.1 EDMA3TC Configuration

Each transfer controller on a device is designed differently based on considerations like performance
requirements, system topology (main SCR bus width, external memory bus width), gate count, etc. The
parameters that determine the TC configurations are:

•

FIFOSIZE: Determines the size in bytes for the Data FIFO that is the temporary buffer for the in-flight
data. The data FIFO is where the read return data read by the TC read controller from the source
endpoint is stored and subsequently written out to the destination endpoint by the TC write controller.

•

Default Burst Size (DBS): The DBS is the maximum number of bytes per read/write command issued
by a transfer controller.

•

BUSWIDTH: The width of the read and write data buses in bytes, for the TC read and write controller,
respectively. This is typically equal to the bus width of the main SCR interface.

•

DSTREGDEPTH: This determines the number of Destination FIFO register set. The number of
Destination FIFO register set for a transfer controller, determines the maximum number of outstanding
transfer requests (TR pipelining).

Of the four parameters, the FIFOSIZE, BUSWIDTH, and DSTREGDEPTH values are fixed in design for a
given device. The default burst size (DBS) for EDMA3_0_TC0 and EDMA3_0_TC1 is configurable by the
chip configuration 0 register (CFGCHIP0) in the System Configuration Module and for EDMA3_1_TC0 is
configurable by the chip configuration 1 register (CFGCHIP1) in the System Configuration Module.

provides the configuration of the individual EDMA3 transfer controllers on the device.

The burst size for each transfer controlled can be programmed to be 16-, 32-, or 64-bytes. The default
values for DBS are typically chosen for optimal performance in most intended-use conditions; therefore, if
you decide to use a value other then the default, you should evaluate the impact on performance.
Depending on the FIFOSIZE and source/destination locations the performance for the transfer can vary
significantly for different burst size values.

NOTE:

It is expected that the DBS value for a transfer controller is static and should be based on

the application requirement. It is not recommended that the DBS value be changed on-the-
fly.

Table 17-12. EDMA3 Transfer Controller Configurations

Parameter

EDMA3_0_TC0

EDMA3_0_TC1

EDMA3_1_TC0

FIFOSIZE

128 bytes

128 bytes

256 bytes

BUSWIDTH

8 bytes (64 bits)

8 bytes (64 bits)

8 bytes (64 bits)

DSTREGDEPTH

4 entries

4 entries

4 entries

DBS (default)

16 bytes

16 bytes

16 bytes

Error interrupt

EDMA3_0_TC0_ERRINT

EDMA3_0_TC1_ERRINT

EDMA3_1_TC0_ERRINT

EDMA3 channel controller
used

EDMA3_0_CC0

EDMA3_0_CC0

EDMA3_1_CC0

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Summary of Contents for AM1808

Page 1: ...AM1808 AM1810 Sitara ARM Microprocessor Technical Reference Manual Literature Number SPRUH82C April 2013 Revised September 2016 ...

Page 2: ... Block Diagram 92 4 System Memory 93 4 1 Introduction 94 4 2 ARM Memories 94 4 3 Peripherals 94 5 Memory Protection Unit MPU 95 5 1 Introduction 96 5 1 1 Purpose of the MPU 96 5 1 2 Features 96 5 1 3 Block Diagram 96 5 1 4 MPU Default Configuration 97 5 2 Architecture 97 5 2 1 Privilege Levels 97 5 2 2 Memory Protection Ranges 98 5 2 3 Permission Structures 99 5 2 4 Protection Check 100 5 2 5 MPU ...

Page 3: ...lock Generation 133 7 2 2 Steps for Programming the PLLs 134 7 3 PLLC Registers 136 7 3 1 PLLC0 Revision Identification Register REVID 137 7 3 2 PLLC1 Revision Identification Register REVID 138 7 3 3 Reset Type Status Register RSTYPE 138 7 3 4 PLLC0 Reset Control Register RSCTRL 139 7 3 5 PLLC0 Control Register PLLCTL 140 7 3 6 PLLC1 Control Register PLLCTL 141 7 3 7 PLLC0 OBSCLK Select Register O...

Page 4: ...ndling 172 8 6 PSC Registers 173 8 6 1 Revision Identification Register REVID 174 8 6 2 Interrupt Evaluation Register INTEVAL 174 8 6 3 PSC0 Module Error Pending Register 0 modules 0 15 MERRPR0 175 8 6 4 PSC1 Module Error Pending Register 0 modules 0 31 MERRPR0 175 8 6 5 PSC0 Module Error Clear Register 0 modules 0 15 MERRCR0 176 8 6 6 PSC1 Module Error Clear Register 0 modules 0 31 MERRCR0 176 8 ...

Page 5: ...ker Mechanism Protection 205 10 3 Master Priority Control 205 10 4 Interrupt Support 207 10 4 1 Interrupt Events and Requests 207 10 4 2 Interrupt Multiplexing 207 10 5 SYSCFG Registers 207 10 5 1 Revision Identification Register REVID 209 10 5 2 Device Identification Register 0 DEVIDR0 209 10 5 3 Boot Configuration Register BOOTCFG 210 10 5 4 Chip Revision Identification Register CHIPREVIDR 210 1...

Page 6: ...or Size Register VSR 297 11 4 13 Vector Null Register VNR 298 11 4 14 Global Prioritized Index Register GPIR 298 11 4 15 Global Prioritized Vector Register GPVR 299 11 4 16 System Interrupt Status Raw Set Register 1 SRSR1 299 11 4 17 System Interrupt Status Raw Set Register 2 SRSR2 300 11 4 18 System Interrupt Status Raw Set Register 3 SRSR3 300 11 4 19 System Interrupt Status Raw Set Register 4 S...

Page 7: ...5 INTC Methodology 345 13 8 Registers 348 13 8 1 PRUSS Memory Map 349 13 8 2 INTC Registers 356 14 DDR2 mDDR Memory Controller 367 14 1 Introduction 368 14 1 1 Purpose of the Peripheral 368 14 1 2 Features 368 14 1 3 Functional Block Diagram 369 14 1 4 Supported Use Case Statement 369 14 1 5 Industry Standard s Compliance Statement 369 14 2 Architecture 370 14 2 1 Clock Control 370 14 2 2 Signal D...

Page 8: ...cations 433 15 3 1 Absolute Time Stamp Operation Rising Edge Trigger Example 434 15 3 2 Absolute Time Stamp Operation Rising and Falling Edge Trigger Example 436 15 3 3 Time Difference Delta Operation Rising Edge Trigger Example 438 15 3 4 Time Difference Delta Operation Rising and Falling Edge Trigger Example 440 15 3 5 Application of the APWM Mode 442 15 4 Registers 449 15 4 1 Time Stamp Counter...

Page 9: ...fier Submodule Registers 557 16 4 4 Dead Band Generator Submodule Registers 561 16 4 5 PWM Chopper Submodule Register 564 16 4 6 Trip Zone Submodule Registers 565 16 4 7 Event Trigger Submodule Registers 569 16 4 8 High Resolution PWM Submodule Registers 572 17 Enhanced Direct Memory Access EDMA3 Controller 575 17 1 Introduction 576 17 1 1 Overview 576 17 1 2 Features 576 17 1 3 Functional Block D...

Page 10: ...w 718 18 2 5 Programming Interface 719 18 2 6 EMAC Control Module 730 18 2 7 MDIO Module 731 18 2 8 EMAC Module 736 18 2 9 MAC Interface 738 18 2 10 Packet Receive Operation 742 18 2 11 Packet Transmit Operation 747 18 2 12 Receive and Transmit Latency 748 18 2 13 Transfer Node Priority 748 18 2 14 Reset Considerations 749 18 2 15 Initialization 750 18 2 16 Interrupt Support 752 18 2 17 Power Mana...

Page 11: ... 19 4 13 NAND Flash Status Register NANDFSR 914 19 4 14 NAND Flash n ECC Registers NANDF1ECC NANDF4ECC 915 19 4 15 NAND Flash 4 Bit ECC LOAD Register NAND4BITECCLOAD 916 19 4 16 NAND Flash 4 Bit ECC Register 1 NAND4BITECC1 917 19 4 17 NAND Flash 4 Bit ECC Register 2 NAND4BITECC2 917 19 4 18 NAND Flash 4 Bit ECC Register 3 NAND4BITECC3 918 19 4 19 NAND Flash 4 Bit ECC Register 4 NAND4BITECC4 918 19...

Page 12: ...tement 957 21 1 5 Terminology Used in This Document 957 21 2 Architecture 958 21 2 1 Clock Control 958 21 2 2 Memory Map 958 21 2 3 Signal Descriptions 958 21 2 4 Pin Multiplexing and General Purpose I O Control Blocks 959 21 2 5 Protocol Description 960 21 2 6 Operation 960 21 2 7 Reset Considerations 975 21 2 8 Initialization 975 21 2 9 Interrupt Support 976 21 2 10 EDMA Event Support 977 21 2 1...

Page 13: ... Mode Register ICMDR 1013 22 3 10 I2C Interrupt Vector Register ICIVR 1017 22 3 11 I2C Extended Mode Register ICEMDR 1018 22 3 12 I2C Prescaler Register ICPSC 1019 22 3 13 I2C Revision Identification Register REVID1 1020 22 3 14 I2C Revision Identification Register REVID2 1020 22 3 15 I2C DMA Control Register ICDMAC 1021 22 3 16 I2C Pin Function Register ICPFUNC 1022 22 3 17 I2C Pin Direction Regi...

Page 14: ... 3 Pin Function Register PFUNC 1139 24 1 4 Pin Direction Register PDIR 1141 24 1 5 Pin Data Output Register PDOUT 1143 24 1 6 Pin Data Input Register PDIN 1145 24 1 7 Pin Data Set Register PDSET 1147 24 1 8 Pin Data Clear Register PDCLR 1149 24 1 9 Global Control Register GBLCTL 1151 24 1 10 Audio Mute Control Register AMUTE 1153 24 1 11 Digital Loopback Control Register DLBCTL 1155 24 1 12 Digita...

Page 15: ...e of the Peripheral 1193 25 1 2 Features 1193 25 1 3 Functional Block Diagram 1194 25 1 4 Industry Standard Compliance Statement 1194 25 2 Architecture 1195 25 2 1 Clock Control 1195 25 2 2 Signal Descriptions 1195 25 2 3 Pin Multiplexing 1195 25 2 4 Endianness Considerations 1195 25 2 5 Clock Frames and Data 1196 25 2 6 McBSP Buffer FIFO BFIFO 1210 25 2 7 McBSP Standard Operation 1210 25 2 8 μ La...

Page 16: ...4 26 3 2 MMC SD Mode Single Block Write Operation Using CPU 1287 26 3 3 MMC SD Mode Single Block Write Operation Using the EDMA 1289 26 3 4 MMC SD Mode Single Block Read Operation Using the CPU 1289 26 3 5 MMC SD Mode Single Block Read Operation Using EDMA 1291 26 3 6 MMC SD Mode Multiple Block Write Operation Using CPU 1291 26 3 7 MMC SD Mode Multiple Block Write Operation Using EDMA 1293 26 3 8 ...

Page 17: ...nd Register SECOND 1328 27 3 2 Minute Register MINUTE 1328 27 3 3 Hour Register HOUR 1329 27 3 4 Day of the Month Register DAY 1330 27 3 5 Month Register MONTH 1330 27 3 6 Year Register YEAR 1331 27 3 7 Day of the Week Register DOTW 1331 27 3 8 Alarm Second Register ALARMSECOND 1332 27 3 9 Alarm Minute Register ALARMMINUTE 1332 27 3 10 Alarm Hour Register ALARMHOUR 1333 27 3 11 Alarm Day of the Mo...

Page 18: ... BISTAFR 1381 28 4 9 BIST Control Register BISTCR 1381 28 4 10 BIST FIS Count Register BISTFCTR 1384 28 4 11 BIST Status Register BISTSR 1384 28 4 12 BIST DWORD Error Count Register BISTDECR 1385 28 4 13 BIST DWORD Error Count Register TIMER1MS 1385 28 4 14 Global Parameter 1 Register GPARAM1R 1386 28 4 15 Global Parameter 2 Register GPARAM2R 1387 28 4 16 Port Parameter Register PPARAMR 1388 28 4 ...

Page 19: ...on Considerations 1434 29 2 19 Initialization 1434 29 2 20 Timing Diagrams 1435 29 3 Registers 1441 29 3 1 SPI Global Control Register 0 SPIGCR0 1441 29 3 2 SPI Global Control Register 1 SPIGCR1 1442 29 3 3 SPI Interrupt Register SPIINT0 1444 29 3 4 SPI Interrupt Level Register SPILVL 1446 29 3 5 SPI Flag Register SPIFLG 1447 29 3 6 SPI Pin Control Register 0 SPIPC0 1449 29 3 7 SPI Pin Control Reg...

Page 20: ...1 Timer Reload Register 34 REL34 1497 30 2 12 Timer Capture Register 12 CAP12 1498 30 2 13 Timer Capture Register 34 CAP34 1498 30 2 14 Timer Interrupt Control and Status Register INTCTLSTAT 1499 31 Universal Asynchronous Receiver Transmitter UART 1501 31 1 Introduction 1502 31 1 1 Purpose of the Peripheral 1502 31 1 2 Features 1502 31 1 3 Functional Block Diagram 1502 31 1 4 Industry Standard s C...

Page 21: ...nel Control Register UPCTL 1558 32 3 5 uPP Interface Configuration Register UPICR 1560 32 3 6 uPP Interface Idle Value Register UPIVR 1562 32 3 7 uPP Threshold Configuration Register UPTCR 1563 32 3 8 uPP Interrupt Raw Status Register UPISR 1564 32 3 9 uPP Interrupt Enabled Status Register UPIER 1566 32 3 10 uPP Interrupt Enable Set Register UPIES 1568 32 3 11 uPP Interrupt Enable Clear Register U...

Page 22: ...mber Register HCFMNUMBER 1597 33 3 17 HC Periodic Start Register HCPERIODICSTART 1598 33 3 18 HC Low Speed Threshold Register HCLSTHRESHOLD 1598 33 3 19 HC Root Hub A Register HCRHDESCRIPTORA 1599 33 3 20 HC Root Hub B Register HCRHDESCRIPTORB 1600 33 3 21 HC Root Hub Status Register HCRHSTATUS 1601 33 3 22 HC Port 1 Status and Control Register HCRHPORTSTATUS1 1602 33 3 23 HC Port 2 Status and Con...

Page 23: ...4 4 26 Interrupt Enable Register for INTRRX INTRRXE 1713 34 4 27 Interrupt Register for Common USB Interrupts INTRUSB 1714 34 4 28 Interrupt Enable Register for INTRUSB INTRUSBE 1715 34 4 29 Frame Number Register FRAME 1715 34 4 30 Index Register for Selecting the Endpoint Status and Control Registers INDEX 1716 34 4 31 Register to Enable the USB 2 0 Test Modes TESTMODE 1716 34 4 32 Maximum Packet...

Page 24: ...4 74 CDMA Scheduler Table Word n Registers WORD 0 WORD 63 1744 34 4 75 Queue Manager Revision Identification Register QMGRREVID 1746 34 4 76 Queue Manager Queue Diversion Register DIVERSION 1746 34 4 77 Queue Manager Free Descriptor Buffer Starvation Count Register 0 FDBSC0 1747 34 4 78 Queue Manager Free Descriptor Buffer Starvation Count Register 1 FDBSC1 1748 34 4 79 Queue Manager Free Descript...

Page 25: ...Channel n Image Address Offset Register CnIMGOFFSET 1804 35 3 22 Channel n Horizontal Ancillary Address Offset Register CnHANCOFFSET 1804 35 3 23 Channel n Horizontal Size Configuration Register C0HCFG and C1HCFG 1805 35 3 24 Channel n Vertical Size Configuration 0 Register C0VCFG0 and C1VCFG0 1806 35 3 25 Channel n Vertical Size Configuration 1 Register C0VCFG1 and C1VCFG1 1806 35 3 26 Channel n ...

Page 26: ...1 5 16 Programmable Range Memory Protection Page Attributes Register PROGn_MPPA 112 5 17 Fault Address Register FLTADDRR 113 5 18 Fault Status Register FLTSTAT 114 5 19 Fault Clear Register FLTCLR 115 6 1 Overall Clocking Diagram 118 6 2 USB Clocking Diagram 121 6 3 DDR2 mDDR Memory Controller Clocking Diagram 123 6 4 EMIFA Clocking Diagram 124 6 5 EMAC Clocking Diagram 125 6 6 uPP Clocking Diagra...

Page 27: ...aluation Register INTEVAL 174 8 3 PSC0 Module Error Pending Register 0 MERRPR0 175 8 4 PSC1 Module Error Pending Register 0 MERRPR0 175 8 5 PSC0 Module Error Clear Register 0 MERRCR0 176 8 6 PSC1 Module Error Clear Register 0 MERRCR0 176 8 7 Power Error Pending Register PERRPR 177 8 8 Power Error Clear Register PERRCR 177 8 9 Power Domain Transition Command Register PTCMD 178 8 10 Power Domain Tra...

Page 28: ...0 31 Pin Multiplexing Control 13 Register PINMUX13 247 10 32 Pin Multiplexing Control 14 Register PINMUX14 249 10 33 Pin Multiplexing Control 15 Register PINMUX15 251 10 34 Pin Multiplexing Control 16 Register PINMUX16 254 10 35 Pin Multiplexing Control 17 Register PINMUX17 256 10 36 Pin Multiplexing Control 18 Register PINMUX18 258 10 37 Pin Multiplexing Control 19 Register PINMUX19 260 10 38 Sus...

Page 29: ... Set Register 2 ESR2 304 11 28 System Interrupt Enable Set Register 3 ESR3 304 11 29 System Interrupt Enable Set Register 4 ESR4 305 11 30 System Interrupt Enable Clear Register 1 ECR1 305 11 31 System Interrupt Enable Clear Register 2 ECR2 306 11 32 System Interrupt Enable Clear Register 3 ECR3 306 11 33 System Interrupt Enable Clear Register 4 ECR4 307 11 34 Channel Map Registers CMRn 307 11 35 ...

Page 30: ... 14 6 DEAC Command 376 14 7 ACTV Command 377 14 8 DDR2 mDDR READ Command 378 14 9 DDR2 mDDR WRT Command 379 14 10 DDR2 mDDR MRS and EMRS Command 380 14 11 Byte Alignment 380 14 12 DDR2 mDDR SDRAM Column Row and Bank Access 384 14 13 Address Mapping Diagram IBANKPOS 1 385 14 14 SDRAM Column Row Bank Access IBANKPOS 1 386 14 15 DDR2 mDDR Memory Controller FIFO Block Diagram 387 14 16 DDR2 mDDR Memor...

Page 31: ... 444 15 16 Multiphase channel Interleaved PWM Example Using 3 eCAP Modules 447 15 17 Time Stamp Counter Register TSCTR 449 15 18 Counter Phase Control Register CTRPHS 450 15 19 Capture 1 Register CAP1 450 15 20 Capture 2 Register CAP2 451 15 21 Capture 3 Register CAP3 451 15 22 Capture 4 Register CAP4 452 15 23 ECAP Control Register 1 ECCTL1 452 15 24 ECAP Control Register 2 ECCTL2 454 15 25 ECAP ...

Page 32: ... Duty 100 506 16 31 PWM Chopper Submodule 507 16 32 PWM Chopper Submodule Signals and Registers 508 16 33 Simple PWM Chopper Submodule Waveforms Showing Chopping Action Only 509 16 34 PWM Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses 509 16 35 PWM Chopper Submodule Waveforms Showing the Pulse Width Duty Cycle Control of Sustaining Pulses 510 16 36 Trip Zone S...

Page 33: ... Band Generator Control Register DBCTL 562 16 78 Dead Band Generator Rising Edge Delay Register DBRED 563 16 79 Dead Band Generator Falling Edge Delay Register DBFED 563 16 80 PWM Chopper Control Register PCCTL 564 16 81 Trip Zone Select Register TZSEL 565 16 82 Trip Zone Control Register TZCTL 566 16 83 Trip Zone Enable Interrupt Register TZEINT 566 16 84 Trip Zone Flag Register TZFLG 567 16 85 T...

Page 34: ...ock Transfer Example 639 17 34 Smaller Packet Data Transfers Example 640 17 35 Channel Options Parameter OPT 641 17 36 Channel Source Address Parameter SRC 643 17 37 A Count B Count Parameter A_B_CNT 643 17 38 Channel Destination Address Parameter DST 644 17 39 Source B Index Destination B Index Parameter SRC_DST_BIDX 644 17 40 Link Address B Count Reload Parameter LINK_BCNTRLD 645 17 41 Source C ...

Page 35: ...e Register ERREN 691 17 87 Error Clear Register ERRCLR 692 17 88 Error Details Register ERRDET 693 17 89 Error Interrupt Command Register ERRCMD 694 17 90 Read Command Rate Register RDRATE 695 17 91 Source Active Options Register SAOPT 696 17 92 Source Active Source Address Register SASRC 697 17 93 Source Active Count Register SACNT 697 17 94 Source Active Destination Address Register SADST 698 17...

Page 36: ...ister CnMISCSTAT 768 18 23 EMAC Control Module Interrupt Core 0 2 Receive Interrupts Per Millisecond Register CnRXIMAX 769 18 24 EMAC Control Module Interrupt Core 0 2 Transmit Interrupts Per Millisecond Register CnTXIMAX 770 18 25 MDIO Revision ID Register REVID 771 18 26 MDIO Control Register CONTROL 772 18 27 PHY Acknowledge Status Register ALIVE 773 18 28 PHY Link Status Register LINK 773 18 2...

Page 37: ...ation Control Register EMCONTROL 815 18 70 FIFO Control Register FIFOCONTROL 815 18 71 MAC Configuration Register MACCONFIG 816 18 72 Soft Reset Register SOFTRESET 816 18 73 MAC Source Address Low Bytes Register MACSRCADDRLO 817 18 74 MAC Source Address High Bytes Register MACSRCADDRHI 817 18 75 MAC Hash Address Register 1 MACHASH1 818 18 76 MAC Hash Address Register 2 MACHASH2 818 18 77 Back Off ...

Page 38: ...e Configuration Register AWCCR 899 19 33 SDRAM Configuration Register SDCR 901 19 34 SDRAM Refresh Control Register SDRCR 903 19 35 Asynchronous n Configuration Register CEnCFG 904 19 36 SDRAM Timing Register SDTIMR 906 19 37 SDRAM Self Refresh Exit Timing Register SDSRETR 907 19 38 EMIFA Interrupt Raw Register INTRAW 908 19 39 EMIFA Interrupt Mask Register INTMSK 909 19 40 EMIFA Interrupt Mask Se...

Page 39: ...2 and 3 Set Rise Trigger Register SET_RIS_TRIG23 944 20 31 GPIO Banks 4 and 5 Set Rise Trigger Register SET_RIS_TRIG45 944 20 32 GPIO Banks 6 and 7 Set Rise Trigger Register SET_RIS_TRIG67 944 20 33 GPIO Bank 8 Set Rise Trigger Register SET_RIS_TRIG8 945 20 34 GPIO Banks 0 and 1 Clear Rise Trigger Register CLR_RIS_TRIG01 946 20 35 GPIO Banks 2 and 3 Clear Rise Trigger Register CLR_RIS_TRIG23 946 2...

Page 40: ... Emulation Management Register PWREMU_MGMT 979 21 19 GPIO Enable Register GPIO_EN 980 21 20 GPIO Direction 1 Register GPIO_DIR1 981 21 21 GPIO Data 1 Register GPIO_DAT1 981 21 22 GPIO Direction 2 Register GPIO_DIR2 982 21 23 GPIO Data 2 Register GPIO_DAT2 983 21 24 Host Port Interface Control Register HPIC Host Access Permissions 984 21 25 Host Port Interface Control Register HPIC CPU Access Permi...

Page 41: ...BPP 1040 23 7 16 BPP Data Memory Organization TFT Mode Only Little Endian 1040 23 8 12 BPP Data Memory Organization Little Endian 1041 23 9 8 BPP Data Memory Organization 1041 23 10 4 BPP Data Memory Organization 1041 23 11 2 BPP Data Memory Organization 1042 23 12 1 BPP Data Memory Organization 1042 23 13 Monochrome and Color Output 1044 23 14 Raster Mode Display Format 1045 23 15 LCD Revision Id...

Page 42: ... and Slot 1089 24 13 Bit Order and Word Alignment Within a Slot Examples 1090 24 14 Definition of Frame and Frame Sync Width 1091 24 15 Transmit Clock Generator Block Diagram 1093 24 16 Receive Clock Generator Block Diagram 1094 24 17 Frame Sync Generator Block Diagram 1095 24 18 Individual Serializer and Connections Within McASP 1096 24 19 Receive Format Unit 1097 24 20 Transmit Format Unit 1098 ...

Page 43: ...e Sync Control Register AFSXCTL 1174 24 62 Transmit Clock Control Register ACLKXCTL 1175 24 63 Transmit High Frequency Clock Control Register AHCLKXCTL 1176 24 64 Transmit TDM Time Slot Register XTDM 1177 24 65 Transmitter Interrupt Control Register XINTCTL 1178 24 66 Transmitter Status Register XSTAT 1179 24 67 Current Transmit TDM Time Slot Register XSLOT 1180 24 68 Transmit Clock Check Control ...

Page 44: ...19 25 30 Decision Tree Response to Transmit Frame Synchronization Pulse 1221 25 31 Unexpected Transmit Frame Synchronization Pulse 1221 25 32 McBSP Buffer FIFO BFIFO Block Diagram 1222 25 33 Companding Flow 1224 25 34 Companding Data Formats 1224 25 35 Transmit Data Companding Format in DXR 1224 25 36 Companding of Internal Data 1225 25 37 DX Timing for Multichannel Operation 1227 25 38 Alternatin...

Page 45: ...0 MMC Status Register 1 MMCST1 1301 26 21 MMC Interrupt Mask Register MMCIM 1302 26 22 MMC Response Time Out Register MMCTOR 1304 26 23 MMC Data Read Time Out Register MMCTOD 1305 26 24 MMC Block Length Register MMCBLEN 1306 26 25 MMC Number of Blocks Register MMCNBLK 1307 26 26 MMC Number of Blocks Counter Register MMCNBLC 1307 26 27 MMC Data Receive Register MMCDRR 1308 26 28 MMC Data Transmit R...

Page 46: ...cing Control Register CCC_CTL 1379 28 7 Command Completion Coalescing Ports Register CCC_PORTS 1380 28 8 BIST Active FIS Register BISTAFR 1381 28 9 BIST Control Register BISTCR 1382 28 10 BIST FIS Count Register BISTFCTR 1384 28 11 BIST Status Register BISTSR 1384 28 12 BIST DWORD Error Count Register BISTDECR 1385 28 13 BIST DWORD Error Count Register TIMER1MS 1385 28 14 Global Parameter 1 Regist...

Page 47: ...18 SPI Global Control Register 0 SPIGCR0 1441 29 19 SPI Global Control Register 1 SPIGCR1 1442 29 20 SPI Interrupt Register SPIINT0 1444 29 21 SPI Interrupt Level Register SPILVL 1446 29 22 SPI Flag Register SPIFLG 1447 29 23 SPI Pin Control Register 0 SPIPC0 1449 29 24 SPI Pin Control Register 1 SPIPC1 1450 29 25 SPI Pin Control Register 2 SPIPC2 1451 29 26 SPI Pin Control Register 3 SPIPC3 1452 ...

Page 48: ...Timer Capture Register 34 CAP34 1498 30 28 Timer Interrupt Control and Status Register INTCTLSTAT 1499 30 29 Timer Compare Register CMPn 1500 31 1 UART Block Diagram 1503 31 2 UART Clock Generation Diagram 1504 31 3 Relationships Between Data Bit BCLK and UART Input Clock 1505 31 4 UART Protocol Formats 1507 31 5 UART Interface Using Autoflow Diagram 1510 31 6 Autoflow Functional Timing Waveforms ...

Page 49: ...8 32 20 uPP Interface Configuration Register UPICR 1560 32 21 uPP Interface Idle Value Register UPIVR 1562 32 22 uPP Threshold Configuration Register UPTCR 1563 32 23 uPP Interrupt Raw Status Register UPISR 1564 32 24 uPP Interrupt Enabled Status Register UPIER 1566 32 25 uPP Interrupt Enable Set Register UPIES 1568 32 26 uPP Interrupt Enable Clear Register UPIEC 1570 32 27 uPP End of Interrupt Re...

Page 50: ...620 34 7 IDLE Mode Flow Chart 1621 34 8 TX Mode Flow Chart 1622 34 9 RX Mode Flow Chart 1623 34 10 Setup Phase of a Control Transaction Flow Chart 1633 34 11 IN Data Phase Flow Chart 1635 34 12 OUT Data Phase Flow Chart 1637 34 13 Completion of SETUP or OUT Data Phase Flow Chart 1639 34 14 Completion of IN Data Phase Flow Chart 1641 34 15 USB Controller Block Diagram 1648 34 16 Host Packet Descrip...

Page 51: ... Host Transmit Endpoint TXMAXP 1717 34 59 Control Status Register for Endpoint 0 in Peripheral Mode PERI_CSR0 1718 34 60 Control Status Register for Endpoint 0 in Host Mode HOST_CSR0 1719 34 61 Control Status Register for Peripheral Transmit Endpoint PERI_TXCSR 1720 34 62 Control Status Register for Host Transmit Endpoint HOST_TXCSR 1721 34 63 Maximum Packet Size for Peripheral Host Receive Endpoi...

Page 52: ...2 1749 34 106 Queue Manager Free Descriptor Buffer Starvation Count Register 3 FDBSC3 1750 34 107 Queue Manager Linking RAM Region 0 Base Address Register LRAM0BASE 1750 34 108 Queue Manager Linking RAM Region 0 Size Register LRAM0SIZE 1751 34 109 Queue Manager Linking RAM Region 1 Base Address Register LRAM1BASE 1751 34 110 Queue Manager Queue Pending Register 0 PEND0 1752 34 111 Queue Manager Qu...

Page 53: ...m Field Vertical Ancillary Data Buffer Start Address Register CnBVANC 1803 35 38 Channel n Image Address Offset Register CnIMGOFFSET 1804 35 39 Channel n Horizontal Ancillary Address Offset Register CnHANCOFFSET 1804 35 40 Channel n Horizontal Size Configuration Register CnHCFG 1805 35 41 Channel n Vertical Size Configuration 0 Register CnVCFG0 1806 35 42 Channel n Vertical Data Size Configuration...

Page 54: ...nd Address Register PROGn_MPEAR Field Descriptions 111 5 18 MPU2 Programmable Range n End Address Register PROGn_MPEAR Field Descriptions 111 5 19 Programmable Range Memory Protection Page Attributes Register PROGn_MPPA Field Descriptions 112 5 20 Fault Address Register FLTADDRR Field Descriptions 113 5 21 Fault Status Register FLTSTAT Field Descriptions 114 5 22 Fault Clear Register FLTCLR Field ...

Page 55: ...d Descriptions 157 7 35 PLLC0 Clock Status Register CKSTAT Field Descriptions 158 7 36 PLLC1 Clock Status Register CKSTAT Field Descriptions 159 7 37 PLLC0 SYSCLK Status Register SYSTAT Field Descriptions 160 7 38 PLLC1 SYSCLK Status Register SYSTAT Field Descriptions 161 7 39 Emulation Performance Counter 0 Register EMUCNT0 Field Descriptions 162 7 40 Emulation Performance Counter 1 Register EMUC...

Page 56: ... Multiplexing Control 0 Register PINMUX0 Field Descriptions 221 10 23 Pin Multiplexing Control 1 Register PINMUX1 Field Descriptions 223 10 24 Pin Multiplexing Control 2 Register PINMUX2 Field Descriptions 225 10 25 Pin Multiplexing Control 3 Register PINMUX3 Field Descriptions 227 10 26 Pin Multiplexing Control 4 Register PINMUX4 Field Descriptions 229 10 27 Pin Multiplexing Control 5 Register PI...

Page 57: ...e Register VBR Field Descriptions 297 11 14 Vector Size Register VSR Field Descriptions 297 11 15 Vector Null Register VNR Field Descriptions 298 11 16 Global Prioritized Index Register GPIR Field Descriptions 298 11 17 Global Prioritized Vector Register GPVR Field Descriptions 299 11 18 System Interrupt Status Raw Set Register 1 SRSR1 Field Descriptions 299 11 19 System Interrupt Status Raw Set R...

Page 58: ...and Branch Register Op2 334 13 20 Format 4b Quick Arithmetic Test and Branch Immediate Op2 335 13 21 Format 5a Quick Bit Test and Branch Register Op2 336 13 22 Format 5b Quick Bit Test and Branch Immediate Op2 337 13 23 Format 6a LBBO SBBO Register Offset 338 13 24 Format 6b LBBO SBBO Immediate Offset 339 13 25 Format 6c LBCO SBCO Register Offset 340 13 26 Format 6d LBCO SBCO Immediate Offset 341 ...

Page 59: ...68 STATESETINT0 Register 361 13 69 STATESETINT0 Register Field Descriptions 361 13 70 STATESETINT1 Register 361 13 71 STATESETINT1 Register Field Descriptions 361 13 72 STATCLRINT0 Register 361 13 73 STATCLRINT0 Register Field Descriptions 361 13 74 STATCLRINT1 Register 362 13 75 STATCLRINT1 Register Field Descriptions 362 13 76 ENABLESET0 Register 362 13 77 ENABLESET0 Register Field Descriptions ...

Page 60: ...DRPYC1R Configuration 402 14 21 DDR2 mDDR Memory Controller Registers 403 14 22 Revision ID Register REVID Field Descriptions 403 14 23 SDRAM Status Register SDRSTAT Field Descriptions 404 14 24 SDRAM Configuration Register SDCR Field Descriptions 405 14 25 SDRAM Refresh Control Register SDRCR Field Descriptions 408 14 26 SDRAM Timing Register 1 SDTIMR1 Field Descriptions 409 14 27 SDRAM Timing Re...

Page 61: ...trol Register 1 ECCTL1 Field Descriptions 452 15 21 ECAP Control Register 2 ECCTL2 Field Descriptions 454 15 22 ECAP Interrupt Enable Register ECEINT Field Descriptions 456 15 23 ECAP Interrupt Flag Register ECFLG Field Descriptions 457 15 24 ECAP Interrupt Clear Register ECCLR Field Descriptions 458 15 25 ECAP Interrupt Forcing Register ECFRC Field Descriptions 459 15 26 Revision ID Register REVI...

Page 62: ...me Base Status Register TBSTS Field Descriptions 552 16 54 Time Base Phase Register TBPHS Field Descriptions 553 16 55 Time Base Counter Register TBCNT Field Descriptions 553 16 56 Time Base Period Register TBPRD Field Descriptions 554 16 57 Counter Compare Submodule Registers 554 16 58 Counter Compare Control Register CMPCTL Field Descriptions 555 16 59 Counter Compare A Register CMPA Field Descr...

Page 63: ...t Mapping 608 17 11 Number of Interrupts 608 17 12 EDMA3 Transfer Controller Configurations 615 17 13 Read Write Command Optimization Rules 621 17 14 EDMA3 Channel Controller EDMA3CC Parameter RAM PaRAM Entries 640 17 15 Channel Options Parameters OPT Field Descriptions 641 17 16 Channel Source Address Parameter SRC Field Descriptions 643 17 17 A Count B Count Parameter A_B_CNT Field Descriptions ...

Page 64: ...CR Field Descriptions 683 17 61 QDMA Event Enable Set Register QEESR Field Descriptions 683 17 62 QDMA Secondary Event Register QSER Field Descriptions 684 17 63 QDMA Secondary Event Clear Register QSECR Field Descriptions 685 17 64 EDMA3 Transfer Controller EDMA3TC Registers 686 17 65 Revision ID Register REVID Field Descriptions 687 17 66 EDMA3TC Configuration Register TCCFG Field Descriptions 6...

Page 65: ...odule Interrupt Core 0 2 Receive Interrupt Status Register CnRXSTAT 766 18 18 EMAC Control Module Interrupt Core 0 2 Transmit Interrupt Status Register CnTXSTAT 767 18 19 EMAC Control Module Interrupt Core 0 2 Miscellaneous Interrupt Status Register CnMISCSTAT 768 18 20 EMAC Control Module Interrupt Core 0 2 Receive Interrupts Per Millisecond Register CnRXIMAX 769 18 21 EMAC Control Module Interru...

Page 66: ...808 18 62 Receive Buffer Offset Register RXBUFFEROFFSET Field Descriptions 808 18 63 Receive Filter Low Priority Frame Threshold Register RXFILTERLOWTHRESH Field Descriptions 809 18 64 Receive Channel n Flow Control Threshold Register RXnFLOWTHRESH Field Descriptions 809 18 65 Receive Channel n Free Buffer Count Register RXnFREEBUFFER Field Descriptions 810 18 66 MAC Control Register MACCONTROL Fi...

Page 67: ... Fields 871 19 26 SR Field Value For the EMIFA to K4S641632H TC L 70 Interface 876 19 27 SDTIMR Field Calculations for the EMIFA to K4S641632H TC L 70 Interface 878 19 28 RR Calculation for the EMIFA to K4S641632H TC L 70 Interface 879 19 29 RR Calculation for the EMIFA to K4S641632H TC L 70 Interface 879 19 30 SDCR Field Values For the EMIFA to K4S641632H TC L 70 Interface 880 19 31 EMIFA Input T...

Page 68: ...20 3 Revision ID Register REVID Field Descriptions 932 20 4 GPIO Interrupt Per Bank Enable Register BINTEN Field Descriptions 933 20 5 GPIO Direction Register DIRn Field Descriptions 935 20 6 GPIO Output Data Register OUT_DATAn Field Descriptions 937 20 7 GPIO Set Data Register SET_DATAn Field Descriptions 939 20 8 GPIO Clear Data Register CLR_DATAn Field Descriptions 941 20 9 GPIO Input Data Regi...

Page 69: ...iptions 1021 22 23 I2C Pin Function Register ICPFUNC Field Descriptions 1022 22 24 I2C Pin Direction Register ICPDIR Field Descriptions 1023 22 25 I2C Pin Data In Register ICPDIN Field Descriptions 1024 22 26 I2C Pin Data Out Register ICPDOUT Field Descriptions 1025 22 27 I2C Pin Data Set Register ICPDSET Field Descriptions 1026 22 28 I2C Pin Data Clear Register ICPDCLR Field Descriptions 1027 23 ...

Page 70: ...s 1155 24 20 Digital Mode Control Register DITCTL Field Descriptions 1156 24 21 Receiver Global Control Register RGBLCTL Field Descriptions 1157 24 22 Receive Format Unit Bit Mask Register RMASK Field Descriptions 1158 24 23 Receive Bit Stream Format Register RFMT Field Descriptions 1159 24 24 Receive Frame Sync Control Register AFSRCTL Field Descriptions 1161 24 25 Receive Clock Control Register ...

Page 71: ... 1230 25 16 Transmit Channel Assignment and Control When Eight Transmit Partitions are Used 1230 25 17 Selecting a Transmit Multichannel Selection Mode With the XMCM Bits 1231 25 18 Reset State of McBSP Pins 1234 25 19 Receiver Clock and Frame Configurations 1235 25 20 Transmitter Clock and Frame Configurations 1235 25 21 McBSP Emulation Modes Selectable With the FREE and SOFT Bits of SPCR 1241 25...

Page 72: ...ter SDIOCTL Field Descriptions 1315 26 26 SDIO Status Register 0 SDIOST0 Field Descriptions 1316 26 27 SDIO Interrupt Enable Register SDIOIEN Field Descriptions 1317 26 28 SDIO Interrupt Status Register SDIOIST Field Descriptions 1317 26 29 MMC FIFO Control Register MMCFIFOCTL Field Descriptions 1318 27 1 Real Time Clock Signals 1321 27 2 Real Time Clock RTC Registers 1327 27 3 Second Register SEC...

Page 73: ...ister IDR Field Description 1390 28 24 Port Command List Base Address Register P0CLB Field Description 1391 28 25 Port FIS Base Address Register P0FB Field Description 1391 28 26 Port Interrupt Status Register P0IS Field Descriptions 1392 28 27 Port Interrupt Enable Register P0IE Field Descriptions 1394 28 28 Port Command Register P0CMD Field Descriptions 1395 28 29 Port Task File Data Register P0...

Page 74: ...e and Clock Modes 1484 30 7 Timer Emulation Modes Selection 1486 30 8 Timer Registers 1486 30 9 Revision ID Register REVID Field Descriptions 1488 30 10 Emulation Management Register EMUMGT Field Descriptions 1488 30 11 GPIO Interrupt Control and Enable Register GPINTGPEN Field Descriptions 1489 30 12 GPIO Data and Direction Register GPDATGPDIR Field Descriptions 1490 30 13 Timer Counter Register ...

Page 75: ...7 32 7 Basic Operating Mode Selection 1549 32 8 Sample uPP Parameters for Duplex Mode 0 1550 32 9 uPP Parameters Useful for System Tuning 1551 32 10 uPP Registers 1555 32 11 uPP Peripheral Identification Register UPPID Field Descriptions 1555 32 12 uPP Peripheral Control Register UPPCR Field Descriptions 1556 32 13 uPP Digital Loopback Register UPDLB Field Descriptions 1557 32 14 uPP Channel Contr...

Page 76: ...eld Descriptions 1598 33 19 HC Low Speed Threshold Register HCLSTHRESHOLD Field Descriptions 1598 33 20 HC Root Hub A Register HCRHDESCRIPTORA Field Descriptions 1599 33 21 HC Root Hub B Register HCRHDESCRIPTORB Field Descriptions 1600 33 22 HC Root Hub Status Register HCRHSTATUS Field Descriptions 1601 33 23 HC Port 1 Status and Control Register HCRHPORTSTATUS1 Field Descriptions 1602 33 24 HC Po...

Page 77: ...34 50 Generic RNDIS EP4 Size Register GENRNDISSZ4 Field Descriptions 1709 34 51 Function Address Register FADDR Field Descriptions 1709 34 52 Power Management Register POWER Field Descriptions 1710 34 53 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 INTRTX Field Descriptions 1711 34 54 Interrupt Register for Receive Endpoints 1 to 4 INTRRX Field Descriptions 1712 34 55 Interrupt...

Page 78: ...gister TDFDQ Field Descriptions 1739 34 98 CDMA Emulation Control Register DMAEMU Field Descriptions 1740 34 99 CDMA Transmit Channel n Global Configuration Registers TXGCR n Field Descriptions 1740 34 100 CDMA Receive Channel n Global Configuration Registers RXGCR n Field Descriptions 1741 34 101 Receive Channel n Host Packet Configuration Registers A RXHPCRA n Field Descriptions 1742 34 102 Rece...

Page 79: ...ter CnTVANC Field Descriptions 1803 35 25 Channel n Bottom Field Vertical Ancillary Data Buffer Start Address Register CnBVANC Field Descriptions 1803 35 26 Channel n Image Address Offset Register CnIMGOFFSET Field Descriptions 1804 35 27 Channel n Horizontal Ancillary Address Offset Register CnHANCOFFSET Field Descriptions 1804 35 28 Channel n Horizontal Size Configuration Register CnHCFG Field D...

Page 80: ...sists of the following primary components ARM subsystem and associated memories A set of I O peripherals Notational Conventions This document uses the following conventions Hexadecimal numbers are shown with the suffix h For example the following number is 40 hexadecimal decimal 64 40h Registers in this document are shown in figures and described in tables Each register figure shows a rectangle di...

Page 81: ...evised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Overview Chapter 1 SPRUH82C April 2013 Revised September 2016 Overview Topic Page 1 1 Introduction 82 1 2 ARM Subsystem 82 ...

Page 82: ...uction The AM1808 AM1810 ARM microprocessor contains an ARM RISC CPU for general purpose processing and systems control The AM1808 AM1810 ARM microprocessor consists of the following primary components ARM subsystem and associated memories A set of I O peripherals A powerful DMA subsystem and SDRAM EMIF interface Block Diagram A block diagram for the AM1808 AM1810 ARM microprocessor is shown in Fi...

Page 83: ...orporated ARM Subsystem Chapter 2 SPRUH82C April 2013 Revised September 2016 ARM Subsystem Topic Page 2 1 Introduction 84 2 2 Operating States Modes 85 2 3 Processor Status Registers 85 2 4 Exceptions and Exception Vectors 86 2 5 The 16 BIS 32 BIS Concept 87 2 6 16 BIS 32 BIS Advantages 87 2 7 Co Processor 15 CP15 88 ...

Page 84: ... all important The ARM926EJ S processor supports the 32 bit ARM and the 16 bit THUMB instruction sets enabling you to trade off between high performance and high code density This includes features for efficient execution of Java byte codes and providing Java performance similar to Just in Time JIT Java interpreter without associated code overhead The ARM926EJ S processor supports the ARM debug ar...

Page 85: ...An FIQ interrupt causes the processor to enter the FIQ mode Different stacks must be set up for different modes The stack pointer SP automatically changes to the SP of the mode that was entered 2 3 Processor Status Registers The processor status register PSR controls the enabling and disabling of interrupts and setting the mode of operation of the processor The 8 least significant bits PSR 7 0 are...

Page 86: ...t priority to lowest priority are reset data abort FIQ IRQ pre fetch abort undefined instruction and SWI SWI and undefined instruction have the same priority The ARM is configured with the VINITHI signal set high VINITHI 1 such that the vector table is located at address FFFF 0000h This address maps to the beginning of the ARM local RAM 8 KB NOTE The VINITHI signal is configurable by way of the re...

Page 87: ...uctions and to address a large address space efficiently When processing 32 bit data a 16 bit architecture takes at least two instructions to perform the same task as a single 32 bit instruction However not all of the code in a program processes 32 bit data for example code that performs character string handling and some instructions like branches do not process any data at all If a 16 bit archit...

Page 88: ...urned to the ARM9EJ S core If the protection check carried out by the MMU on the MVA does not abort and the MVA tag is not in the cache then the MMU translates the MVA to produce the PA NOTE See the Programmers Model of the ARM926EJ S Technical Reference Manual TRM downloadable from http infocenter arm com help index jsp for more detailed information 2 7 2 Memory Management Unit MMU The ARM926EJ S...

Page 89: ...Virtual Address TAG stored in the TAG RAM This means that the MMU is not involved in Dcache write back operations removing the possibility of TLB misses related to the write back address Cache maintenance operations to provide efficient invalidation of the following The entire Dcache or Icache Regions of the Dcache or Icache The entire Dcache Regions of virtual memory They also provide operations ...

Page 90: ... Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated System Interconnect Chapter 3 SPRUH82C April 2013 Revised September 2016 System Interconnect Topic Page 3 1 Introduction 91 3 2 System Interconnect Block Diagram 92 ...

Page 91: ...do not rely on the EDMA3 or on a CPU to perform transfers to and from them The system master peripherals include the ARM the EDMA3 transfer controllers EMAC HPI LCDC PRU subsystems USBs uPP SATA and VPIF Not all master peripherals may connect to all slave peripherals The supported connections are designated by an X in Table 3 1 1 Peripheral group SYSCFG EMAC eCAP0 eCAP1 eCAP2 eHRPWM0 eHRPWM1 GPIO ...

Page 92: ...RAM SCR4 MMC SD0 SPI0 UART0 EDMA3_0_TC0 EDMA3_0_TC1 SCR F5 EDMA3_1_CC0 EDMA3_1_TC0 USB0 Cfg HPI LCDC EDMA3_1_CC0 uPP VPIF SATA MMC SD1 BR F3 SCR F6 SYSCFG1 EMAC EMAC MDIO USB1 Cfg GPIO PSC1 I2C1 PLLC1 Clock Domain SYSCLK4 CPU 4 Synchronous BR F4 BR F5 SCR F7 McBSP0 McBSP1 UART1 UART2 McASP0 SCR F8 eHRPWM0 eHRPWM1 Timer64P2 Timer64P3 eCAP0 eCAP1 eCAP2 SPI1 Async 3 PLL1 Clock Domain Clock Domain SYS...

Page 93: ...er 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated System Memory Chapter 4 SPRUH82C April 2013 Revised September 2016 System Memory Topic Page 4 1 Introduction 94 4 2 ARM Memories 94 4 3 Peripherals 94 ...

Page 94: ...chip RAM is accessible by the ARM and is also accessible by several master peripherals Writes to this RAM by all masters is atomic External Memories This device has two external memory interfaces that provide multiple external memory options accessible by the CPU and master peripherals EMIF 8 16 bit wide package dependent asynchronous EMIF module that supports asynchronous devices such as ASRAM NA...

Page 95: ... Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Memory Protection Unit MPU Chapter 5 SPRUH82C April 2013 Revised September 2016 Memory Protection Unit MPU Topic Page 5 1 Introduction 96 5 2 Architecture 97 5 3 MPU Registers 102 ...

Page 96: ...rammable address ranges Supports 0 or 1 fixed range Supports read write and execute access privileges Supports privilege ID associations with ranges Generates an interrupt when there is a protection violation and saves violating transfer parameters Supports protection of its own registers 5 1 3 Block Diagram Figure 5 1 shows a block diagram of the MPU An access to a protected memory must pass thro...

Page 97: ...ss determines what level of permissions the originator of the memory access might have Two privilege levels are supported supervisor and user Supervisor level is generally granted access to peripheral registers and the memory protection configuration User level is generally confined to the memory spaces that the OS specifically designates for its use ARM CPU instruction and data accesses have a pr...

Page 98: ... range must be protected in order to prevent unintended disallowed aliased access to protected memory One of the programmable address ranges could be used to detect accesses to this unpopulated memory The MPU divides its assigned memory into address ranges Each MPU can support one fixed address range and multiple programmable address ranges The fixed address range is configured to an exact address...

Page 99: ...emory protection page attribute registers MPPA AID0 through AID11 are used to specify the allowed privilege IDs An additional allowed ID bit AIDX captures access made by all privilege IDs not covered by AID0 through AID11 When set to 1 the AID bit grants access to the corresponding ID When cleared to 0 the AID bit denies access to the corresponding requestor 5 2 3 2 Request Type Based Permissions ...

Page 100: ...ore if a transfer matches 2 ranges one that is RW and one that is RX then the final permission is just R 5 2 5 MPU Register Protection Access to the range start and end address registers MPSAR and MPEAR and memory protection page attribute registers MPPA is also protected All non debug writes must be by a supervisor entity A protection fault can occur from a register write with invalid permissions...

Page 101: ...isters The transfer parameters that caused the violation are saved in the MPU registers 5 2 8 2 Interrupt Multiplexing The interrupts from both MPUs are combined with the boot configuration module into a single interrupt called MPU_BOOTCFG_ERR The combined interrupt is routed to the ARM interrupt controller Table 5 5 shows the interrupt sources that are combined to make MPU_BOOTCFG_ERR Table 5 5 M...

Page 102: ... 01E1 4228h PROG3_MPPA Programmable range 3 memory protection page attributes register Section 5 3 12 01E1 4230h PROG4_MPSAR Programmable range 4 start address register Section 5 3 10 1 01E1 4234h PROG4_MPEAR Programmable range 4 end address register Section 5 3 11 1 01E1 4238h PROG4_MPPA Programmable range 4 memory protection page attributes register Section 5 3 12 01E1 4240h PROG5_MPSAR Programm...

Page 103: ...ble range 6 end address register Section 5 3 11 2 01E1 5258h PROG6_MPPA Programmable range 6 memory protection page attributes register Section 5 3 12 01E1 5260h PROG7_MPSAR Programmable range 7 start address register Section 5 3 10 2 01E1 5274h PROG7_MPEAR Programmable range 7 end address register Section 5 3 11 2 01E1 5268h PROG7_MPPA Programmable range 7 memory protection page attributes regist...

Page 104: ... all AIDs may be supported on your device Unsupported AIDs should be cleared to 0 in the memory page protection attributes registers MPPA See for a list of AIDs supported on your device 1 For MPU1 2 For MPU2 Figure 5 4 Configuration Register CONFIG 31 24 23 20 19 16 ADDR_WIDTH NUM_FIXED NUM_PROG R 0 1 or 6h 2 R 0 1 or 1 2 R 6h 1 or Ch 2 15 12 11 1 0 NUM_AIDS Reserved ASSUME_ALLOWED R Ch R 0 R 1 LE...

Page 105: ...The IRAWSTAT is shown in Figure 5 5 and described in Table 5 10 Figure 5 5 Interrupt Raw Status Set Register IRAWSTAT 31 16 Reserved R 0 15 2 1 0 ADDRERR PROTERR R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 5 10 Interrupt Raw Status Set Register IRAWSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 ADDRERR Address violation error Reading ...

Page 106: ... Figure 5 6 Interrupt Enable Status Clear Register IENSTAT 31 16 Reserved R 0 15 2 1 0 ADDRERR PROTERR R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 5 11 Interrupt Enable Status Clear Register IENSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 ADDRERR Address violation error If the interrupt is enabled reading this bit reflects the statu...

Page 107: ...iolation error enable 0 Writing 0 has no effect 1 Interrupt is enabled 0 PROTERR_EN Protection violation error enable 0 Writing 0 has no effect 1 Interrupt is enabled 5 3 6 Interrupt Enable Clear Register IENCLR Reading the interrupt enable clear register IENCLR returns the interrupts that are enabled Software can write to IENCLR to clear disable an interrupt Writes of 0 have no effect The IENCLR ...

Page 108: ...register FXD_MPEAR which instead read as 0 The FXD_MPSAR is shown in Figure 5 9 Figure 5 9 Fixed Range Start Address Register FXD_MPSAR 31 0 Reserved R 0 LEGEND R Read only n value after reset 5 3 8 Fixed Range End Address Register FXD_MPEAR The fixed range end address register FXD_MPEAR holds the end address for the fixed range The fixed address range manages access to the DDR2 mDDR SDRAM control...

Page 109: ...R W 1 R W 1 R W 1 R W 1 R W 1 R 0 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 LEGEND R W Read Write R Read only n value after reset Table 5 14 Fixed Range Memory Protection Page Attributes Register FXD_MPPA Field Descriptions Bit Field Value Description 31 26 Reserved 0 Reserved 25 22 Reserved Fh Reserved 21 10 AIDn Controls access from ID n 0 Access is denied 1 Access is granted 9 AIDX Contro...

Page 110: ...e width of the address field in PROGn_MPSAR and the programmable range n end address register PROGn_MPEAR For example to protect a 64 KB page starting at byte address 8001 0000h write 8001 0000h to PROGn_MPSAR and 8001 FFFFh to PROGn_MPEAR 5 3 10 1 MPU1 Programmable Range n Start Address Register PROG1_MPSAR PROG6_MPSAR The PROGn_MPSAR for MPU1 is shown in Figure 5 12 and described in Table 5 15 F...

Page 111: ...Programmable Range n End Address Register PROG1_MPEAR PROG6_MPEAR The PROGn_MPEAR for MPU1 is shown in Figure 5 14 and described in Table 5 17 Figure 5 14 MPU1 Programmable Range n End Address Register PROGn_MPEAR 31 10 9 0 END_ADDR Reserved R W 20 007Fh R 3FFh LEGEND R W Read Write R Read only n value after reset Table 5 17 MPU1 Programmable Range n End Address Register PROGn_MPEAR Field Descript...

Page 112: ... W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R 0 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 LEGEND R W Read Write R Read only n value after reset Table 5 19 Programmable Range Memory Protection Page Attributes Register PROGn_MPPA Field Descriptions Bit Field Value Description 31 26 Reserved 0 Reserved 25 22 Reserved Fh Reserved 21 10 AIDn Controls access from ID n 0 Access is denied 1 Access is g...

Page 113: ...er FLTADDRR The fault address register FLTADDRR holds the address of the first protection fault transfer The FLTADDRR is shown in Figure 5 17 and described in Table 5 20 Figure 5 17 Fault Address Register FLTADDRR 31 0 FLTADDR R 0 LEGEND R Read only n value after reset Table 5 20 Fault Address Register FLTADDRR Field Descriptions Bit Field Value Description 31 0 FLTADDR 0 FFFF FFFFh Memory address...

Page 114: ...END R Read only n value after reset Table 5 21 Fault Status Register FLTSTAT Field Descriptions Bit Field Value Description 31 24 Reserved 0 Reserved 23 16 MSTID 0 FFh Master ID of fault transfer 15 13 Reserved 0 Reserved 12 9 PRIVID 0 Fh Privilege ID of fault transfer 8 6 Reserved 0 Reserved 5 0 TYPE 0 3Fh Fault type The TYPE bit field is cleared when a 1 is written to the CLEAR bit in the fault ...

Page 115: ...ster FLTSTAT as well as produce an interrupt Only the TYPE bit field in FLTSTAT is cleared when a 1 is written to the CLEAR bit The FLTCLR is shown in Figure 5 19 and described in Table 5 22 Figure 5 19 Fault Clear Register FLTCLR 31 16 Reserved R 0 15 1 0 Reserved CLEAR R 0 W 0 LEGEND R Read only W Write only n value after reset Table 5 22 Fault Clear Register FLTCLR Field Descriptions Bit Field ...

Page 116: ...ubmit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Device Clocking Chapter 6 SPRUH82C April 2013 Revised September 2016 Device Clocking Topic Page 6 1 Overview 117 6 2 Frequency Flexibility 119 6 3 Peripheral Clocking 120 ...

Page 117: ...ot require a fixed ratio to the ARM these are PLL0_SYSCLK3 and PLL0_SYSCLK7 Figure 6 1 shows the clocking architecture Table 6 1 Device Clock Inputs Peripheral Input Clock Signal Name Oscillator PLL OSCIN RTC RTC_XI JTAG TCK RTCK EMAC RMII RMII_MHZ_50_CLK EMAC MII MII_TXCLK MII_RXCLK USB2 0 and USB1 1 USB_REFCLKIN I2Cs I2Cn_SCL Timers TM64Pn_IN12 SATA SATA_REFCLKP SATA_REFCLKN SPIs SPIn_CLK uPP UP...

Page 118: ... 2 CLKSRC DDR2 mDDR VPIF PLL1 Controller A A B C D E F PRU 1 0 CFGCHIP3 EMA_CLKSRC 1 0 CFGCHIP3 ASYNC3_CLKSRC PLL Ref CLK Overview www ti com 118 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Device Clocking Figure 6 1 Overall Clocking Diagram A See Section 6 3 1 for USB clocking B See Section 6 3 2 for DDR2 mDDR clockin...

Page 119: ...em clock domains support This flexibility does have limitations as follows OSCIN input frequency is limited to a supported range The output of the PLL Multiplier must be within the range specified in the device specific data manual The output of each PLLDIV block must be less than or equal to the maximum device frequency specified in the device specific data manual NOTE The above limitations are p...

Page 120: ...be selected when it is not possible such as when specific audio rates are required to operate the device at one of the allowed input frequencies to the USB2 0 subsystem The USB2 0 subsystem peripheral bus clock is sourced from PLL0_SYSCLK2 The USB1 1 subsystem requires both a 48 MHz CLK48 and a 12 MHz CLK12 clock input The 12 MHz clock is derived from the 48 MHz clock The 48 MHz clock required by ...

Page 121: ...N CLK48MHz output from USB2 0 PHY USB_REFCLKIN must be 12 24 48 19 2 38 4 13 26 20 or 40 MHz The PLL inside the USB2 0 PHY can be configured to accept any of these input clock frequencies 0 1 USB_REFCLKIN USB_REFCLKIN USB_REFCLKIN must be 48 MHz The PLL inside the USB2 0 PHY can be configured to accept this input clock frequency 1 0 PLL0_AUXCLK CLK48MHz output from USB2 0 PHY PLL0_AUXCLK must be 1...

Page 122: ...e following observations are made To achieve the maximum frequency 150 MHz supported by the DDR2 mDDR memory controller and the typical CPU frequency of 300 MHz the output of the PLL multiplier should be set to be 300 MHz and the DDR_CLK source should be set to PLL1_SYSCLK1 The frequency of the PLL1 direct output clock is fixed at the output frequency of the PLL1 multiplier block The PLLDIV1 block...

Page 123: ...re 6 3 DDR2 mDDR Memory Controller Clocking Diagram 1 See Section 6 2 for explanation of POSTDIV divider modes Table 6 5 DDR2 mDDR Memory Controller MCLK Frequencies OSCIN Frequency PLL1 Multiplier Register Setting PLL1 Multiplier Frequency PLL1 Post Divider Mode 1 PLL1 POSTDIV Output Frequency PLL1 PLLDIV1 Register Setting PLL1_SYSCLK1 MCLK 24 18h 600 MHz Div2 300 MHz 8000h 300 MHz 150 MHz 24 15h...

Page 124: ...typical frequency of 100 MHz supported by EMIFA and the typical CPU frequency of 300 MHz the output of the PLL multiplier should be set to 600 MHz and the EMA_CLK source should be set to PLL0_SYSCLK3 with the PLLDIV3 register set to 3 The frequency of the DIV4P5 clock is fixed at the output frequency of the PLL multiplier block divided by 4 5 The PLLDIV3 block that sets the divider ratio for PLL0_...

Page 125: ...hen the RMII interface is active the RMII 50 MHz reference clock is sourced either from an external clock on the RMII_MHZ_50_CLK pin or from PLL0_SYSCLK7 as shown in Figure 6 5 The PINMUX15_3_0 bits in the pin multiplexing control 15 register PINMUX15 of the System Configuration Module control this clock selection PINMUX15_3_0 0 enables sourcing of the 50 MHz reference clock from an external sourc...

Page 126: ...ain PLL configurations do not support a 50 MHz clock on PLL0_SYSCLK7 Table 6 7 EMAC Reference Clock Frequencies OSCIN Frequency PLL Multiplier Register Setting Multiplier Frequency Post Divider Mode 1 POSTDIV Output Frequency PLLDIV7 Register Setting PLL0_SYSCLK7 25 24 600 MHz Div2 300 MHz 5 50 MHz Div3 200 MHz 3 50 MHz Div4 150 MHz 2 50 MHz 25 18 450 MHz Div2 225 MHz Not Applicable 2 Div3 150 MHz...

Page 127: ...0_SYSCLK2 The transmit clock is sourced by three different clocks PLL0_SYSCLK2 default PLL1_SYSCLK2 or the externally driven UPP_2xTXCLK pin The transmit clock source is selected by the UPP_TX_CLKSRC and ASYNC3_CLKSRC bits in the chip configuration 3 register CFGCHIP3 of the System Configuration Module Table 6 8 lists the register values that select each of the three possible clock sources Regardl...

Page 128: ...SYSCLK2 by configuring the ASYNC3_CLKSRC bit in the chip configuration 3 register CFGCHIP3 of the System Configuration Module The transmit and receive clocks are sourced internally or externally by configuring the McASP clock control registers ACLKRCTL AHCLKRCTL ACLKXCTL and AHCLKXCTL If an external clock is driven into a high frequency master clock AHCLKX or AHCLKR the McASP module allows for a m...

Page 129: ...directly from the oscillator input Timer64P0 P1 I2C0 Synchronous Peripherals Synchronous peripherals have their frequencies derived from the ARM clock frequency The peripheral system clock frequency changes accordingly if the PLL0 frequency changes Most synchronous peripherals have internal dividers so they can generate their required clock frequencies MMC SDs PLL0_SYSCLK2 HPI PLL0_SYSCLK2 UART0 P...

Page 130: ...tion Feedback Copyright 2013 2016 Texas Instruments Incorporated Phase Locked Loop Controller PLLC Chapter 7 SPRUH82C April 2013 Revised September 2016 Phase Locked Loop Controller PLLC Topic Page 7 1 Introduction 131 7 2 PLL Controllers 131 7 3 PLLC Registers 136 ...

Page 131: ...peripherals including DDR2 mDDR and may generate clocks that are asynchronous to the PLL0 clocks PLL1 operations are software programmable through the PLL controller 1 PLLC1 registers Figure 7 1 shows the PLLC0 and PLLC1 architecture The PLL0 and PLL1 multipliers are controlled by their respective PLL multiplier control register PLLM The PLLM defaults to a multiplier value of 13h at power up which...

Page 132: ... 0 1 PLLCTL PLLEN PLLCTL CLKMODE POSTDIV PLLC0 OBSCLK CLKOUT Pin DIV4 5 OSCDIV PLL Controller 0 PLL Controller 1 SYSCLK2 SYSCLK3 SYSCLK1 OSCIN 14h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh SYSCLK1 SYSCLK2 SYSCLK3 SYSCLK4 SYSCLK5 SYSCLK6 SYSCLK7 PLLC1 OBSCLK OCSEL OCSRC 14h 17h 18h 19h SYSCLK1 SYSCLK2 SYSCLK3 OCSEL OCSRC OSCDIV PLLC1 OBSCLK DEEPSLEEP Enable PLL Controllers www ti com 132 SPRUH82C April 2013 ...

Page 133: ...s used the resulting clock will not have a 50 duty cycle Instead the duty cycle will be 44 4 The EMIFA uses PLL0_SYSCLK3 by default but can be configured to use a 4 5 divide down of PLL0_PLLOUT instead of PLL0_SYSCLK3 by programming the EMA_CLKSRC and DIV45PENA bits in the chip configuration 3 register CFGCHIP3 of the system configuration SYSCFG module 3 The ASYNC3 modules use PLL0_SYSCLK2 by defa...

Page 134: ...on from stopping modules when the module clocks are disabled For example the watchdog timer that runs on the PLL0_AUXCLK will stop if this PLL clock is unintentionally disabled The PLL lock bits are located within the system configuration SYSCFG module When set the PLL_MASTER_LOCK bit in the chip configuration 0 register CFGCHIP0 locks PLLC0 When set the PLL1_MASTER_LOCK bit in the chip configurat...

Page 135: ...LLSTAT to clear to 0 completion of divider change 7 Set the PLLRST bit in PLLCTL to 1 brings PLL out of reset 8 Wait for the PLL to lock See the device specific data manual for PLL lock time 9 Set the PLLEN bit in PLLCTL to 1 removes PLL from bypass mode 7 2 2 3 Changing PLL Multiplier If the PLL is not powered down PLLPWRDN bit in PLLCTL is cleared to 0 perform the following procedure to change t...

Page 136: ...ect Register Section 7 3 7 01C1 1110h PLLM PLLC0 PLL Multiplier Control Register Section 7 3 9 01C1 1114h PREDIV PLLC0 Pre Divider Control Register Section 7 3 10 01C1 1118h PLLDIV1 PLLC0 Divider 1 Register Section 7 3 11 01C1 111Ch PLLDIV2 PLLC0 Divider 2 Register Section 7 3 13 01C1 1120h PLLDIV3 PLLC0 Divider 3 Register Section 7 3 15 01C1 1124h OSCDIV PLLC0 Oscillator Divider 1 Register Sectio...

Page 137: ... A138h PLLCMD PLLC1 PLL Controller Command Register Section 7 3 24 01E1 A13Ch PLLSTAT PLLC1 PLL Controller Status Register Section 7 3 25 01E1 A140h ALNCTL PLLC1 Clock Align Control Register Section 7 3 27 01E1 A144h DCHANGE PLLC1 PLLDIV Ratio Change Status Register Section 7 3 29 01E1 A148h CKEN PLLC1 Clock Enable Control Register Section 7 3 31 01E1 A14Ch CKSTAT PLLC1 Clock Status Register Secti...

Page 138: ...f multiple reset sources are asserted simultaneously RSTYPE records the reset source that deasserts last If multiple reset sources are asserted and deasserted simultaneously RSTYPE latches the highest priority reset source RSTYPE is shown in Figure 7 4 and described in Table 7 6 Figure 7 4 Reset Type Status Register RSTYPE 31 16 Reserved R 0 15 3 2 1 0 Reserved PLLSWRST XWRST POR R 0 R 0 R 0 R 0 L...

Page 139: ...s locked Any write to the register following a successful unlock relocks the register RSCTRL is shown in Figure 7 5 and described in Table 7 7 Figure 7 5 Reset Control Register RSCTRL 31 17 16 Reserved SWRST R 0 R W 1 15 0 KEY R W 3h LEGEND R W Read Write R Read only n value after reset Table 7 7 Reset Control Register RSCTRL Field Descriptions Bit Field Value Description 31 17 Reserved 0 Reserved...

Page 140: ...n value after reset Table 7 8 PLLC0 Control Register PLLCTL Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 EXTCLKSRC External clock source selection 0 Use OSCIN for the PLL bypass clock 1 Use PLL1_SYSCLK3 for the PLL bypass clock 8 CLKMODE Reference clock selection 0 Internal oscillator crystal 1 Square wave 7 6 Reserved 1 Reserved 5 PLLENSRC 0 This bit must be cleared ...

Page 141: ...LPWRDN PLLEN R 1 R W 1 R W 1 R W 0 R 0 R W 1 R W 0 LEGEND R W Read Write R Read only n value after reset Table 7 9 PLLC1 Control Register PLLCTL Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 6 Reserved 1 Reserved 5 PLLENSRC 0 This bit must be cleared before the PLLEN bit will have any effect 4 Reserved 1 Reserved Write the default value when modifying this register 3 PL...

Page 142: ...g a direct input clock divider The OCSEL is shown in Figure 7 8 and described in Table 7 10 Figure 7 8 PLLC0 OBSCLK Select Register OCSEL 31 16 Reserved R 0 15 5 4 0 Reserved OCSRC R 0 R W 14h LEGEND R W Read Write R Read only n value after reset Table 7 10 PLLC0 OBSCLK Select Register OCSEL Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 0 OCSRC 0 1Fh PLLC0 OBSCLK source...

Page 143: ...urposes in addition to its normal function of being a direct input clock divider The OCSEL is shown in Figure 7 9 and described in Table 7 11 Figure 7 9 PLLC1 OBSCLK Select Register OCSEL 31 16 Reserved R 0 15 5 4 0 Reserved OCSRC R 0 R W 14h LEGEND R W Read Write R Read only n value after reset Table 7 11 PLLC1 OBSCLK Select Register OCSEL Field Descriptions Bit Field Value Description 31 5 Reser...

Page 144: ...alues for a given OSCIN is defined by the minimum and maximum frequency limits on the PLL VCO frequency See the device specific data manual for PLL VCO frequency specification limits 7 3 10 PLLC0 Pre Divider Control Register PREDIV The PLLC0 pre divider control register PREDIV is shown in Figure 7 11 and described in Table 7 13 Figure 7 11 PLLC0 Pre Divider Control Register PREDIV 31 16 Reserved R...

Page 145: ... Reserved 15 D1EN Divider 1 enable 0 Divider 1 is disabled 1 Divider 1 is enabled 14 5 Reserved 0 Reserved 4 0 RATIO 0 1Fh Divider ratio Divider Value RATIO 1 RATIO defaults to 0 PLL divide by 1 7 3 12 PLLC1 Divider 1 Register PLLDIV1 The PLLC1 divider 1 register PLLDIV1 controls the divider for PLL1_SYSCLK1 PLLDIV1 is shown in Figure 7 13 and described in Table 7 15 Figure 7 13 PLLC1 Divider 1 Re...

Page 146: ... Reserved 15 D2EN Divider 2 enable 0 Divider 2 is disabled 1 Divider 2 is enabled 14 5 Reserved 0 Reserved 4 0 RATIO 0 1Fh Divider ratio Divider Value RATIO 1 RATIO defaults to 1 PLL divide by 2 7 3 14 PLLC1 Divider 2 Register PLLDIV2 The PLLC1 divider 2 register PLLDIV2 controls the divider for PLL1_SYSCLK2 PLLDIV2 is shown in Figure 7 15 and described in Table 7 17 Figure 7 15 PLLC1 Divider 2 Re...

Page 147: ...Reserved 15 D3EN Divider 3 enable 0 Divider 3 is disabled 1 Divider 3 is enabled 14 5 Reserved 0 Reserved 4 0 RATIO 0 1Fh Divider ratio Divider Value RATIO 1 RATIO defaults to 2h PLL divide by 3 7 3 16 PLLC1 Divider 3 Register PLLDIV3 The PLLC1 divider 3 register PLLDIV3 controls the divider for PLL1_SYSCLK3 PLLDIV3 is shown in Figure 7 17 and described in Table 7 19 Figure 7 17 PLLC1 Divider 3 Re...

Page 148: ...d 0 Reserved 15 D4EN Divider 4 enable 0 Divider 4 is disabled 1 Divider 4 is enabled 14 5 Reserved 0 Reserved 4 0 RATIO 0 1Fh Divider ratio Divider Value RATIO 1 RATIO defaults 3 PLL divide by 4 7 3 18 PLLC0 Divider 5 Register PLLDIV5 The PLLC0 divider 5 register PLLDIV5 controls the divider for PLL0_SYSCLK5 PLLDIV5 is shown in Figure 7 19 and described in Table 7 21 Figure 7 19 PLLC0 Divider 5 Re...

Page 149: ... Reserved 15 D6EN Divider 6 enable 0 Divider 6 is disabled 1 Divider 6 is enabled 14 5 Reserved 0 Reserved 4 0 RATIO 0 1Fh Divider ratio Divider Value RATIO 1 RATIO defaults to 0 PLL divide by 1 7 3 20 PLLC0 Divider 7 Register PLLDIV7 The PLLC0 divider 7 register PLLDIV7 controls the divider for PLL0_SYSCLK7 PLLDIV7 is shown in Figure 7 21 and described in Table 7 23 Figure 7 21 PLLC0 Divider 7 Re...

Page 150: ...it in the PLLC0 clock enable control register CKEN must be set to 1 14 5 Reserved 0 Reserved 4 0 RATIO 0 1Fh Divider ratio Divider value RATIO 1 For example RATIO 0 means divide by 1 7 3 22 PLLC1 Oscillator Divider 1 Register OSCDIV The PLLC1 oscillator divider 1 register OSCDIV controls the divider for PLLC1 OBSCLK dividing down the clock selected as the PLLC1 OBSCLK source The PLLC1 OBSCLK signa...

Page 151: ...DEN Post divider enable 0 Post divider is disabled 1 Post divider is enabled 14 5 Reserved 0 Reserved 4 0 RATIO 0 1Fh Divider ratio Divider Value RATIO 1 RATIO defaults to 1 PLL post divide by 2 7 3 24 PLL Controller Command Register PLLCMD The PLL controller command register PLLCMD contains the command bit for phase alignment A write of 1 initiates the command a write of 0 clears the bit but has ...

Page 152: ...tatus Register PLLSTAT 31 16 Reserved R 0 15 3 2 1 0 Reserved STABLE Reserved GOSTAT R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 7 28 PLL Controller Status Register PLLSTAT Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 STABLE OSC counter done oscillator assumed to be stable By the time the device comes out of reset this bit should become 1 0 No 1 Yes 1 ...

Page 153: ...1 R W 1 LEGEND R W Read Write R Read only n value after reset Table 7 29 PLLC0 Clock Align Control Register ALNCTL Field Descriptions Bit Field Value Description 31 7 Reserved 3h Reserved 6 ALN7 PLL0_SYSCLK7 needs to be aligned to others selected in this register 0 No 1 Yes 5 ALN6 PLL0_SYSCLK6 needs to be aligned to others selected in this register 0 No 1 Yes 4 ALN5 PLL0_SYSCLK5 needs to be aligne...

Page 154: ...d described in Table 7 30 Figure 7 28 PLLC1 Clock Align Control Register ALNCTL 31 16 Reserved R 0 15 3 2 1 0 Reserved ALN3 ALN2 ALN1 R 0 R W 1 R W 1 R W 1 LEGEND R W Read Write R Read only n value after reset Table 7 30 PLLC1 Clock Align Control Register ALNCTL Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 ALN3 PLL1_SYSCLK3 needs to be aligned to others selected in thi...

Page 155: ...0 LEGEND R Read only n value after reset Table 7 31 PLLC0 PLLDIV Ratio Change Status Register DCHANGE Field Descriptions Bit Field Value Description 31 7 Reserved 0 Reserved 6 SYS7 PLL0_SYSCLK7 divide ratio is modified 0 Ratio is not modified 1 Ratio is modified 5 SYS6 PLL0_SYSCLK6 divide ratio is modified 0 Ratio is not modified 1 Ratio is modified 4 SYS5 PLL0_SYSCLK5 divide ratio is modified 0 R...

Page 156: ...d described in Table 7 32 Figure 7 30 PLLC1 PLLDIV Ratio Change Status Register DCHANGE 31 16 Reserved R 0 15 3 2 1 0 Reserved SYS3 SYS2 SYS1 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 7 32 PLLC1 PLLDIV Ratio Change Status Register DCHANGE Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 SYS3 PLL1_SYSCLK3 divide ratio is modified 0 Ratio is not modified 1...

Page 157: ...o toggle both the OBSEN bit and the OD1EN bit in the PLLC0 oscillator divider 1 register OSCDIV must be set to 1 0 AUXEN AUXCLK enable Actual PLLC0 AUXCLK status is shown in the PLLC0 clock status register CKSTAT 0 PLLC0 AUXCLK is disabled 1 PLLC0 AUXCLK is enabled 7 3 31 PLLC1 Clock Enable Control Register CKEN The PLLC1 clock enable control register CKEN controls the PLLC1 OBSCLK clock CKEN is s...

Page 158: ...Table 7 35 Figure 7 33 PLLC0 Clock Status Register CKSTAT 31 16 Reserved R 0 15 2 1 0 Reserved OBSEN AUXEN R 0 R 1 R 1 LEGEND R Read only n value after reset Table 7 35 PLLC0 Clock Status Register CKSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 OBSEN OBSCLK on status PLLC0 OBSCLK is controlled in the PLLC0 oscillator divider 1 register OSCDIV by the OBSEN bit in th...

Page 159: ...gister SYSTAT CKSTAT is shown in Figure 7 34 and described in Table 7 36 Figure 7 34 PLLC1 Clock Status Register CKSTAT 31 16 Reserved R 0 15 2 1 0 Reserved OBSEN Reserved R 2h R 0 R 0 LEGEND R Read only n value after reset Table 7 36 PLLC1 Clock Status Register CKSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 OBSEN OBSCLK on status PLLC1 OBSCLK is controlled in the...

Page 160: ...ribed in Table 7 37 Figure 7 35 PLLC0 SYSCLK Status Register SYSTAT 31 8 Reserved R 1 7 6 5 4 3 2 1 0 Reserved SYS7ON SYS6ON SYS5ON SYS4ON SYS3ON SYS2ON SYS1ON R 1 R 1 R 1 R 1 R 1 R 1 R 1 R 1 LEGEND R W Read Write R Read only n value after reset Table 7 37 PLLC0 SYSCLK Status Register SYSTAT Field Descriptions Bit Field Value Description 31 7 Reserved 3h Reserved 6 SYS7ON PLL0_SYSCLK7 on status 0 ...

Page 161: ...ctual clock on off status which depends on the DnEN bit in PLLC1 PLLDIVn SYSTAT is shown in Figure 7 36 and described in Table 7 38 Figure 7 36 PLLC1 SYSCLK Status Register SYSTAT 31 8 Reserved R 0 7 3 2 1 0 Reserved SYS3ON SYS2ON SYS1ON R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 7 38 PLLC1 SYSCLK Status Register SYSTAT Field Descriptions Bit Field Value Descriptio...

Page 162: ...0 31 0 COUNT R 0 LEGEND R Read only n value after reset Table 7 39 Emulation Performance Counter 0 Register EMUCNT0 Field Descriptions Bit Field Value Description 31 0 COUNT 0 FFFF FFFFh Counter value for lower 64 bits 7 3 37 Emulation Performance Counter 1 Register EMUCNT1 The emulation performance counter 1 register EMUCNT1 is shown in Figure 7 38 and described in Table 7 40 EMUCNT1 is for emula...

Page 163: ...porated Power and Sleep Controller PSC Chapter 8 SPRUH82C April 2013 Revised September 2016 Power and Sleep Controller PSC Topic Page 8 1 Introduction 164 8 2 Power Domain and Module Topology 164 8 3 Executing State Transitions 169 8 4 IcePick Emulation Support in the PSC 170 8 5 PSC Interrupts 170 8 6 PSC Registers 173 ...

Page 164: ...es two PSC modules Each PSC module consists of an Always On power domain an additional pseudo internal power domain that manages the sleep modes for the RAMs present in the L3 RAM Each PSC module controls clock states for several on the on chip modules controllers and interconnect components Table 8 1 and Table 8 2 lists the set of peripherals modules that are controlled by the PSC the power domai...

Page 165: ...RM AlwaysON PD0 SwRstDisable 15 Not Used 1 Note that the SATA module requires forced state transitions Table 8 2 PSC1 Default Module Configuration LPSC Number Module Name Power Domain Default Module State Auto Sleep Wake Only 0 EDMA3_1 Channel Controller 0 AlwaysON PD0 SwRstDisable 1 USB0 USB2 0 AlwaysON PD0 SwRstDisable 2 USB1 USB1 1 AlwaysON PD0 SwRstDisable 3 GPIO AlwaysON PD0 SwRstDisable 4 HP...

Page 166: ...nd PSC1 the Always ON domain or PD0 power domain is always in the ON state when the chip is powered on This domain is not programmable to OFF state See details on PDCTL register Additionally for both PSC0 and PSC1 the PD1 power domains the internal pseudo power domain can either be in the ON state or OFF state Furthermore for these power domains the transition from ON to OFF state is further quali...

Page 167: ...to Sleep Auto Wake Only modules disabling the clock is not supported and they should be kept in their default Enable state Table 8 1 and Table 8 2 each have a column to indicate whether or not the LPSC configuration for a module is Auto Sleep Wake Only Modules that have a Yes marked for the Auto Sleep Wake Only column can be programmed in software to be in Enable Auto Sleep and Auto Wake states on...

Page 168: ...ate also has its module reset de asserted and its module clock disabled similar to the Disable state However this is a special state once a module is configured in this state by software it can automatically transition to Enable state whenever there is an internal read write request made to it and after servicing the request it will automatically transition into the sleep state with module reset r...

Page 169: ... before you can invoke the PSC module state transition See the individual peripheral user guides for more details For example the external memory controller requires that you first place the SDRAM memory in self refresh mode before you invoke the PSC module state transitions if you want to maintain the memory contents The following procedure is directly applicable for all modules that are controll...

Page 170: ...ed local and module resets NOTE When emulation tools remove the above commands the PSC immediately executes a state transition based on the current values in the NEXT bit in PDCTL0 and the NEXT bit in MDCTLn as set by software 8 5 PSC Interrupts The PSC has an interrupt that is tied to the core interrupt controller This interrupt is named PSCINT in the interrupt map The PSC interrupt is generated ...

Page 171: ...al reset When wait reset is asserted by emulation When block reset is asserted by emulation and software attempts to change the state of local reset 8 5 2 Interrupt Registers The PSC interrupt enable bits are the EMUIHBIE bit in PDCTL1 PSC0 the EMUIHBIE and the EMURSTIE bits in MDCTLn where n is the modules that have IcePick emulation support as specified in Section 8 4 NOTE To interrupt the CPU t...

Page 172: ...oller To interrupt the CPU PSCn_ALLINT must be enabled in the device interrupt controller See the ARM Interrupt Controller AINTC chapter for more information on interrupts The CPU enters the interrupt service routine ISR when it receives the interrupt 1 Read the P n bit in PERRPR and or the M n bit in MERRPR0 the M n bit in MERRPR1 to determine the source of the interrupt s 2 For each active event...

Page 173: ...8 6 15 01C1 0404h PDCFG1 Power Domain 1 Configuration Register Section 8 6 16 01C1 0800h 01C1 083Ch MDSTAT0 MDSTAT15 Module Status n Register modules 0 15 Section 8 6 17 01C1 0A00h 01C1 0A3Ch MDCTL0 MDCTL15 Module Control n Register modules 0 15 Section 8 6 18 Table 8 7 Power and Sleep Controller 1 PSC1 Registers Address Acronym Register Description Section 01E2 7000h REVID Revision Identification...

Page 174: ...n Identification Register REVID Field Descriptions Bit Field Value Description 31 0 REV 4482 5A00h Peripheral revision ID 8 6 2 Interrupt Evaluation Register INTEVAL The interrupt evaluation register INTEVAL is shown in Figure 8 2 and described in Table 8 9 Figure 8 2 Interrupt Evaluation Register INTEVAL 31 16 Reserved R 0 15 1 0 Reserved ALLEV R 0 W 0 LEGEND R Read only W Write only n value afte...

Page 175: ...R 0 R 0 R 0 LEGEND R Read only n value after reset Table 8 10 PSC0 Module Error Pending Register 0 MERRPR0 Field Descriptions Bit Field Value Description 31 15 Reserved 0 Reserved 14 M 14 Module interrupt status bit for module 14 ARM 0 Module 14 does not have an error condition 1 Module 14 has an error condition See the module status 14 register MDSTAT14 for the error condition 13 0 Reserved 0 Res...

Page 176: ...or Clear Register 0 MERRCR0 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 Reserved 0 Reserved Write the default value when modifying this register 14 M 14 Clears the interrupt status bit M 14 set in the PSC0 module error pending register 0 MERRPR0 and the interrupt status bits set in the module status 14 register MDSTAT14 0 A write of 0 has no effect 1 A write of 1 cl...

Page 177: ...have an error condition 1 RAM Pseudo power domain has an error condition See the power domain 1 status register PDSTAT1 for the error condition 0 Reserved 0 Reserved 8 6 8 Power Error Clear Register PERRCR The power error clear register PERRCR is shown in Figure 8 8 and described in Table 8 13 Figure 8 8 Power Error Clear Register PERRCR 31 16 Reserved R 0 15 2 1 0 Reserved P 1 Rsvd R 0 W 0 R 0 LE...

Page 178: ... Pseudo PD1 power domain GO transition command 0 A write of 0 has no effect 1 A write of 1 causes the PSC to evaluate all the NEXT fields relevant to this power domain including PDCTL NEXT for this domain and MDCTL NEXT for all the modules residing on this domain If any of the NEXT fields are not matching the corresponding current state PDSTAT STATE MDSTAT STATE the PSC will transition those respe...

Page 179: ...15 2 1 0 Reserved GOSTAT 1 GOSTAT 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 8 15 Power Domain Transition Status Register PTSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 GOSTAT 1 RAM Pseudo PD1 power domain transition status 0 No transition in progress 1 RAM Pseudo power domain is transitioning that is either the power domain is transitioning or mod...

Page 180: ...ield Descriptions Bit Field Value Description 31 12 Reserved 0 Reserved 11 EMUIHB Emulation alters domain state 0 Interrupt is not active No emulation altering user desired power domain states 1 Interrupt is active Emulation alters user desired power domain state 10 Reserved 0 Reserved 9 PORDONE Power_On_Reset POR Done status 0 Power domain POR is not done 1 Power domain POR is done 8 POR Power Do...

Page 181: ...ield Descriptions Bit Field Value Description 31 12 Reserved 0 Reserved 11 EMUIHB Emulation alters domain state 0 Interrupt is not active No emulation altering user desired power domain states 1 Interrupt is active Emulation alters user desired power domain state 10 Reserved 0 Reserved 9 PORDONE Power_On_Reset POR Done status 0 Power domain POR is not done 1 Power domain POR is done 8 POR Power Do...

Page 182: ...reset Table 8 18 Power Domain 0 Control Register PDCTL0 Field Descriptions Bit Field Value Description 31 24 Reserved 0 Reserved 23 16 WAKECNT 0 FFh RAM wake count delay value Not recommended to change the default value 1Fh Bits 23 30 GOOD2ACCESS wake delay Bits 19 16 ON2GOOD wake delay 15 12 PDMODE 0 Fh Power down mode 0 Eh Reserved Fh Core on RAM array on RAM periphery on 11 10 Reserved 0 Reserv...

Page 183: ...ay value Not recommended to change the default value 1Fh Bits 23 30 GOOD2ACCESS wake delay Bits 19 16 ON2GOOD wake delay 15 12 PDMODE 0 Fh Power down mode 0 Core off RAM array off RAM periphery off 1h Core off RAM array retention RAM periphery off deep sleep 2h 3h Reserved 4h Core retention RAM array off RAM periphery off 5h Core retention RAM array retention RAM periphery off deep sleep 6h 7h Res...

Page 184: ... 3 2 1 0 Reserved PD_LOCK ICEPICK RAM_PSM ALWAYSON R 0 R 1 R 1 R 0 R 1 LEGEND R Read only n value after reset Table 8 20 Power Domain 0 Configuration Register PDCFG0 Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 PD_LOCK PDCTL NEXT lock For Always ON power domain this bit is a don t care 0 PDCTL NEXT bit is locked and cannot be changed in software 1 PDCTL NEXT bit is not...

Page 185: ... 3 2 1 0 Reserved PD_LOCK ICEPICK RAM_PSM ALWAYSON R 0 R 1 R 1 R 0 R 1 LEGEND R Read only n value after reset Table 8 21 Power Domain 1 Configuration Register PDCFG1 Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 PD_LOCK PDCTL NEXT lock For Always ON power domain this bit is a don t care 0 PDCTL NEXT bit is locked and cannot be changed in software 1 PDCTL NEXT bit is not...

Page 186: ...nt you must set the EMUIHBIE bit in MDCTL14 16 EMURST Emulation alters module reset This bit applies to ARM module module 14 This field is 0 for all other modules 0 No emulation altering user desired module reset state 1 Emulation altered user desired module reset state If you desire to generate a PSCINT upon this event you must set the EMURSTIE bit in the module control 14 register MDCTL14 15 13 ...

Page 187: ...rces the module state programmed in the NEXT bit in the module control 14 register MDCTL14 ignoring and bypassing all the clock stop request handshakes managed by the PSC to change the state of the clocks to the module Note It is not recommended to use the FORCE bit to disable the module clock unless specified 0 Force is disabled 1 Force is enabled 30 11 Reserved 0 Reserved 10 EMUIHBIE Interrupt e...

Page 188: ...ND R W Read Write R Read only n value after reset Table 8 24 PSC1 Module Control n Register MDCTLn Field Descriptions Bit Field Value Description 31 FORCE Force enable This bit forces the module state programmed in the NEXT bit in the module control 14 register MDCTL14 ignoring and bypassing all the clock stop request handshakes managed by the PSC to change the state of the clocks to the module No...

Page 189: ...3 Revised September 2016 Power Management Topic Page 9 1 Introduction 190 9 2 Power Consumption Overview 190 9 3 PSC and PLLC Overview 190 9 4 Features 191 9 5 Clock Management 192 9 6 ARM Sleep Mode Management 193 9 7 RTC Only Mode 195 9 8 Dynamic Voltage and Frequency Scaling DVFS 195 9 9 Deep Sleep Mode 196 9 10 Additional Peripheral Power Management Considerations 200 ...

Page 190: ...t impact on overall power consumption and thus on the battery life Dynamic power can be reduced by scaling the operating voltage when the performance requirements are not that high and the device can be operated at a corresponding lower frequency The capacitance is the capacitance of the switching nodes or the load capacitances on the switching I O pins The static power as the name suggests is ind...

Page 191: ... running I O clocks Core Sleep Management ARM subsystem sleep modes The ARM CPU can be put in sleep mode Additionally the ARM subsystem clock can be completely gated when not in use Reduces the dynamic power consumption Voltage Management RTC only mode Allows removing power from all core and I O supply and just have the real time clock RTC running Reduces the dynamic and static power for standby m...

Page 192: ... within the module when the logic is not active This is transparent to you but reduces overall dynamic power consumption when modules are not active 9 5 2 Module Clock Frequency Scaling Module clock frequency is scalable by programming the PLL multiply and divide parameters Additionally some modules might also have internal clock dividers Reducing the clock frequency reduces the dynamic switching ...

Page 193: ...t will remain in this state until an interrupt request IRQ FIQ occurs The following sequence exemplifies how to enter the WFI mode Enable any interrupt for example an external interrupt that you plan to use as the wake up interrupt to exit from the WFI mode Enable the WFI mode using the following CP15 instruction MCR p15 0 r3 c7 c0 4 The following sequence describes the procedure to wake up from t...

Page 194: ... Check for completion of all ARM master requests the ARM polls transfer completion statuses of all Master peripherals 2 Enable the interrupt to be used as the wake up interrupt for example one of the CHIPSIG interrupts controlled by the chip signal register CHIPSIG in the System Configuration SYSCFG Module chapter CHIPSIG 0 CHIPSIG 1 etc that will be used to wake up the ARM during the ARM clock on...

Page 195: ...ill meeting task requirements DVFS requires control over the clock frequency and the operating voltage of the device elements By intelligently switching these elements to their optimal operating points it is possible to minimize the power consumption of the device for a given task For reasons related to the device clock architecture process etc DVFS is used only for a few discrete steps not over a...

Page 196: ...modified you can configure the ASYNC3 domain to be clocked from PLL1_SYSCLK2 PLL1 is mainly used to clock the DDR2 mDDR memory controller When peripherals are immune to changes in the ARM clock frequency their internal clock dividers do not have to be adjusted for changes in their input clock frequencies 9 8 2 Voltage Scaling Considerations The operating voltage of the device must be totally contr...

Page 197: ...he delay before the Deep Sleep logic releases the clocks to the device during wake up allowing the oscillator to stabilize 10 Set the SLEEPENABLE bit in DEEPSLEEP to 1 This automatically clears the SLEEPCOMPLETE bit 11 Begin polling the SLEEPCOMPLETE bit until it is set to 1 This bit is set once the device is woken up from Deep Sleep mode 12 The external controller drives the DEEPSLEEP pin low to ...

Page 198: ... chapter This count determines the delay before the Deep Sleep logic releases the clocks to the device during wake up allowing the oscillator to stabilize 10 Set the SLEEPENABLE bit in DEEPSLEEP to 1 This automatically clears the SLEEPCOMPLETE bit Also the device now enters the Deep Sleep mode since the DEEPSLEEP pin is low For more details on the clock stop procedure of the DDR2 mDDR memory contr...

Page 199: ...driven low by either an external device or the RTC_ALARM pin The Deep Sleep mode begins 3 The PLL controller reference clock is gated 4 The on chip oscillator is disabled If the device is being clocked by an external source this clock may stay enabled the power savings from turning off this clock is minimal 5 The DEEPSLEEP pin is driven high and the on chip oscillator is enabled 6 The Deep Sleep c...

Page 200: ...3 Configure the GP0 8 pin to generate interrupts on the falling edge of the GPIO signal 4 An external device drives the GP0 8 pin low 5 Software prepares the device for Deep Sleep mode 6 Set the SLEEPENABLE bit in DEEPSLEEP to 1 The Deep Sleep mode is immediately started and all device clocks are stopped Also the SLEEPCOMPLETE bit is automatically cleared 9 9 4 2 Exiting Deep Sleep Mode To exit th...

Page 201: ... cannot be stopped by software running on the device To correctly take the memory out of self refresh after coming back from RTC only mode follow these steps 1 Before going into RTC only mode disconnect the DDR2 mDDR memory controller CKE output pin from the memory ensure the memory s CKE input pin continues to be driven low 2 After coming back from RTC only mode configure the device to the desire...

Page 202: ... This device includes internal pull up and pull down resistors that prevent floating input pins These internal resistors are generally very weak and their use is intended for pins that are not connected on the board design For pins that are connected external pull up and pull down resistors are recommended When an input pin is externally driven to a valid logic level through an external pull up re...

Page 203: ...16 Texas Instruments Incorporated System Configuration SYSCFG Module Chapter 10 SPRUH82C April 2013 Revised September 2016 System Configuration SYSCFG Module Topic Page 10 1 Introduction 204 10 2 Protection 204 10 3 Master Priority Control 205 10 4 Interrupt Support 207 10 5 SYSCFG Registers 207 ...

Page 204: ... The system configuration module controls several global operations of the device therefore the module supports protection against erroneous and illegal accesses to the registers in its memory map The protection mechanisms that are present in the module are A special key sequence that needs to be written into a set of registers in the system configuration module to allow write ability to the rest ...

Page 205: ...CFG module registers are accessible and can be configured as per the application requirements 10 3 Master Priority Control The on chip peripherals modules are essentially divided into two broad categories masters and slaves The master peripherals are typically capable of initiating their own read write data access requests this includes the ARM EDMA3 transfer controllers and peripherals that do no...

Page 206: ...MA3_0_TC0 EDMA3_0_TC1 and EDMA3_1_TC0 is configurable through fields in the master priority 1 register MSTPRI1 not the EDMA3CC QUEPRI register 3 LCDC traffic is typically real time sensitive therefore the default priority of 5 which is lower as compared to the default priority of several masters is not recommended You should reconfigure the LCDC priority to the highest or equal to other high prior...

Page 207: ...nly when the CPU is in privileged mode 1 This register is for internal use only Table 10 3 System Configuration Module 0 SYSCFG0 Registers Address Acronym Register Description Access Section 01C1 4000h REVID Revision Identification Register Section 10 5 1 01C1 4008h DIEIDR0 1 Die Identification Register 0 01C1 400Ch DIEIDR1 1 Die Identification Register 1 01C1 4010h DIEIDR2 1 Die Identification Re...

Page 208: ...d mode Section 10 5 10 15 01C1 415Ch PINMUX15 Pin Multiplexing Control 15 Register Privileged mode Section 10 5 10 16 01C1 4160h PINMUX16 Pin Multiplexing Control 16 Register Privileged mode Section 10 5 10 17 01C1 4164h PINMUX17 Pin Multiplexing Control 17 Register Privileged mode Section 10 5 10 18 01C1 4168h PINMUX18 Pin Multiplexing Control 18 Register Privileged mode Section 10 5 10 19 01C1 4...

Page 209: ...ion Identification Register REVID Field Descriptions Bit Field Value Description 31 0 REV 4E84 0102h Revision ID Revision information for the SYSCFG module 10 5 2 Device Identification Register 0 DEVIDR0 The device identification register 0 DEVIDR0 contains a software readable version of the JTAG ID device Software can use this register to determine the version of the device on which it is executi...

Page 210: ...le 10 7 Boot Configuration Register BOOTCFG Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 0 BOOTMODE 0 FFFFh Boot Mode This reflects the state of the boot mode pins 10 5 4 Chip Revision Identification Register CHIPREVIDR The chip revision identification register CHIPREVIDR provides the software readable silicon revision information for the device The CHIPREVID is show...

Page 211: ...her of these kick registers will cause the memory mapped registers to be locked again and block out any write accesses to registers in the SYSCFG module 10 5 5 1 Kick 0 Register KICK0R The KICK0R is shown in Figure 10 5 and described in Table 10 9 Figure 10 5 Kick 0 Register KICK0R 31 0 KICK1 R W 0 LEGEND R W Read Write n value after reset Table 10 9 Kick 0 Register KICK0R Field Descriptions Bit F...

Page 212: ...egister HOST0CFG In a typical application the BOOTRDY bit should not be cleared The HOST0CFG is shown in Figure 10 7 and described in Table 10 11 Figure 10 7 Host 0 Configuration Register HOST0CFG 31 16 Reserved R 0 15 1 0 Reserved BOOTRDY R 0 R W 1 LEGEND R W Read Write R Read only n value after reset Table 10 11 Host 0 Configuration Register HOST0CFG Field Descriptions Bit Field Value Descriptio...

Page 213: ...he interrupt and allows setting of the interrupt status The IRAWSTAT is shown in Figure 10 8 and described in Table 10 12 Figure 10 8 Interrupt Raw Status Set Register IRAWSTAT 31 16 Reserved R 0 15 2 1 0 Reserved ADDRERR PROTERR R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 12 Interrupt Raw Status Set Register IRAWSTAT Field Descriptions Bit Field Value Descriptio...

Page 214: ...1 16 Reserved R 0 15 2 1 0 Reserved ADDRERR PROTERR R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 13 Interrupt Enable Status Clear Register IENSTAT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved Always read 0 1 ADDRERR Addressing violation error Reading this bit field reflects the interrupt enabled status 0 Indicates the interrupt is not se...

Page 215: ...on error 0 Writing a 0 has not effect 1 Writing a 1 enables this interrupt 0 PROTERR_EN Protection violation error 0 Writing a 0 has not effect 1 Writing a 1 enables this interrupt 10 5 7 4 Interrupt Enable Clear Register IENCLR The interrupt enable clear register IENCLR allows clearing disable the interrupt for address and or protection violation condition It also shows the value of the interrupt...

Page 216: ...d EOIVECT R 0 W 0 LEGEND R Read only W Write only n value after reset Table 10 16 End of Interrupt Register EOI Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved Always read 0 7 0 EOIVECT 0 FFh EOI vector value Write the interrupt distribution value of the chip 10 5 8 Fault Registers The fault registers are a group of registers responsible for capturing the details on the fau...

Page 217: ...8 Figure 10 14 Fault Status Register FLTSTAT 31 24 23 16 ID MSTID R 0 R 0 15 13 12 9 8 6 5 0 Reserved PRIVID Reserved TYPE R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 10 18 Fault Status Register FLTSTAT Field Descriptions Bit Field Value Description 31 24 ID 0 FFh Transfer ID of the first fault transfer 23 16 MSTID 0 FFh Master ID of the first fault transfer 15 13 Reserved 0 Reser...

Page 218: ...g this register 30 28 Reserved 4h Reserved Write the default value when modifying this register 27 Reserved 0 Reserved Write the default value when modifying this register 26 24 Reserved 4h Reserved Write the default value when modifying this register 23 Reserved 0 Reserved Write the default value when modifying this register 22 20 SATA 0 7h SATA port priority Bit 0 priority 0 highest bit 7h prior...

Page 219: ...iority Bit 0 priority 0 highest bit 7h priority 7 lowest 27 Reserved 0 Reserved Write the default value when modifying this register 26 24 VPIF_DMA_0 0 7h VPIF DMA0 port priority Bit 0 priority 0 highest bit 7h priority 7 lowest 23 Reserved 0 Reserved Write the default value when modifying this register 22 20 Reserved 4h Reserved Write the default value when modifying this register 19 Reserved 0 R...

Page 220: ...d Write the default value when modifying this register 26 24 USB1 0 7h USB1 USB1 1 port priority Bit 0 priority 0 highest bit 7h priority 7 lowest 23 Reserved 0 Reserved Write the default value when modifying this register 22 20 UHPI 0 7h HPI port priority Bit 0 priority 0 highest bit 7h priority 7 lowest 19 Reserved 0 Reserved Write the default value when modifying this register 18 16 Reserved 0 ...

Page 221: ...led information about the pin multiplexing and control is covered in the device specific data manual Access to the pin multiplexing utility is available in AM18xx Pin Multiplexing Utility Application Report SPRABA2 10 5 10 1 Pin Multiplexing Control 0 Register PINMUX0 Figure 10 18 Pin Multiplexing Control 0 Register PINMUX0 31 28 27 24 23 20 19 16 PINMUX0_31_28 PINMUX0_27_24 PINMUX0_23_20 PINMUX0_...

Page 222: ...PRU0_R30 18 O 3h Reserved X 4h Selects Function UART1_RTS O 5h 7h Reserved X 8h Selects Function GP0 11 I O 9h Fh Reserved X 15 12 PINMUX0_15_12 AFSX GP0 12 PRU0_R31 19 Control 0 Selects Function PRU0_R31 19 I 1h Selects Function AFSX I O 2h 7h Reserved X 8h Selects Function GP0 12 I O 9h Fh Reserved X 11 8 PINMUX0_11_8 AFSR GP0 13 PRU0_R31 20 Control 0 Selects Function PRU0_R31 20 I 1h Selects Fu...

Page 223: ...ld Descriptions Bit Field Value Description Type 1 31 28 PINMUX1_31_28 AXR8 CLKS1 ECAP1_APWM1 GP0 0 PRU0_R31 8 Control 0 Selects Function PRU0_R31 8 I 1h Selects Function AXR8 I O 2h Selects Function CLKS1 I 3h Reserved X 4h Selects Function ECAP1_APWM1 I O 5h 7h Reserved X 8h Selects Function GP0 0 I O 9h Fh Reserved X 27 24 PINMUX1_27_24 AXR9 DX1 GP0 1 Control 0 Pin is 3 stated Z 1h Selects Func...

Page 224: ... Function GP0 4 I O 9h Fh Reserved X 11 8 PINMUX1_11_8 AXR13 CLKX1 GP0 5 Control 0 Pin is 3 stated Z 1h Selects Function AXR13 I O 2h Selects Function CLKX1 I O 3h 7h Reserved X 8h Selects Function GP0 5 I O 9h Fh Reserved X 7 4 PINMUX1_7_4 AXR14 CLKR1 GP0 6 Control 0 Pin is 3 stated Z 1h Selects Function AXR14 I O 2h Selects Function CLKR1 I O 3h 7h Reserved X 8h Selects Function GP0 6 I O 9h Fh ...

Page 225: ...lexing Control 2 Register PINMUX2 Field Descriptions Bit Field Value Description Type 1 31 28 PINMUX2 _31_28 AXR0 ECAP0_APWM0 GP8 7 MII_TXD 0 CLK S0 Control 0 Selects Function CLKS0 I 1h Selects Function AXR0 I O 2h Selects Function ECAP0_APWM0 I O 3h Reserved X 4h Selects Function GP8 7 I O 5h 7h Reserved X 8h Selects Function MII_TXD 0 O 9h Fh Reserved X 27 24 PINMUX2 _27_24 AXR1 DX0 GP1 9 MII_T...

Page 226: ... Reserved X 4h Selects Function GP1 12 I O 5h 7h Reserved X 8h Selects Function MII_COL I 9h Fh Reserved X 11 8 PINMUX2 _11_8 AXR5 CLKX0 GP1 13 MII_TXCLK Control 0 Pin is 3 stated Z 1h Selects Function AXR5 I O 2h Selects Function CLKX0 I O 3h Reserved X 4h Selects Function GP1 13 I O 5h 7h Reserved X 8h Selects Function MII_TXCLK I 9h Fh Reserved X 7 4 PINMUX2 _7_4 AXR6 CLKR0 GP1 14 MII_TXEN PRU0...

Page 227: ...ptions Bit Field Value Description Type 1 31 28 PINMUX3_31_28 SPI0_SCS 2 UART0_RTS GP8 1 MII_RXD 0 SATA_CP_DET Control 0 Selects Function SATA_CP_DET I 1h Selects Function SPI0_SCS 2 I O 2h Selects Function UART0_RTS O 3h Reserved X 4h Selects Function GP8 1 I O 5h 7h Reserved X 8h Selects Function MII_RXD 0 I 9h Fh Reserved X 27 24 PINMUX3_27_24 SPI0_SCS 3 UART0_CTS GP8 2 MII_RXD 1 SATA_MP_SWITCH...

Page 228: ...lects Function EPWMSYNCO O 3h Reserved X 4h Selects Function GP8 5 I O 5h 7h Reserved X 8h Selects Function MII_CRS I 9h Fh Reserved X 11 8 PINMUX3_11_8 SPI0_SOMI EPWMSYNCI GP8 6 MII_RXER Control 0 Pin is 3 stated Z 1h Selects Function SPI0_SOMI I O 2h Selects Function EPWMSYNCI I 3h Reserved X 4h Selects Function GP8 6 I O 5h 7h Reserved X 8h Selects Function MII_RXER I 9h Fh Reserved X 7 4 PINMU...

Page 229: ...egister PINMUX4 Field Descriptions Bit Field Value Description Type 1 31 28 PINMUX4_31_28 SP1_SCS 2 UART1_TXD SATA_CP_POD GP1 0 Control 0 Pin is 3 stated Z 1h Selects Function SP1_SCS 2 I O 2h Selects Function UART1_TXD O 3h Reserved X 4h Selects Function SATA_CP_POD O 5h 7h Reserved X 8h Selects Function GP1 0 I O 9h Fh Reserved X 27 24 PINMUX4_27_24 SPI1_SCS 3 UART1_RXD SATA_LED GP1 1 Control 0 ...

Page 230: ...d X 4h Selects Function TM64P3_OUT12 O 5h 7h Reserved X 8h Selects Function GP1 4 I O 9h Fh Reserved X 11 8 PINMUX4_11_8 SPI1_SCS 7 I2C0_SCL TM64P2_OUT12 GP1 5 Control 0 Pin is 3 stated Z 1h Selects Function SPI1_SCS 7 I O 2h Selects Function I2C0_SCL I O 3h Reserved X 4h Selects Function TM64P2_OUT12 O 5h 7h Reserved X 8h Selects Function GP1 5 I O 9h Fh Reserved X 7 4 PINMUX4_7_4 SPI0_SCS 0 TM64...

Page 231: ...NMUX5 Field Descriptions Bit Field Value Description Type 1 31 28 PINMUX5_31_28 EMA_BA 0 GP2 8 Control 0 Pin is 3 stated Z 1h Selects Function EMA_BA 0 O 2h 7h Reserved X 8h Selects Function GP2 8 I O 9h Fh Reserved X 27 24 PINMUX5_27_24 EMA_BA 1 GP2 9 Control 0 Pin is 3 stated Z 1h Selects Function EMA_BA 1 O 2h 7h Reserved X 8h Selects Function GP2 9 I O 9h Fh Reserved X 23 20 PINMUX5_23_20 SPI1...

Page 232: ...ved X 8h Selects Function GP2 13 I O 9h Fh Reserved X 7 4 PINMUX5_7_4 SPI1_SCS 0 EPWM1B PRU0_R30 7 GP2 14 TM64P3_IN12 Control 0 Selects Function TM64P3_IN12 I 1h Selects Function SPI1_SCS 0 I O 2h Selects Function EPWM1B I O 3h Reserved X 4h Selects Function PRU0_R30 7 O 5h 7h Reserved X 8h Selects Function GP2 14 I O 9h Fh Reserved X 3 0 PINMUX5_3_0 SPI1_SCS 1 EPWM1A PRU0_R30 8 GP2 15 TM64P2_IN12...

Page 233: ...S 0 GP2 0 Control 0 Pin is 3 stated Z 1h Selects Function EMA_CS 0 O 2h 7h Reserved X 8h Selects Function GP2 0 I O 9h Fh Reserved X 27 24 PINMUX6_27_24 EMA_WAIT 1 PRU0_R30 1 GP2 1 PRU0_R31 1 Control 0 Selects Function PRU0_R31 1 I 1h Selects Function EMA_WAIT 1 I 2h 3h Reserved X 4h Selects Function PRU0_R30 1 O 5h 7h Reserved X 8h Selects Function GP2 1 I O 9h Fh Reserved X 23 20 PINMUX6_23_20 E...

Page 234: ...ects Function EMA_RAS O 2h 3h Reserved X 4h Selects Function PRU0_R30 3 O 5h 7h Reserved X 8h Selects Function GP2 5 I O 9h Fh Reserved X 7 4 PINMUX6_7_4 EMA_SDCKE PRU0_R30 4 GP2 6 PRU0_R31 4 Control 0 Selects Function PRU0_R31 4 I 1h Selects Function EMA_SDCKE O 2h 3h Reserved X 4h Selects Function PRU0_R30 4 O 5h 7h Reserved X 8h Selects Function GP2 6 I O 9h Fh Reserved X 3 0 PINMUX6_3_0 EMA_CL...

Page 235: ...Value Description Type 1 31 28 PINMUX7_31_28 EMA_WAIT 0 PRU0_R30 0 GP3 8 PRU0_R31 0 Control 0 Selects Function PRU0_R31 0 I 1h Selects Function EMA_WAIT 0 I 2h 3h Reserved X 4h Selects Function PRU0_R30 0 O 5h 7h Reserved X 8h Selects Function GP3 8 I O 9h Fh Reserved X 27 24 PINMUX7_27_24 EMA_A_RW GP3 9 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A_RW O 2h 7h Reserved X 8h Selects Functio...

Page 236: ...ue Description Type 1 11 8 PINMUX7_11_8 EMA_CS 4 GP3 13 Control 0 Pin is 3 stated Z 1h Selects Function EMA_CS 4 O 2h 7h Reserved X 8h Selects Function GP3 13 I O 9h Fh Reserved X 7 4 PINMUX7_7_4 EMA_CS 3 GP3 14 Control 0 Pin is 3 stated Z 1h Selects Function EMA_CS 3 O 2h 7h Reserved X 8h Selects Function GP3 14 I O 9h Fh Reserved X 3 0 PINMUX7_3_0 EMA_CS 2 GP3 15 Control 0 Pin is 3 stated Z 1h S...

Page 237: ...er PINMUX8 Field Descriptions Bit Field Value Description Type 1 31 28 PINMUX8_31_28 EMA_D 8 GP3 0 Control 0 Pin is 3 stated Z 1h Selects Function EMA_D 8 I O 2h 7h Reserved X 8h Selects Function GP3 0 I O 9h Fh Reserved X 27 24 PINMUX8_27_24 EMA_D 9 GP3 1 Control 0 Pin is 3 stated Z 1h Selects Function EMA_D 9 I O 2h 7h Reserved X 8h Selects Function GP3 1 I O 9h Fh Reserved X 23 20 PINMUX8_23_20...

Page 238: ...ue Description Type 1 11 8 PINMUX8_11_8 EMA_D 13 GP3 5 Control 0 Pin is 3 stated Z 1h Selects Function EMA_D 13 I O 2h 7h Reserved X 8h Selects Function GP3 5 I O 9h Fh Reserved X 7 4 PINMUX8_7_4 EMA_D 14 GP3 6 Control 0 Pin is 3 stated Z 1h Selects Function EMA_D 14 I O 2h 7h Reserved X 8h Selects Function GP3 6 I O 9h Fh Reserved X 3 0 PINMUX8_3_0 EMA_D 15 GP3 7 Control 0 Pin is 3 stated Z 1h Se...

Page 239: ...ter PINMUX9 Field Descriptions Bit Field Value Description Type 1 31 28 PINMUX9_31_28 EMA_D 0 GP4 8 Control 0 Pin is 3 stated Z 1h Selects Function EMA_D 0 I O 2h 7h Reserved X 8h Selects Function GP4 8 I O 9h Fh Reserved X 27 24 PINMUX9_27_24 EMA_D 1 GP4 9 Control 0 Pin is 3 stated Z 1h Selects Function EMA_D 1 I O 2h 7h Reserved X 8h Selects Function GP4 9 I O 9h Fh Reserved X 23 20 PINMUX9_23_2...

Page 240: ...ue Description Type 1 11 8 PINMUX9_11_8 EMA_D 5 GP4 13 Control 0 Pin is 3 stated Z 1h Selects Function EMA_D 5 I O 2h 7h Reserved X 8h Selects Function GP4 13 I O 9h Fh Reserved X 7 4 PINMUX9_7_4 EMA_D 6 GP4 14 Control 0 Pin is 3 stated Z 1h Selects Function EMA_D 6 I O 2h 7h Reserved X 8h Selects Function GP4 14 I O 9h Fh Reserved X 3 0 PINMUX9_3_0 EMA_D 7 GP4 15 Control 0 Pin is 3 stated Z 1h Se...

Page 241: ...ter PINMUX10 Field Descriptions Bit Field Value Description Type 1 31 28 PINMUX10_31_28 EMA_A 16 MMCSD0_DAT 5 PRU1_R30 24 GP4 0 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A 16 O 2h Selects Function MMCSD0_DAT 5 I O 3h Reserved X 4h Selects Function PRU1_R30 24 O 5h 7h Reserved X 8h Selects Function GP4 0 I O 9h Fh Reserved X 27 24 PINMUX10_27_24 EMA_A 17 MMCSD0_DAT 4 PRU1_R30 25 GP4 1 Con...

Page 242: ...1 I O 3h Reserved X 4h Selects Function PRU1_R30 28 O 5h 7h Reserved X 8h Selects Function GP4 4 I O 9h Fh Reserved X 11 8 PINMUX10_11_8 EMA_A 21 MMCSD0_DAT 0 PRU1_R30 29 GP4 5 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A 21 O 2h Selects Function MMCSD0_DAT 0 I O 3h Reserved X 4h Selects Function PRU1_R30 29 O 5h 7h Reserved X 8h Selects Function GP4 5 I O 9h Fh Reserved X 7 4 PINMUX10_7_...

Page 243: ...8 PRU1_R30 16 GP5 8 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A 8 O 2h 3h Reserved X 4h Selects Function PRU1_R30 16 O 5h 7h Reserved X 8h Selects Function GP5 8 I O 9h Fh Reserved X 27 24 PINMUX11_27_24 EMA_A 9 PRU1_R30 17 GP5 9 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A 9 O 2h 3h Reserved X 4h Selects Function PRU1_R30 17 O 5h 7h Reserved X 8h Selects Function GP5 9 I O 9h F...

Page 244: ... 13 PRU1_R31 21 Control 0 Selects Function PRU1_R31 21 I 1h Selects Function EMA_A 13 O 2h Selects Function PRU0_R30 21 O 3h Reserved X 4h Selects Function PRU1_R30 21 O 5h 7h Reserved X 8h Selects Function GP5 13 I O 9h Fh Reserved X 7 4 PINMUX11_7_4 EMA_A 14 MMCSD0_DAT 7 PRU1_R30 22 GP5 14 PRU1_R31 22 Control 0 Selects Function PRU1_R31 22 I 1h Selects Function EMA_A 14 O 2h Selects Function MMC...

Page 245: ...ol 12 Register PINMUX12 Field Descriptions Bit Field Value Description Type 1 31 28 PINMUX12_31_28 EMA_A 0 GP5 0 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A 0 O 2h 7h Reserved X 8h Selects Function GP5 0 I O 9h Fh Reserved X 27 24 PINMUX12_27_24 EMA_A 1 GP5 1 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A 1 O 2h 7h Reserved X 8h Selects Function GP5 1 I O 9h Fh Reserved X 23 20 PI...

Page 246: ... PINMUX12_11_8 EMA_A 5 GP5 5 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A 5 O 2h 7h Reserved X 8h Selects Function GP5 5 I O 9h Fh Reserved X 7 4 PINMUX12_7_4 EMA_A 6 GP5 6 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A 6 O 2h 7h Reserved X 8h Selects Function GP5 6 I O 9h Fh Reserved X 3 0 PINMUX12_3_0 EMA_A 7 PRU1_R30 15 GP5 7 Control 0 Pin is 3 stated Z 1h Selects Function EMA_A...

Page 247: ...scriptions Bit Field Value Description Type 1 31 28 PINMUX13_31_28 PRU0_R30 26 UHPI_HRW UPP_CHA_WAIT GP6 8 PRU1_R31 17 Control 0 Selects Function PRU1_R31 17 I 1h Selects Function PRU0_R30 26 O 2h Selects Function UHPI_HRW I 3h Reserved X 4h Selects Function UPP_CHA_WAIT I O 5h 7h Reserved X 8h Selects Function GP6 8 I O 9h Fh Reserved X 27 24 PINMUX13_27_24 PRU0_R30 27 UHPI_HHWIL UPP_CHA_ENABLE G...

Page 248: ...eserved X 4h Selects Function PRU1_R30 11 O 5h 7h Reserved X 8h Selects Function GP6 12 I O 9h Fh Reserved X 11 8 PINMUX13_11_8 PRU0_R30 31 UHPI_HRDY PRU1_R30 12 GP6 13 Control 0 Pin is 3 stated Z 1h Selects Function PRU0_R30 31 O 2h Selects Function UHPI_HRDY O 3h Reserved X 4h Selects Function PRU1_R30 12 O 5h 7h Reserved X 8h Selects Function GP6 13 I O 9h Fh Reserved X 7 4 PINMUX13_7_4 CLKOUT ...

Page 249: ...MUX14_31_28 VP_DIN 2 UHPI_HD 10 UPP_D 10 RMII_RXER PRU0_R31 24 Control 0 Selects Function PRU0_R31 24 I 1h Selects Function VP_DIN 2 I 2h Selects Function UHPI_HD 10 I O 3h Reserved X 4h Selects Function UPP_D 10 I O 5h 7h Reserved X 8h Selects Function RMII_RXER I 9h Fh Reserved X 27 24 PINMUX14_27_24 VP_DIN 3 UHPI_HD 11 UPP_D 11 RMII_RXD 0 PRU0_R31 25 Control 0 Selects Function PRU0_R31 25 I 1h ...

Page 250: ...ects Function UPP_D 14 I O 5h 7h Reserved X 8h Selects Function RMII_TXD 0 O 9h Fh Reserved X 11 8 PINMUX14_11_8 VP_DIN 7 UHPI_HD 15 UPP_D 15 RMII_TXD 1 PRU0_R31 29 Control 0 Selects Function PRU0_R31 29 I 1h Selects Function VP_DIN 7 I 2h Selects Function UHPI_HD 15 I O 3h Reserved X 4h Selects Function UPP_D 15 I O 5h 7h Reserved X 8h Selects Function RMII_TXD 1 O 9h Fh Reserved X 7 4 PINMUX14_7...

Page 251: ...UX15_31_28 VP_DIN 10 UHPI_HD 2 UPP_D 2 PRU0_R30 10 PRU0_R31 10 Control 0 Selects Function PRU0_R31 10 I 1h Selects Function VP_DIN 10 I 2h Selects Function UHPI_HD 2 I O 3h Reserved X 4h Selects Function UPP_D 2 I O 5h 7h Reserved X 8h Selects Function PRU0_R30 10 O 9h Fh Reserved X 27 24 PINMUX15_27_24 VP_DIN 11 UHPI_HD 3 UPP_D 3 PRU0_R30 11 PRU0_R31 11 Control 0 Selects Function PRU0_R31 11 I 1h...

Page 252: ...HPI_HD 6 UPP_D 6 PRU0_R30 14 PRU0_R31 14 Control 0 Selects Function PRU0_R31 14 I 1h Selects Function VP_DIN 14 _HSYNC I 2h Selects Function UHPI_HD 6 I O 3h Reserved X 4h Selects Function UPP_D 6 I O 5h 7h Reserved X 8h Selects Function PRU0_R30 14 O 9h Fh Reserved X 11 8 PINMUX15_11_8 VP_DIN 15 _VSYNC UHPI_HD 7 UPP_D 7 PRU0_R30 15 PRU0_R31 15 Control 0 Selects Function PRU0_R31 15 I 1h Selects F...

Page 253: ...ects Function PRU0_R31 23 Enables sourcing of the 50 MHz reference clock from an external source on the RMII_MHZ_50_CLK pin to the EMAC I 1h Selects Function VP_DIN 1 I 2h Selects Function UHPI_HD 9 I O 3h Reserved X 4h Selects Function UPP_D 9 I O 5h 7h Reserved X 8h Selects Function RMII_MHZ_50_CLK Enables sourcing of the 50 MHz reference clock from PLL0_SYSCLK7 to the EMAC Also PLL0_SYSCLK7 is ...

Page 254: ...ield Value Description Type 1 31 28 PINMUX16_31_28 VP_DOUT 2 LCD_D 2 UPP_XD 10 GP7 10 PRU1_R31 10 Control 0 Selects Function PRU1_R31 10 I 1h Selects Function VP_DOUT 2 O 2h Selects Function LCD_D 2 I O 3h Reserved X 4h Selects Function UPP_XD 10 I O 5h 7h Reserved X 8h Selects Function GP7 10 I O 9h Fh Reserved X 27 24 PINMUX16_27_24 VP_DOUT 3 LCD_D 3 UPP_XD 11 GP7 11 PRU1_R31 11 Control 0 Select...

Page 255: ...lects Function UPP_XD 14 I O 5h 7h Reserved X 8h Selects Function GP7 14 I O 9h Fh Reserved X 11 8 PINMUX16_11_8 VP_DOUT 7 LCD_D 7 UPP_XD 15 GP7 15 PRU1_R31 15 Control 0 Selects Function PRU1_R31 15 I 1h Selects Function VP_DOUT 7 O 2h Selects Function LCD_D 7 I O 3h Reserved X 4h Selects Function UPP_XD 15 I O 5h 7h Reserved X 8h Selects Function GP7 15 I O 9h Fh Reserved X 7 4 PINMUX16_7_4 VP_DI...

Page 256: ...scription Type 1 31 28 PINMUX17_31_28 VP_DOUT 10 LCD_D 10 UPP_XD 2 GP7 2 BOOT 2 Control 0 Selects Function BOOT 2 I 1h Selects Function VP_DOUT 10 O 2h Selects Function LCD_D 10 I O 3h Reserved X 4h Selects Function UPP_XD 2 I O 5h 7h Reserved X 8h Selects Function GP7 2 I O 9h Fh Reserved X 27 24 PINMUX17_27_24 VP_DOUT 11 LCD_D 11 UPP_XD 3 GP7 3 BOOT 3 Control 0 Selects Function BOOT 3 I 1h Selec...

Page 257: ...lects Function UPP_XD 6 I O 5h 7h Reserved X 8h Selects Function GP7 6 I O 9h Fh Reserved X 11 8 PINMUX17_11_8 VP_DOUT 15 LCD_D 15 UPP_XD 7 GP7 7 BOOT 7 Control 0 Selects Function BOOT 7 I 1h Selects Function VP_DOUT 15 O 2h Selects Function LCD_D 15 I O 3h Reserved X 4h Selects Function UPP_XD 7 I O 5h 7h Reserved X 8h Selects Function GP7 7 I O 9h Fh Reserved X 7 4 PINMUX17_7_4 VP_DOUT 0 LCD_D 0...

Page 258: ...tion Type 1 31 28 PINMUX18_31_28 MMCSD1_DAT 6 LCD_MCLK PRU1_R30 6 GP8 10 PRU1_R31 7 Control 0 Selects Function PRU1_R31 7 I 1h Selects Function MMCSD1_DAT 6 I O 2h Selects Function LCD_MCLK O 3h Reserved X 4h Selects Function PRU1_R30 6 O 5h 7h Reserved X 8h Selects Function GP8 10 I O 9h Fh Reserved X 27 24 PINMUX18_27_24 MMCSD1_DAT 7 LCD_PCLK PRU1_R30 7 GP8 11 Control 0 Pin is 3 stated Z 1h Sele...

Page 259: ...s Function MMCSD1_CLK O 3h Reserved X 4h Selects Function UPP_CHB_START I O 5h 7h Reserved X 8h Selects Function GP8 14 I O 9h Fh Reserved X 11 8 PINMUX18_11_8 PRU0_R30 25 MMCSD1_DAT 0 UPP_CHB_CLOCK GP8 15 PRU1_R31 27 Control 0 Selects Function PRU1_R31 27 I 1h Selects Function PRU0_R30 25 O 2h Selects Function MMCSD1_DAT 0 I O 3h Reserved X 4h Selects Function UPP_CHB_CLOCK I O 5h 7h Reserved X 8...

Page 260: ...Type 1 31 28 PINMUX19_31_28 RTCK GP8 0 Control 0 Selects Function RTCK O 1h Selects Function RTCK O 2h 7h Reserved X 8h Selects Function GP8 0 I O 9h Fh Reserved X 27 24 PINMUX19_27_24 LCD_AC_ENB_CS GP6 0 PRU1_R31 28 Control 0 Selects Function PRU1_R31 28 I 1h Reserved X 2h Selects Function LCD_AC_ENB_CS O 3h 7h Reserved X 8h Selects Function GP6 0 I O 9h Fh Reserved X 23 20 PINMUX19_23_20 VP_CLKO...

Page 261: ... MMCSD1_DAT 3 PRU1_R30 3 GP6 4 PRU1_R31 4 Control 0 Selects Function PRU1_R31 4 I 1h Selects Function VP_CLKIN2 I 2h Selects Function MMCSD1_DAT 3 I O 3h Reserved X 4h Selects Function PRU1_R30 3 O 5h 7h Reserved X 8h Selects Function GP6 4 I O 9h Fh Reserved X 7 4 PINMUX19_7_4 MMCSD1_DAT 4 LCD_VSYNC PRU1_R30 4 GP8 8 PRU1_R31 5 Control 0 Selects Function PRU1_R31 5 I 1h Selects Function MMCSD1_DAT...

Page 262: ...1 7 6 5 4 3 2 1 0 MCBSP0SRC PRUSRC EMACSRC UPPSRC TIMER64P_3SRC ECAP2SRC ECAP1SRC ECAP0SRC R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 LEGEND R W Read Write n value after reset Table 10 42 Suspend Source Register SUSPSRC Field Descriptions Bit Field Value Description 31 30 Reserved 1 Reserved Write the default value to all bits when modifying this register 29 TIMER64P_2SRC Timer2 64 Emulation ...

Page 263: ...nd Source 0 ARM is the source of the emulation suspend 1 No emulation suspend 13 SATASRC SATA Emulation Suspend Source 0 ARM is the source of the emulation suspend 1 No emulation suspend 12 HPISRC HPI Emulation Suspend Source 0 ARM is the source of the emulation suspend 1 No emulation suspend 11 10 Reserved 1 Reserved Write the default value to all bits when modifying this register 9 USB0SRC USB0 ...

Page 264: ... Source Register SUSPSRC Field Descriptions continued Bit Field Value Description 2 ECAP2SRC ECAP2 Emulation Suspend Source 0 ARM is the source of the emulation suspend 1 No emulation suspend 1 ECAP1SRC ECAP1 Emulation Suspend Source 0 ARM is the source of the emulation suspend 1 No emulation suspend 0 ECAP0SRC ECAP0 Emulation Suspend Source 0 ARM is the source of the emulation suspend 1 No emulat...

Page 265: ...described in Table 10 43 Figure 10 39 Chip Signal Register CHIPSIG 31 16 Reserved R 0 15 5 4 3 2 1 0 Reserved Rsvd CHIPSIG3 CHIPSIG2 CHIPSIG1 CHIPSIG0 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 10 43 Chip Signal Register CHIPSIG Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 Reserved 0 Reserved Write the default value wh...

Page 266: ...completed the interrupt service The CHIPSIG_CLR is shown in Figure 10 40 and described in Table 10 44 For more information on ARM interrupts see the ARM Interrupt Controller AINTC chapter Figure 10 40 Chip Signal Clear Register CHIPSIG_CLR 31 16 Reserved R 0 15 5 4 3 2 1 0 Reserved Rsvd CHIPSIG3 CHIPSIG2 CHIPSIG1 CHIPSIG0 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value ...

Page 267: ... level as all transfer requests are internally broken down by the transfer controller up to DBS size byte chunks and on a system level each master s priority configured by the MSTPRI register is evaluated at burst size boundaries The DBS value can significantly impact the standalone throughput performance depending on the source and destination bus width frequency burst support etc and the TC FIFO...

Page 268: ... the intra packet efficiency for the EDMA3_1 transfers Additionally it also facilitates preemption at a system level as all transfer requests are internally broken down by the transfer controller up to DBS size byte chunks and on a system level each master s priority configured by the MSTPRI register is evaluated at burst size boundaries The DBS value can significantly impact the standalone throug...

Page 269: ...MAC C1 RX Pulse Interrupt Dh EMAC C1 TX Pulse Interrupt Eh EMAC C1 Miscellaneous Interrupt Fh EMAC C2 RX Threshold Pulse Interrupt 10h EMAC C2 RX Pulse Interrupt 11h EMAC C2 TX Pulse Interrupt 12h EMAC C2 Miscellaneous Interrupt 13h 1Fh Reserved 26 22 CAP1SRC Selects the eCAP1 module event input 0 eCAP1 Pin input 1h McASP0 TX DMA Event 2h McASP0 RX DMA Event 3h 6h Reserved 7h EMAC C0 RX Threshold ...

Page 270: ...elect 0 Host address is a word address 1 Host address is a byte address 15 HPIENA HPI Enable Bit 0 HPI is disabled 1 HPI is enabled 14 13 EDMA31TC0DBS EDMA3_1_TC0 Default Burst Size 0 16 bytes 1h 32 bytes 2h 64 bytes 3h Reserved 12 TBCLKSYNC eHRPWM Module Time Base Clock Synchronization Allows you to globally synchronize all enabled eHRPWM modules to the time base clock TBCLK 0 Time base clock TBC...

Page 271: ...Clock is not present power is not good and PLL has not locked 1 Clock is present power is good and PLL has locked 16 USB0VBUSSENSE Status of USB2 0 PHY VBUS sense 0 PHY is not sensing voltage presence on the VBUS pin 1 PHY is sensing voltage presence on the VBUS pin 15 RESET USB2 0 PHY reset 0 Not in reset 1 USB2 0 PHY in reset 14 13 USB0OTGMODE USB2 0 OTG subsystem mode 0 No override PHY drive si...

Page 272: ...not altered USB_DP is connected to D and USB_DM is connected to D 7 USB1SUSPENDM USB1 1 suspend mode 0 Needs to be 0 whenever USB1 1 PHY is unpowered 1 Enable USB1 1 PHY 6 USB0PHY_PLLON Drives USB2 0 PHY allowing or preventing it from stopping the 48 MHz clock during USB SUSPEND 0 USB2 0 PHY is allowed to stop the 48 MHz clock during USB SUSPEND 1 USB2 0 PHY is prevented from stopping the 48 MHz c...

Page 273: ...trol for the source of the EMIFA module clock The CFGCHIP3 is shown in Figure 10 44 and described in Table 10 48 Figure 10 44 Chip Configuration 3 Register CFGCHIP3 31 16 Reserved R 0 15 9 8 Reserved RMII_SEL R W 7Fh R W 1 7 6 5 4 3 2 1 0 Reserved UPP_TX_CLKSRC PLL1_MASTER_LOCK ASYNC3_CLKSRC PRUEVTSEL DIV45PENA EMA_CLKSRC Reserved R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Wri...

Page 274: ...gister CFGCHIP4 is used for clearing the AMUNTEIN signal for McASP0 Writing a 1 causes a single pulse that clears the latched GPIO interrupt for AMUTEIN of McASP0 if it was previously set reads always return a value of 0 The CFGCHIP4 is shown in Figure 10 45 and described in Table 10 49 Figure 10 45 Chip Configuration 4 Register CFGCHIP4 31 16 Reserved R 0 15 8 7 1 0 Reserved Reserved AMUTECLR0 R ...

Page 275: ...iption 31 19 Reserved 0 Reserved 18 VREFEN Internal DDR I O Vref enable 0 Connected to pad external reference 1 Reserved 17 16 VREFTAP Selection for internal reference voltage level 0 Vref 50 0 of VDDS 1h 3h Reserved 15 READY VTP Ready status 0 VTP is not ready 1 VTP is ready 14 IOPWRDN Power down enable for DDR input buffer 0 Disable power down control by the PWRDNEN bit in the DDR PHY control re...

Page 276: ...Texas Instruments Incorporated System Configuration SYSCFG Module Table 10 50 VTP I O Control Register VTPIO_CTL Field Descriptions continued Bit Field Value Description 5 3 D Drive strength control bit 0 5h Reserved 6h 100 drive strength 7h Reserved 2 0 F Digital filter control bit 0 6h Reserved 7h Digital filter is enabled ...

Page 277: ...ption 31 12 Reserved 0 Reserved 11 10 ODT_TERMON Controls Thevenin termination mode while I O is in read or write mode Termination is not supported on this device 0 No termination 1h 3h Reserved 9 8 ODT_TERMOFF Controls Thevenin termination mode while I O is not in read or write mode Termination is not supported on this device 0 No termination 1h 3h Reserved 7 6 Reserved 0 Reserved 5 DDR_PDENA Ena...

Page 278: ...er reset Table 10 52 Deep Sleep Register DEEPSLEEP Field Descriptions Bit Field Value Description 31 SLEEPENABLE Deep sleep enable The software must clear this bit to 0 when the device is awakened from deep sleep 0 Device is in normal operating mode DEEPSLEEP pin has no effect 1 Deep sleep mode is enabled setting DEEPSLEEP pin low initiates oscillator shut down 30 SLEEPCOMPLETE Deep sleep complete...

Page 279: ...r pin group n is disabled 1 Internal pull up or pull down functionality for pin group n is enabled 10 5 23 Pullup Pulldown Select Register PUPD_SEL The pullup pulldown select register PUPD_SEL selects between the pull up or pull down functionality for the pin group n defined in your device specific data manual The PUPD_SEL is shown in Figure 10 50 and described in Table 10 54 and Table 10 55 NOTE ...

Page 280: ...EL 19 1 Pin Group CP 19 is configured for pull up by default 18 PUPDSEL 18 1 Pin Group CP 18 is configured for pull up by default 17 PUPDSEL 17 1 Pin Group CP 17 is configured for pull up by default 16 PUPDSEL 16 1 Pin Group CP 16 is configured for pull up by default 15 PUPDSEL 15 1 Pin Group CP 15 is configured for pull up by default 14 PUPDSEL 14 1 Pin Group CP 14 is configured for pull up by de...

Page 281: ...ual for pin group information Receivers should only be disabled if the associated pin group is not being used 0 LVCMOS receivers for pin group n are disabled 1 LVCMOS receivers for pin group n are enabled 10 5 25 Power Down Control Register PWRDN The power down control register PWRDN enables or disables the SATA clock receiver The PWRDN is shown in Figure 10 52 and described in Table 10 57 Figure ...

Page 282: ...Copyright 2013 2016 Texas Instruments Incorporated ARM Interrupt Controller AINTC Chapter 11 SPRUH82C April 2013 Revised September 2016 ARM Interrupt Controller AINTC Topic Page 11 1 Introduction 283 11 2 Interrupt Mapping 283 11 3 AINTC Methodology 286 11 4 AINTC Registers 290 ...

Page 283: ...upt can be enabled and disabled Hardware prioritization of interrupts Combining of interrupts from IPs to a single system interrupt Supports two active low debug interrupts See the ARM926EJ Technical Reference Manual for information about the ARM s FIQ and IRQ interrupts 11 2 Interrupt Mapping The AINTC supports up to 101 system interrupts from different peripherals to be mapped to 32 channels ins...

Page 284: ...C Interrupt 20 SPI0_INT SPI0 Interrupt 21 T64P0_TINT12 Timer64P0 Interrupt TINT12 22 T64P0_TINT34 Timer64P0 Interrupt TINT34 23 T64P1_TINT12 Timer64P1 Interrupt TINT12 24 T64P1_TINT34 Timer64P1 Interrupt TINT34 25 UART0_INT UART0 Interrupt 26 Reserved 27 PROTERR SYSCFG Protection Shared Interrupt 28 SYSCFG_CHIPINT0 SYSCFG CHIPSIG Register 29 SYSCFG_CHIPINT1 SYSCFG CHIPSIG Register 30 SYSCFG_CHIPIN...

Page 285: ...67 SATA_INT SATA Controller Interrupt 68 T64P2_ALL Timer64P2 Combined Interrupt TINT12 and TINT34 69 ECAP0 eCAP0 Interrupt 70 ECAP1 eCAP1 Interrupt 71 ECAP2 eCAP2 Interrupt 72 MMCSD1_INT0 MMCSD1 MMC SD Interrupt 73 MMCSD1_INT1 MMCSD1 SDIO Interrupt 74 T64P2_CMPINT0 Timer64P2 Compare Interrupt 0 75 T64P2_CMPINT1 Timer64P2 Compare Interrupt 1 76 T64P2_CMPINT2 Timer64P2 Compare Interrupt 2 77 T64P2_C...

Page 286: ... device peripherals The AINTC receives the system interrupts and maps them to internal channels The channels are used to combine and prioritize system interrupts These channels are then mapped onto the host interface that is typically a smaller number of host interrupts or a vector input Interrupts from system side are active high in polarity Also they are pulse type of interrupts The AINTC encomp...

Page 287: ...of system interrupt N is indicated by the Nth bit of SECR1 SECR4 Since there exists 101 system interrupts four 32 bit registers are used to capture the enabled status of interrupts The pending status reflects whether the system interrupt occurred since the last time the status register bit was cleared Each bit in the status register is individually clearable 11 3 4 Interrupt Channel Mapping The AI...

Page 288: ...et the active interrupt index to the host interrupt enable index set register HIEISR 5 Write clear the active interrupt index to the host interrupt enable index clear register HIEICR 11 3 7 Interrupt Nesting If interrupt service routines ISRs consume a large number of CPU cycles and may delay the servicing of other interrupts the AINTC can perform a nesting function in its prioritization Nesting i...

Page 289: ...ter n SECRn or by writing the appropriate index to the system interrupt status indexed clear register SICR 7 Acknowledge and enable the ARM hardware interrupt 8 Execute the ISR at the address stored from step 5 During this step interrupts enabled by the new nest priority level will be able to preempt the ISR 9 Disable the ARM hardware interrupt 10 Discard the most recent priority level in the nest...

Page 290: ...1 4 5 FFFE E024h SICR System Interrupt Status Indexed Clear Register Section 11 4 6 FFFE E028h EISR System Interrupt Enable Indexed Set Register Section 11 4 7 FFFE E02Ch EICR System Interrupt Enable Indexed Clear Register Section 11 4 8 FFFE E034h HIEISR Host Interrupt Enable Indexed Set Register Section 11 4 9 FFFE E038h HIEICR Host Interrupt Enable Indexed Clear Register Section 11 4 10 FFFE E0...

Page 291: ...2 Section 11 4 34 FFFE F100h HINLR1 Host Interrupt Nesting Level Register 1 Section 11 4 35 FFFE F104h HINLR2 Host Interrupt Nesting Level Register 2 Section 11 4 36 FFFE F500h HIER Host Interrupt Enable Register Section 11 4 37 FFFE F600h HIPVR1 Host Interrupt Prioritized Vector Register 1 Section 11 4 38 FFFE F604h HIPVR2 Host Interrupt Prioritized Vector Register 2 Section 11 4 39 11 4 1 Revisi...

Page 292: ...eserved R 0 R W 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 11 4 Control Register CR Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 PRHOLDMODE Enables priority holding mode 0 No priority holding Prioritized MMRs will continually update 1 Priority holding enabled Prioritized Index and Vector Address MMRs will hold their value after the first is...

Page 293: ...bal enable 11 4 4 Global Nesting Level Register GNLR The global nesting level register GNLR allows the checking and setting of the global nesting level across all host interrupts when automatic global nesting mode is set The nesting level is the channel and all of lower priority that are nested out because of a current interrupt The GNLR is shown in Figure 11 6 and described in Table 11 6 Figure 1...

Page 294: ...d Set Register SISR Field Descriptions Bit Field Value Description 31 7 Reserved 0 Reserved 6 0 INDEX 0 7Fh Writes set the status of the interrupt given in the INDEX value Reads return 0 11 4 6 System Interrupt Status Indexed Clear Register SICR The system interrupt status indexed clear register SICR allows clearing the status of an interrupt The interrupt to clear is the INDEX value written This ...

Page 295: ...Set Register EISR Field Descriptions Bit Field Value Description 31 7 Reserved 0 Reserved 6 0 INDEX 0 7Fh Writes set the enable of the interrupt given in the INDEX value Reads return 0 11 4 8 System Interrupt Enable Indexed Clear Register EICR The system interrupt enable indexed clear register EICR allows disabling an interrupt The interrupt to disable is the INDEX value written This clears the En...

Page 296: ...eld Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 INDEX Writes set the enable of the host interrupt given in the INDEX value Reads return 0 0 Writing a 0 sets FIQ 1 Writing a 1 sets IRQ 11 4 10 Host Interrupt Enable Indexed Clear Register HIEICR The host interrupt enable indexed clear register HIEICR allows disabling a host interrupt output The host interrupt to disable is th...

Page 297: ... 4 12 Vector Size Register VSR The vector size register VSR holds the sizes of the individual ISR routines in the vector table This is only the sizes to space the calculated vector addresses for the initial ISR targets the ISR targets could branch off to the full ISR routines The VSR is shown in Figure 11 14 and described in Table 11 14 NOTE The VSR must be configured even if the desired value is ...

Page 298: ... Description 31 0 NULL 0 FFFF FFFFh ISR Null Address 11 4 14 Global Prioritized Index Register GPIR The global prioritized index register GPIR shows the interrupt number of the highest priority interrupt pending across all the host interrupts The GPIR is shown in Figure 11 16 and described in Table 11 16 Figure 11 16 Global Prioritized Index Register GPIR 31 30 16 NONE Reserved R 1 R 0 15 10 9 0 R...

Page 299: ...tly highest priority interrupts vector address across all the host interrupts 11 4 16 System Interrupt Status Raw Set Register 1 SRSR1 The system interrupt status raw set register 1 SRSR1 shows the pending enabled status of the system interrupts 0 to 31 Software can write to SRSR1 to set a system interrupt without a hardware trigger There is one bit per system interrupt The SRSR1 is shown in Figur...

Page 300: ...upt raw status and setting of the system interrupts 32 to 63 Reads return the raw status 0 Writing a 0 has no effect 1 Write a 1 in bit position n to set the status of the system interrupt n 32 11 4 18 System Interrupt Status Raw Set Register 3 SRSR3 The system interrupt status raw set register 3 SRSR3 shows the pending enabled status of the system interrupts 64 to 95 Software can write to SRSR3 t...

Page 301: ...atus 0 Writing a 0 has no effect 1 Write a 1 in bit position n to set the status of the system interrupt n 96 11 4 20 System Interrupt Status Enabled Clear Register 1 SECR1 The system interrupt status enabled clear register 1 SECR1 shows the pending enabled status of the system interrupts 0 to 31 Software can write to SECR1 to clear a system interrupt after it has been serviced If a system interru...

Page 302: ...pts 32 to 63 Reads return the enabled status before enabling with the Enable Registers 0 Writing a 0 has no effect 1 Write a 1 in bit position n to clear the status of the system interrupt n 32 11 4 22 System Interrupt Status Enabled Clear Register 3 SECR3 The system interrupt status enabled clear register 3 SECR3 shows the pending enabled status of the system interrupts 64 to 95 Software can writ...

Page 303: ...led Clear Register 4 SECR4 Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 0 ENBL_STATUS n System interrupt enabled status and clearing of the system interrupts 96 to 100 Reads return the enabled status before enabling with the Enable Registers 0 Writing a 0 has no effect 1 Write a 1 in bit position n to clear the status of the system interrupt n 96 11 4 24 System Interru...

Page 304: ...NABLE n System interrupt 32 to 63 enable Read returns the enable value 0 disabled 1 enabled 0 Writing a 0 has no effect 1 Write a 1 in bit position n to set the enable for system interrupt n 32 11 4 26 System Interrupt Enable Set Register 3 ESR3 The system interrupt enable set register 3 ESR3 enables system interrupts 64 to 95 to trigger outputs System interrupts that are not enabled do not interr...

Page 305: ...erved 0 Reserved 4 0 ENABLE n System interrupt 96 to 100 enable Read returns the enable value 0 disabled 1 enabled 0 Writing a 0 has no effect 1 Write a 1 in bit position n to set the enable for system interrupt n 96 11 4 28 System Interrupt Enable Clear Register 1 ECR1 The system interrupt enable clear register 1 ECR1 disables system interrupts 0 to 31 to map to channels System interrupts that ar...

Page 306: ...LE n System interrupt 32 to 63 disable Read returns the enable value 0 disabled 1 enabled 0 Writing a 0 has no effect 1 Write a 1 in bit position n to clear the enable for system interrupt n 32 11 4 30 System Interrupt Enable Clear Register 3 ECR3 The system interrupt enable clear register 3 ECR3 disables system interrupts 64 to 95 to map to channels System interrupts that are not enabled do not i...

Page 307: ... 0 Reserved 4 0 DISABLE n System interrupt 96 to 100 disable Read returns the enable value 0 disabled 1 enabled 0 Writing a 0 has no effect 1 Write a 1 in bit position n to clear the enable for system interrupt n 96 11 4 32 Channel Map Registers CMR0 CMR25 The channel map registers CMR0 CMR25 define the channel for each system interrupt There is one register per 4 system interrupts The CMRn is sho...

Page 308: ...s Bit Field Value Description 31 NONE 0 1 No Interrupt is pending 30 10 Reserved 0 Reserved 9 0 PRI_INDX 0 3FFh Interrupt number of the highest priority pending interrupt for FIQ host interrupt 11 4 34 Host Interrupt Prioritized Index Register 2 HIPIR2 The host interrupt prioritized index register 2 HIPIR2 shows the highest priority current pending interrupt for the IRQ interrupt The HIPIR2 is sho...

Page 309: ... level for the FIQ host interrupt Writes set the nesting level for the FIQ host interrupt In auto mode the value is updated internally unless the OVERRIDE is set and then the write data is used 11 4 36 Host Interrupt Nesting Level Register 2 HINLR2 The host interrupt nesting level register 2 HINLR2 displays and controls the nesting level for IRQ host interrupt The nesting level controls which chan...

Page 310: ... These bits are updated when writing to the host interrupt enable indexed set register HIEISR and the host interrupt disable indexed clear register HIDISR The HIER is shown in Figure 11 39 and described in Table 11 39 Figure 11 39 Host Interrupt Enable Register HIER 31 16 Reserved R 0 15 2 1 0 Reserved IRQ FIQ R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 11 39 Host I...

Page 311: ...oritized Vector Register 1 HIPVR1 Field Descriptions Bit Field Value Description 31 0 ADDR 0 FFFF FFFFh The currently highest priority interrupt vector address across for the FIQ host interrupt 11 4 39 Host Interrupt Prioritized Vector Register 2 HIPVR2 The host interrupt prioritized vector register 2 HIPVR2 shows the interrupt vector address of the highest priority interrupt pending for IRQ host ...

Page 312: ...vised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Boot Considerations Chapter 12 SPRUH82C April 2013 Revised September 2016 Boot Considerations Topic Page 12 1 Introduction 313 ...

Page 313: ...he system configuration SYSCFG module when device reset is deasserted Boot mode selection is determined by the values of the BOOT pins The following boot modes are supported NAND Flash boot 8 bit NAND 16 bit NAND NOR Flash boot NOR Direct boot 8 bit or 16 bit NOR Legacy boot 8 bit or 16 bit NOR AIS boot 8 bit or 16 bit HPI boot I2C0 I2C1 boot EEPROM Master Mode External Host Slave Mode SPI0 SPI1 b...

Page 314: ... Real Time Unit Subsystem PRUSS Chapter 13 SPRUH82C April 2013 Revised September 2016 Programmable Real Time Unit Subsystem PRUSS Topic Page 13 1 Overview 315 13 2 Description 317 13 3 Constants Table 318 13 4 PRU Module Interface 319 13 5 Instruction Set 320 13 6 Instruction Formats 323 13 7 PRU Interrupt Controller 341 13 8 Registers 348 ...

Page 315: ...ween the two PRUs and the device level host CPU The two PRUs are optimized for performing embedded tasks that require manipulation of packed memory mapped data structures handling of system events that have tight real time constraints and interfacing with systems external to the device 13 1 Overview The PRU is a optimized for performing embedded tasks that require manipulation of packed memory map...

Page 316: ...ory Register Base Register Offset Register Base 8 bit Immediate Offset Register Base with auto increment decrement Constant Table Base Register Offset Constant Table Base 8 bit Immediate Offset Constant Table Base with auto increment decrement Data Path Width 32 Bits Instruction Width 32 Bits Accessibility to Internal PRU Structures Provides 32 bit Slave with 3 regions Instruction RAM Control Stat...

Page 317: ...ed on a four bus architecture which allows instructions to be fetched and executed concurrently with data transfers Additionally an input is provided in order to allow external status information to be reflected in the internal processor status register The figure below shows a block diagram of the processing element and the associated instruction RAM ROM that contains the code that is to be execu...

Page 318: ...s are just ones that are expected to be commonly used enough so to be hard coded into the PRU constants table 2 Constants table entries 24 through 31 are not fully hard coded but contain a programmable bitfield ex c24_blk_index 3 0 that is programmable through the PRU control register space 0x01C3_7000 0x01C3_73FF for PRU0 and 0x01C3_7800 0x01C3_7BFF for PRU1 Table 13 1 Constants Table 1 Entry Reg...

Page 319: ...e other PRU The host to be signaled is determined by the system interrupt to interrupt channel mapping programmable Refer to Section 13 7 for more details 13 4 2 Status Mapping R31 Interrupt Events Input The PRU Real Time Status Interface directly feeds information into register 31 R31 of the PRU s internal register file The firmware on the PRU uses the status information to make decisions during ...

Page 320: ...s into internal register s using a register as the base address and a register or an 8 bit immediate as the offset 1 WdCnt VBUS 2 WdCnt VBUSP SBBO Store Burst Base Offset Store variable length burst of bytes through one of the memory interfaces from internal register s using a register as the base address and a register or 8 bit immediate as the offset 1 WdCnt LBCO Load Burst Constant Offset Load ...

Page 321: ... with a bit specied by the 5 LSBs of Op2 cleared during the copy 1 SET Set Bit Copies Rs1 to Rd but with a bit specied by the 5 LSBs of Op2 set during the copy 1 LMBD Left most Bit Detect Scans Rs1 from the leftmost bit for a bit equal to bit 0 of Rs2 When found the bit number 0 to 31 is written to Rd If not found the value 32 is written to Rd 1 SCAN Scan Register File Scans the register file for ...

Page 322: ... the program counter if Op2 is less than Rs1 1 QBLE Quick Branch Less Than or Equal Compares Op2 to Rs1 and adds BrOff to the program counter if Op2 is less than or equal to Rs1 1 QBEQ Quick Branch Equal Compares Op2 to Rs1 and adds BrOff to the program counter if Op2 is equal to Rs1 1 QBNE Quick Branch Not Equal Compares Op2 to Rs1 and adds BrOff to the program counter if Op2 is not equal to Rs1 ...

Page 323: ...D 9 OR 10 XOR 11 NOT 12 MIN 13 MAX 14 CLR 15 SET 24 IO 0 Op2 is a register 23 21 Rs2Sel 0 Select bits 7 0 from the source register 2 1 Select bits 15 8 from the source register 2 2 Select bits 23 16 from the source register 2 3 Select bits 31 24 from the source register 2 4 Select bits 15 0 from the source register 2 5 Select bits 23 8 from the source register 2 6 Select bits 31 16 from the source...

Page 324: ...scription 7 5 RdSel 0 Select bits 7 0 of the destination register 1 Select bits 15 8 of the destination register 2 Select bits 23 16 of the destination register 3 Select bits 31 24 of the destination register 4 Select bits 15 0 of the destination register 5 Select bits 23 8 of the destination register 6 Select bits 31 16 of the destination register 7 Select bits 31 0 of the destination register 4 ...

Page 325: ...d 2 15 13 Rs1Sel 0 Select bits 7 0 from the source register 1 1 Select bits 15 8 from the source register 1 2 Select bits 23 16 from the source register 1 3 Select bits 31 24 from the source register 1 4 Select bits 15 0 from the source register 1 5 Select bits 23 8 from the source register 1 6 Select bits 31 16 from the source register 1 7 Select bits 31 0 from the source register 1 12 8 Rs1 0 31...

Page 326: ...ng represents the 7 most significant bits of all format 2 instructions Figure 13 4 Format 2 31 29 28 25 24 0 OP SUBOB RESERVED LEGEND R W Read Write R Read only n value after reset Table 13 9 Format 2 Bit Field Description 31 29 OP 0b001 Specifies Format 2 28 25 SUBOB 0 JMP 1 JAL 2 LDI 3 LMBD 4 SCAN 5 HALT 6 currently reserved for MVIx 7 13 RESERVED 14 currently reserved for RFI Return From Interr...

Page 327: ...ct bits 31 24 from the source register 2 4 Select bits 15 0 from the source register 2 5 Select bits 23 8 from the source register 2 6 Select bits 31 16 from the source register 2 7 Select bits 31 0 from the source register 2 20 16 Rs2 0 31 This field selects the register number which contains the value to be copied to the program counter 15 8 RESERVED 7 5 RdSel 0 Select bits 7 0 of the destinatio...

Page 328: ...L Jump and Link 24 IO 1 Jump operand is a 16 bit immediate value 23 8 Imm 0h FFFFh This field is the 16 bit immediate value to be copied to the program counter 7 5 RdSel 0 Select bits 7 0 of the destination register 1 Select bits 15 8 of the destination register 2 Select bits 23 16 of the destination register 3 Select bits 31 24 of the destination register 4 Select bits 15 0 of the destination reg...

Page 329: ... Select bits 23 16 of the destination register 3 Select bits 31 24 of the destination register 4 Select bits 15 0 of the destination register 5 Select bits 23 8 of the destination register 6 Select bits 31 16 of the destination register 7 Select bits 31 0 of the destination register 7 5 RdSel 0 Select bits 7 0 of the destination register 1 Select bits 15 8 of the destination register 2 Select bits...

Page 330: ... bits 7 0 from Rs2 1 Select bits 15 8 from Rs2 2 Select bits 23 16 from Rs2 3 Select bits 31 24 from Rs2 4 Select bits 15 0 from Rs2 5 Select bits 23 8 from Rs2 6 Select bits 31 16 from Rs2 7 Select bits 31 0 from Rs2 20 16 Rs2 0 31 Rs2 register number 0 31 15 13 Rs1Sel 0 Select bits 7 0 from Rs1 1 Select bits 15 8 from Rs1 2 Select bits 23 16 from Rs1 3 Select bits 31 24 from Rs1 4 Select bits 15...

Page 331: ...Specifies Format 2 28 25 SUBOB 3 Specifies LMBD 24 IO 1 Op2 is an 8 bit immediate 23 16 Imm2 0 255 Immediate for src2 15 13 Rs2Sel 0 Select bits 7 0 from Rs1 1 Select bits 15 8 from Rs1 2 Select bits 23 16 from Rs1 3 Select bits 31 24 from Rs1 4 Select bits 15 0 from Rs1 5 Select bits 23 8 from Rs1 6 Select bits 31 16 from Rs1 7 Select bits 31 0 from Rs1 12 8 Rs1 0 31 Rd register number 7 5 RdSel ...

Page 332: ...set Table 13 15 Format 2f SCAN Register Op2 Bit Field Description 31 29 OP 0b001 Specifies Format 2 28 25 SUBOB 4 Specifies SCAN 24 IO 0 Op2 is a register 23 21 Rs2Sel 0 Select bits 7 0 from Rs2 1 Select bits 15 8 from Rs2 2 Select bits 23 16 from Rs2 3 Select bits 31 24 from Rs2 4 Select bits 15 0 from Rs2 5 Select bits 23 8 from Rs2 6 Select bits 31 16 from Rs2 7 Select bits 31 0 from Rs2 20 16 ...

Page 333: ...l 7 Select bits 31 0 from Rs1 12 8 Rs1 0 31 Must be identical to Rd 7 5 RdSel 7 Select bits 31 0 from Rd 4 0 Rd 0 31 Rd register number 0 31 Figure 13 12 Format 2h HALT 31 29 28 25 24 0 OP SUBOP RESERVED LEGEND R W Read Write R Read only n value after reset Table 13 17 Format 2h HALT Bit Field Description 31 29 OP 0b001 Specifies Format 2 28 25 SUBOB 5 Specifies HALT 24 0 RESERVED Figure 13 13 For...

Page 334: ...et for the branch 24 IO 0 Op2 is a register 23 21 Rs2Sel 0 Select bits 7 0 from the source register 2 1 Select bits 15 8 from the source register 2 2 Select bits 23 16 from the source register 2 3 Select bits 31 24 from the source register 2 4 Select bits 15 0 from the source register 2 5 Select bits 23 8 from the source register 2 6 Select bits 31 16 from the source register 2 7 Select bits 31 0 ...

Page 335: ...branch should be taken if Op2 Rs1 1 27 LT 0 1 Less Than If set specifies that branch should be taken if Op2 Rs1 1 26 25 BrOff 9 8 0 3 This field contains the 2 MSBs of the 2s complement signed offset for the branch 24 IO 1 Op2 is an 8 bit immediate value 23 16 Imm 0 255 8 bit immediate value to be used as second operand to be compared 15 13 Rs1Sel 0 Select bits 7 0 from the source register 1 1 Sel...

Page 336: ...Rs2Sel 0 Select bits 7 0 from the source register 2 1 Select bits 15 8 from the source register 2 2 Select bits 23 16 from the source register 2 3 Select bits 31 24 from the source register 2 4 Select bits 15 0 from the source register 2 5 Select bits 23 8 from the source register 2 6 Select bits 31 16 from the source register 2 7 Select bits 31 0 from the source register 2 20 16 Rs2 0 31 This fie...

Page 337: ...If set specifies that branch should be taken if Rs1 Op2 4 0 0 1 26 25 BrOff 9 8 0 3 This field contains the 2 MSBs of the 2s complement signed offset for the branch 24 IO 1 Op2 is a 5 bit immediate value 23 21 RESERVED 20 16 Imm 0 31 This field selects the bit number of the first operand which is to be compared 15 13 Rs1Sel 0 Select bits 7 0 from the source register 1 1 Select bits 15 8 from the s...

Page 338: ...rom the offset register 1 Select bits 15 8 from the offset register 2 Select bits 23 16 from the offset register 3 Select bits 31 24 from the offset register 4 Select bits 15 0 from the offset register 5 Select bits 23 8 from the offset register 6 Select bits 31 16 from the offset register 7 Select bits 31 0 from the offset register 20 16 Ro 0 31 This field selects the register number which contai...

Page 339: ...mat 6a 6b 28 LoadStore 0 SBBO 1 LBBO 27 25 BurstLen 6 4 The following 3 fields specify the burst length in bytes for the transfer 24 IO 1 The offset is an immediate 8 bit value 23 16 Imm 0 255 Immediate 8 bit offset value 15 13 BurstLen 3 1 12 8 Rb 0 31 This field selects the register number which contains the base address for the transfer 7 BurstLen 0 0 123 byte count BurstLen 1 1 124 Bytes 124 b...

Page 340: ...e offset register 1 Select bits 15 8 from the offset register 2 Select bits 23 16 from the offset register 3 Select bits 31 24 from the offset register 4 Select bits 15 0 from the offset register 5 Select bits 23 8 from the offset register 6 Select bits 31 16 from the offset register 7 Select bits 31 0 from the offset register 20 16 Ro 0 31 This field selects the register number which contains the...

Page 341: ...bits 23 16 127 byte count R0 bits 31 24 6 5 RxByteAddr 0 3 This field selects the beginning byte number in the source destination register for the data transfer 4 0 Rx 0 30 This field selects the beginning source destination register number for the data transfer 13 7 PRU Interrupt Controller 13 7 1 Introduction The PRUSS interrupt controller INTC is an hardware interface between interrupts coming ...

Page 342: ...nnected to bit 31 in register 31 for PRU0 and PRU1 Host Interrupts 2 through 9 exported from PRUSS for signaling ARM and DSP interrupt controllers generating system Events PRUSS_EVTOUT0 to PRUSS_EVTOUT7 respectively Figure 13 22 13 7 3 PRUSS System Events System events 0 through 31 are external to the PRUSS subsystem and generated from different peripherals The source of the first 32 events from t...

Page 343: ...VT3 13 UART0 Interrupt Timer64P3_T12CMPEVT4 14 UART1 Interrupt Timer64P3_T12CMPEVT5 15 I2C0 Interrupt Timer64P3_T12CMPEVT6 16 I2C1 Interrupt Timer64P3_T12CMPEVT7 17 UART2 Interrupt Timer64P0_T12CMPEVT0 or Timer64P0_T12CMPEVT1 or Timer64P0_T12CMPEVT2 or Timer64P0_T12CMPEVT3 or Timer64P0_T12CMPEVT4 or Timer64P0_T12CMPEVT5 or Timer64P0_T12CMPEVT6 or Timer64P0_T12CMPEVT7 18 MMCSD0 Interrupt 0 Timer64P...

Page 344: ...er Mapping Events PRUSS_EVTOUT0 to PRUSS_EVTOUT7 are mapped to the ARM and DSP interrupt controllers The following tables show the interrupt mapping Table 13 28 ARM Interrupt Controller Mapping Event Number Source 3 EVTOUT0 4 EVTOUT1 5 EVTOUT2 6 EVTOUT3 7 EVTOUT4 8 EVTOUT5 9 EVTOUT6 10 EVTOUT7 Table 13 29 DSP Interrupt Controller Mapping Event Number Source 6 EVTOUT0 17 EVTOUT1 22 EVTOUT2 35 EVTOU...

Page 345: ...nd host interfacing Figure 13 23 illustrates the flow of system interrupts through the functions to the host The following subsections describe each part of the flow Figure 13 23 13 7 5 1 Interrupt Processing This block does following tasks Synchronization of slower and asynchronous interrupts Conversion of polarity to active high Conversion of interrupt type to pulse interrupts After the processi...

Page 346: ...st priority Channels are used to group the system interrupts into a smaller number of priorities that can be given to a host interface with a very small number of interrupt inputs When multiple system interrupts are mapped to the same channel their interrupts are ORed together so that when either is active the output is active The channel map registers CMR1 CMR16 define the channel for each system...

Page 347: ...the interrupt is completely serviced the nesting level for the host interrupt is returned to its original value The host interrupt nesting level registers HINLR1 and HINLR2 display and control the nesting level for each host interrupt The nesting level controls which channel and lower priority channels are nested There is one register per host interrupt Software manually performs the nesting of in...

Page 348: ...system event to INTC channel through CHANMAP registers 3 Map channel to host interrupt through HOSTMAP registers Recommend channel x be mapped to host interrupt x 4 Clear system interrupt by writing 1s to SECR registers 5 Enable host interrupt by writing index value to HOSTINTENIDX register 6 Enable interrupt nesting if desired 7 Globally enable all interrupts through GLBLEN register 13 8 Register...

Page 349: ...000 0x000001FF Data RAM 0 1 Data RAM 1 1 0x00000200 0x00001FFF Reserved Reserved 0x00002000 0x000021FF Data RAM 1 1 Data RAM 0 1 0x00002200 0x00003FFF Reserved Reserved 0x00004000 0x00006FFF INTC Registers INTC Registers 0x00007000 0x000077FF PRU0 Registers PRU0 Registers 0x00007800 0x00007FFF PRU1 Registers PRU1 Registers 0x00008000 0x0000FFFF Reserved Reserved 0x00010000 0xFFFFFFFF Reserved Rese...

Page 350: ...rogrammable Pointer Register 0 2Ch CONTABPROPTR1 PRU Constant Table Programmable Pointer Register 1 400h to 47Ch INTGPR0 to INTGPR31 PRU Internal General Purpose Registers for Debug 480h to 4FCh INTCTER0 to INTCTER31 PRU Internal Constants Table Entry Registers for Debug 13 8 1 3 1 CONTROL Register Offset 0h Figure 13 24 CONTROL Register 31 16 PCRESETVAL R W 0 15 14 9 8 7 4 3 2 1 0 RUNS TATE RESER...

Page 351: ...U Sleep Indicator This bit indicates whether or not the PRU is currently asleep 0 PRU is not asleep 1 PRU is asleep If this bit is written to a 0 the PRU will be forced to power up from sleep mode 1 ENABLE R W 0 Processor Enable This bit controls whether or not the PRU is allowed to fetch new instructions 0 PRU is disabled 1 PRU is enabled If this bit is de asserted while the PRU is currently runn...

Page 352: ...P Register Offset 8h 31 0 BITWISEENABLES R W 0 LEGEND R W Read Write R Read only n value after reset Figure 13 26 WAKEUP Register 31 0 BITWISEENABLES R W 0 LEGEND R W Read Write R Read only n value after reset Table 13 36 WAKEUP Register Field Descriptions Bit Field Type Reset Description 31 0 BITWISEENA BLES R W 0 Wakeup Enables This field is ANDed with the incoming R31 status inputs whose bit po...

Page 353: ...s always less than or equal to cycle count Figure 13 28 STALLCNT Register 31 0 STALLCOUNT R 0 LEGEND R W Read Write R Read only n value after reset Table 13 38 STALLCNT Register Field Descriptions Bit Field Type Reset Description 31 0 STALLCOUN T R 0 This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled both bits ENABLE and COUNTENABLE set in the...

Page 354: ...hpad memory This register is formatted as follows Figure 13 30 CONTABPROPTR0 Register 31 16 15 0 C29 C28 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 13 40 CONTABPROPTR0 Register Field Descriptions Bit Field Type Reset Description 31 16 C29 R W 0 PRU Constant Entry 29 Pointer This field sets the value that will appear in bits 23 8 of entry 29 in the PRU Constant Table 15...

Page 355: ... to INTGPR31 Register Field Descriptions Bit Field Type Reset Description 31 0 INTGPRn R W X PRU Internal GP Register n Reading writing this field directly inspects modifies the corresponding internal register in the PRU internal regfile 13 8 1 3 10 INTCTER0 to INTCTER31 Register Offset 480h 4 n This register allows an external agent to debug the PRU while it is disabled Since some of the constant...

Page 356: ...RUSS Interrupt Controller INTC Registers Address Offset Register Name Description 0h REVID Revision ID Register 4h CONTROL Control Register 10h GLBLEN Global Enable Register 1Ch GLBLNSTLVL Global Nesting Level Register 20h STATIDXSET System Interrupt Status Indexed Set Register 24h STATIDXCLR System Interrupt Status Indexed Clear Register 28h ENIDXSET System Interrupt Enable Indexed Set Register 2...

Page 357: ...set Description 31 0 REV R O 1 Revision ID 13 8 2 2 CONTROL Register Offset 4h The Control Register holds global control parameters and can forces a soft reset on the module Table 13 48 CONTROL Register 31 4 3 2 1 0 RESERVED NEST MODE RESE RVED R 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 13 49 CONTROL Register Field Descriptions Bit Field Type Reset Description 31 4 R...

Page 358: ...eset Description 31 OVERRIDE W O X Always read as 0 Writes of 1 override the automatic nesting and set the nesting_level to the written data 30 9 RESERVED R 0 8 0 NESTLEVEL R W Ah The current global nesting level highest channel that is nested Writes set the nesting level In auto nesting mode this value is updated internally unless the auto_override bit is set 13 8 2 5 STATIDXSET Register Offset 2...

Page 359: ... n value after reset Table 13 59 ENIDXSET Register Field Descriptions Bit Field Type Reset Description 31 10 RESERVED R 0 9 0 INDEX W S 0 Writes set the enable of the interrupt given in the index value Reads return 0 13 8 2 8 ENIDXCLR Register Offset 2Ch The System Interrupt Enable Indexed Clear Register allows disabling an interrupt The interrupt to disable is the index value written This clears ...

Page 360: ...DXCLR Register Field Descriptions Bit Field Type Reset Description 31 10 RESERVED R 0 9 0 INDEX W C 0 Writes clear the enable of the host interrupt given in the index value Reads return 0 13 8 2 11 GLBLPRIIDX Register Offset 80h The Global Prioritized Index Register shows the interrupt number of the highest priority interrupt pending across all the host interrupts Table 13 66 GLBLPRIIDX Register 3...

Page 361: ...SETINT1 Register Field Descriptions Bit Field Type Reset Description 31 0 RAW_STATU S W S 0 System interrupt raw status and setting of the system interrupts 32 to 63 Reads return the raw status Write a 1 in a bit position to set the status of the system interrupt Writing a 0 has no effect 13 8 2 14 STATCLRINT0 Register Offset 280h The System Interrupt Status Enabled Clear Registers show the pendin...

Page 362: ...e system interrupt Writing a 0 has no effect 13 8 2 16 ENABLESET0 Register Offset 300h The System Interrupt Enable Set Register enables system interrupts to trigger outputs System interrupts that are not enabled do not interrupt the host There is a bit per system interrupt Table 13 76 ENABLESET0 Register 31 0 ENABLE W S 0 LEGEND R W Read Write R Read only n value after reset Table 13 77 ENABLESET0...

Page 363: ...nabled do not interrupt the host There is a bit per system interrupt Table 13 82 ENABLECLR1 Register 31 0 ENABLE W C 0 LEGEND R W Read Write R Read only n value after reset Table 13 83 ENABLECLR1 Register Field Descriptions Bit Field Type Reset Description 31 0 ENABLE W C 0 System interrupt enables system interrupts 32 to 63 Read returns the enable value 0 disabled 1 enabled Write a 1 in a bit pos...

Page 364: ...interrupt for channel N 1 7 0 CHANN_MA P R W 0 Sets the host interrupt for channel N 13 8 2 22 HOSTINTPRIIDX0 to HOSTINTPRIIDX9 Register Offset 900h to 928h The Host Interrupt Prioritized Index Registers show the highest priority current pending interrupt for the host interrupt There is one register per host interrupt Table 13 88 HOSTINTPRIIDX0 to HOSTINTPRIIDX9 Register 31 30 10 9 0 NONE RESERVED...

Page 365: ...ions Bit Field Type Reset Description 31 0 POLARITY R W Default_polari ty N Interrupt polarity of the system interrupts 32 to 63 0 active low 1 active high 13 8 2 25 TYPE0 Register Offset D80h The Interrupt Type Registers define the type of the system interrupts The type of all system interrupts is pulse always write 0 to the bits of this register Table 13 94 TYPE0 Register 31 0 TYPE R W Default_t...

Page 366: ...LVL0 to HOSTINTNSTLVL9 Register Field Descriptions Bit Field Type Reset Description 31 AUTO_OVER RIDE W O 0 Reads return 0 Writes of a 1 override the auto updating of the nesting_level and use the write data 30 9 RESERVED R 0 8 0 NESTING_L EVEL R W 0 Reads return the current nesting level for the host interrupt Writes set the nesting level for the host interrupt In auto mode the value is updated i...

Page 367: ... Instruments Incorporated DDR2 mDDR Memory Controller Chapter 14 SPRUH82C April 2013 Revised September 2016 DDR2 mDDR Memory Controller This chapter describes the DDR2 mobile DDR mDDR memory controller Topic Page 14 1 Introduction 368 14 2 Architecture 370 14 3 Supported Use Cases 398 14 4 Registers 403 ...

Page 368: ...e not supported The DDR2 mDDR memory is the major memory location for program and data storage 14 1 2 Features The DDR2 mDDR memory controller supports the following features JESD79D 2 standard compliant DDR2 SDRAM JESD209 standard compliant mobile DDR mDDR Data bus width of 16 bits CAS latencies DDR2 2 3 4 and 5 mDDR 2 and 3 Internal banks DDR2 1 2 4 and 8 mDDR 1 2 and 4 Burst length 8 Burst type...

Page 369: ... central resource SCR Figure 14 1 Data Paths to DDR2 mDDR Memory Controller 14 1 4 Supported Use Case Statement The DDR2 mDDR memory controller supports JESD79D 2 DDR2 SDRAM memories and the JESD209 mobile DDR mDDR SDRAM memories utilizing 16 bits of the DDR2 mDDR memory controller data bus See Section 14 3 for more details 14 1 5 Industry Standard s Compliance Statement The DDR2 mDDR memory contr...

Page 370: ...mmon DDR2 mDDR SDRAM device 14 2 1 Clock Control The DDR2 mDDR memory controller receives two input clocks from internal clock sources VCLK and 2X_CLK Figure 14 2 VCLK is a divided down version of the PLL0 clock 2X_CLK is the PLL1 clock 2X_CLK should be configured to clock at the frequency of the desired data rate or stated similarly it should operate at twice the frequency of the desired DDR2 mDD...

Page 371: ...wo clock domains within the DDR2 mDDR memory controller The two clock domains are driven by VCLK and a divided down by 2 version of 2X_CLK called MCLK The command FIFO write FIFO and read FIFO described in Section 14 2 6 are all on the VCLK domain From this VCLK drives the interface to the peripheral bus The MCLK domain consists of the DDR2 mDDR memory controller state machine and memory mapped re...

Page 372: ...ength reference Reference output for drive strength calibration of N and P channel outputs Tie to ground via 50 ohm 5 tolerance 1 16th watt resistor 49 9 ohm 5 tolerance is acceptable DDR_VREF pwr Voltage reference input Voltage reference input for the SSTL_18 I O buffers Note even in the case of mDDR an external resistor divider connected to this pin is necessary 14 2 3 Protocol Description s The...

Page 373: ...10 Previous Cycles Current Cycle ACTV H H L L H H Bank Row Address DCAB H H L L H L X X H DEAC H H L L H L Bank X L MRS H H L L L L BA OP Code EMRS H H L L L L BA OP Code READ H H L H L H BA Column Address L READ with precharge H H L H L H BA Column Address H WRT H H L H L L BA Column Address L WRT with precharge H H L H L L BA Column Address H REFR H H L L L H X X X SLFREFR entry H L L L L H X X ...

Page 374: ...cally preceded by a DCAB command ensuring the deactivation of all CE spaces and banks selected Following the DCAB command the DDR2 mDDR memory controller begins performing refreshes at a rate defined by the refresh rate RR bit in the SDRAM refresh control register SDRCR Page information is always invalid before and after a REFR command thus a refresh cycle always forces a page miss This type of re...

Page 375: ... Memory Controller 14 2 3 2 Deactivation DCAB and DEAC The precharge all banks command DCAB is performed after a reset to the DDR2 mDDR memory controller or following the initialization sequence DDR2 mDDR SDRAMs also require this cycle prior to a refresh REFR and mode set register commands MRS and EMRS During a DCAB command DDR_A 10 is driven high to ensure the deactivation of all banks Figure 14 ...

Page 376: ... com 376 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated DDR2 mDDR Memory Controller The DEAC command closes a single bank of memory specified by the bank select signals Figure 14 6 shows the timings diagram for a DEAC command Figure 14 6 DEAC Command ...

Page 377: ...emory The ACTV command opens a row of memory allowing future accesses reads or writes with minimum latency The value of DDR_BA 2 0 selects the bank and the value of DDR_A 13 0 selects the row When the DDR2 mDDR memory controller issues an ACTV command a delay of tRCD is incurred before a read or write command is issued Figure 14 7 shows an example of an ACTV command Reads or writes to the currentl...

Page 378: ...DDR2 mDDR memory controller uses a burst length of 8 and has a programmable CAS latency of 2 3 4 or 5 The CAS latency is three cycles in Figure 14 8 Read latency is equal to CAS latency plus additive latency The DDR2 mDDR memory controller always configures the memory to have an additive latency of 0 so read latency equals CAS latency Since the default burst size is 8 the DDR2 mDDR memory controll...

Page 379: ...tency is equal to CAS latency minus 1 cycles For mDDR write latency is equal to 1 cycle always All writes have a burst length of 8 The use of the DDR_DQM outputs allows byte and halfword writes to be executed Figure 14 9 shows the timing for a DDR2 write on the DDR2 mDDR memory controller If the transfer request is for less than 8 words depending on the scheduling result and the pending commands t...

Page 380: ... commands When the MRS or EMRS command is executed the value on DDR_BA 2 0 selects the mode register to be written and the data on DDR_A 13 0 is loaded into the register Figure 14 10 shows the timing for an MRS and EMRS command The DDR2 mDDR memory controller only issues MRS and EMRS commands during the DDR2 mDDR memory controller initialization sequence See Section 14 2 13 for more information Fi...

Page 381: ...its is determined by the number of valid address pins for the device and does not need to be set in a register When IBANKPOS is set to 1 the memory controller operates with special address mapping In this case the number of column row and bank address bits is determined by the PAGESIZE ROWSIZE and IBANK fields The ROWSIZE field is in the SDRAM configuration register 2 SDCR2 See Table 14 4 for a de...

Page 382: ... logical address increments When the DDR2 mDDR memory controller reaches a page row boundary it moves onto the same page row in the next bank This movement continues until the same page has been accessed in all banks To the DDR2 mDDR SDRAM this process looks as shown in Figure 14 12 By traversing across banks while remaining on the same row page the DDR2 mDDR memory controller maximizes the number...

Page 383: ... com Architecture 383 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated DDR2 mDDR Memory Controller Logical Address to DDR2 mDDR SDRAM Address Map NOTE M is number of columns as determined by PAGESIZE minus 1 P is number of banks as determined by IBANK minus 1 and N is number of rows as determined by both PAGESIZE and IBANK ...

Page 384: ...DRAM device Table 14 6 shows which source address bits map to the SDRAM column row and bank address bits for all combinations of PAGESIZE ROWSIZE and IBANK When IBANKPOS is set to 1 the effect of the address mapping scheme is that as the source address increments across an SDRAM page boundary the memory controller proceeds to the next page in the same bank This movement along the same bank continu...

Page 385: ...P www ti com Architecture 385 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated DDR2 mDDR Memory Controller Figure 14 13 Address Mapping Diagram IBANKPOS 1 NOTE M is number of columns as determined by PAGESIZE minus 1 P is number of banks as determined by IBANK minus 1 and N is number of rows as determined by ROWSIZE minus 1...

Page 386: ...DDR2 mDDR Memory Controller Interface To move data efficiently from on chip resources to external DDR2 mDDR SDRAM memory the DDR2 mDDR memory controller makes use of a command FIFO a write FIFO a read FIFO and command and data schedulers Table 14 7 describes the purpose of each FIFO Figure 14 15 shows the block diagram of the DDR2 mDDR memory controller FIFOs Commands write data and read data arri...

Page 387: ...ferent masters The DDR2 mDDR memory controller first reorders commands from each master based on the following rules Selects the oldest command first command in the queue Selects a read before a write if The read is to a different block address 2048 bytes than the write The read has greater or equal priority The second bullet above may be viewed as an exception to the first bullet This means that ...

Page 388: ...ults from the following conditions A continuous stream of high priority read commands can block a low priority write command A continuous stream of DDR2 mDDR SDRAM commands to a row in an open bank can block commands to the closed row in the same bank To avoid these conditions the DDR2 mDDR memory controller can momentarily raises the priority of the oldest command in the command FIFO after a set ...

Page 389: ...the REFR command Refresh Release Backlog count is greater than 3 Indicates the level at which enough REFR commands have been performed and the DDR2 mDDR memory controller may service new memory access requests Refresh Need Backlog count is greater than 7 Indicates the DDR2 mDDR memory controller should raise the priority level of a REFR command above servicing a new memory access Refresh Must Back...

Page 390: ...that you set IBANKPOS to 1 to avoid bank interleaving When IBANKPOS is cleared to 0 it is the responsibility of software to move critical data into the banks that are to be refreshed during partial array self refresh Refer to Section 14 2 5 2 for more information on IBANKPOS and addressing mapping in general Table 14 9 Configuration Bit Field for Partial Array Self refresh Bit Field Bit Value Bit ...

Page 391: ...t_n resets the state machine only it does not reset the controller s registers which allows soft reset from PSC or WDT to reset the module without resetting the configuration registers and reduces the programming overhead for setting up access to the DDR2 mDDR device If the DDR2 mDDR memory controller is reset independently of other peripherals the user s software should not perform memory as well...

Page 392: ...isable on the DDR2 mDDR device single ended strobe differential strobe etc The DDR2 mDDR memory controller programs the mode and extended mode registers of the DDR2 mDDR memory by issuing MRS and EMRS commands during the initialization sequence The SDRAMEN MSDRAMEN DDREN and DDR2EN bits in the SDRAM configuration register SDCR determine if the DDR2 mDDR memory controller will perform a DDR2 or mob...

Page 393: ...DDR2 mDDR SDRAM Field Function Selection DDR_A 12 0 12 Output Buffer Enable Output buffer enable DDR_A 11 0 11 RDQS Enable RDQS disable DDR_A 10 1 10 DQS enable Disables differential DQS signaling DDR_A 9 7 0 9 7 OCD Calibration Program Exit OCD calibration DDR_A 6 0 6 ODT Value Rtt Cleared to 0 to select 75 ohms This feature is not supported because the DDR_ODT signal is not pinned out DDR_A 5 3 ...

Page 394: ...RDN bit in the VTP IO control register VTPIO_CTL b Clear LOCK bit in VTPIO_CTL c Pulse CLKRZ bit in VTPIO_CTL i Set CLKRZ bit and wait at least 1 VTP clock cycle clock cycle wait can be achieved by performing a read modify write of VTPIO_CTL in the next step ii Clear CLKRZ bit and wait at least 1 VTP clock cycle clock cycle wait can be achieved by performing a read modify write of VTPIO_CTL in the...

Page 395: ... master peripherals to mDDR DDR2 memory The optimal value should be determined based on system considerations however a value of 20h or 30h is sufficient for typical applications NOTE Some memory data sheet timing values such as those programmed into the SDRAM timing register 1 SDTIMR1 and SDRAM timing register 2 SDTIMR2 may need to be relaxed in order to compensate for signal delays introduced by...

Page 396: ...dule off Gating input clocks off to the DDR2 mDDR memory controller achieves higher power savings when compared to the power savings of self refresh mode and power down mode The input clocks are turned off outside of the DDR2 mDDR memory controller through the use of the Power and Sleep Controller PSC and the PLL controller 1 PLLC1 Figure 14 17 shows the connections between the DDR2 mDDR memory co...

Page 397: ... memory in self refresh mode 3 Set the MCLKSTOPEN bit in SDRCR to 1 This enables the DDR2 mDDR memory controller to shut off the MCLK 4 Wait 150 CPU clock cycles to allow the MCLK to stop 5 Program the PSC to disable the DDR2 mDDR memory controller VCLK You must not disable VCLK in power down mode use only for self refresh mode see notes in this section 6 For maximum power savings the PLL PLLC1 sh...

Page 398: ...ith a variety of DDR2 mDDR devices By programming the SDRAM configuration register SDCR SDRAM refresh control register SDRCR SDRAM timing register 1 SDTIMR1 and SDRAM timing register 2 SDTIMR2 the DDR2 mDDR memory controller can be configured to meet the data sheet specification for DDR2 SDRAM as well as mDDR memory devices This section presents an example describing how to interface the DDR2 memo...

Page 399: ...o a mDDR device the SDRAM configuration register 2 SDCR2 must be programmed in addition to the registers mentioned above Configuring SDRAM Configuration Register SDCR The SDRAM configuration register SDCR contains register fields that configure the DDR2 mDDR memory controller to match the data bus width CAS latency number of banks and page size of the attached memory In this example we assume the ...

Page 400: ... SDRCR is defined as the rate at which the attached memory device is refreshed in DDR2 mDDR cycles The value of this field may be calculated using the following equation RR DDR2 mDDR clock frequency DDR2 mDDR memory refresh period Table 14 16 displays the DDR2 400 refresh rate specification Table 14 16 DDR2 Memory Refresh Specification Symbol Description Value tREF Average Periodic Refresh Interva...

Page 401: ..._CLK 1 Table 14 18 SDTIMR1 Configuration Register Field Name DDR2 Data Manual Parameter Name Description Data Manual Value nS Formula Register field must be Register Value T_RFC tRFC Refresh cycle time 127 5 tRFC fDDR2 mDDR_CLK 1 19 T_RP tRP Precharge command to refresh or activate command 15 tRP fDDR2 mDDR_CLK 1 2 T_RCD tRCD Activate command to read write command 15 tRCD fDDR2 mDDR_CLK 1 2 T_WR t...

Page 402: ...alues minus 1 Table 14 20 shows the resulting DRPYC1R configuration When calculating round trip board delay the signals of primary concern are the differential clock signals DDR_CLK and DDR_CLK and data strobe signals DDR_DQS For these signals calculate the round trip board delay from the DDR memory controller to the memory and then choose the maximum delay to determine the RL value In this exampl...

Page 403: ... Bus Burst Priority Register Section 14 4 7 40h PC1 Performance Counter 1 Register Section 14 4 8 44h PC2 Performance Counter 2 Register Section 14 4 9 48h PCC Performance Counter Configuration Register Section 14 4 10 4Ch PCMRS Performance Counter Master Region Select Register Section 14 4 11 50h PCT Performance Counter Time Register Performance Counter Time Register PCT 60h DRPYRCR DDR PHY Reset...

Page 404: ... 0 R 0 LEGEND R Read only n value after reset Table 14 23 SDRAM Status Register SDRSTAT Field Descriptions Bit Field Value Description 31 Reserved 0 Reserved 30 DUALCLK Dual clock Specifies whether the VCLK and MCLK inputs are asynchronous This bit should always be read as 1 0 VCLK and MCLK are not asynchronous 1 VCLK and MCLK are asynchronous 29 3 Reserved 0 Reserved 2 PHYRDY DDR2 mDDR memory con...

Page 405: ...e This bit is used in conjunction with the DDR2TERM0 bit to make a 2 bit field This bit is writeable only when the BOOTUNLOCK bit is unlocked See the DDR2TERM0 bit Note that the reset value of DDR2TERM 1 0 10 these bits must be cleared and forced to 00 to disable the termination because the ODT feature is not supported 26 IBANK_POS Internal Bank position 0 Normal addressing 1 Special addressing Ty...

Page 406: ...DLL disable for DDR SDRAM This bit is writeable only when the BOOTUNLOCK bit is unlocked To change this bit value use the following sequence 1 Write a 1 to the BOOTUNLOCK bit 2 Write a 0 to the BOOTUNLOCK bit along with the desired value of the DDRDLL_DIS bit 0 Enable DLL 1 Disable DLL inside DDR SDRAM 18 DDRDRIVE0 0 3h SDRAM drive strength This bit is used in conjunction with the DDRDRIVE1 bit to...

Page 407: ... fields may be changed 14 NM SDRAM data bus width 0 Reserved 1 16 bit bus width 13 12 Reserved 0 Reserved 11 9 CL 0 7h SDRAM CAS latency This bit is writeable only when the TIMUNLOCK bit is unlocked To change this bit value use the following sequence 1 Write a 1 to the TIMUNLOCK bit 2 Write a 0 to the TIMUNLOCK bit along with the desired value of the CL bit 0 1h Reserved 2h CAS Latency 2 3h CAS La...

Page 408: ...GEND R W Read Write R Read only n value after reset Table 14 25 SDRAM Refresh Control Register SDRCR Field Descriptions Bit Field Value Description 31 LPMODEN Low power mode enable 0 Disable low power mode 1 Enable low power mode The state of bit SR_PD selects either self refresh or power down mode 30 MCLKSTOPEN MCLK stop enable 0 Disables MCLK stopping MCLK may not be stopped 1 Enables MCLK stopp...

Page 409: ...the DDR2 mDDR data sheet Calculate by T_RP trp DDR_CLK 1 21 19 T_RCD 0 7h Specifies the minimum number of DDR_CLK cycles from an activate command to a read or write command minus 1 Corresponds to the trcd AC timing parameter in the DDR2 mDDR data sheet Calculate by T_RCD trcd DDR_CLK 1 18 16 T_WR 0 7h Specifies the minimum number of DDR_CLK cycles from the last write transfer to a precharge comman...

Page 410: ...fresh_rate 1 Round down to the nearest cycle 26 25 T_XP 0 3h Specifies the minimum number of DDR_CLK cycles from Power Down exit to any other command except a read command minus 1 Corresponds to the txp or tcke AC timing parameter in the DDR2 mDDR data sheet This field must satisfy the greater of tXP or tCKE If txp tcke then calculate by T_XP txp 1 If txp tcke then calculate by T_XP tcke 1 24 23 T...

Page 411: ...re 14 25 and described in Table 14 28 Figure 14 25 SDRAM Configuration Register 2 SDCR2 31 19 18 16 Reserved PASR R 0 R W 0 15 3 2 0 Reserved ROWSIZE R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 14 28 SDRAM Configuration Register 2 SDCR2 Field Descriptions Bit Field Value Description 31 19 Reserved 0 Reserved 18 16 PASR 0 7h Partial array self refresh 0 4 banks will be ref...

Page 412: ...COUNT bits are cleared to 00h then the DDR2 mDDR memory controller always honors the master priority regardless of open row bank status For most systems the PBBPR should be set to a moderately low value to provide an acceptable balance of DDR2 mDDR efficiency and latency for high priority masters for example 10h or 20h The PBBPR is shown in Figure 14 26 and described in Table 14 29 Figure 14 26 Pe...

Page 413: ...e Power and Sleep Controller PSC chapter The performance counter 1 register PC1 is shown in Figure 14 27 and described in Table 14 30 Figure 14 27 Performance Counter 1 Register PC1 31 0 Counter1 R 0 LEGEND R Read only n value after reset Table 14 30 Performance Counter 1 Register PC1 Field Descriptions Bit Field Value Description 31 0 Counter1 0 FFFF FFFFh 32 bit counter that can be configured as...

Page 414: ...cesses DDR2 mDDR SDRAM DDR2 mDDR memory controller memory mapped register accesses The REGION_SEL2 bit field value in the performance counter master region select register PCMRS is a don t care 1 Chip select filter is enabled If the REGION_SEL2 bit field value in the performance counter master region select register PCMRS is REGION_SEL2 0 PC2 counts accesses to DDR2 mDDR SDRAM memory REGION_SEL2 7...

Page 415: ...the DDR2 mDDR memory controller receives Counter increments for transfers aligned to the default burst size DBS are equal to the transfer size of data written to the DDR2 mDDR memory controller divided by the DBS 4h 0 0 Counts the number of external memory controller cycles DDR_CLK cycles that the command FIFO is full Use the following to calculate the counter value as a percentage counter value t...

Page 416: ...Fh Master ID for performance counter 2 register PC2 For the Master ID value for master peripherals in the device see the System Configuration SYSCFG Module chapter 23 20 Reserved 0 Any writes to these bit s must always have a value of 0 19 16 REGION_SEL2 0 Fh Region select for performance counter 2 register PC2 0 PC2 counts total DDR2 mDDR accesses 1h 6h Reserved 7h PC2 counts total DDR2 mDDR memo...

Page 417: ...er that continuously counts number for DDR_CLK cycles elapsed after the DDR2 mDDR memory controller is brought out of reset 14 4 12 DDR PHY Reset Control Register DRPYRCR The DDR PHY reset control register DRPYRCR is used to reset the DDR PHY The DRPYRCR is shown in Figure 14 32 and described in Table 14 36 Figure 14 32 DDR PHY Reset Control Register DRPYRCR 31 16 Reserved R 0 15 11 10 9 0 Reserve...

Page 418: ... condition has not occurred 1 Illegal memory access type See Section 14 2 14 for more details 1 0 Reserved 0 Reserved 14 4 14 Interrupt Masked Register IMR The interrupt masked register IMR displays the status of the interrupt when it is enabled If the interrupt condition occurs and the corresponding bit in the interrupt mask set register IMSR is set then the IMR bit is set The IMR bit is not set ...

Page 419: ...t mask clear register IMCR the interrupt is not enabled and neither bit is set to 1 Figure 14 35 Interrupt Mask Set Register IMSR 31 16 Reserved R 0 15 3 2 1 0 Reserved LTMSET Reserved R 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 14 39 Interrupt Mask Set Register IMSR Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 LTMSET Line trap interrupt s...

Page 420: ... in the interrupt mask set register IMSR the interrupt is not enabled and neither bit is set to 1 Figure 14 36 Interrupt Mask Clear Register IMCR 31 16 Reserved R 0 15 3 2 1 0 Reserved LTMCLR Reserved R 0 R W1C 0 R 0 LEGEND R W Read Write R Read only W1C Write 1 to clear writing 0 has no effect n value after reset Table 14 40 Interrupt Mask Clear Register IMCR Field Descriptions Bit Field Value De...

Page 421: ... PHY Control Register 1 DRPYC1R Field Descriptions Bit Field Value Description 31 15 Reserved 0 Reserved 14 12 CONFIG_DLL_MODE DLL configuration Controls the value assigned to the config_dll_mode input 0 1h DLL REFCLK is enabled 2h DLL REFCLK is disabled 3h 7h Reserved 11 8 Reserved 0 Reserved 7 EXT_STRBEN Internal External strobe gating 0 Internal strobe gating mode 1 External strobe gating mode ...

Page 422: ...re eCAP Module Chapter 15 SPRUH82C April 2013 Revised September 2016 Enhanced Capture eCAP Module The enhanced capture eCAP module is essential in systems where accurate timing of external events is important This chapter describes the eCAP module Topic Page 15 1 Introduction 423 15 2 Architecture 424 15 3 Applications 433 15 4 Registers 449 ...

Page 423: ... train signals Decoding current or voltage amplitude derived from duty cycle encoded current voltage sensors 15 1 2 Features The eCAP module includes the following features 32 bit time base counter 4 event time stamp registers each 32 bits Edge polarity selection for up to four sequenced time stamp capture events Interrupt on either of the four events Single shot capture of up to four event time s...

Page 424: ... bit time base counter 4 32 bit time stamp capture registers CAP1 CAP4 4 stage sequencer Modulo4 counter that is synchronized to external events ECAP pin rising falling edges Independent edge polarity rising falling edge selection for all 4 events Input capture signal prescaling from 2 62 One shot compare register 2 bits to freeze captures after 1 to 4 time stamp events Control for continuous time...

Page 425: ...enerator with 32 bit capabilities when it is not being used for input captures The counter operates in count up mode providing a time base for asymmetrical pulse width modulation PWM waveforms The CAP1 and CAP2 registers become the active period and compare registers respectively while CAP3 and CAP4 registers become the period and capture shadow registers respectively Figure 15 2 is a high level v...

Page 426: ...logic CTR 0 31 PRD 0 31 CMP 0 31 CTR CMP CTR PRD CTR_OVF OVF APWM mode Delta mode SYNC 4 Capture events CEVT 1 4 APRD shadow 32 32 MODE SELECT ECCTL2 SYNCI_EN SYNCOSEL SWSYNC ECCTL2 CAP APWM Edge Polarity Select ECCTL1 CAPxPOL ECCTL1 EVTPS ECCTL1 CAPLDEN CTRRSTx ECCTL2 RE ARM CONT ONESHT STOP_WRAP Registers ECEINT ECFLG ECCLR ECFRC Architecture www ti com 426 SPRUH82C April 2013 Revised September ...

Page 427: ...nced Capture eCAP Module 15 2 2 1 Event Prescaler An input capture signal pulse train can be prescaled by N 2 62 in multiples of 2 or can bypass the prescaler This is useful when very high frequency signals are used as inputs Figure 15 4 shows a functional diagram and Figure 15 5 shows the operation of the prescale function Figure 15 4 Event Prescale Control 1 When a prescale value of 1 is chosen ...

Page 428: ...ng 0 1 2 3 0 and wraps around unless stopped A 2 bit stop register is used to compare the Mod4 counter output and when equal stops the Mod4 counter and inhibits further loads of the CAP1 CAP4 registers This occurs during one shot operation The continuous one shot block Figure 15 6 controls the start stop and reset zero functions of the Mod4 counter via a mono shot type of action that can be trigge...

Page 429: ...unter and Phase Control This counter Figure 15 7 provides the time base for event captures and is clocked via the system clock A phase register is provided to achieve synchronization with other counters via a hardware and software forced sync This is useful in APWM mode when a phase offset between modules is needed On any of the four event loads an option to reset the 32 bit counter is given This ...

Page 430: ... interrupt source from the eCAPn module going to the interrupt controller Seven interrupt events CEVT1 CEVT2 CEVT3 CEVT4 CNTOVF CTR PRD CTR CMP can be generated The interrupt enable register ECEINT is used to enable disable individual interrupt event sources The interrupt flag register ECFLG indicates if any interrupt event has been latched and contains the global interrupt flag bit INT An interru...

Page 431: ...et ECEINT ECFLG Latch Clear Latch Set CMPEQ ECFRC ECCLR ECCLR Clear ECFLG ECEINT Clear Latch Set ECFRC CTROVF ECFLG 0 1 0 Generate interrupt pulse when input 1 Latch Clear Set ECCLR ECAPxINT ECFLG www ti com Architecture 431 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced Capture eCAP Module Figure 15 8 Interrupts...

Page 432: ...rresponding shadow registers CAP3 CAP4 This emulates immediate mode Writing to the shadow registers CAP3 CAP4 will invoke the shadow mode During initialization you must write to the active registers for both period and compare This automatically copies the initial values into the shadow values For subsequent compare updates during run time you only need to use the shadow registers Figure 15 9 PWM ...

Page 433: ...0x1 CTRRSTx bits define EC_ABS_MODE 0x0 define EC_DELTA_MODE 0x1 PRESCALE bits define EC_BYPASS 0x0 define EC_DIV1 0x0 define EC_DIV2 0x1 define EC_DIV4 0x2 define EC_DIV6 0x3 define EC_DIV8 0x4 define EC_DIV10 0x5 ECCTL2 ECAP Control Reg 2 CONT ONESHOT bit define EC_CONTINUOUS 0x0 define EC_ONESHOT 0x1 STOPVALUE bit define EC_EVENT1 0x0 define EC_EVENT2 0x1 define EC_EVENT3 0x2 define EC_EVENT4 0...

Page 434: ...e TSCTR counts up without resetting and capture events are qualified on the rising edge only this gives period and frequency information On an event the TSCTR contents time stamp is first captured then Mod4 counter is incremented to the next state When the TSCTR reaches FFFF FFFFh maximum value it wraps around to 0000 0000h not shown in Figure 15 10 if this occurs the CTROVF counter overflow flag ...

Page 435: ... ECCTL1 CAPLDEN EC_ENABLE ECCTL1 PRESCALE EC_DIV1 ECCTL2 CAP_APWM EC_CAP_MODE ECCTL2 CONT_ONESHT EC_CONTINUOUS ECCTL2 SYNCO_SEL EC_SYNCO_DIS ECCTL2 SYNCI_EN EC_DISABLE ECCTL2 TSCTRSTOP EC_RUN Example 15 1 Code Snippet for CAP Mode Absolute Time Rising Edge Trigger Code snippet for CAP mode Absolute Time Rising edge trigger Run Time e g CEVT4 triggered ISR call TSt1 ECAPxRegs CAP1 Fetch Time Stamp ...

Page 436: ...13 2016 Texas Instruments Incorporated Enhanced Capture eCAP Module 15 3 2 Absolute Time Stamp Operation Rising and Falling Edge Trigger Example In Figure 15 11 the eCAP operating mode is almost the same as in the previous section except capture events are qualified as either rising or falling edge this now gives both period and duty cycle information Period1 t3 t1 Period2 t5 t3 etc Duty Cycle1 on...

Page 437: ...1 CAPLDEN EC_ENABLE ECCTL1 PRESCALE EC_DIV1 ECCTL2 CAP_APWM EC_CAP_MODE ECCTL2 CONT_ONESHT EC_CONTINUOUS ECCTL2 SYNCO_SEL EC_SYNCO_DIS ECCTL2 SYNCI_EN EC_DISABLE ECCTL2 TSCTRSTOP EC_RUN Example 15 2 Code Snippet for CAP Mode Absolute Time Rising and Falling Edge Trigger Code snippet for CAP mode Absolute Time Rising Falling edge triggers Run Time e g CEVT4 triggered ISR call TSt1 ECAPxRegs CAP1 Fe...

Page 438: ...unts up without resetting and Mod4 counter wraps around is used In Delta time mode TSCTR is Reset back to Zero on every valid event Here Capture events are qualified as Rising edge only On an event TSCTR contents time stamp is captured first and then TSCTR is reset to Zero The Mod4 counter then increments to the next state If TSCTR reaches FFFF FFFFh maximum value before the next event it wraps ar...

Page 439: ... ECCTL1 CTRRST4 EC_DELTA_MODE ECCTL1 CAPLDEN EC_ENABLE ECCTL1 PRESCALE EC_DIV1 ECCTL2 CAP_APWM EC_CAP_MODE ECCTL2 CONT_ONESHT EC_CONTINUOUS ECCTL2 SYNCO_SEL EC_SYNCO_DIS ECCTL2 SYNCI_EN EC_DISABLE ECCTL2 TSCTRSTOP EC_RUN Example 15 3 Code Snippet for CAP Mode Delta Time Rising Edge Trigger Code snippet for CAP mode Delta Time Rising edge trigger Run Time e g CEVT1 triggered ISR call Note here Time...

Page 440: ... Falling Edge Trigger Example In Figure 15 13 the eCAP operating mode is almost the same as in previous section except Capture events are qualified as either Rising or Falling edge this now gives both Period and Duty cycle information Period1 T1 T2 Period2 T3 T4 etc Duty Cycle1 on time T1 Period1 100 etc Duty Cycle1 off time T2 Period1 100 etc During initialization you must write to the active reg...

Page 441: ...ABLE ECCTL1 PRESCALE EC_DIV1 ECCTL2 CAP_APWM EC_CAP_MODE ECCTL2 CONT_ONESHT EC_CONTINUOUS ECCTL2 SYNCO_SEL EC_SYNCO_DIS ECCTL2 SYNCI_EN EC_DISABLE ECCTL2 TSCTRSTOP EC_RUN Example 15 4 Code Snippet for CAP Mode Delta Time Rising and Falling Edge Triggers Code snippet for CAP mode Delta Time Rising and Falling edge triggers Run Time e g CEVT1 triggered ISR call Note here Time stamp directly represen...

Page 442: ...e PWM Generation Independent Channel s Example In this example the eCAP module is configured to operate as a PWM generator Here a very simple single channel PWM waveform is generated from output pin APWMn The PWM polarity is active high which means that the compare value CAP2 reg is now a compare register represents the on time high level of the period Alternatively if the APWMPOL bit is configure...

Page 443: ...le i e compare value Run Time Instant 2 e g another ISR call ECAPxRegs CAP2 0x500 Set Duty cycle i e compare value 15 3 5 2 Multichannel PWM Generation with Synchronization Example Figure 15 15 takes advantage of the synchronization feature between eCAP modules Here 4 independent PWM channels are required with different frequencies but at integer multiples of each other to avoid beat frequencies H...

Page 444: ...aster APWM 1 module Time Time APRD 1 ACMP 1 0000 0000 APWM1 o p pin CTR PRD SyncOut 20 000 7 000 TSCTR FFFF FFFFh dc dc dc Applications www ti com 444 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced Capture eCAP Module Figure 15 15 Multichannel PWM Example Using 4 eCAP Modules ...

Page 445: ...onization Register Bit Value CAP1 CAP1 10000 CTRPHS CTRPHS 0 ECCTL2 CAP_APWM EC_APWM_MODE ECCTL2 APWMPOL EC_ACTV_HI ECCTL2 SYNCI_EN EC_ENABLE ECCTL2 SYNCO_SEL EC_SYNCI ECCTL2 TSCTRSTOP EC_RUN Table 15 8 ECAP3 Initialization for Multichannel PWM Generation with Synchronization Register Bit Value CAP1 CAP1 5000 CTRPHS CTRPHS 0 ECCTL2 CAP_APWM EC_APWM_MODE ECCTL2 APWMPOL EC_ACTV_HI ECCTL2 SYNCI_EN EC...

Page 446: ...Set Duty cycle i e compare value 550 ECAP4Regs CAP2 6500 Set Duty cycle i e compare value 6500 15 3 5 3 Multichannel PWM Generation with Phase Control Example In Figure 15 16 the Phase control feature of the APWM mode is used to control a 3 phase Interleaved DC DC converter topology This topology requires each phase to be off set by 120 from each other Hence if Leg 1 controlled by APWM1 is the ref...

Page 447: ...700 SYNCO pulse CTR PRD APWM1 Φ2 120 Φ3 240 CTRPHS 2 800 CTRPHS 3 400 APWM2 APWM3 TSCTR www ti com Applications 447 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced Capture eCAP Module Figure 15 16 Multiphase channel Interleaved PWM Example Using 3 eCAP Modules ...

Page 448: ...00 ECCTL2 CAP_APWM EC_APWM_MODE ECCTL2 APWMPOL EC_ACTV_HI ECCTL2 SYNCI_EN EC_ENABLE ECCTL2 SYNCO_SEL EC_SYNCI ECCTL2 TSCTRSTOP EC_RUN Table 15 12 ECAP3 Initialization for Multichannel PWM Generation with Phase Control Register Bit Value CAP1 CAP1 1200 CTRPHS CTRPHS 400 ECCTL2 CAP_APWM EC_APWM_MODE ECCTL2 APWMPOL EC_ACTV_HI ECCTL2 SYNCI_EN EC_ENABLE ECCTL2 SYNCO_SEL EC_SYNCO_DIS ECCTL2 TSCTRSTOP EC...

Page 449: ... Offset Value Register 2 Section 15 4 2 8h CAP1 Capture 1 Register 2 Section 15 4 3 Ch CAP2 Capture 2 Register 2 Section 15 4 4 10h CAP3 Capture 3 Register 2 Section 15 4 5 14h CAP4 Capture 4 Register 2 Section 15 4 6 28h ECCTL1 Capture Control Register 1 1 Section 15 4 7 2Ah ECCTL2 Capture Control Register 2 1 Section 15 4 8 2Ch ECEINT Capture Interrupt Enable Register 1 Section 15 4 9 2Eh ECFLG ...

Page 450: ...er phase value register that can be programmed for phase lag lead This register shadows TSCTR and is loaded into TSCTR upon either a SYNCI event or S W force via a control bit Used to achieve phase control synchronization with respect to other eCAP and EPWM time bases 15 4 3 Capture 1 Register CAP1 The capture 1 register CAP1 is shown in Figure 15 19 and described in Table 15 16 Figure 15 19 Captu...

Page 451: ...F FFFFh This register can be loaded written by Time Stamp i e counter value during a capture event Software may be useful for test purposes ACMP active register when used in APWM mode 15 4 5 Capture 3 Register CAP3 The capture 3 register CAP3 is shown in Figure 15 21 and described in Table 15 18 Figure 15 21 Capture 3 Register CAP3 31 0 CAP3 R W 0 LEGEND R W Read Write n value after reset Table 15...

Page 452: ...gure 15 23 and described in Table 15 20 Figure 15 23 ECAP Control Register 1 ECCTL1 15 14 13 9 8 FREE SOFT PRESCALE CAPLDEN R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 CTRRST4 CAP4POL CTRRST3 CAP3POL CTRRST2 CAP2POL CTRRST1 CAP1POL R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write n value after reset Table 15 20 ECAP Control Register 1 ECCTL1 Field Descriptions Bit Field Value Descriptio...

Page 453: ...olute time stamp 1 Reset counter after Event 3 time stamp has been captured used in difference mode operation 4 CAP3POL Capture Event 3 Polarity select 0 Capture Event 3 triggered on a rising edge RE 1 Capture Event 3 triggered on a falling edge FE 3 CTRRST2 Counter Reset on Capture Event 2 0 Do not reset counter on Capture Event 2 absolute time stamp 1 Reset counter after Event 2 time stamp has b...

Page 454: ...APn APWMn pin operates as a capture input 1 ECAP module operates in APWM mode This mode forces the following configuration Resets TSCTR on CTR PRD event period boundary Permits shadow loading on CAP1 and 2 registers Disables loading of time stamps into CAP1 4 registers ECAPn APWMn pin operates as a APWM output 8 SWSYNC Software forced Counter TSCTR Synchronizing This provides a convenient software...

Page 455: ...in one shot mode Wrap after Capture Event 2 in continuous mode 2h Stop after Capture Event 3 in one shot mode Wrap after Capture Event 3 in continuous mode 3h Stop after Capture Event 4 in one shot mode Wrap after Capture Event 4 in continuous mode Notes STOP_WRAP is compared to Mod4 counter and when equal 2 actions occur Mod4 counter is stopped frozen Capture register loads are inhibited In one s...

Page 456: ...terrupt source 6 CTR PRD Counter Equal Period Interrupt Enable 0 Disable Period Equal as an Interrupt source 1 Enable Period Equal as an Interrupt source 5 CTROVF Counter Overflow Interrupt Enable 0 Disable counter Overflow as an Interrupt source 1 Enable counter Overflow as an Interrupt source 4 CEVT4 Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source 1 Enable Captu...

Page 457: ... flag is only active in APWM mode 0 Indicates no event occurred 1 Indicates the counter TSCTR reached the period register value APRD and was reset 5 CTROVF Counter Overflow Status Flag This flag is active in CAP and APWM mode 0 Indicates no event occurred 1 Indicates the counter TSCTR has made the transition from 0xFFFFFFFF to 0x00000000 4 CEVT4 Capture Event 4 Status Flag This flag is only active...

Page 458: ...tion 6 CTR PRD Counter Equal Period Status Flag 0 Writing a 0 has no effect Always reads back a 0 1 Writing a 1 clears the CTR PRD flag condition 5 CTROVF Counter Overflow Status Flag 0 Writing a 0 has no effect Always reads back a 0 1 Writing a 1 clears the CTROVF flag condition 4 CEVT4 Capture Event 4 Status Flag 0 Writing a 0 has no effect Always reads back a 0 1 Writing a 1 clears the CEVT3 fl...

Page 459: ...ns Bit Field Value Description 15 8 Reserved 0 Reserved 7 CTR CMP Force Counter Equal Compare Interrupt 0 No effect Always reads back a 0 1 Writing a 1 sets the CTR CMP flag bit 6 CTR PRD Force Counter Equal Period Interrupt 0 No effect Always reads back a 0 1 Writing a 1 sets the CTR PRD flag bit 5 CTROVF Force Counter Overflow 0 No effect Always reads back a 0 1 Writing a 1 to this bit sets the ...

Page 460: ... Capture eCAP Module 15 4 13 Revision ID Register REVID The revision ID register REVID is shown in Figure 15 29 and described in Table 15 26 Figure 15 29 Revision ID Register REVID 31 0 REV R 44D2 2100h LEGEND R Read only n value after reset Table 15 26 Revision ID Register REVID Field Descriptions Bit Field Value Description 31 0 REV 44D2 2100h Revision ID ...

Page 461: ...Resolution Pulse Width Modulator eHRPWM Chapter 16 SPRUH82C April 2013 Revised September 2016 Enhanced High Resolution Pulse Width Modulator eHRPWM This chapter describes the enhanced high resolution pulse width modulator eHRPWM Topic Page 16 1 Introduction 462 16 2 Architecture 467 16 3 Applications to Power Topologies 526 16 4 Registers 550 ...

Page 462: ... this feature Each ePWM module is indicated by a numerical value starting with 1 For example ePWM1 is the first instance and ePWM3 is the 3rd instance in the system and ePWMx indicates any instance The ePWM modules are chained together via a clock synchronization scheme that allows them to operate as a single system when required Additionally this synchronization scheme can be extended to the capt...

Page 463: ...PWM2A EPWM2B EPWM1A EPWM1B EPWM1INT EPWM2INT EPWMxINT To eCAP1 TZ1 TZn to TZ1 TZn to Interrupt Controller www ti com Introduction 463 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 16 1 Multiple ePWM Modules ...

Page 464: ...one signals TZ1 to TZn These input signals alert the ePWM module of an external fault condition Each module on a device can be configured to either use or ignore any of the trip zone signals The trip zone signal can be configured as an asynchronous input through the GPIO peripheral See your device specific data manual to determine how many trip zone pins are available in the device Time base synch...

Page 465: ...16 Counter compare CC CMPB active 16 CTR CMPB CMPB shadow 16 CMPAHR 8 EPWMA EPWMB Dead band DB PC chopper PWM zone TZ Trip CTR 0 EPWMxA EPWMxB EPWMxTZINT TZ1 to TZn HiRes PWM HRPWM CTR PRD CTR 0 CTR CMPB CTR CMPA CTR_Dir Event trigger and interrupt ET EPWMxINT CTR 0 www ti com Introduction 465 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instru...

Page 466: ...No Counter Compare Control Register CMPAHR 10h 1 No Extension for HRPWM Counter Compare A Register 2 CMPA 12h 1 Yes Counter Compare A Register CMPB 14h 1 Yes Counter Compare B Register Action Qualifier Submodule Registers AQCTLA 16h 1 No Action Qualifier Control Register for Output A EPWMxA AQCTLB 18h 1 No Action Qualifier Control Register for Output B EPWMxB AQSFRC 1Ah 1 No Action Qualifier Softw...

Page 467: ...on up or down of the time base counter after a synchronization event Configure how the time base counter will behave when the device is halted by an emulator Specify the source for the synchronization output of the ePWM module Synchronization input signal Time base counter equal to zero Time base counter equal to counter compare B CMPB No output synchronization signal generated Section 16 2 3 Coun...

Page 468: ...Force EPWMxA and or EPWMxB low Force EPWMxA and or EPWMxB to a high impedance state Configure EPWMxA and or EPWMxB to ignore any trip condition Configure how often the ePWM will react to each trip zone pin One shot Cycle by cycle Enable the trip zone to initiate an interrupt Bypass the trip zone module entirely Section 16 2 8 Event trigger ET Enable the ePWM events that will trigger an interrupt S...

Page 469: ...it define TB_SYNC_IN 0x0 define TB_CTR_ZERO 0x1 define TB_CTR_CMPB 0x2 define TB_SYNC_DISABLE 0x3 HSPCLKDIV and CLKDIV bits define TB_DIV1 0x0 define TB_DIV2 0x1 define TB_DIV4 0x2 PHSDIR bit define TB_DOWN 0x0 define TB_UP 0x1 CMPCTL Compare Control LOADAMODE and LOADBMODE bits define CC_CTR_ZERO 0x0 define CC_CTR_PRD 0x1 define CC_CTR_ZERO_PRD 0x2 define CC_LD_DISABLE 0x3 SHDWAMODE and SHDWBMODE...

Page 470: ... TZCTL Trip zone Control TZA and TZB bits define TZ_HIZ 0x0 define TZ_FORCE_HI 0x1 define TZ_FORCE_LO 0x2 define TZ_NONE 0x3 ETSEL Event trigger Select INTSEL bit define ET_CTR_ZERO 0x1 define ET_CTR_PRD 0x2 define ET_CTRU_CMPA 0x4 define ET_CTRD_CMPA 0x5 define ET_CTRU_CMPB 0x6 define ET_CTRD_CMPB 0x7 ETPS Event trigger Prescale INTPRD bit define ET_DISABLE 0x0 define ET_1ST 0x1 define ET_2ND 0x2...

Page 471: ...ion logic allows the time base of multiple ePWM modules to work together as a single system Figure 16 4 illustrates the time base module s place within the ePWM Figure 16 4 Time Base Submodule Block Diagram 16 2 3 1 Purpose of the Time Base Submodule You can configure the time base submodule for the following Specify the ePWM time base counter TBCNT frequency or period to control how often events ...

Page 472: ... used to control and monitor the time base submodule 1 This register is available only on ePWM instances that include the high resolution extension HRPWM On ePWM modules that do not include the HRPWM this location is reserved See your device specific data manual to determine which ePWM instances include this feature Table 16 3 Time Base Submodule Registers Acronym Register Description Address Offs...

Page 473: ...ut logic CTR_dir Time base counter direction Indicates the current direction of the ePWM s time base counter This signal is high when the counter is increasing and low when it is decreasing CTR_max Time base counter equal max value TBCNT FFFFh Generated event when the TBCNT value reaches its maximum value This signal is only used only as a status bit TBCLK Time base clock This is a prescaled versi...

Page 474: ...egister The shadow register buffers or provides a temporary holding location for the active register It has no direct effect on any control hardware At a strategic point in time the shadow register s content is transferred to the active register This prevents corruption or spurious operation due to the register being asynchronously modified by software The memory address of the shadow period regis...

Page 475: ...solution Pulse Width Modulator eHRPWM 16 2 3 3 2 Time Base Counter Synchronization A time base synchronization scheme connects all of the ePWM modules on a device Each ePWM module has a synchronization input EPWMxSYNCI and a synchronization output EPWMxSYNCO The input synchronization for the first instance ePWM1 comes from an external pin The possible synchronization connections for the remaining ...

Page 476: ...BCTL PHSEN bit configures the ePWM to ignore the synchronization input pulse The synchronization pulse can still be allowed to flow through to the EPWMxSYNCO and be used to synchronize other ePWM modules In this way you can set up a master time base for example ePWM1 and downstream modules ePWM2 ePWMx may elect to run in synchronization with the master 16 2 3 4 Phase Locking the Time Base Clocks o...

Page 477: ...alue TBPRD value www ti com Architecture 477 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 16 8 Time Base Up Count Mode Waveforms ...

Page 478: ...CTR 0 CNT_max CTR PRD Architecture www ti com 478 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 16 9 Time Base Down Count Mode Waveforms Figure 16 10 Time Base Up Down Count Waveforms TBCTL PHSDIR 0 Count Down on Synchronization Event ...

Page 479: ...PRD www ti com Architecture 479 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 16 11 Time Base Up Down Count Waveforms TBCTL PHSDIR 1 Count Up on Synchronization Event ...

Page 480: ...B CTR 0 EPWMxINT EPWMxA EPWMxB TZ1 to TZn CTR CMPA Time Base TB CTR PRD CTR 0 CTR_Dir EPWMxSYNCI EPWMxSYNCO EPWMxTZINT PWM chopper PC Event Trigger and Interrupt ET Trip Zone TZ GPIO MUX Interrupt controller Interrupt controller Architecture www ti com 480 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resol...

Page 481: ...bmodule Table 16 5 lists the registers used to control and monitor the counter compare submodule Table 16 6 lists the key signals associated with the counter compare submodule 1 This register is available only on ePWM modules with the high resolution extension HRPWM On ePWM modules that do not include the HRPWM this location is reserved Refer to the device specific data manual to determine which e...

Page 482: ...ich register is written to or read from is determined by the CMPCTL SHDWAMODE and CMPCTL SHDWBMODE bits These bits enable and disable the CMPA shadow register and CMPB shadow register respectively The behavior of the two load modes is described below Shadow Mode The shadow mode for the CMPA is enabled by clearing the CMPCTL SHDWAMODE bit and the shadow register for CMPB is enabled by clearing the ...

Page 483: ...umentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 16 14 Counter Compare Event Waveforms in Up Count Mode NOTE An EPWMxSYNCI external synchronization event can cause a discontinuity in the TBCNT count sequence This can lead to a compare event being skipped This skipping is considered normal operation and must be taken...

Page 484: ...ti com 484 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 16 16 Counter Compare Events in Up Down Count Mode TBCTL PHSDIR 0 Count Down on Synchronization Event Figure 16 17 Counter Compare Events in Up Down Count Mode TBCTL PHSDIR 1 Count Up on Synchronization E...

Page 485: ...alifier Submodule 16 2 5 1 Purpose of the Action Qualifier Submodule The action qualifier submodule is responsible for the following Qualifying and generating actions set clear toggle based on the following events CTR PRD Time base counter equal to the period TBCNT TBPRD CTR 0 Time base counter equal to zero TBCNT 0000h CTR CMPA Time base counter equal to the counter compare A register TBCNT CMPA ...

Page 486: ... zero TBCNT 0000h CTR CMPA Time base counter equal to the counter compare A TBCNT CMPA CTR CMPB Time base counter equal to the counter compare B TBCNT CMPB Software forced event Asynchronous event initiated by software The software forced action is a useful asynchronous event This control is handled by registers AQSFRC and AQCSFRC The action qualifier submodule controls how the two outputs EPWMxA ...

Page 487: ... a given output For example both CTR CMPA and CTR CMPB can operate on output EPWMxA All qualifier actions are configured via the control registers found at the end of this section For clarity the drawings in this chapter use a set of symbolic actions These symbols are summarized in Figure 16 20 Each symbol represents an action as a marker in time Some actions are fixed in time zero and period whil...

Page 488: ...if TBCNT is Decrementing TBCNT TBPRD down to TBCNT 1 1 Highest Software forced event Software forced event 2 Counter equals CMPB on up count CBU Counter equals CMPB on down count CBD 3 Counter equals CMPA on up count CAU Counter equals CMPA on down count CAD 4 Counter equals zero Counter equals period TBPRD 5 Counter equals CMPB on down count CBD 1 Counter equals CMPB on up count CBU 1 6 Lowest Co...

Page 489: ...ompare register value In a running system the active compare registers CMPA and CMPB are typically updated from their respective shadow registers once every period The user specifies when the update will take place either when the time base counter reaches zero or when the time base counter reaches period There are some cases when the action based on the new value can be delayed by one period or t...

Page 490: ...ieved by using equal compare matches on the up count and down count portions of the waveform In the example shown CMPA is used to make the comparison When the counter is incrementing the CMPA match will pull the PWM output high Likewise when the counter is decrementing the compare match will pull the PWM signal low When CMPA 0 the PWM signal is low for the entire period giving the 0 duty waveform ...

Page 491: ...ut signals from ePWMx Up Down means Count up and down mode Up means up count mode and Dwn means down count mode Sym Symmetric Asym Asymmetric Table 16 13 and Table 16 14 contains initialization and runtime register configurations for the waveforms in Figure 16 22 Figure 16 22 Up Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Active High 1 PWM period TBPRD 1 TTBCLK...

Page 492: ...nter TBCTL CTRMODE TB_UP PHSEN TB_DISABLE Phase loading disabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_DISABLE HSPCLKDIV TB_DIV1 TBCLK SYSCLK CLKDIV TB_DIV1 CMPA CMPA 350 15Eh Compare A 350 TBCLK counts CMPB CMPB 200 C8h Compare B 200 TBCLK counts CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA ZRO AQ_SET CAU AQ_CLEAR AQCTLB ...

Page 493: ... Up Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Active Low 1 PWM period TBPRD 1 TTBCLK 2 Duty modulation for EPWMxA is set by CMPA and is active low that is the low time duty is proportional to CMPA 3 Duty modulation for EPWMxB is set by CMPB and is active low that is the low time duty is proportional to CMPB 4 The Do Nothing actions X are shown for completenes...

Page 494: ...nter TBCTL CTRMODE TB_UP PHSEN TB_DISABLE Phase loading disabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_DISABLE HSPCLKDIV TB_DIV1 TBCLK SYSCLK CLKDIV TB_DIV1 CMPA CMPA 350 15Eh Compare A 350 TBCLK counts CMPB CMPB 200 C8h Compare B 200 TBCLK counts CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA PRD AQ_CLEAR CAU AQ_SET AQCTLB ...

Page 495: ... Table 16 18 contains initialization and runtime register configurations for the waveforms Figure 16 24 Use the code in Example 16 1 to define the headers Figure 16 24 Up Count Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA 1 PWM frequency 1 TBPRD 1 TTBCLK 2 Pulse can be placed anywhere within the PWM cycle 0000h TBPRD 3 High time duty proportional to CMPB CMPA 4 EPWMxB ...

Page 496: ...CNT 0 Clear TB counter TBCTL CTRMODE TB_UP PHSEN TB_DISABLE Phase loading disabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_DISABLE HSPCLKDIV TB_DIV1 TBCLK SYSCLK CLKDIV TB_DIV1 CMPA CMPA 200 C8h Compare A 200 TBCLK counts CMPB CMPB 400 190h Compare B 400 TBCLK counts CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET CB...

Page 497: ...er configurations for the waveforms in Figure 16 25 Use the code in Example 16 1 to define the headers Figure 16 25 Up Down Count Dual Edge Symmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Active Low 1 PWM period 2 x TBPRD TTBCLK 2 Duty modulation for EPWMxA is set by CMPA and is active low that is the low time duty is proportional to CMPA 3 Duty modulation for EPWMxB is set by ...

Page 498: ...r TBCTL CTRMODE TB_UPDOWN PHSEN TB_DISABLE Phase loading disabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_DISABLE HSPCLKDIV TB_DIV1 TBCLK SYSCLK CLKDIV TB_DIV1 CMPA CMPA 400 190h Compare A 400 TBCLK counts CMPB CMPB 500 1F4h Compare B 500 TBCLK counts CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET CAD AQ_CLEAR AQCTL...

Page 499: ... 16 1 to define the headers Figure 16 26 Up Down Count Dual Edge Symmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Complementary 1 PWM period 2 TBPRD TTBCLK 2 Duty modulation for EPWMxA is set by CMPA and is active low i e low time duty proportional to CMPA 3 Duty modulation for EPWMxB is set by CMPB and is active high i e high time duty proportional to CMPB 4 Outputs EPWMx can d...

Page 500: ...r TBCTL CTRMODE TB_UPDOWN PHSEN TB_DISABLE Phase loading disabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_DISABLE HSPCLKDIV TB_DIV1 TBCLK SYSCLK CLKDIV TB_DIV1 CMPA CMPA 350 15Eh Compare A 350 TBCLK counts CMPB CMPB 400 190h Compare B 400 TBCLK counts CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET CAD AQ_CLEAR AQCTL...

Page 501: ... 16 1 to define the headers Figure 16 27 Up Down Count Dual Edge Asymmetric Waveform With Independent Modulation on EPWMxA Active Low 1 PWM period 2 TBPRD TBCLK 2 Rising edge and falling edge can be asymmetrically positioned within a PWM cycle This allows for pulse placement techniques 3 Duty modulation for EPWMxA is set by CMPA and CMPB 4 Low time duty for EPWMxA is proportional to CMPA CMPB 5 To...

Page 502: ...lear TB counter TBCTL CTRMODE TB_UPDOWN PHSEN TB_DISABLE Phase loading disabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_DISABLE HSPCLKDIV TB_DIV1 TBCLK SYSCLK CLKDIV TB_DIV1 CMPA CMPA 250 FAh Compare A 250 TBCLK counts CMPB CMPB 450 1C2h Compare B 450 TBCLK counts CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET CBD A...

Page 503: ... edge placement using both the CMPA and CMPB resources of the ePWM module However if the more classical edge delay based dead band with polarity control is required then the dead band generator submodule should be used The key functions of the dead band generator submodule are Generating appropriate signal pairs EPWMxA and EPWMxB with dead band relationship from a single EPWMxA input Programming s...

Page 504: ...ll be referred to as EPWMxA In and EPWMxB In Using the DBCTL IN_MODE control bits the signal source for each delay falling edge or rising edge can be selected EPWMxA In is the source for both falling edge and rising edge delay This is the default mode EPWMxA In is the source for falling edge delay EPWMxB In is the source for rising edge delay EPWMxA In is the source for rising edge delay EPWMxB In...

Page 505: ...ate drivers The waveforms for these typical cases are shown in Figure 16 30 Note that to generate equivalent waveforms to Figure 16 30 configure the action qualifier submodule to generate the signal as shown for EPWMxA Mode 6 Bypass rising edge delay and Mode 7 Bypass falling edge delay Finally the last two entries in Table 16 26 show combinations where either the falling edge delay FED or rising ...

Page 506: ...s waveforms for typical cases where 0 duty 100 Figure 16 30 Dead Band Waveforms for Typical Cases 0 Duty 100 The dead band submodule supports independent values for rising edge RED and falling edge FED delays The amount of delay is programmed using the DBRED and DBFED registers These are 10 bit registers and their value represents the number of time base clock TBCLK periods a signal edge is delaye...

Page 507: ...module The PWM chopper submodule allows a high frequency carrier signal to modulate the PWM waveform generated by the action qualifier and dead band submodules This capability is important if you need pulse transformer based gate drivers to control the power switching elements Figure 16 31 PWM Chopper Submodule 16 2 7 1 Purpose of the PWM Chopper Submodule The key functions of the PWM chopper subm...

Page 508: ...6 2 7 3 Operational Highlights for the PWM Chopper Submodule Figure 16 32 shows the operational details of the PWM chopper submodule The carrier clock is derived from SYSCLKOUT Its frequency and duty cycle are controlled via the CHPFREQ and CHPDUTY bits in the PCCTL register The one shot block is a feature that provides a high energy first pulse to ensure hard and fast power switch turn on while t...

Page 509: ... not shown Details of the one shot and duty cycle control are discussed in the following sections Figure 16 33 Simple PWM Chopper Submodule Waveforms Showing Chopping Action Only 16 2 7 4 1 One Shot Pulse The width of the first pulse can be programmed to any of 16 possible pulse width values The width or period of the first pulse is given by T1stpulse TSYSCLKOUT 8 OSHTWTH Where TSYSCLKOUT is the p...

Page 510: ...er and associated circuitry Saturation is one such consideration To assist the gate drive designer the duty cycles of the second and subsequent pulses have been made programmable These sustaining pulses ensure the correct drive strength and polarity is maintained on the power switch gate during the on period and hence a programmable duty cycle allows a design to be tuned or optimized via software ...

Page 511: ... indicates external fault or trip conditions and the ePWM outputs can be programmed to respond accordingly when faults occur See your device specific data manual to determine the number of trip zone pins available for the device Figure 16 36 Trip Zone Submodule 16 2 8 1 Purpose of the Trip Zone Submodule The key functions of the trip zone submodule are Trip inputs TZ1 to TZn can be flexibly mapped...

Page 512: ...a valid event present on the TZn inputs The TZ n input can be individually configured to provide either a cycle by cycle or one shot trip event for a ePWM module The configuration is determined by the TZSEL CBCn and TZSEL OSHTn bits where n corresponds to the trip pin respectively Cycle by Cycle CBC When a cycle by cycle trip event occurs the action specified in the TZCTL register is carried out i...

Page 513: ...ent Configure the ePWM2 registers as follows TZSEL OSHT1 1 enables TZ as a one shot event source for ePWM2 TZCTL TZA 1 EPWM2A will be forced high on a trip event TZCTL TZB 1 EPWM2B will be forced high on a trip event Scenario B A cycle by cycle event on TZ5 pulls both EPWM1A EPWM1B low A one shot event on TZ1 or TZ6 puts EPWM2A into a high impedance state Configure the ePWM1 registers as follows T...

Page 514: ...C1 to CBCn TZCLR OST TZFRC OSHT Sync Trip logic Trip Trip CBC trip event OSHT trip event EPWMxA EPWMxB EPWMxA EPWMxB TZCTL TZB TZCTL TZA Async Trip Set Clear TZFLG CBC TZCLR CBC Set Clear TZFLG OST TZn TZ1 TZSEL OSHT1 to OSHTn TZn Architecture www ti com 514 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Res...

Page 515: ...o the CPU Figure 16 39 Event Trigger Submodule 16 2 9 1 Purpose of the Event Trigger Submodule The key functions of the event trigger submodule are Receives event inputs generated by the time base and counter compare submodules Uses the time base direction information for up down event qualification Uses prescaling logic to issue interrupt requests at Every event Every second event Every third eve...

Page 516: ... 2 9 3 Operational Overview of the Event Trigger Submodule The following sections describe the event trigger submodule s operational highlights Each ePWM module has one interrupt request line connected to the interrupt controller as shown in Figure 16 40 Figure 16 40 Event Trigger Submodule Inter Connectivity to Interrupt Controller The event trigger submodule monitors various event conditions the...

Page 517: ...PA when the timer is decrementing Time base counter equal to the compare B register CMPB when the timer is incrementing Time base counter equal to the compare B register CMPB when the timer is decrementing The number of events that have occurred can be read from the interrupt event counter ETPS INTCNT register bits That is when the specified event occurs the ETPS INTCNT bits are incremented until ...

Page 518: ...G INT ETSEL INTSEL 000 001 010 011 100 101 111 101 0 0 CTRU CMPA CTRD CMPA CTRU CMPB CTRD CMPB CTR 0 CTR PRD Architecture www ti com 518 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 16 42 Event Trigger Interrupt Generator ...

Page 519: ... Trip CTR 0 EPWMxA EPWMxB EPWMxTZINT TZ1 to TZn HiRes PWM HRPWM CTR PRD CTR 0 CTR CMPB CTR CMPA CTR_Dir Event trigger and interrupt ET EPWMxINT CTR 0 www ti com Architecture 519 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM 16 2 10 High Resolution PWM HRPWM Submodule ...

Page 520: ...effective resolution for conventionally generated PWM is a function of PWM frequency or period and system clock frequency Figure 16 44 Resolution Calculations for Conventionally Generated PWM If the required PWM operating frequency does not offer sufficient resolution in PWM mode you may want to consider HRPWM As an example of improved performance offered by HRPWM Table 16 31 shows resolution in b...

Page 521: ...system clock and edge position in terms of MEP steps which are controlled via an 8 bit field in the Compare A extension register CMPAHR Figure 16 45 Operating Logic Using MEP A For MEP range and rounding adjustment To generate an HRPWM waveform configure the TBM CCM and AQM registers as you would to generate a conventional PWM of a given frequency and polarity The HRPWM works together with the TBM...

Page 522: ... valid only when operating from the CMPAHR register and should be chosen to be the same as the regular load option for the CMPA register If TBPHSHR is used then this option has no effect 16 2 10 5 Operational Highlights for the High Resolution PWM Submodule The MEP logic is capable of placing an edge in one of 255 8 bits discrete time steps each of which has a time resolution on the order of 150 p...

Page 523: ...s is equivalent to an edge position of 320 ns instead of the desired 324 ns This data is shown in Table 16 34 By utilizing the MEP you can achieve an edge position much closer to the desired point of 324 ns Table 16 34 shows that in addition to the CMPA value 22 steps of the MEP CMPAHR register will position the edge at 323 96 ns resulting in almost zero error In this example it is assumed that th...

Page 524: ... in ns Furthermore it makes the code more transportable across multiple converter types running different PWM frequencies To implement the mapping scheme a two step scaling procedure is required Assumptions for this example System clock SYSCLKOUT 10 ns 100 MHz PWM frequency 1 25 MHz 1 800 ns Required PWM duty cycle PWMDuty 0 405 40 5 PWM period in terms of coarse steps PWMperiod 800 ns 10 ns 80 Nu...

Page 525: ...s not available all the way down to 0 duty cycle Although for the first 3 or 6 cycles the HRPWM capabilities are not available regular PWM duty control is still fully operational down to 0 duty In most applications this should not be an issue as the controller regulation point is usually not designed to be close to 0 duty cycle Figure 16 47 Low Duty Cycle Range Limitation Example When PWM Frequenc...

Page 526: ...tandalone module or to operate in synchronization with other identical ePWM modules 16 3 1 Overview of Multiple Modules Previously in this user s guide all discussions have described the operation of a single module To facilitate the understanding of multiple modules working together in a system the ePWM module described in reference is represented by the more simplified block diagram shown in Fig...

Page 527: ...PWM boundaries SyncOut connected to CTR PRD Master mode provides a sync at any programmable point in time SyncOut connected to CTR CMPB Module is in standalone mode and provides No sync to other modules SyncOut connected to X disabled Options for SyncOut Sync flow through SyncOut connected to SyncIn Master mode provides a sync at PWM boundaries SyncOut connected to CTR PRD Master mode provides a s...

Page 528: ...ulator eHRPWM 16 3 3 Controlling Multiple Buck Converters With Independent Frequencies One of the simplest power converter topologies is the buck A single ePWM module configured as a master can control two buck stages with the same PWM frequency If independent frequency control is required for each buck converter then one ePWM module must be allocated for each converter stage Figure 16 51 shows fo...

Page 529: ...errupt I P I P I P I www ti com Applications to Power Topologies 529 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 16 52 Buck Waveforms for Figure 16 51 Note Only three bucks shown here ...

Page 530: ...AQ_SET Table 16 36 EPWM2 Initialization for Figure 16 52 Register Bit Value Comments TBPRD TBPRD 1400 578h Period 1401 TBCLK counts TBPHS TBPHS 0 Clear Phase Register to 0 TBCTL CTRMODE TB_UP PHSEN TB_DISABLE Phase loading disabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_DISABLE CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA P...

Page 531: ...ion for Example in Figure 16 52 Run Time Note Example execution of one run time instance EPwm1Regs CMPA half CMPA 700 adjust duty for output EPWM1A EPwm2Regs CMPA half CMPA 700 adjust duty for output EPWM2A EPwm3Regs CMPA half CMPA 500 adjust duty for output EPWM3A 16 3 4 Controlling Multiple Buck Converters With Same Frequencies If synchronization is a requirement ePWM module 2 can be configured ...

Page 532: ...A CA CA CA CB CB CB CB Applications to Power Topologies www ti com 532 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 16 54 Buck Waveforms for Figure 16 53 Note FPWM2 FPWM1 ...

Page 533: ...CTLB CBU AQ_SET Set actions for EPWM1B CBD AQ_CLEAR Table 16 39 EPWM2 Initialization for Figure 16 53 Register Bit Value Comments TBPRD TBPRD 600 258h Period 1200 TBCLK counts TBPHS TBPHS 0 Clear Phase Register to 0 TBCTL CTRMODE TB_UPDOWN PHSEN TB_ENABLE Phase loading enabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_IN Sync flow through CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO...

Page 534: ...control of multiple switching elements can also be addressed with these same ePWM modules It is possible to control a Half H bridge stage with a single ePWM module This control can be extended to multiple stages Figure 16 55 shows control of two synchronized Half H bridge stages where stage 2 can operate at integer multiple N frequencies of stage 1 Figure 16 56 shows the waveforms generated by the...

Page 535: ...CB CA A CB CA Z A CB CA Z A CB Z CA A CB Z CA www ti com Applications to Power Topologies 535 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 16 56 Half H Bridge Waveforms for Figure 16 55 Note FPWM2 FPWM1 ...

Page 536: ...CTLB ZRO AQ_CLEAR Set actions for EPWM1B CAD AQ_SET Table 16 41 EPWM2 Initialization for Figure 16 55 Register Bit Value Comments TBPRD TBPRD 600 258h Period 1200 TBCLK counts TBPHS TBPHS 0 Clear Phase Register to 0 TBCTL CTRMODE TB_UPDOWN PHSEN TB_ENABLE Phase loading enabled PRDLD TB_SHADOW SYNCOSEL TB_SYNC_IN Sync flow through CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO...

Page 537: ...h Modulator eHRPWM 16 3 6 Controlling Dual 3 Phase Inverters for Motors ACI and PMSM The idea of multiple modules controlling a single power stage can be extended to the 3 phase Inverter case In such a case six switching elements can be controlled using three PWM modules one for each leg of the inverter Each leg must switch at the same frequency and all legs must be synchronized A master two slave...

Page 538: ...CA CA CA CA CA CA CA CA CA CA Applications to Power Topologies www ti com 538 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 16 58 3 Phase Inverter Waveforms for Figure 16 57 Only One Inverter Shown ...

Page 539: ..._CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET Set actions for EPWM1A CAD AQ_CLEAR DBCTL MODE DB_FULL_ENABLE Enable Dead band module POLSEL DB_ACTV_HIC Active Hi complementary DBFED DBFED 50 FED 50 TBCLKs DBRED 50 RED 50 TBCLKs Table 16 43 EPWM2 Initialization for Figure 16 57 Register Bit Value Comments TBPRD TBPRD 800 320h Period 1600 TBCLK counts TBPHS TBPHS 0 Clear Phase Register to 0 TBCTL CTRMODE...

Page 540: ...HADOW SYNCOSEL TB_SYNC_IN Sync flow through CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET Set actions for EPWM3A CAD AQ_CLEAR DBCTL MODE DB_FULL_ENABLE Enable Dead band module POLSEL DB_ACTV_HIC Active Hi complementary DBFED DBFED 50 FED 50 TBCLKs DBRED 50 RED 50 TBCLKs Example 16 6 Code Snippet for Configur...

Page 541: ...BPHS multiple PWM modules can address another class of power topologies that rely on phase relationship between legs or stages for correct operation As described in the TB module section a PWM module can be configured to allow a SyncIn pulse to cause the TBPHS register to be loaded into the TBCNT register To illustrate this concept Figure 16 59 shows a master and slave module with a phase relation...

Page 542: ...e 1 configured as the master To work the phase relationship between adjacent modules must be F 120 This is achieved by setting the slave TBPHS registers 2 and 3 with values of 1 3 and 2 3 of the period value respectively For example if the period register is loaded with a value of 600 counts then TBPHS slave 2 200 and TBPHS slave 3 400 Both slave modules are synchronized to the master 1 module Thi...

Page 543: ...EPWM3B Phase reg Slave En SyncIn EPWM3A 1 2 3 VIN EPWM2B EPWM2A EPWM3A EPWM3B VOUT Φ 0 Φ 120 Φ 120 Φ 240 www ti com Applications to Power Topologies 543 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 16 61 Control of a 3 Phase Interleaved DC DC Converter ...

Page 544: ... Z I A P CA CA A P CA CA A P CA CA Applications to Power Topologies www ti com 544 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 16 62 3 Phase Interleaved DC DC Converter Waveforms for Figure 16 61 ...

Page 545: ...n CTR 0 AQCTLA CAU AQ_SET Set actions for EPWM1A CAD AQ_CLEAR DBCTL MODE DB_FULL_ENABLE Enable Dead band module POLSEL DB_ACTV_HIC Active Hi complementary DBFED DBFED 20 FED 20 TBCLKs DBRED 20 RED 20 TBCLKs Table 16 46 EPWM2 Initialization for Figure 16 61 Register Bit Value Comments TBPRD TBPRD 450 1C2h Period 900 TBCLK counts TBPHS TBPHS 300 Phase 300 900 360 120 TBCTL CTRMODE TB_UPDOWN PHSEN TB...

Page 546: ..._SYNC_IN Sync flow through PHSDIR TB_UP Count UP on sync CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR 0 LOADBMODE CC_CTR_ZERO Load on CTR 0 AQCTLA CAU AQ_SET Set actions for EPWM3A CAD AQ_CLEAR DBCTL MODE DB_FULL_ENABLE Enable Dead band module POLSEL DB_ACTV_HIC Active Hi complementary DBFED DBFED 20 FED 20 TBCLKs DBRED 20 RED 20 TBCLKs Example 16 7 Code Snippet...

Page 547: ...ly change the phase value on a cycle by cycle basis This feature lends itself to controlling a class of power topologies known as phase shifted full bridge or zero voltage switched full bridge Here the controlled parameter is not duty cycle this is kept constant at approximately 50 percent instead it is the phase relationship between legs Such a system can be implemented by allocating the resource...

Page 548: ...ransition Z CA Z I Z I Z I Z CB A CA CB A Z Z CB A CA Z Z CB A CA Applications to Power Topologies www ti com 548 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Enhanced High Resolution Pulse Width Modulator eHRPWM Figure 16 64 ZVS Full H Bridge Waveforms ...

Page 549: ...D 70 TBCLKs Table 16 49 EPWM2 Initialization for Figure 16 63 Register Bit Value Comments TBPRD TBPRD 1200 4B0h Period 1201 TBCLK counts TBPHS TBPHS 0 Clear Phase Register to 0 TBCTL CTRMODE TB_UP PHSEN TB_ENABLE Slave module PRDLD TB_SHADOW SYNCOSEL TB_SYNC_IN Sync flow through CMPA CMPA 600 258h Set 50 duty for EPWM2A CMPCTL SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on C...

Page 550: ...able 16 51 should be considered as reserved locations and the register contents should not be modified 1 This register is only available on ePWM instances that include the high resolution PWM HRPWM extension otherwise this location is reserved See your device specific data manual to determine which instances include the HRPWM Table 16 51 Time Base Submodule Registers Offset Acronym Register Descri...

Page 551: ...counter before the synchronization event In the up count and down count modes this bit is ignored 0 Count down after the synchronization event 1 Count up after the synchronization event 12 10 CLKDIV 0 7h Time base Clock Prescale Bits These bits determine part of the time base clock prescale value TBCLK SYSCLKOUT HSPCLKDIV CLKDIV 0 1 default on reset 1h 2 2h 4 3h 8 4h 16 5h 32 6h 64 7h 128 9 7 HSPC...

Page 552: ...ows 0 Up count mode 1h Down count mode 2h Up down count mode 3h Stop freeze counter operation default on reset 16 4 1 2 Time Base Status Register TBSTS The time base status register TBSTS is shown in Figure 16 66 and described in Table 16 53 Figure 16 66 Time Base Status Register TBSTS 15 3 2 1 0 Reserved CTRMAX SYNCI CTRDIR R 0 R W1C 0 R W1C 0 R 1 LEGEND R W Read Write R W1C Read Write 1 to clear...

Page 553: ...e If TBCTL PHSEN 1 then the time base counter TBCNT will be loaded with the phase TBPHS when a synchronization event occurs The synchronization event can be initiated by the input synchronization signal EPWMxSYNCI or by a software forced synchronization 16 4 1 4 Time Base Counter Register TBCNT The time base counter register TBCNT is shown in Figure 16 68 and described in Table 16 55 Figure 16 68 ...

Page 554: ...er equals zero If TBCTL PRDLD 1 then the shadow is disabled and any write or read will go directly to the active register that is the register actively controlling the hardware The active and shadow registers share the same memory map address 16 4 2 Counter Compare Submodule Registers Table 16 57 lists the memory mapped registers for the counter compare submodule See your device specific data manu...

Page 555: ...ce a load strobe occurs 0 CMPA shadow FIFO not full yet 1 Indicates the CMPA shadow FIFO is full a CPU write will overwrite the current shadow value 7 Reserved 0 Reserved 6 SHDWBMODE Counter compare B CMPB Register Operating Mode 0 Shadow mode Operates as a double buffer All writes via the CPU access the shadow register 1 Immediate mode Only the active compare B register is used All writes and rea...

Page 556: ...can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers The actions that can be defined in the AQCTLA and AQCTLB registers include Do nothing the event is ignored Clear Pull the EPWMxA and or EPWMxB signal low Set Pull the EPWMxA and or EPWMxB signal high Toggle the EPWMxA and or EPWMxB signal Shadowing of this register is enabled ...

Page 557: ...f this register is enabled and disabled by the CMPCTL SHDWBMODE bit By default this register is shadowed If CMPCTL SHDWBMODE 0 then the shadow is enabled and any write or read will automatically go to the shadow register In this case the CMPCTL LOADBMODE bit field determines which event will load the active register from the shadow register Before a write the CMPCTL SHDWBFULL bit can be read to de...

Page 558: ... output high 3h Toggle EPWMxA output low output signal will be forced high and a high signal will be forced low 7 6 CAD 0 3h Action when the counter equals the active CMPA register and the counter is decrementing 0 Do nothing action disabled 1h Clear force EPWMxA output low 2h Set force EPWMxA output high 3h Toggle EPWMxA output low output signal will be forced high and a high signal will be force...

Page 559: ...ut high 3h Toggle EPWMxB output low output signal will be forced high and a high signal will be forced low 7 6 CAD 0 3h Action when the counter equals the active CMPA register and the counter is decrementing 0 Do nothing action disabled 1h Clear force EPWMxB output low 2h Set force EPWMxB output high 3h Toggle EPWMxB output low output signal will be forced high and a high signal will be forced low...

Page 560: ... immediately the active register is directly accessed by the CPU and is not loaded from the shadow register 5 OTSFB One Time Software Forced Event on Output B 0 Writing a 0 zero has no effect Always reads back a 0 This bit is auto cleared once a write to this register is complete that is a forced event is initiated This is a one shot forced event It can be overridden by another subsequent event on...

Page 561: ...s no effect 1h Forces a continuous low on output B 2h Forces a continuous high on output B 3h Software forcing is disabled and has no effect 1 0 CSFA 0 3h Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register 0 Forcing disabled ...

Page 562: ...hown in Figure 16 29 This allows you to selectively invert one of the delayed signals before it is sent out of the dead band submodule The following descriptions correspond to classical upper lower switch control as found in one leg of a digital motor control inverter These assume that DBCTL OUT_MODE 1 1 and DBCTL IN_MODE 0 0 Other enhanced modes are also possible but not regarded as typical usage...

Page 563: ...r reset Table 16 68 Dead Band Generator Rising Edge Delay Register DBRED Field Descriptions Bits Name Value Description 15 10 Reserved 0 Reserved 9 0 DEL 0 3FFh Rising Edge Delay Count 10 bit counter 16 4 4 3 Dead Band Generator Falling Edge Delay Register DBFED The dead band generator falling edge delay register DBFED is shown in Figure 16 79 and described in Table 16 69 Figure 16 79 Dead Band Ge...

Page 564: ...ead only n value after reset Table 16 70 PWM Chopper Control Register PCCTL Bit Descriptions Bits Name Value Description 15 11 Reserved 0 Reserved 10 8 CHPDUTY 0 7h Chopping Clock Duty Cycle 0 Duty 1 8 12 5 1h Duty 2 8 25 0 2h Duty 3 8 37 5 3h Duty 4 8 50 0 4h Duty 5 8 62 5 5h Duty 6 8 75 0 6h Duty 7 8 87 5 7h Reserved 7 5 CHPFREQ 0 7h Chopping Clock Frequency 0 Divide by 1 no prescale 1h Divide b...

Page 565: ...ns are available in the device See your device specific data manual Figure 16 81 Trip Zone Select Register TZSEL 15 9 8 7 1 0 Reserved OSHTn 1 OSHT1 Reserved CBCn 1 CBC1 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write n value after reset Table 16 72 Trip Zone Submodule Select Register TZSEL Field Descriptions Bits Name Value Description 15 8 OSHTn Trip zone n TZn select One Shot OSHT trip zone enabl...

Page 566: ... 3h When a trip event occurs the following action is taken on output EPWMxA Which trip zone pins can cause an event is defined in the TZSEL register Section 16 4 6 1 0 High impedance EPWMxA High impedance state 1h Force EPWMxA to a high state 2h Force EPWMxA to a low state 3h Do nothing no action is taken on EPWMxA 16 4 6 3 Trip Zone Enable Interrupt Register TZEINT The trip zone enable interrupt ...

Page 567: ...red 1 Indicates a trip event has occurred on a pin selected as a cycle by cycle trip source The TZFLG CBC bit will remain set until it is manually cleared by the user If the cycle by cycle trip event is still present when the CBC bit is cleared then CBC will be immediately set again The specified condition on the pins is automatically cleared when the ePWM time base counter reaches zero TBCNT 0000...

Page 568: ...effect Always reads back a 0 1 Clears the trip interrupt flag for this ePWM module TZFLG INT NOTE No further EPWMxTZINT interrupts will be generated until the flag is cleared If the TZFLG INT bit is cleared and any of the other flag bits are set then another interrupt pulse will be generated Clearing all flag bits will prevent further interrupts 16 4 6 6 Trip Zone Force Register TZFRC The trip zon...

Page 569: ...rigger Force Register Section 16 4 7 5 16 4 7 1 Event Trigger Selection Register ETSEL The event trigger selection register ETSEL is shown in Figure 16 87 and described in Table 16 79 Figure 16 87 Event Trigger Selection Register ETSEL 15 4 3 2 0 Reserved INTEN INTSEL R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 16 79 Event Trigger Selection Register ETSEL Field Desc...

Page 570: ...t has occurred 2h 2 events have occurred 3h 3 events have occurred 1 0 INTPRD 0 3h ePWM Interrupt EPWMx_INT Period Select These bits determine how many selected ETSEL INTSEL events need to occur before an interrupt is generated To be generated the interrupt must be enabled ETSEL INT 1 If the interrupt status flag is set from a previous interrupt ETFLG INT 1 then no interrupt will be generated unti...

Page 571: ...tes that an ePWMx interrupt EWPMx_INT was generated No further interrupts will be generated until the flag bit is cleared Up to one interrupt can be pending while the ETFLG INT bit is still set If an interrupt is pending it will not be generated until after the ETFLG INT bit is cleared Refer to Figure 16 42 16 4 7 4 Event Trigger Clear Register ETCLR The event trigger clear register ETCLR is shown...

Page 572: ...L register The INT flag bit will be set regardless 0 Writing 0 to this bit will be ignored Always reads back a 0 1 Generates an interrupt on EPWMxINT and set the INT flag bit This bit is used for test purposes 16 4 8 High Resolution PWM Submodule Registers Table 16 84 lists the memory mapped registers for the high resolution PWM submodule See your device specific data manual for the memory address...

Page 573: ...ister TBPHSHR Field Descriptions Bit Field Value Description 15 8 TBPHSH 0 FFh Time base phase high resolution bits 7 0 Reserved 0 Reserved 16 4 8 2 Counter Compare A High Resolution Register CMPAHR The counter compare A high resolution register CMPAHR is shown in Figure 16 93 and described in Table 16 86 Figure 16 93 Counter Compare A High Resolution Register CMPAHR 15 8 7 0 CMPAHR Reserved R W 0...

Page 574: ...TR PRD counter equal period Note Load mode selection is valid only if CTLMODE 0 has been selected You should select this event to match the selection of the CMPA load mode CMPCTL LOADMODE bits in the EPWM module as follows 0 Load on CTR 0 Time base counter equal to zero TBCNT 0000h 1h Load on CTR PRD Time base counter equal to period TBCNT TBPRD 2h Load on either CTR 0 or CTR PRD should not be use...

Page 575: ...f transfer geometries and transfer sequences This chapter describes the features and operations of the EDMA3 controller Section 17 1 provides a brief overview features and terminology Section 17 2 provides the architecture details and common operations of the EDMA3 channel controllers EDMA3_m_CC0 and the EDMA3 transfer controllers EDMA3_m_TCn Section 17 3 contains examples and common usage scenari...

Page 576: ...parameter RAM PaRAM channel control registers and interrupt control registers The EDMA3CC serves to prioritize incoming software requests or events from peripherals and submits transfer requests TR to the EDMA3 transfer controller The EDMA3 transfer controllers are responsible for data movement The transfer request packets TRP submitted by the EDMA3CC contains the transfer context based on which t...

Page 577: ...arameter RAM PaRAM entries 2 event queues 4 shadow regions 2 transfer controllers EDMA3_0_TC0 and EDMA3_0_TC1 5 interrupts EDMA3_0_CC0_INT0 EDMA3_0_CC0_INT1 EDMA3_0_CC0_INT2 EDMA3_0_CC0_INT3 EDMA3_0_CC0_ERRINT EDMA3_1_CC0 32 DMA channels 8 QDMA channels 128 parameter RAM PaRAM entries 1 event queue 4 shadow regions 1 transfer controller EDMA3_1_TC0 5 interrupts EDMA3_1_CC0_INT0 EDMA3_1_CC0_INT1 ED...

Page 578: ...n be configured for 16 32 or 64 bytes burst size See the Chip Configuration 0 Register CFGCHIP0 in the System Configuration SYSCFG Module chapter for details to change the default burst size value Error interrupt EDMA3_0_TC0_ERRINT EDMA3 channel controller used EDMA3_0_CC0 EDMA3_0_TC1 FIFIOSIZE 128 bytes BUSWIDTH Read Write Controllers 8 byte 64 bits DSTREGDEPTH 4 DBS default 16 bytes The default ...

Page 579: ...iagram Figure 17 1 shows a block diagram of the EDMA3 controller Figure 17 1 EDMA3 Controller Block Diagram 17 1 4 Terminology Used in This Document The following are some terms used in this chapter Term Meaning A synchronized transfer A transfer type where 1 dimension is serviced per synchronization event AB synchronized transfer A transfer type where 2 dimensions are serviced per synchronization...

Page 580: ... set A PaRAM set that has all count fields cleared except for the link field A dummy PaRAM set has at least one of the count fields nonzero Null transfer A trigger event for a null PaRAM set results in the EDMA3CC performing a null transfer This is an error condition A dummy transfer is not an error condition QDMA channel One of the 8 channels that can be triggered when writing to the trigger word...

Page 581: ...errupt processing registers for enabling disabling interrupt to be sent to the CPU interrupt status clearing registers Additionally there are Region registers Region registers allow DMA resources DMA channels and interrupts to be assigned to unique regions which can be owned by unique EDMA programmers a use model for hetero multi core devices or by unique tasks threads a use model for single core ...

Page 582: ...f the TR and is responsible for submitting a valid transfer request TR to the appropriate EDMA3TC based on the event queue to EDMA3TC association Q0 goes to TC0 and Q1 goes to TC1 etc For more details see Section 17 2 3 The EDMA3TC receives the request and is responsible for data movement as specified in the transfer request packet TRP and other necessary tasks like buffering ensuring transfers ar...

Page 583: ...int by the write controller Completion interface The completion interface sends completion codes to the EDMA3CC when a transfer completes and is used for generating interrupts and chained events see Section 17 2 5 for details on transfer completion reporting Figure 17 3 EDMA3 Transfer Controller EDMA3TC Block Diagram When the EDMA3TC is idle and receives its first TR the TR is received in the DMA ...

Page 584: ...roller However the overall TR pipelining is also subject to the amount of free space in the data FIFO 17 2 2 Types of EDMA3 Transfers An EDMA3 transfer is always defined in terms of three dimensions Figure 17 4 shows the three dimensions used by EDMA3 transfers These three dimensions are defined as 1st Dimension or Array A The 1st dimension in a transfer consists of ACNT contiguous bytes 2nd Dimen...

Page 585: ...fer information for one array only Thus BCNT CCNT events are needed to completely service a PaRAM set Arrays are always separated by SRCBIDX and DSTBIDX as shown in Figure 17 5 where the start address of Array N is equal to the start address of Array N 1 plus source SRCBIDX or destination DSTBIDX Frames are always separated by SRCCIDX and DSTCIDX For A synchronized transfers after the frame is exh...

Page 586: ...service a PaRAM set Arrays are always separated by SRCBIDX and DSTBIDX as shown in Figure 17 6 Frames are always separated by SRCCIDX and DSTCIDX Note that for AB synchronized transfers after a TR for the frame is submitted the address update is to add SRCCIDX DSTCIDX to the beginning address of the beginning array in the frame This is different from A synchronized transfers where the address is u...

Page 587: ...ansfer parameters such as source address destination address transfer counts indexes options etc See your device specific data manual for the addresses of the PaRAM set entries The PaRAM structure supports flexible ping pong circular buffering channel chaining and autoreloading linking The first n PaRAM sets are directly mapped to the DMA channels where n is the number of DMA channels supported in...

Page 588: ...t between destination arrays within a frame 2nd dimension Valid values range from 32 768 and 32 767 14h 1 LINK Link Address The PaRAM address containing the PaRAM set to be linked copied from when the current PaRAM set is exhausted A value of FFFFh specifies a null link BCNTRLD BCNT Reload The count value used to reload BCNT when BCNT decrements to 0 TR submitted for the last array in 2nd dimensio...

Page 589: ... 0 and 65 535 Therefore the maximum number of bytes in an array is 65 535 bytes 64K 1 bytes ACNT must be greater than or equal to 1 for a TR to be submitted to EDMA3TC A transfer with ACNT equal to 0 is considered either a null or dummy transfer See Section 17 2 3 5 and Section 17 2 5 3 for details on dummy null completion conditions 17 2 3 2 5 Count for 2nd Dimension BCNT BCNT is a 16 bit unsigne...

Page 590: ...the beginning of the current array pointed to by SRC address to the beginning of the first source array in the next frame It applies to both A synchronized and AB synchronized transfers Note that when SRCCIDX is applied the current array in an A synchronized transfer is the last array in the frame Figure 17 5 while the current array in an AB synchronized transfer is the first array in the frame Fi...

Page 591: ...serviced A dummy transfer is a legal transfer of 0 bytes See Section 17 4 2 5 8 and Section 17 4 2 2 1 for more information on the SER and EMR registers respectively 17 2 3 5 Dummy Versus Null Transfer Comparison There are some differences in the way the EDMA3CC logic treats a dummy versus a null transfer request A null transfer request is an error condition but a dummy transfer is a legal transfe...

Page 592: ...ate source and destination addresses between arrays based on SRCBIDX and DSTBIDX Table 17 3 shows the details of parameter updates that occur within EDMA3CC for A synchronized and AB synchronized transfers 1 In all cases no updates occur if OPT STATIC 1 for the current PaRAM set Table 17 3 Parameter Updates in EDMA3CC for Non Null Non Dummy PaRAM Set A Synchronized Transfer AB Synchronized Transfe...

Page 593: ...sociated parameter set The EDMA3CC reads the entire PaRAM set 8 words from the PaRAM set specified by LINK and writes all 8 words to the PaRAM set associated with the current channel Figure 17 8 shows an example of a linked transfer Any PaRAM set in the PaRAM can be used as a link reload parameter set however it is recommended that the PaRAM sets associated with peripheral synchronization events s...

Page 594: ... only if the transfer source or destination on chip memory off chip memory controllers slave peripherals support the constant addressing mode See your device specific data manual to verify if constant addressing mode is supported If the constant addressing mode is not supported the similar logical transfer can be achieved using the increment INCR mode SAM DAM 0 by appropriately programming the cou...

Page 595: ...Parameter set 0 0 01C0 4000h 01C0 4040h 01C0 4060h 01C0 4020h 2 3 1 Parameter set 1 Parameter set 2 Parameter set 3 Byte address Set PaRAM 0h 0h Link FFFFh 0h 0h 0h 0h 0h 0h 0h 0h 0h PaRAM set 3 Null PaRAM set 0h 1CA0 4FE0h 127 Parameter set 127 c After completion of PaRAM set 127 link to null set OPT Y SRC Y BCNT Y ACNT Y DST Y SRCBIDX Y DSTBIDX Y Link Y FFFFh BCNTRLD Y CCNT Y SRCCIDX Y DSTCIDX Y...

Page 596: ... 4040h 01C0 4060h 01C0 4020h 2 3 1 Parameter set 1 Parameter set 2 Parameter set 3 Byte address Set PaRAM CCNT X SRCCIDX X Link 4FE0h SRCBIDX X ACNT X DSTCIDX X Rsvd BCNTRLD X DSTBIDX X DST X SRC X PaRAM set 3 OPT X 1CA0 4FE0h 127 Parameter set 127 c After completion of PaRAM set 127 link to self OPT X SRC X BCNT X ACNT X DST X SRCBIDX X DSTBIDX X Link 4FE0h BCNTRLD X CCNT X SRCCIDX X DSTCIDX X Rs...

Page 597: ...in the appropriate event queue When the event reaches the head of the queue it is evaluated for submission as a transfer request to the transfer controller If the PaRAM set is valid not a NULL set then a transfer request packet TRP is submitted to the EDMA3TC and the En bit in ER is cleared At this point a new event can be safely received by the EDMA3CC If the PaRAM set associated with the channel...

Page 598: ...nsfer Request Chaining is a mechanism by which the completion of one transfer automatically sets the event for another channel When a chained completion code is detected the value of which is dictated by the transfer completion code TCC 5 0 in OPT of the PaRAM set associated with the channel it results in the corresponding bit in the chained event register CER to be set CER E TCC 1 Once a bit is s...

Page 599: ...a second QDMA event for the same QDMA channel occurs prior to the original being cleared the second QDMA event gets captured in the QDMA event miss register QEMR En 1 17 2 4 3 Comparison Between DMA and QDMA Channels The primary difference between DMA and QDMA channels is the event channel synchronization QDMA events are either autotriggered or link triggered Autotriggering allows QDMA channels to...

Page 600: ...ctates which of the 64 bits in the chain event register CER TCC and or interrupt pending register IPR TCC is set See Section 17 2 9 for details on interrupts and Section 17 2 8 for details on chaining You can also selectively program whether the transfer controller sends back completion codes on completion of the final transfer request TR of a parameter set TCCHEN or TCINTEN for all but the final ...

Page 601: ... 2 3 3 In both cases the EDMA3 channel controller does not submit the associated transfer request to the EDMA3 transfer controller s However if the set dummy null has the OPT field programmed to return completion code intermediate final interrupt chaining completion then it will set the appropriate bits in the interrupt pending register IPR or chained event register CER The internal early completi...

Page 602: ...s Table 17 5 EDMA3 DMA Channel to PaRAM Mapping PaRAM Set Number Mapping PaRAM Set 0 DMA Channel 0 Reload QDMA PaRAM Set 1 DMA Channel 1 Reload QDMA PaRAM Set 2 DMA Channel 2 Reload QDMA PaRAM Set 3 DMA Channel 3 Reload QDMA PaRAM Set 4 DMA Channel 4 Reload QDMA PaRAM Set 5 DMA Channel 5 Reload QDMA PaRAM Set 6 DMA Channel 6 Reload QDMA PaRAM Set 7 DMA Channel 7 Reload QDMA PaRAM Set 8 DMA Channel...

Page 603: ...hannels and the PaRAM sets is programmable The QDMA channel n mapping register QCHMAPn in the EDMA3CC provides programmability for the QDMA channels to be mapped to any of the PaRAM sets in the PaRAM memory map Figure 17 10 illustrates the use of QCHMAP Additionally QCHMAP allows you to program the trigger word in the PaRAM set for the QDMA channel A trigger word is one of the 8 words in the PaRAM...

Page 604: ...t a single fixed location in the EDMA3CC memory map These registers control EDMA3 resource mapping and provide debug visibility and error tracking information See your device specific data manual for the EDMA3CC memory map The channel registers including DMA QDMA and interrupt registers are accessible via the global channel region address range or in the shadow n channel region address range s For...

Page 605: ...registers need to be programmed to assign ownership of DMA channels to the respective region Accesses to DMA event registers and interrupt registers via the shadow region address map are filtered through DRAE A value of 1 in the corresponding DRAE bit implies that the corresponding DMA interrupt channel is accessible a value of 0 in the corresponding DRAE bit forces writes to be discarded and retu...

Page 606: ...haining is different from linking Section 17 2 3 7 The EDMA3 link feature reloads the current channel parameter set with the linked parameter set The EDMA3 chaining feature does not modify or update any channel parameter set it provides a synchronization event to the chained channel see Section 17 2 4 1 3 for chain triggered transfer requests Chaining is achieved at either final transfer completio...

Page 607: ...Interrupt 95 17 2 9 1 Transfer Completion Interrupts The EDMA3CC is responsible for generating transfer completion interrupts to the CPU The EDMA3 generates a single completion interrupt per shadow region on behalf of all DMA QDMA channels Various control registers and bit fields facilitate EDMA3 interrupt generation The transfer completion code TCC value is directly mapped to the bits of the inte...

Page 608: ...r normal completion Table 17 11 shows the number of interrupts occurring in different synchronized scenarios Consider channel 31 programmed with ACNT 3 BCNT 4 CCNT 5 and TCC 30 Table 17 11 Number of Interrupts Options A Synchronized AB Synchronized TCINTEN 1 ITCINTEN 0 1 Last TR 1 Last TR TCINTEN 0 ITCINTEN 1 19 All but the last TR 4 All but the last TR TCINTEN 1 ITCINTEN 1 20 All TRs 5 All TRs 17...

Page 609: ...The DRAE for all regions is expected to be set up at system initialization and to remain static for an extended period of time The interrupt enable registers should be used for dynamic enable disable of individual interrupts Because there is no relation between the TCC value and the DMA QDMA channel it is possible for example for DMA channel 0 to have the OPT TCC 31 in its associated PaRAM set Thi...

Page 610: ...l IPR bits are cleared the EDMA3CC will assert additional completion interrupts It is possible that when one interrupt is serviced many other transfer completions result in additional bits being set in IPR thereby resulting in additional interrupts It is likely that each of these bits in IPR would need different types of service therefore the ISR must check all pending interrupts and continue unti...

Page 611: ...l be a unique and nonoverlapping in most cases assignment of the channels and interrupts among the different shadow regions This allows the interrupt registers IER IESR IECR IPR and ICR in the different shadow regions to functionally operate in an independent manner and nonoverlapping The above examples for the interrupt service routine is based on this assumption 17 2 9 3 Interrupt Evaluation Ope...

Page 612: ...OPT is set to 1 exceeding the maximum limit of 31 This also gets latched in the EDMA3CC error register CCERR Figure 17 13 illustrates the EDMA3CC error interrupt generation operation If any of the bits are set in the error registers due to any error condition the EDMA3_m_CC0_ERRINT always is asserted as there are no enables for masking these error events Similar to the transfer completion interrup...

Page 613: ...nt is processed and submitted as a transfer request packet TRP to the associated EDMA3 transfer controller A lower numbered queue has a higher dequeuing priority then a higher numbered queue For example Q0 has higher priority than Q1 if Q0 and Q1 both have at least one event entry and if both TC0 and TC1 can accept transfer requests then the event in Q0 is dequeued first and its associated PaRAM s...

Page 614: ...RTPTR field may be used to index appropriately into the 16 event entries The NUMVAL number of entries starting from STRTPTR are indicative of events still queued in the respective queue The remaining entries may be read to determine which events have already been de queued and submitted to the associated transfer controller 17 2 10 3 Queue Resource Tracking The EDMA3CC event queue includes waterma...

Page 615: ...ter set The number of Destination FIFO register set for a transfer controller determines the maximum number of outstanding transfer requests TR pipelining Of the four parameters the FIFOSIZE BUSWIDTH and DSTREGDEPTH values are fixed in design for a given device The default burst size DBS for EDMA3_0_TC0 and EDMA3_0_TC1 is configurable by the chip configuration 0 register CFGCHIP0 in the System Con...

Page 616: ... transfer such that the read side is equivalent to ACNT 64 BCNT 1 Cmd0 32 byte Cmd0 32 byte Write Controller Since DSTBIDX ACNT it is not optimized Cmd0 8 byte Cmd1 8 byte Cmd2 8 byte Cmd3 8 byte Cmd4 8 byte Cmd5 8 byte Cmd6 8 byte Cmd7 8 byte 2 ACNT 64 BCNT 1 SRCADDR 31 DSTADDR 513 Read Controller Read address is not aligned Cmd0 1 byte now the SRCADDR is aligned to 32 for the next command Cmd1 3...

Page 617: ...d to derive a brief history of TRs serviced through the transfer controller Additionally the EDMA3TC status register TCSTAT has dedicated bit fields to indicate the ongoing activity within different parts of the transfer controller The SRCACTV bit indicates whether the source active set is active The DSTACTV bit indicates the number of TRs resident in the destination register active set at a given...

Page 618: ...ther it is a non null and non dummy transfer request TR 4 The EDMA3CC clears the ER En or CER En ESR En QER En bit and the SER En bit as soon as it determines the TR is non null In the case of a null set the SER En bit remains set It submits the non null non dummy TR to the associated transfer controller If the TR was programmed for early completion the EDMA3CC immediately sets the interrupt pendi...

Page 619: ... implementation rules to deal with concurrent events channels transfers etc The following subsections detail various arbitration details whenever there might be occurrence of concurrent activity Figure 17 14 shows the different places EDMA3 priorities come into play 17 2 13 1 Channel Priority The DMA event register ER captures all external peripheral events connected to the EDMA3CC likewise the QD...

Page 620: ...with the lower numbered higher priority queue is busy processing earlier transfer requests and the transfer controller associated with the higher numbered lower priority queue is idle then the event in the higher numbered lower priority queue will dequeue first 17 2 13 4 Master Transfer Controller Priority All master peripherals on the device have a programmable priority level When multiple master...

Page 621: ...r certain conditions For 2D transfers that is BCNT arrays of ACNT bytes if the ACNT value is less than or equal to the DBS value then the transfer controller will try to optimize the TR into a 1D transfer in order to maximize efficiency The optimization only takes place if the EDMA3TC recognizes that the 2D transfer is organized as a single dimension SAM DAM 0 increment mode SRC DST BIDX ACNT the ...

Page 622: ...ontents are undefined after device reset and you should not rely on parameters to be reset to a known state The PaRAM set must be initialized to a desired value before it is used 17 2 17 Power Management The EDMA3 EDMA3CC and EDMA3TC can be placed in reduced power modes to conserve power during periods of low activity The power management of the peripheral is controlled by the device Power and Sle...

Page 623: ...viced by the EDMA 17 3 Transfer Examples The EDMA3 channel controller performs a variety of transfers depending on the parameter configuration The following sections provides a description and PaRAM configuration for some typical use case scenarios 17 3 1 Block Move Example The most basic transfer performed by the EDMA3 is a block move During device operation it is often necessary to transfer a bl...

Page 624: ... for 2nd Dimension BCNT Count for 1st Dimension ACNT 1180 0000h Channel Destination Address DST 0000h 0000h Destination BCNT Index DSTBIDX Source BCNT Index SRCBIDX 0000h FFFFh BCNT Reload BCNTRLD Link Address LINK 0000h 0000h Destination CCNT Index DSTCIDX Source CCNT Index SRCCIDX 0000h 0001h Reserved Count for 3rd Dimension CCNT b Channel Options Parameter OPT Content 31 30 28 27 24 23 22 21 20...

Page 625: ...ixel frame of video data is stored in external memory SDRAM Each pixel is represented by a 16 bit halfword The CPU extracts a 16 12 pixel subframe of the image for processing To facilitate more efficient processing time by the CPU the EDMA3 places the subframe in internal L2 SRAM Figure 17 17 shows the transfer of a subframe from external memory to L2 Figure 17 18 shows the parameters for this tra...

Page 626: ...y with each array occupying a portion of contiguous memory spaces For these instances the EDMA3 can reorganize the data into the desired format Figure 17 19 shows the data sorting In order to determine the parameter entry values the following need to be considered ACNT Program this to be the size in bytes of an array BCNT Program this to be the number of arrays in a frame CCNT Program this to be t...

Page 627: ...t for 2nd Dimension BCNT Count for 1st Dimension ACNT 1180 0000h Channel Destination Address DST 0010h 0004h Destination BCNT Index DSTBIDX Source BCNT Index SRCBIDX 0000h FFFFh BCNT Reload BCNTRLD Link Address LINK 0004h 1000h Destination CCNT Index DSTCIDX Source CCNT Index SRCCIDX 0000h 0004h Reserved Count for 3rd Dimension CCNT b Channel Options Parameter OPT Content 31 30 28 27 24 23 22 21 2...

Page 628: ... the CPU Data is always provided with some kind of synchronization event as either one element per event nonbursting or multiple elements per event bursting 17 3 4 1 Nonbursting Peripherals Nonbursting peripherals include the on chip multichannel buffered serial port McBSP and many external devices such as codecs Regardless of the peripheral the DMA channel configuration is the same The McBSP tran...

Page 629: ...nt for 2nd Dimension BCNT Count for 1st Dimension ACNT 1180 0000h Channel Destination Address DST 0001h 0000h Destination BCNT Index DSTBIDX Source BCNT Index SRCBIDX 0000h FFFFh BCNT Reload BCNTRLD Link Address LINK 0000h 0000h Destination CCNT Index DSTCIDX Source CCNT Index SRCCIDX 0000h 0004h Reserved Count for 3rd Dimension CCNT b Channel Options Parameter OPT Content 31 30 28 27 24 23 22 21 ...

Page 630: ... using AB synchronization The source address is set to the location of the video framer peripheral and the destination address is set to the start of the data buffer Since the input address is static the SRCBIDX is 0 no modification to the source address The destination is made up of arrays of contiguous linear elements therefore the DSTBIDX is set to pixel size 2 bytes ANCT is equal to the pixel ...

Page 631: ...VT for every element transmitted To service the data streams the DMA channels associated with the McBSP must be set up for 1D to 1D transfers with A synchronization Figure 17 26 shows the parameters for the parameter entries for the channel for these transfers In order to service the McBSP continuously throughout CPU operation the channels must be linked to a duplicate PaRAM set in the PaRAM After...

Page 632: ...00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0000 0 000 0000 0 0 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM c EDMA Parameters for Transmit Channel PaRAM Set 2 being Linked to PaRAM Set 65 Parameter Contents Parameter 0010 1000h Channel Options Parameter OPT 1180 1000h Channel Source Address SRC 0080h 0001h Count for 2nd Dimension BCNT C...

Page 633: ... 1 00 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0000 0 000 0000 0 0 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM c EDMA Reload Parameters PaRAM Set 65 for Transmit Channel Parameter Contents Parameter 0010 1000h Channel Options Parameter OPT 1180 1000h Channel Source Address SRC 0080h 0001h Count for 2nd Dimension BCNT Count for 1st Dimen...

Page 634: ...ut of the ping buffers the CPU manipulates the data in the pong buffers When both CPU and EDMA3 activity completes they switch The EDMA3 then writes over the old input data and transfers the new output data Figure 17 28 shows the ping pong scheme for this example To change the continuous operation example such that a ping pong buffering scheme is used the DMA channels need only a moderate change I...

Page 635: ...rect Memory Access EDMA3 Controller 17 3 4 4 1 Synchronization with the CPU In order to utilize the ping pong buffering technique the system must signal the CPU when to begin to access the new data set After the CPU finishes processing an input buffer ping it waits for the EDMA3 to complete before switching to the alternate pong buffer In this example both channels provide their channel numbers as...

Page 636: ...0 00 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved TCC 15 12 11 10 8 7 4 3 2 1 0 0011 0 000 0000 0 0 0 0 TCC TCCMOD FWID Reserved STATIC SYNCDIM DAM SAM c EDMA Parameters for Channel 2 Using PaRAM Set 2 Linked to Pong Set 65 Parameter Contents Parameter 0010 2000h Channel Options Parameter OPT 1180 1000h Channel Source Address SRC 0080h 0001h Count for 2nd Dimension BCNT Count for ...

Page 637: ...LD Link Address LINK 0000h 0000h Destination CCNT Index DSTCIDX Source CCNT Index SRCCIDX 0000h 0001h Reserved Count for 3rd Dimension CCNT Figure 17 31 Ping Pong Buffering for McBSP Example Ping PaRAM a EDMA Ping Parameters for Channel 3 at Set 65 Linked to Set 64 Parameter Contents Parameter 0010 D000h Channel Options Parameter OPT 01D0 0000h Channel Source Address SRC 0080h 0001h Count for 2nd ...

Page 638: ...termediate transfer chaining ITCCHEN is for breaking up large transfers A large transfer may lock out other transfers of the same priority level for the duration of the transfer For example a large transfer on queue 0 from the internal memory to the external memory using the EMIF may starve other EDMA3 transfers on the same queue In addition this large high priority transfer may prevent the EMIF f...

Page 639: ...s event 31 ITCCHEN 1 TCC 001 1 111b and sets CER E31 1 B Transfer complete chaining synchronizes event 31 TCCHEN 1 TCC 001 1 111b and sets CER E31 1 to CPU Enable transfer complete chaining OPT TCCHEN 1 OPT TCC 001 1111b Enable intermediate transfer complete chaining OPT ITCCHEN 1 OPT TCC 001 1111b Disable intermediate transfer OPT TCINTEN 1 OPT ITCCHEN 0 complete chaining OPT TCC 001 1111b comple...

Page 640: ...s section discusses the registers of the EDMA3 controller 17 4 1 Parameter RAM PaRAM Entries Table 17 14 lists the parameter RAM PaRAM entries for the EDMA3 channel controller EDMA3CC See your device specific data manual for the memory address of these registers Table 17 14 EDMA3 Channel Controller EDMA3CC Parameter RAM PaRAM Entries Offset Acronym Parameter Section 0h OPT Channel Options Section ...

Page 641: ...ining is disabled 1 Intermediate transfer complete chaining is enabled When enabled the chained event register CER bit is set on every intermediate chained transfer completion upon completion of every intermediate TR in the PaRAM set except the final TR in the PaRAM set The bit position set in CER is the TCC value specified 22 TCCHEN Transfer complete chaining enable 0 Transfer complete chaining i...

Page 642: ...transfers 2 SYNCDIM Transfer synchronization dimension 0 A synchronized Each event triggers the transfer of a single array of ACNT bytes 1 AB synchronized Each event triggers the transfer of BCNT arrays of ACNT bytes 1 DAM Destination address mode 0 Increment INCR mode Destination addressing within an array increments Destination is not a FIFO 1 Constant addressing CONST mode Destination addressin...

Page 643: ...ddress of the source 17 4 1 3 A Count B Count Parameter A_B_CNT The A count B count parameter A_B_CNT specifies the number of bytes within the 1st dimension of a transfer and the number of arrays of length ACNT The A_B_CNT is shown in Figure 17 37 and described in Table 17 17 Figure 17 37 A Count B Count Parameter A_B_CNT 31 16 BCNT R W x 15 0 ACNT R W x LEGEND R W Read Write n value after reset x...

Page 644: ...e B index destination B index parameter SRC_DST_BIDX specifies the value 2s complement used for source address modification between each array in the 2nd dimension and the value 2s complement used for destination address modification between each array in the 2nd dimension The SRC_DST_BIDX is shown in Figure 17 39 and described in Table 17 19 Figure 17 39 Source B Index Destination B Index Paramet...

Page 645: ... 17 20 Figure 17 40 Link Address B Count Reload Parameter LINK_BCNTRLD 31 16 BCNTRLD R W x 15 0 LINK R W x LEGEND R W Read Write n value after reset x value is indeterminate after reset Table 17 20 Link Address B Count Reload Parameter LINK_BCNTRLD Field Descriptions Bit Field Value Description 31 16 BCNTRLD 0 FFFFh B count reload The count value used to reload BCNT in the A count B count paramete...

Page 646: ...ndex Destination C Index Parameter SRC_DST_CIDX Field Descriptions Bit Field Value Description 31 16 DSTCIDX 0 FFFFh Destination C index Signed value specifying the byte address offset between frames within a block 3rd dimension Valid values range from 32 768 and 32 767 15 0 SRCCIDX 0 FFFFh Source C index Signed value specifying the byte address offset between frames within a block 3rd dimension V...

Page 647: ...P7 QDMA Channel 7 Mapping Register Section 17 4 2 1 3 240h DMAQNUM0 DMA Channel Queue Number Register 0 Section 17 4 2 1 4 244h DMAQNUM1 DMA Channel Queue Number Register 1 Section 17 4 2 1 4 248h DMAQNUM2 DMA Channel Queue Number Register 2 Section 17 4 2 1 4 24Ch DMAQNUM3 DMA Channel Queue Number Register 3 Section 17 4 2 1 4 260h QDMAQNUM QDMA Channel Queue Number Register Section 17 4 2 1 5 28...

Page 648: ...ar Register Section 17 4 2 6 5 1078h IEVAL Interrupt Evaluate Register Section 17 4 2 6 6 1080h QER QDMA Event Register Section 17 4 2 7 1 1084h QEER QDMA Event Enable Register Section 17 4 2 7 2 1088h QEECR QDMA Event Enable Clear Register Section 17 4 2 7 3 108Ch QEESR QDMA Event Enable Set Register Section 17 4 2 7 4 1090h QSER QDMA Secondary Event Register Section 17 4 2 7 5 1094h QSECR QDMA S...

Page 649: ...able Register 2228h EECR Event Enable Clear Register 2230h EESR Event Enable Set Register 2238h SER Secondary Event Register 2240h SECR Secondary Event Clear Register 2250h IER Interrupt Enable Register 2258h IECR Interrupt Enable Clear Register 2260h IESR Interrupt Enable Set Register 2268h IPR Interrupt Pending Register 2270h ICR Interrupt Clear Register 2278h IEVAL Interrupt Evaluate Register 2...

Page 650: ...VID Field Descriptions Bit Field Value Description 31 0 REV Peripheral identifier 4001 5300h Uniquely identifies the EDMA3CC and the specific revision of the EDMA3CC 17 4 2 1 2 EDMA3CC Configuration Register CCCFG The EDMA3CC configuration register CCCFG provides the features resources for the EDMA3CC in a particular device The CCCFG is shown in Figure 17 44 and described in Table 17 25 Figure 17 ...

Page 651: ...try n corresponds to channel n 1 Reserved 23 22 Reserved 0 Reserved 21 20 NUM_REGN 0 3h Number of shadow regions 0 1h Reserved 2h 4 regions 3h Reserved 19 Reserved 0 Reserved 18 16 NUM_EVQUE 0 7h Number of queues number of transfer controllers 0 Reserved 1h 2 event queues 2h 2 transfer controllers 3h 7h Reserved 15 Reserved 0 Reserved 14 12 NUM_PAENTRY 0 7h Number of PaRAM sets 0 2h Reserved 3h 12...

Page 652: ...MA channel mapping registers for all QDMA channels point to the PaRAM set 0 Prior to using any QDMA channel QCHMAPn should be programmed appropriately to point to a different PaRAM set Figure 17 45 QDMA Channel n Mapping Register QCHMAPn 31 16 Reserved R 0 15 14 13 5 4 2 1 0 Reserved PAENTRY TRWORD Reserved R 0 R W 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 17 26 QDMA ...

Page 653: ...ement or which EDMA3TC receives the TR request Figure 17 46 DMA Channel Queue Number Register n DMAQNUMn 31 30 28 27 26 24 23 22 20 19 18 16 Rsvd En Rsvd En Rsvd En Rsvd En R 0 R W 0 R 0 R W 0 R 0 R W 0 R 0 R W 0 15 14 12 11 10 8 7 6 4 3 2 0 Rsvd En Rsvd En Rsvd En Rsvd En R 0 R W 0 R 0 R W 0 R 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 17 27 DMA Channel Queue Nu...

Page 654: ...E2 Rsvd E1 Rsvd E0 R 0 R W 0 R 0 R W 0 R 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 17 29 QDMA Channel Queue Number Register QDMAQNUM Field Descriptions Bit Field Value Description 31 0 En 0 7h QDMA queue number Contains the event queue number to be used for the corresponding QDMA channel 0 Event n is queued on Q0 1h Event n is queued on Q1 Available only for EDM...

Page 655: ...R bit for a channel is also set if an event on that channel encounters a NULL entry or a NULL TR is serviced If any EMR bit is set and all errors including bits in other error registers QEMR CCERR were previously cleared the EDMA3CC generates an error interrupt See Section 17 2 9 4 for details on EDMA3CC error interrupt generation The EMR is shown in Figure 17 48 and described in Table 17 30 Figur...

Page 656: ... 17 49 and described in Table 17 31 Figure 17 49 Event Missed Clear Register EMCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W ...

Page 657: ... QEMR bit is set and all errors including bits in other error registers EMR or CCERR were previously cleared the EDMA3CC generates an error interrupt See Section 17 2 9 4 for details on EDMA3CC error interrupt generation The QEMR is shown in Figure 17 50 and described in Table 17 32 Figure 17 50 QDMA Event Missed Register QEMR 31 16 Reserved R 0 15 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E...

Page 658: ...ars the corresponding missed event bit in QEMR writing a 0 has no effect The QEMCR is shown in Figure 17 51 and described in Table 17 33 Figure 17 51 QDMA Event Missed Clear Register QEMCR 31 16 Reserved R 0 15 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND W Write only n value after reset Table 17 33 QDMA Event Missed Clear Register QEMCR Field Descr...

Page 659: ...ERR they can only be cleared by writing to the corresponding bits in the EDMA3CC error clear register CCERRCLR The CCERR is shown in Figure 17 52 and described in Table 17 34 Figure 17 52 EDMA3CC Error Register CCERR 31 17 16 Reserved TCCERR R 0 R 0 15 2 1 0 Reserved QTHRXCD1 QTHRXCD0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 17 34 EDMA3CC Error Register CCERR Field Descriptions Bit...

Page 660: ...d described in Table 17 35 Figure 17 53 EDMA3CC Error Clear Register CCERRCLR 31 17 16 Reserved TCCERR W 0 W 0 15 2 1 0 Reserved QTHRXCD1 QTHRXCD0 W 0 W 0 W 0 LEGEND W Write only n value after reset Table 17 35 EDMA3CC Error Clear Register CCERRCLR Field Descriptions Bit Field Value Description 31 17 Reserved 0 Reserved 16 TCCERR Transfer completion code error clear 0 No effect 1 Clears the TCCERR...

Page 661: ...ults in reasserting the EDMA3CC error interrupt if there are any outstanding error bits set due to subsequent error conditions Writes of 0 have no effect The EEVAL is shown in Figure 17 54 and described in Table 17 36 Figure 17 54 Error Evaluate Register EEVAL 31 16 Reserved R 0 15 2 1 0 Reserved Rsvd EVAL R 0 R W 0 W 0 LEGEND R W Read Write R Read only W Write only n value after reset Table 17 36...

Page 662: ...ection 17 2 9 The DRAEm is shown in Figure 17 55 and described in Table 17 37 Figure 17 55 DMA Region Access Enable Register for Region m DRAEm 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E15 E14 E1...

Page 663: ...e 17 38 Figure 17 56 QDMA Region Access Enable for Region m QRAEm 31 16 Reserved R 0 15 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 17 38 QDMA Region Access Enable for Region m QRAEm Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 En QDMA region access ...

Page 664: ...E15 and Q1E0 to Q1E15 Each register details the event number ENUM and the event type ETYPE For example if the value in Q1E4 is read as 0000 004Fh this means the 4th entry in queue 1 is a manually triggered event on DMA channel 15 The QxEy is shown in Figure 17 57 and described in Table 17 39 Figure 17 57 Event Queue Entry Registers QxEy 31 16 Reserved R 0 15 8 7 6 5 4 0 Reserved ETYPE Rsvd ENUM R ...

Page 665: ...0 Threshold specified by the Qn bit in the queue watermark threshold A register QWMTHRA has not been exceeded 1 Threshold specified by the Qn bit in the queue watermark threshold A register QWMTHRA has been exceeded 23 21 Reserved 0 Reserved 20 16 WM 0 1Fh Watermark for maximum queue usage Watermark tracks the most entries that have been in queue n since reset or since the last time that the water...

Page 666: ...ription 31 13 Reserved 0 Reserved 12 8 Q1 0 1Fh Queue threshold for queue 1 value The QTHRXCD1 bit in the EDMA3CC error register CCERR and the THRXCD bit in the queue status register 1 QSTAT1 are set when the number of events in queue 1 at an instant in time visible via the NUMVAL bit in QSTAT1 equals or exceeds the value specified by Q1 0 10h The default is 16 maximum allowed 11h Disables the thr...

Page 667: ...uest active The COMPACTV field reflects the count for the number of completion requests submitted to the transfer controllers This count increments every time a TR is submitted and is programmed to report completion the TCINTEN or TCCCHEN bits in OPT in the parameter entry associated with the TR are set to 1 The counter decrements for every valid TCC received back from the transfer controllers If ...

Page 668: ...7 42 EDMA3CC Status Register CCSTAT Field Descriptions continued Bit Field Value Description 1 QEVTACTV QDMA event active 0 No enabled QDMA events are active within the EDMA3CC 1 At least one enabled QDMA event QER is active within the EDMA3CC 0 EVTACTV DMA event active 0 No enabled DMA events are active within the EDMA3CC 1 At least one enabled DMA event ER and EER ESR CER is active within the ED...

Page 669: ...eady set and another event is received on the same channel event then the corresponding event is latched in the event miss register EMR En provided that the event was enabled EER En 1 Event n can be cleared by the CPU writing a 1 to corresponding event bit in the event clear register ECR The setting of an event is a higher priority relative to clear operations via hardware or software If set and c...

Page 670: ...t is set in the event register it remains set until EDMA3CC submits a transfer request for that event or the CPU clears the event by setting the corresponding bit in ECR The ECR is shown in Figure 17 62 and described in Table 17 44 Figure 17 62 Event Clear Register ECR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 W 0 W 0 W 0 W 0 W ...

Page 671: ...ons via hardware If set and clear conditions occur concurrently the set condition wins If the event was previously set then EMR would be set since an event is lost If the event was previously clear then the event remains set and is prioritized for submission to the event queues Manually triggered transfers via writes to ESR allow the CPU to submit DMA requests in the system these are relevant for ...

Page 672: ...gister are cleared when the corresponding events are prioritized and serviced If the En bit is already set and another chaining completion code is return for the same event then the corresponding event is latched in the event missed register EMR En 1 The setting of an event is a higher priority relative to clear operations via hardware If set and clear conditions occur concurrently the set conditi...

Page 673: ...y set in the event register enables the EDMA3CC to process the already set event like any other new event The EER settings do not have any effect on chained events CER En 1 and manually set events ESR En 1 The EER is shown in Figure 17 65 and described in Table 17 47 Figure 17 65 Event Enable Register EER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 E31 E30 E29 E28 E27 E26 E25 E24 E23 E22 E21 E...

Page 674: ...lear Register EECR Field Descriptions Bit Field Value Description 31 0 En Event enable clear for events 0 31 0 No effect 1 Event is disabled Corresponding bit in the event enable register EER is cleared En 0 17 4 2 5 7 Event Enable Set Register EESR The event enable register EER cannot be modified by directly writing to it The intent is to ease the software burden for the case where multiple tasks...

Page 675: ...E23 E22 E21 E20 E19 E18 E17 E16 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 17 50 Secondary Event Register SER Field Descriptions Bit Field Value Description 31 0 En Secondary eve...

Page 676: ...nels The IER cannot be written to directly To set any interrupt bit in IER a 1 must be written to the corresponding interrupt bit in the interrupt enable set registers IESR Similarly to clear any interrupt bit in IER a 1 must be written to the corresponding interrupt bit in the interrupt enable clear register IECR The IER is shown in Figure 17 70 and described in Table 17 52 Figure 17 70 Interrupt...

Page 677: ...able Clear Register IECR Field Descriptions Bit Field Value Description 31 0 En Interrupt enable clear for channels 0 31 0 No effect 1 Corresponding bit in the interrupt enable register IER is cleared In 0 17 4 2 6 3 Interrupt Enable Set Register IESR The interrupt enable set register IESR is used to enable interrupts Writes of 1 to the bits in IESR set the corresponding interrupt bits in the inte...

Page 678: ...er IPR In if n 0 to 31 Note that once a bit is set in the interrupt pending registers it remains set it is your responsibility to clear these bits The bits set in IPR are cleared by writing a 1 to the corresponding bits in the interrupt clear registers ICR The IPR is shown in Figure 17 73 and described in Table 17 55 Figure 17 73 Interrupt Pending Register IPR 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 679: ...upts The ICR is shown in Figure 17 74 and described in Table 17 56 Figure 17 74 Interrupt Clear Register ICR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 I31 I30 I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 I16 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 W 0 W 0 W 0 W 0 W 0 W 0...

Page 680: ...cribed in Table 17 57 Figure 17 75 Interrupt Evaluate Register IEVAL 31 16 Reserved R 0 15 2 1 0 Reserved Rsvd EVAL R 0 W 0 W 0 LEGEND R Read only W Write only n value after reset Table 17 57 Interrupt Evaluate Register IEVAL Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 Reserved 0 Reserved Always write 0 to this bit writes of 1 to this bit are not supported and attempt...

Page 681: ...ched only if the QDMA event enable register QEER channel n bit is also enabled QEER En 1 Once a bit is set in QER then the corresponding QDMA event auto trigger is evaluated by the EDMA3CC logic for an associated transfer request submission to the transfer controllers The setting of an event is a higher priority relative to clear operations via hardware If set and clear conditions occur concurrent...

Page 682: ...clear register QEECR it will disable the corresponding QDMA channel The QDMA event register will not latch any event for a QDMA channel if it is not enabled via QEER The QEER is shown in Figure 17 77 and described in Table 17 59 Figure 17 77 QDMA Event Enable Register QEER 31 16 Reserved R 0 15 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read onl...

Page 683: ... Field Value Description 31 8 Reserved 0 Reserved 7 0 En QDMA event enable clear for channels 0 7 0 No effect 1 QDMA event is disabled Corresponding bit in the QDMA event enable register QEER is cleared En 0 17 4 2 7 4 QDMA Event Enable Set Register QEESR The QDMA event enable register QEER cannot be modified by directly writing to the register in order to ease the software burden when multiple ta...

Page 684: ...e software using QSECR needs to clear the QSER bits for the EDMA3CC to evaluate subsequent QDMA events on the channel Based on whether the associated TR is valid or it is a null or dummy TR the implications on the state of QSER and the required user action in order to submit another QDMA transfer might be different The QSER is shown in Figure 17 80 and described in Table 17 62 Figure 17 80 QDMA Se...

Page 685: ...y event clear register SECR operation which only clears the secondary event register SER bits and does not affect the event registers The QSECR is shown in Figure 17 81 and described in Table 17 63 Figure 17 81 QDMA Secondary Event Clear Register QSECR 31 16 Reserved R 0 15 8 7 6 5 4 3 2 1 0 Reserved E7 E6 E5 E4 E3 E2 E1 E0 R 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 LEGEND R Read only W Write only n valu...

Page 686: ...ection 17 4 3 6 8 260h SADSTBREF Source Active Destination Address B Reference Register Section 17 4 3 6 9 280h DFCNTRLD Destination FIFO Set Count Reload Register Section 17 4 3 6 10 284h DFSRCBREF Destination FIFO Set Source Address B Reference Register Section 17 4 3 6 11 288h DFDSTBREF Destination FIFO Set Destination Address B Reference Register Section 17 4 3 6 12 300h DFOPT0 Destination FIF...

Page 687: ... 3 6 17 3D4h DFMPPRXY3 Destination FIFO Memory Protection Proxy Register 3 Section 17 4 3 6 18 17 4 3 1 Revision Identification Register REVID The revision identification register REVID is a constant register that uniquely identifies the EDMA3TC and specific revision of the EDMA3TC The REVID is shown in Figure 17 82 and described in Table 17 65 Figure 17 82 Revision ID Register REVID 31 0 REV R 40...

Page 688: ...IDTH Rsvd FIFOSIZE R 0 R x R 0 R x R 0 R x LEGEND R Read only n value after reset x value is indeterminate after reset Table 17 66 EDMA3TC Configuration Register TCCFG Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 8 DREGDEPTH 0 3h Destination register FIFO depth parameterization 0 1 entry 1h 2 entry 2h 4 entry for EDMA3TC0 and EDMA3TC1 3h Reserved 7 6 Reserved 0 Reserv...

Page 689: ...ation FIFO contains 1 TR 2h Destination FIFO contains 2 TR 3h Destination FIFO contains 3 TR 4h Destination FIFO contains 4 TR Full if DSTREGDEPTH 4 If the destination register FIFO is empty then any TR written to Prog Set immediately transitions to the destination register FIFO If the destination register FIFO is not empty and not full then any TR written to Prog Set immediately transitions to th...

Page 690: ...ue after reset Table 17 68 Error Status Register ERRSTAT Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 MMRAERR MMR address error 0 MMR address error is not detected 1 User attempted to read or write to an invalid address in configuration memory map 2 TRERR Transfer request TR error event 0 Transfer request TR error is not detected 1 Transfer request TR detected that vio...

Page 691: ...0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 17 69 Error Enable Register ERREN Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 MMRAERR Interrupt enable for MMR address error MMRAERR 0 MMRAERR is disabled 1 MMRAERR is enabled and contributes to the state of EDMA3TC error interrupt generation 2 TRERR Interrupt enable for transfer request error TRERR 0...

Page 692: ...ptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 MMRAERR Interrupt enable clear for the MMR address error MMRAERR bit in the error status register ERRSTAT 0 No effect 1 Clears the MMRAERR bit in the error status register ERRSTAT but does not clear the error details register ERRDET 2 TRERR Interrupt enable clear for the transfer request error TRERR bit in the error status register ERRS...

Page 693: ... 1 Transfer completion interrupt enable Contains the TCINTEN value in the channel options parameter OPT programmed by the channel controller for the read or write transaction that resulted in an error 15 14 Reserved 0 Reserved 13 8 TCC 0 3Fh Transfer complete code Contains the TCC value in the channel options parameter OPT programmed by the channel controller for the read or write transaction that...

Page 694: ...d register ERRCMD is shown in Figure 17 89 and described in Table 17 72 Figure 17 89 Error Interrupt Command Register ERRCMD 31 16 Reserved R 0 15 1 0 Reserved EVAL R 0 W 0 LEGEND R Read only W Write only n value after reset Table 17 72 Error Interrupt Command Register ERRCMD Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 EVAL Error evaluate 0 No effect 1 EDMA3TC error l...

Page 695: ...RATE can be manipulated to slow down the access rate so that the endpoint may service requests from other masters during the inactive EDMA3TC cycles The RDRATE is shown in Figure 17 90 and described in Table 17 73 NOTE It is expected that the RDRATE value for a transfer controller is static as it is decided based on the application requirement It is not recommended to change this setting on the go...

Page 696: ...ration Module You should use the chip level registers and not QUEPRI to configure the TC priority Figure 17 91 Source Active Options Register SAOPT 31 23 22 21 20 19 18 17 16 Reserved TCCHEN Rsvd TCINTEN Reserved TCC R 0 R W 0 R 0 R W 0 R 0 R W 0 15 12 11 10 8 7 6 4 3 2 1 0 TCC Rsvd FWID Rsvd PRI 1 Reserved DAM SAM R W 0 R 0 R W 0 R 0 R W 0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value...

Page 697: ...EGEND R Read only n value after reset Table 17 75 Source Active Source Address Register SASRC Field Descriptions Bit Field Value Description 31 0 SADDR 0 FFFF FFFFh Source address for program register set EDMA3TC updates value according to source addressing mode SAM bit in the source active options register SAOPT 17 4 3 6 3 Source Active Count Register SACNT The source active count register SACNT ...

Page 698: ... Field Descriptions Bit Field Value Description 31 0 DADDR 0 Always reads as 0 17 4 3 6 5 Source Active B Index Register SABIDX The source active B index register SABIDX is shown in Figure 17 95 and described in Table 17 78 Figure 17 95 Source Active B Index Register SABIDX 31 16 DSTBIDX R 0 15 0 SRCBIDX R 0 LEGEND R Read only n value after reset Table 17 78 Source Active B Index Register SABIDX F...

Page 699: ...evel used by the host to set up the parameter entry in the channel controller This field is set up when the associated TR is submitted to the EDMA3TC The privilege ID is used while issuing Read and write command to the target endpoints so that the target endpoints can perform memory protection checks based on the PRIV of the host that set up the DMA transaction 0 User level privilege 1 Supervisor ...

Page 700: ...it Field Value Description 31 16 Reserved 0 Reserved 15 0 ACNTRLD 0 FFFFh A count reload value Represents the originally programmed value of ACNT The reload value is used to reinitialize ACNT after each array is serviced 17 4 3 6 8 Source Active Source Address B Reference Register SASRCBREF The source active source address B reference register SASRCBREF is shown in Figure 17 98 and described in Ta...

Page 701: ...ve Destination Address B Reference Register SADSTBREF Field Descriptions Bit Field Value Description 31 0 DADDRBREF 0 Always reads as 0 17 4 3 6 10 Destination FIFO Set Count Reload Register DFCNTRLD The destination FIFO set count reload register DFCNTRLD is shown in Figure 17 100 and described in Table 17 83 Figure 17 100 Destination FIFO Set Count Reload Register DFCNTRLD 31 16 Reserved R 0 15 0...

Page 702: ...Address B Reference Register DFSRCBREF Field Descriptions Bit Field Value Description 31 0 SADDRBREF 0 Not applicable Always Read as 0 17 4 3 6 12 Destination FIFO Set Destination Address B Reference DFDSTBREF The destination FIFO set destination address B reference register DFDSTBREF is shown in Figure 17 102 and described in Table 17 85 Figure 17 102 Destination FIFO Set Destination Address B Re...

Page 703: ...Reserved 20 TCINTEN Transfer complete interrupt enable 0 Transfer complete interrupt is disabled 1 Transfer complete interrupt is enabled 19 18 Reserved 0 Reserved 17 12 TCC 0 3Fh Transfer complete code This 6 bit code is used to set the relevant bit in CER or IPR of the EDMA3CC 11 Reserved 0 Reserved 10 8 FWID 0 7h FIFO width Applies if either SAM or DAM is set to constant addressing mode 0 FIFO ...

Page 704: ...DR 0 Always Read as 0 17 4 3 6 15 Destination FIFO Count Register n DFCNTn The destination FIFO count register n DFCNTn is shown in Figure 17 105 and described in Table 17 88 Figure 17 105 Destination FIFO Count Register n DFCNTn 31 16 BCNT R 0 15 0 ACNT R 0 LEGEND R Read only n value after reset Table 17 88 Destination FIFO Count Register n DFCNTn Field Descriptions Bit Field Value Description 31...

Page 705: ...ddress for the destination FIFO register set When a transfer request TR is complete the final value should be the address of the last write command issued 17 4 3 6 17 Destination FIFO B Index Register n DFBIDXn The destination FIFO B index register n DFBIDXn is shown in Figure 17 107 and described in Table 17 90 Figure 17 107 Destination FIFO B Index Register n DFBIDXn 31 16 DSTBIDX R 0 15 0 SRCBI...

Page 706: ...rivilege level used by the EDMA programmer to set up the parameter entry in the channel controller This field is set up when the associated TR is submitted to the EDMA3TC The privilege ID is used while issuing Read and write command to the target endpoints so that the target endpoints can perform memory protection checks based on the PRIV of the host that set up the DMA transaction 0 User level pr...

Page 707: ...inuous mode The peripheral may be set up to continuously generate infinite events for instance in case of the McBSP every time the data shifts out from DXR it generates an XEVT The parameter set may be programmed to expect only a finite number of events and to be terminated by a NULL link After the expected number of events the parameter set is reloaded with a NULL parameter set Because the periph...

Page 708: ...egion completion interrupts For example if DRAE0 E0 and DRAE1 E0 are both set then on completion of a transfer that returns a TCC 0 they will generate both shadow region 0 and 1 completion interrupts 4 While programming a non dummy parameter set ensure the CCNT is not left to zero 5 Enable the EDMA3CC error interrupt in the device controller and attach an interrupt service routine ISR to ensure th...

Page 709: ...ly enable the QDMA channel just before the write to the trigger word See Section 17 3 for parameter set field setups for different types of transfers See the sections on chaining Section 17 2 8 and interrupt completion Section 17 2 9 on how to set up final intermediate completion chaining and or interrupts 3 Interrupt setup a If working in the context of a shadow region ensure the relevant bits in...

Page 710: ...Module Chapter 18 SPRUH82C April 2013 Revised September 2016 EMAC MDIO Module This chapter provides a functional description of the Ethernet Media Access Controller EMAC and physical layer PHY device Management Data Input Output MDIO module integrated in the device Topic Page 18 1 Introduction 711 18 2 Architecture 714 18 3 Registers 757 ...

Page 711: ...o physical layer device PHY EMAC acts as DMA master to either internal or external device memory space Eight receive channels with VLAN tag discrimination for receive quality of service QOS support Eight transmit channels with round robin or fixed priority for transmit quality of service QOS support Ether Stats and 802 3 Stats statistics gathering Transmit CRC generation selectable on a per channe...

Page 712: ...uired parameters in the EMAC module for correct operation The module is designed to allow almost transparent operation of the MDIO interface with very little maintenance from the core processor The EMAC module provides an efficient interface between the processor and the network The EMAC on this device supports 10Base T 10 Mbits sec and 100BaseTX 100 Mbits sec half duplex and full duplex mode and ...

Page 713: ... unique 6 byte address that identifies an Ethernet device on the network In an Ethernet packet a MAC address is used twice first to identify the packet s destination and second to identify the packet s sender or source An Ethernet MAC address is normally specified in hexadecimal using dashes to separate bytes For example 08h 00h 28h 32h 17h 42h The first three bytes normally designate the manufact...

Page 714: ... MAC looks for only certain multicast addresses on a network to reduce traffic load The multicast address list of acceptable packets is specified by the application Physical Layer and Media Notation To identify different Ethernet technologies a simple three field type notation is used The Physical Layer type used by the Ethernet is specified by these fields data rate in Mb s medium type maximum se...

Page 715: ...ackets without CPU intervention This EMAC RAM is also referred to as the CPPI buffer descriptor memory because it complies with the Communications Port Programming Interface CPPI v3 0 standard The packet buffer descriptors can also be placed in other on and off chip memories such as L2 and EMIF There are some tradeoffs in terms of cache performance and throughput when descriptors are placed in the...

Page 716: ...when the network is not idle in either transmit or receive The pin is deasserted when both transmit and receive are idle This signal is not necessarily synchronous to MII_TXCLK nor MII_RXCLK In full duplex operation the MII_CRS pin should be held low MII_RXCLK I Receive clock MII_RXCLK The receive clock is a continuous clock that provides the timing reference for receive operations The MII_RXD MII...

Page 717: ...RMII_TXEN is synchronous to RMII_MHZ_50_CLK RMII_MHZ_50_CLK I RMII reference clock RMII_MHZ_50_CLK The reference clock is used to synchronize all RMII signals RMII_MHZ_50_CLK must be continuous and fixed at 50 MHz RMII_RXD 1 0 I Receive data RMII_RXD The receive data pins are a collection of 2 bits of data RMRDX0 is the least significant bit LSB The signals are synchronized by RMII_MHZ_50_CLK and ...

Page 718: ...eld contains the Ethernet MAC address of the EMAC port for which the frame is intended It may be an individual or multicast including broadcast address When the destination EMAC port receives an Ethernet frame with a destination address that does not match any of its MAC physical addresses and no promiscuous multicast or broadcast channel is enabled it discards the frame Source 6 Source address Th...

Page 719: ...rs for the presence of signal energy coming from other ports If the port transmits the entire frame without detecting signal energy from other Ethernet devices the port is done with the frame 4 If the port detects signal energy from other ports while transmitting it stops transmitting its frame and instead transmits a 48 bit jam signal 5 After transmitting the jam signal the port enters an exponen...

Page 720: ...ist 1 Buffer Pointer The buffer pointer refers to the actual memory buffer that contains packet data during transmit operations or is an empty buffer ready to receive packet data during receive operations 2 Buffer Offset The buffer offset is the offset from the start of the packet buffer to the first byte of valid data This field only has meaning when the buffer descriptor points to a buffer that ...

Page 721: ...a descriptor or a linked list of descriptors to an EMAC descriptor queue for the first time the software application simply writes the pointer to the descriptor or first descriptor of a list to the corresponding HDP register Note that the last descriptor in the list must have its next pointer cleared to 0 This is the only way the EMAC has of detecting the end of the list Therefore in the case wher...

Page 722: ...nd receive interrupts are enabled by setting the mask registers RXINTMASKSET and TXINTMASKSET 2 Global interrupts for the appropriate interrupt core registers are set in the EMAC control module CnRXEN and CnTXEN on core n 3 The CPU interrupt controller is configured to accept Cn_RX_PULSE and Cn_TX_PULSE interrupts from the EMAC control module Whether or not the interrupt is enabled the current sta...

Page 723: ...mple 18 1 Transmit Buffer Descriptor in C Structure Format EMAC Descriptor The following is the format of a single buffer descriptor on the EMAC typedef struct _EMAC_Desc struct _EMAC_Desc pNext Pointer to next descriptor in chain Uint8 pBuffer Pointer to data buffer Uint32 BufOffLen Buffer Offset MSW and Length LSW Uint32 PktFlgLen Packet Flags MSW and Length LSW EMAC_Desc Packet Flags define EMA...

Page 724: ...alue of 000Fh indicates that the first 15 bytes of the buffer are to be ignored by the EMAC and that valid buffer data starts on byte 16 of the buffer The software application must set this value prior to adding the descriptor to the active transmit list This field is not altered by the EMAC Note that this value is only checked on the first descriptor of a given packet where the start of packet SO...

Page 725: ... packet the EOP flag is set and there are no more descriptors in the transmit list next descriptor pointer is NULL The software application can use this bit to detect when the EMAC transmitter for the corresponding channel has halted This is useful when the application appends additional packet descriptors to a transmit queue list that is already owned by the EMAC Note that this flag is valid on E...

Page 726: ... is NULL If the pNext pointer is initially NULL and more empty buffers can be added to the pool the software application may alter this pointer to point to a newly appended descriptor The EMAC will use the new pointer value and proceed to the next descriptor unless the pNext value has already been read In this latter case the receiver will halt the receive channel in question and the software appl...

Page 727: ...NTROL 0x00200000u define EMAC_DSC_FLAG_OVERRUN 0x00100000u define EMAC_DSC_FLAG_CODEERROR 0x00080000u define EMAC_DSC_FLAG_ALIGNERROR 0x00040000u define EMAC_DSC_FLAG_CRCERROR 0x00020000u define EMAC_DSC_FLAG_NOMATCH 0x00010000u 18 2 5 5 3 Buffer Offset This 16 bit field must be initialized to zero by the software application before adding the descriptor to a receive queue Whether or not this fiel...

Page 728: ...t has the EOP flag set This flag is initially cleared by the software application before adding the descriptor to the receive queue This bit is set by the EMAC on EOP descriptors 18 2 5 5 8 Ownership OWNER Flag When set this flag indicates that the descriptor is currently owned by the EMAC This flag is set by the software application before adding the descriptor to the receive descriptor queue Thi...

Page 729: ...ersized and was not discarded because the RXCSFEN bit was set in the RXMBPENABLE 18 2 5 5 16 Control Flag This flag is set by the EMAC in the SOP buffer descriptor if the received packet is an EMAC control frame and was not discarded because the RXCMFEN bit was set in the RXMBPENABLE 18 2 5 5 17 Overrun Flag This flag is set by the EMAC in the SOP buffer descriptor if the received packet was abort...

Page 730: ... includes 8K bytes of internal memory CPPI buffer descriptor memory The internal memory block is essential for allowing the EMAC to operate more independently of the CPU It also prevents memory underflow conditions when the EMAC issues read or write requests to descriptor memory Memory accesses to read or write the actual Ethernet packet data are protected by the EMAC s internal FIFOs A descriptor...

Page 731: ... PHY devices connected to the Ethernet Media Access Controller EMAC The device supports a single PHY being connected to the EMAC at any given time The MDIO module is designed to allow almost transparent operation of the MDIO interface with little maintenance from the CPU The MDIO module continuously polls 32 MDIO addresses in order to enumerate all PHY devices in the system Once a PHY device has b...

Page 732: ...resses in order to enumerate the PHY devices in the system The module tracks whether or not a PHY on a particular address has responded and whether or not the PHY currently has a link Using this information allows the software application to quickly determine which MDIO address the PHY is using 18 2 7 1 3 Active PHY Monitoring Once a PHY candidate has been selected for use the MDIO module transpar...

Page 733: ... PHY alive status register ALIVE and MDIO PHY link status register LINK The corresponding bit for the connected PHY 0 31 is set in ALIVE if the PHY responded to the read request The corresponding bit is set in LINK if the PHY responded and also is currently linked In addition any PHY register read transactions initiated by the application software using USERACCESSn causes ALIVE to be updated The U...

Page 734: ...to the PHY and PHY register you want to write 3 The write operation to the PHY is scheduled and completed by the MDIO module Completion of the write operation can be determined by polling the GO bit in USERACCESSn for a 0 4 Completion of the operation sets the corresponding USERINTRAW bit 0 or 1 in the MDIO user command complete interrupt register USERINTRAW corresponding to USERACCESSn used If in...

Page 735: ...SL is shown in Example 18 3 USERACCESS0 is assumed Note that this implementation does not check the ACK bit in USERACCESSn on PHY register reads does not follow the procedure outlined in Section 18 2 7 2 3 Since the MDIO PHY alive status register ALIVE is used to initially select a PHY it is assumed that the PHY is acknowledging read operations It is possible that a PHY could become inactive at a ...

Page 736: ...e RMII The interface between the EMAC module and the system core is provided through the EMAC control module The EMAC consists of the following logical components The receive path includes receive DMA engine receive FIFO and MAC receiver The transmit path includes transmit DMA engine transmit FIFO and MAC transmitter Statistics logic State RAM Interrupt controller Control registers and logic Clock...

Page 737: ...ters registers for both transmit and receive channels 18 2 8 1 9 EMAC Interrupt Controller The interrupt controller contains the interrupt related registers and logic The 26 raw EMAC interrupts are input to this submodule and masked module interrupts are output 18 2 8 1 10 Control Registers and Logic The EMAC is controlled by a set of memory mapped registers The control logic also signals transmit...

Page 738: ...viced to recover their associated memory buffer Thus it is possible to delay servicing of the EMAC interrupt if there are real time tasks to perform Eight channels are supplied for both transmit and receive operations On transmit the eight channels represent eight independent transmit queues The EMAC can be configured to treat these channels as an equal priority round robin queue or as a set of ei...

Page 739: ...lgorithm Receive flow control does not depend on the value of the incoming frame destination address A collision is generated for any incoming packet regardless of the destination address if any EMAC enabled channel s free buffer register value is less than or equal to the channel s flow threshold value 18 2 9 1 3 2 IEEE 802 3x Based Receive Buffer Flow Control IEEE 802 3x based receive buffer flo...

Page 740: ...checking on the outgoing CRC 18 2 9 2 3 Adaptive Performance Optimization APO The EMAC incorporates adaptive performance optimization APO logic that may be enabled by setting the TXPACE bit in the MAC control register MACCONTROL Transmission pacing to enhance performance is enabled when the TXPACE bit is set Adaptive performance pacing introduces delays into the normal transmission of frames delay...

Page 741: ...s or If the new pause time value is 0 then the transmit pause timer immediately expires else The EMAC transmit pause timer immediately is set to the new pause frame pause time value Any remaining pause time from the previous pause frame is discarded If the TXFLOWEN bit in MACCONTROL is cleared then the pause timer immediately expires The EMAC does not start the transmission of a new data frame any...

Page 742: ...The RXCHnEN bits determine whether the given channel is enabled when set to 1 to receive frames with a matching unicast or multicast destination address The RXBROADEN bit in the receive multicast broadcast promiscuous channel enable register RXMBPENABLE determines if broadcast frames are enabled or filtered If broadcast frames are enabled when set to 1 then they are copied to only a single channel...

Page 743: ...multicast broadcast promiscuous channel enable register RXMBPENABLE 18 2 10 5 Host Free Buffer Tracking The host must track free buffers for each enabled channel including unicast multicast broadcast and promiscuous if receive QOS or receive flow control is used Disabled channel free buffer values are do not cares During initialization the host should write the number of free buffers for each enab...

Page 744: ...e first three CRC bytes If the frame length is 1520 there are 1518 bytes transferred to memory regardless of the RXPASSCRC bit value The last two bytes are the first two CRC bytes If the frame length is 1521 there are 1518 bytes transferred to memory regardless of the RXPASSCRC bit value The last byte is the first CRC byte If the frame length is 1522 there are 1518 bytes transferred to memory The ...

Page 745: ...ed 0 1 1 1 0 Proper oversize jabber code align CRC data and control frames transferred to promiscuous channel No undersized frames are transferred 0 1 1 1 1 All nonaddress matching frames with and without errors transferred to promiscuous channel 1 X 0 0 0 Proper data frames transferred to address match channel 1 X 0 0 1 Proper undersized data frames transferred to address match channel 1 X 0 1 0 ...

Page 746: ...ame reception is filtered and the appropriate statistic s are incremented however the RXCEFEN bit in the receive multicast broadcast promiscuous channel enable register RXMBPENABLE affects overrun frame treatment Table 18 6 shows how the overrun condition is handled for the middle of frame overrun Table 18 6 Middle of Frame Overrun Treatment Address Match RXCAFEN RXCEFEN Middle of Frame Overrun Tr...

Page 747: ...e transmit control register TXCONTROL Write the appropriate TXnHDP with the pointer to the first descriptor to start transmit operations 18 2 11 2 Transmit Channel Teardown The host commands a transmit channel teardown by writing the channel number to the transmit teardown register TXTEARDOWN When a teardown command is issued to an enabled transmit channel the following occurs Any frame currently ...

Page 748: ...ny required buffer descriptor reads for the cell data Latency to system s internal and external RAM can be controlled through the use of the transfer node priority allocation register available at the device level Latency to descriptor RAM is low because RAM is local to the EMAC as it is part of the EMAC control module 18 2 13 Transfer Node Priority The device contains a chip level master priority...

Page 749: ... values Software reset occurs when the receive and transmit DMA controllers are in an idle state to avoid locking up the configuration bus it is the responsibility of the software to verify that there are no pending frames to be transferred After writing a 1 to the SOFTRESET bit it may be polled to determine if the reset has occurred If a 1 is read the reset has not yet occurred if a 0 is read the...

Page 750: ...ule interrupt control registers CnRXTHRESHEN CnRXEN CnTXEN and CnMISCEN The process of mapping the EMAC interrupts to the CPU is done through the CPU interrupt controller Once the interrupt is mapped to a CPU interrupt general masking and unmasking of interrupts to control reentrancy should be done at the chip level by manipulating the interrupt core enable mask registers 18 2 15 3 MDIO Module Ini...

Page 751: ...he receive channel n free buffer count registers RXnFREEBUFFER receive channel n flow control threshold register RXnFLOWTHRESH and receive filter low priority frame threshold register RXFILTERLOWTHRESH 7 Most device drivers open with no multicast addresses so clear the MAC address hash registers MACHASH1 and MACHASH2 to 0 8 Write the receive buffer offset register RXBUFFEROFFSET value typically ze...

Page 752: ...ed to the queue s associated transmit completion pointer in the transmit DMA state RAM The data written by the host buffer descriptor address of the last processed buffer is compared to the data in the register written by the EMAC port address of last buffer descriptor used by the EMAC If the two values are not equal which means that the EMAC has transmitted more packets than the CPU has processed...

Page 753: ...r the host may acknowledge interrupts for every packet The application software must acknowledge the EMAC control module after processing packets by writing the appropriate CnTX key to the EMAC End Of Interrupt Vector register MACEOIVECTOR See Section 18 3 3 12 for the acknowledge key values 18 2 16 1 3 Statistics Interrupt The statistics level interrupt STATPEND is issued when any statistics valu...

Page 754: ...fer count and threshold logic as does flow control but the interrupts are independently enabled from flow control The threshold interrupts are intended to give the host an indication that resources are running low for a particular channel s The applications software must acknowledge the EMAC control module after receiving threshold interrupts by writing the appropriate CnRXTHRESH key to the EMAC E...

Page 755: ...c contained in the EMAC control module Section 18 2 6 3 discusses the interrupt control contained in the EMAC control module For safe interrupt processing upon entry to the ISR the software application should disable interrupts using the EMAC control module registers CnRXTHRESHEN CnRXEN CnTXEN CnMISCEN and then reenable them upon leaving the ISR If any interrupt signals are active at that time thi...

Page 756: ... turned on reset to the peripheral is asserted and clocks to the peripheral are gated after that The registers are reset to their default value When powering up after a synchronized reset all the EMAC submodules need to be reinitialized before any data transmission can happen For more information on the use of the PSC see the Power and Sleep Controller PSC chapter 18 2 18 Emulation Considerations ...

Page 757: ...nable Register Section 18 3 1 6 2Ch C1MISCEN EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Enable Register Section 18 3 1 7 30h C2RXTHRESHEN EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable Register Section 18 3 1 4 34h C2RXEN EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register Section 18 3 1 5 38h C2TXEN EMAC Control Module Interrupt Core 2...

Page 758: ...trol Module Interrupt Core 1 Receive Interrupts Per Millisecond Register Section 18 3 1 12 7Ch C1TXIMAX EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond Register Section 18 3 1 13 80h C2RXIMAX EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond Register Section 18 3 1 12 84h C2TXIMAX EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecon...

Page 759: ...described in Table 18 10 Figure 18 13 EMAC Control Module Software Reset Register SOFTRESET 31 16 Reserved R 0 15 1 0 Reserved RESET R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 18 10 EMAC Control Module Software Reset Register SOFTRESET Bit Field Value Description 31 1 Reserved 0 Reserved 0 RESET Software reset bit for the EMAC Control Module Clears the interrupt status c...

Page 760: ...ion on Interrupt Core 2 0 Pacing for TX interrupts on Core 2 disabled 1 Pacing for TX interrupts on Core 2 enabled 20 C2RXPACEEN Enable pacing for RX interrupt pulse generation on Interrupt Core 2 0 Pacing for RX interrupts on Core 2 disabled 1 Pacing for RX interrupts on Core 2 enabled 19 C1TXPACEEN Enable pacing for TX interrupt pulse generation on Interrupt Core 1 0 Pacing for TX interrupts on ...

Page 761: ...r RX Channel 7 6 RXCH6THRESHEN Enable CnRXTHRESHPULSE interrupt generation for RX Channel 6 0 CnRXTHRESHPULSE generation is disabled for RX Channel 6 1 CnRXTHRESHPULSE generation is enabled for RX Channel 6 5 RXCH5THRESHEN Enable CnRXTHRESHPULSE interrupt generation for RX Channel 5 0 CnRXTHRESHPULSE generation is disabled for RX Channel 5 1 CnRXTHRESHPULSE generation is enabled for RX Channel 5 4...

Page 762: ...nabled for RX Channel 7 6 RXCH6EN Enable CnRXPULSE interrupt generation for RX Channel 6 0 CnRXPULSE generation is disabled for RX Channel 6 1 CnRXPULSE generation is enabled for RX Channel 6 5 RXCH5EN Enable CnRXPULSE interrupt generation for RX Channel 5 0 CnRXPULSE generation is disabled for RX Channel 5 1 CnRXPULSE generation is enabled for RX Channel 5 4 RXCH4EN Enable CnRXPULSE interrupt gen...

Page 763: ... enabled for TX Channel 7 6 TXCH6EN Enable CnTXPULSE interrupt generation for TX Channel 6 0 CnTXPULSE generation is disabled for TX Channel 6 1 CnTXPULSE generation is enabled for TX Channel 6 5 TXCH5EN Enable CnTXPULSE interrupt generation for TX Channel 5 0 CnTXPULSE generation is disabled for TX Channel 5 1 CnTXPULSE generation is enabled for TX Channel 5 4 TXCH4EN Enable CnTXPULSE interrupt g...

Page 764: ...ld Value Description 31 4 Reserved 0 Reserved 3 STATPENDEN Enable CnMISCPULSE interrupt generation when EMAC statistics interrupts are generated 0 CnMISCPULSE generation is disabled for EMAC STATPEND interrupts 1 CnMISCPULSE generation is enabled for EMAC STATPEND interrupts 2 HOSTPENDEN Enable CnMISCPULSE interrupt generation when EMAC host interrupts are generated 0 CnMISCPULSE generation is dis...

Page 765: ...ESHPULSE interrupt 1 RX Channel 6 satisfies conditions to generate a CnRXTHRESHPULSE interrupt 5 RXCH5THRESHSTAT Interrupt status for RX Channel 5 masked by the CnRXTHRESHEN register 0 RX Channel 5 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt 1 RX Channel 5 satisfies conditions to generate a CnRXTHRESHPULSE interrupt 4 RXCH4THRESHSTAT Interrupt status for RX Channel 4 masked...

Page 766: ...interrupt 1 RX Channel 6 satisfies conditions to generate a CnRXPULSE interrupt 5 RXCH5STAT Interrupt status for RX Channel 5 masked by the CnRXEN register 0 RX Channel 5 does not satisfy conditions to generate a CnRXPULSE interrupt 1 RX Channel 5 satisfies conditions to generate a CnRXPULSE interrupt 4 RXCH4STAT Interrupt status for RX Channel 4 masked by the CnRXEN register 0 RX Channel 4 does n...

Page 767: ...E interrupt 1 TX Channel 6 satisfies conditions to generate a CnTXPULSE interrupt 5 TXCH5STAT Interrupt status for TX Channel 5 masked by the CnTXEN register 0 TX Channel 5 does not satisfy conditions to generate a CnTXPULSE interrupt 1 TX Channel 5 satisfies conditions to generate a CnTXPULSE interrupt 4 TXCH4STAT Interrupt status for TX Channel 4 masked by the CnTXEN register 0 TX Channel 4 does...

Page 768: ...eld Value Description 31 4 Reserved 0 Reserved 3 STATPENDSTAT Interrupt status for EMAC STATPEND masked by the CnMISCEN register 0 EMAC STATPEND does not satisfy conditions to generate a CnMISCPULSE interrupt 1 EMAC STATPEND satisfies conditions to generate a CnMISCPULSE interrupt 2 HOSTPENDSTAT Interrupt status for EMAC HOSTPEND masked by the CnMISCEN register 0 EMAC HOSTPEND does not satisfy con...

Page 769: ...llisecond Register CnRXIMAX Bit Field Value Description 31 6 Reserved 0 Reserved 5 0 RXIMAX 2 3Fh RXIMAX is the desired number of CnRXPULSE interrupts generated per millisecond when CnRXPACEEN is enabled in INTCONTROL The pacing mechanism can be described by the following pseudo code while 1 interrupt_count 0 Count interrupts over a 1ms window for i 0 i INTCONTROL INTPRESCALE 250 i interrupt_count...

Page 770: ...Millisecond Register CnTXIMAX Bit Field Value Description 31 6 Reserved 0 Reserved 5 0 TXIMAX 2 3Fh TXIMAX is the desired number of CnTXPULSE interrupts generated per millisecond when CnTXPACEEN is enabled in INTCONTROL The pacing mechanism can be described by the following pseudo code while 1 interrupt_count 0 Count interrupts over a 1ms window for i 0 i INTCONTROL INTPRESCALE 250 i interrupt_cou...

Page 771: ...MDIO User Command Complete Interrupt Unmasked Register Section 18 3 2 7 24h USERINTMASKED MDIO User Command Complete Interrupt Masked Register Section 18 3 2 8 28h USERINTMASKSET MDIO User Command Complete Interrupt Mask Set Register Section 18 3 2 9 2Ch USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register Section 18 3 2 10 80h USERACCESS0 MDIO User Access Register 0 Section 1...

Page 772: ...bles the MDIO state machine 1 Enable the MDIO state machine 29 Reserved 0 Reserved 28 24 HIGHEST_USER_CHANNEL 0 1Fh Highest user channel that is available in the module It is currently set to 1 This implies that MDIOUserAccess1 is the highest available user access channel 23 21 Reserved 0 Reserved 20 PREAMBLE Preamble disable 0 Standard MDIO preamble is used 1 Disables this device from sending MDI...

Page 773: ...n indication of the presence or not of a PHY with the corresponding address Writing a 1 to any bit will clear it writing a 0 has no effect 0 The PHY fails to acknowledge the access 1 The most recent access to the PHY with an address corresponding to the register bit number was acknowledged by the PHY 18 3 2 4 PHY Link Status Register LINK The PHY link status register LINK is shown in Figure 18 28 ...

Page 774: ...ions Bit Field Value Description 31 2 Reserved 0 Reserved 1 USERPHY1 MDIO Link change event raw value When asserted the bit indicates that there was an MDIO link change event that is change in the LINK register corresponding to the PHY address in USERPHYSEL1 Writing a 1 will clear the event writing a 0 has no effect 0 No MDIO link change event 1 An MDIO link change event change in the LINK registe...

Page 775: ...ed value When asserted the bit indicates that there was an MDIO link change event that is change in the LINK register corresponding to the PHY address in USERPHYSEL1 and the corresponding LINKINTENB bit was set Writing a 1 will clear the event writing a 0 has no effect 0 No MDIO link change event 1 An MDIO link change event change in the LINK register corresponding to the PHY address in MDIO user ...

Page 776: ...sked Register USERINTRAW Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 USERACCESS1 MDIO User command complete event bit When asserted the bit indicates that the previously scheduled PHY read or write command using the USERACCESS1 register has completed Writing a 1 will clear the event writing a 0 has no effect 0 No MDIO user command complete event 1 The previously sched...

Page 777: ...0 Reserved 1 USERACCESS1 Masked value of MDIO User command complete interrupt When asserted The bit indicates that the previously scheduled PHY read or write command using that particular USERACCESS1 register has completed Writing a 1 will clear the interrupt writing a 0 has no effect 0 No MDIO user command complete event 1 The previously scheduled PHY read or write command using MDIO user access ...

Page 778: ...1 2 Reserved 0 Reserved 1 USERACCESS1 MDIO user interrupt mask set for USERINTMASKED 1 Setting a bit to 1 will enable MDIO user command complete interrupts for the USERACCESS1 register MDIO user interrupt for USERACCESS1 is disabled if the corresponding bit is 0 Writing a 0 to this bit has no effect 0 MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is disabled 1...

Page 779: ...r Register USERINTMASKCLEAR Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 USERACCESS1 MDIO user command complete interrupt mask clear for USERINTMASKED 1 Setting the bit to 1 will disable further user command complete interrupts for USERACCESS1 Writing a 0 to this bit has no effect 0 MDIO user command complete interrupts for the MDIO user access register USERACCESS1 is ...

Page 780: ...cess when it is convenient for it to do so this is not an instantaneous process Writing a 0 to this bit has no effect This bit is writeable only if the MDIO state machine is enabled This bit will self clear when the requested access has been completed Any writes to USERACCESS0 are blocked when the GO bit is 1 30 WRITE Write enable bit Setting this bit to 1 causes the MDIO transaction to be a regis...

Page 781: ...Register 0 USERPHYSEL0 Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 LINKSEL Link status determination select bit Default value is 0 which implies that the link status is determined by the MDIO state machine This is the only option supported on this device 0 The link status is determined by the MDIO state machine 1 Not supported 6 LINKINTENB Link change interrupt enable...

Page 782: ...cess when it is convenient for it to do so this is not an instantaneous process Writing 0 to this bit has no effect This bit is writeable only if the MDIO state machine is enabled This bit will self clear when the requested access has been completed Any writes to USERACCESS0 are blocked when the GO bit is 1 30 WRITE Write enable bit Setting this bit to 1 causes the MDIO transaction to be a registe...

Page 783: ... Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 LINKSEL Link status determination select bit Default value is 0 which implies that the link status is determined by the MDIO state machine This is the only option supported on this device 0 The link status is determined by the MDIO state machine 1 Not supported 6 LINKINTENB Link change interrupt enable Set to 1 to enable li...

Page 784: ...ACINTMASKCLEAR MAC Interrupt Mask Clear Register Section 18 3 3 20 100h RXMBPENABLE Receive Multicast Broadcast Promiscuous Channel Enable Register Section 18 3 3 21 104h RXUNICASTSET Receive Unicast Enable Set Register Section 18 3 3 22 108h RXUNICASTCLEAR Receive Unicast Clear Register Section 18 3 3 23 10Ch RXMAXLEN Receive Maximum Length Register Section 18 3 3 24 110h RXBUFFEROFFSET Receive B...

Page 785: ...it Channel 5 DMA Head Descriptor Pointer Register Section 18 3 3 46 618h TX6HDP Transmit Channel 6 DMA Head Descriptor Pointer Register Section 18 3 3 46 61Ch TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register Section 18 3 3 46 620h RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register Section 18 3 3 47 624h RX1HDP Receive Channel 1 DMA Head Descriptor Pointer Register Section ...

Page 786: ...3 3 50 15 23Ch TXMCASTFRAMES Multicast Transmit Frames Register Section 18 3 3 50 16 240h TXPAUSEFRAMES Pause Transmit Frames Register Section 18 3 3 50 17 244h TXDEFERRED Deferred Transmit Frames Register Section 18 3 3 50 18 248h TXCOLLISION Transmit Collision Frames Register Section 18 3 3 50 19 24Ch TXSINGLECOLL Transmit Single Collision Frames Register Section 18 3 3 50 20 250h TXMULTICOLL Tr...

Page 787: ...nsmit Revision ID Register TXREVID Field Descriptions Bit Field Value Description 31 0 TXREV Transmit module revision 4EC0 020Dh Current transmit revision value 18 3 3 2 Transmit Control Register TXCONTROL The transmit control register TXCONTROL is shown in Figure 18 40 and described in Table 18 39 Figure 18 40 Transmit Control Register TXCONTROL 31 16 Reserved R 0 15 1 0 Reserved TXEN R 0 R W 0 L...

Page 788: ...0 LEGEND R W Read Write R Read only n value after reset Table 18 40 Transmit Teardown Register TXTEARDOWN Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 0 TXTDNCH 0 7h Transmit teardown channel The transmit channel teardown is commanded by writing the encoded value of the transmit channel to be torn down The teardown register is read as 0 0 Teardown transmit channel 0 1h...

Page 789: ...Receive Revision ID Register RXREVID Field Descriptions Bit Field Value Description 31 0 RXREV Receive module revision 4EC0 020Dh Current receive revision value 18 3 3 5 Receive Control Register RXCONTROL The receive control register RXCONTROL is shown in Figure 18 43 and described in Table 18 42 Figure 18 43 Receive Control Register RXCONTROL 31 16 Reserved R 0 15 1 0 Reserved RXEN R 0 R W 0 LEGE...

Page 790: ... R W 0 LEGEND R W Read Write R Read only n value after reset Table 18 43 Receive Teardown Register RXTEARDOWN Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 0 RXTDNCH 0 7h Receive teardown channel The receive channel teardown is commanded by writing the encoded value of the receive channel to be torn down The teardown register is read as 0 0 Teardown receive channel 0 1h...

Page 791: ...D TX5PEND TX4PEND TX3PEND TX2PEND TX1PEND TX0PEND R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 18 44 Transmit Interrupt Status Unmasked Register TXINTSTATRAW Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7PEND 0 1 TX7PEND raw interrupt read before mask 6 TX6PEND 0 1 TX6PEND raw interrupt read before mask 5 TX5PEND 0 1 TX5PEND raw interr...

Page 792: ...ed R 0 7 6 5 4 3 2 1 0 TX7PEND TX6PEND TX5PEND TX4PEND TX3PEND TX2PEND TX1PEND TX0PEND R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 18 45 Transmit Interrupt Status Masked Register TXINTSTATMASKED Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7PEND 0 1 TX7PEND masked interrupt read 6 TX6PEND 0 1 TX6PEND masked interrupt read 5 TX5PEND 0 ...

Page 793: ...riptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7MASK 0 1 Transmit channel 7 interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 6 TX6MASK 0 1 Transmit channel 6 interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 5 TX5MASK 0 1 Transmit channel 5 interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 4 TX4...

Page 794: ...ptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 TX7MASK 0 1 Transmit channel 7 interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effect 6 TX6MASK 0 1 Transmit channel 6 interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effect 5 TX5MASK 0 1 Transmit channel 5 interrupt mask clear bit Write 1 to disable interrupt a write of 0 has no effec...

Page 795: ... only n value after reset Table 18 48 MAC Input Vector Register MACINVECTOR Field Descriptions Bit Field Value Description 31 28 Reserved 0 Reserved 27 STATPEND 0 1 EMAC module statistics interrupt STATPEND pending status bit 26 HOSTPEND 0 1 EMAC module host error interrupt HOSTPEND pending status bit 25 LINKINT0 0 1 MDIO module USERPHYSEL0 LINKINT0 status bit 24 USERINT0 0 1 MDIO module USERACCES...

Page 796: ...MAC End Of Interrupt Vector Register MACEOIVECTOR Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 0 INTVECT 0 1Fh Acknowledge EMAC Control Module Interrupts 0h Acknowledge C0RXTHRESH Interrupt 1h Acknowledge C0RX Interrupt 2h Acknowledge C0TX Interrupt 3h Acknowledge C0MISC Interrupt STATPEND HOSTPEND MDIO LINKINT0 MDIO USERINT0 4h Acknowledge C1RXTHRESH Interrupt 5h Ackn...

Page 797: ...ield Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 RX7THRESHPEND 0 1 RX7THRESHPEND raw interrupt read before mask 14 RX6THRESHPEND 0 1 RX6THRESHPEND raw interrupt read before mask 13 RX5THRESHPEND 0 1 RX5THRESHPEND raw interrupt read before mask 12 RX4THRESHPEND 0 1 RX4THRESHPEND raw interrupt read before mask 11 RX3THRESHPEND 0 1 RX3THRESHPEND raw interrupt read before mas...

Page 798: ...set Table 18 51 Receive Interrupt Status Masked Register RXINTSTATMASKED Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 RX7THRESHPEND 0 1 RX7THRESHPEND masked interrupt read 14 RX6THRESHPEND 0 1 RX6THRESHPEND masked interrupt read 13 RX5THRESHPEND 0 1 RX5THRESHPEND masked interrupt read 12 RX4THRESHPEND 0 1 RX4THRESHPEND masked interrupt read 11 RX3THRESHPEND 0 1 RX3TH...

Page 799: ... threshold mask set bit Write 1 to enable interrupt a write of 0 has no effect 12 RX4THRESHMASK 0 1 Receive channel 4 threshold mask set bit Write 1 to enable interrupt a write of 0 has no effect 11 RX3THRESHMASK 0 1 Receive channel 3 threshold mask set bit Write 1 to enable interrupt a write of 0 has no effect 10 RX2THRESHMASK 0 1 Receive channel 2 threshold mask set bit Write 1 to enable interru...

Page 800: ...d mask clear bit Write 1 to disable interrupt a write of 0 has no effect 12 RX4THRESHMASK 0 1 Receive channel 4 threshold mask clear bit Write 1 to disable interrupt a write of 0 has no effect 11 RX3THRESHMASK 0 1 Receive channel 3 threshold mask clear bit Write 1 to disable interrupt a write of 0 has no effect 10 RX2THRESHMASK 0 1 Receive channel 2 threshold mask clear bit Write 1 to disable inte...

Page 801: ...ion 31 2 Reserved 0 Reserved 1 HOSTPEND 0 1 Host pending interrupt HOSTPEND raw interrupt read before mask 0 STATPEND 0 1 Statistics pending interrupt STATPEND raw interrupt read before mask 18 3 3 18 MAC Interrupt Status Masked Register MACINTSTATMASKED The MAC interrupt status masked register MACINTSTATMASKED is shown in Figure 18 56 and described in Table 18 55 Figure 18 56 MAC Interrupt Status...

Page 802: ...mask set bit Write 1 to enable interrupt a write of 0 has no effect 0 STATMASK 0 1 Statistics interrupt mask set bit Write 1 to enable interrupt a write of 0 has no effect 18 3 3 20 MAC Interrupt Mask Clear Register MACINTMASKCLEAR The MAC interrupt mask clear register MACINTMASKCLEAR is shown in Figure 18 58 and described in Table 18 57 Figure 18 58 MAC Interrupt Mask Clear Register MACINTMASKCLE...

Page 803: ... the buffer descriptor packet length 29 RXQOSEN Receive quality of service enable bit 0 Receive QOS is disabled 1 Receive QOS is enabled 28 RXNOCHAIN Receive no buffer chaining bit 0 Received frames can span multiple buffers 1 The Receive DMA controller transfers each frame into a single buffer regardless of the frame or buffer size All remaining frame data after the first buffer is discarded The ...

Page 804: ...es 1h Select channel 1 to receive promiscuous frames 2h Select channel 2 to receive promiscuous frames 3h Select channel 3 to receive promiscuous frames 4h Select channel 4 to receive promiscuous frames 5h Select channel 5 to receive promiscuous frames 6h Select channel 6 to receive promiscuous frames 7h Select channel 7 to receive promiscuous frames 15 14 Reserved 0 Reserved 13 RXBROADEN Receive ...

Page 805: ...s continued Bit Field Value Description 2 0 RXMULTCH 0 7h Receive multicast channel select 0 Select channel 0 to receive multicast frames 1h Select channel 1 to receive multicast frames 2h Select channel 2 to receive multicast frames 3h Select channel 3 to receive multicast frames 4h Select channel 4 to receive multicast frames 5h Select channel 5 to receive multicast frames 6h Select channel 6 to...

Page 806: ...31 8 Reserved 0 Reserved 7 RXCH7EN 0 1 Receive channel 7 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 6 RXCH6EN 0 1 Receive channel 6 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 5 RXCH5EN 0 1 Receive channel 5 unicast enable set bit Write 1 to set the enable a write of 0 has no effect May be read 4 RXCH4EN 0 1 R...

Page 807: ...it Field Value Description 31 8 Reserved 0 Reserved 7 RXCH7EN 0 1 Receive channel 7 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 6 RXCH6EN 0 1 Receive channel 6 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 5 RXCH5EN 0 1 Receive channel 5 unicast enable clear bit Write 1 to clear the enable a write of 0 has no effect 4 RXCH4EN 0 ...

Page 808: ...frames with CRC code or alignment error are jabber frames 18 3 3 25 Receive Buffer Offset Register RXBUFFEROFFSET The receive buffer offset register RXBUFFEROFFSET is shown in Figure 18 63 and described in Table 18 62 Figure 18 63 Receive Buffer Offset Register RXBUFFEROFFSET 31 16 Reserved R 0 15 0 RXBUFFEROFFSET R W 0 LEGEND R W Read Write R Read only n value after reset Table 18 62 Receive Buff...

Page 809: ...Reserved 7 0 RXFILTERTHRESH 0 FFh Receive filter low threshold These bits contain the free buffer count threshold value for filtering low priority incoming frames This field should remain 0 if no filtering is desired 18 3 3 27 Receive Channel Flow Control Threshold Registers RX0FLOWTHRESH RX7FLOWTHRESH The receive channel 0 7 flow control threshold register RXnFLOWTHRESH is shown in Figure 18 65 a...

Page 810: ...ield Value Description 31 16 Reserved 0 Reserved 15 0 RXnFREEBUF 0 FFh Receive free buffer count These bits contain the count of free buffers available The RXFILTERTHRESH value is compared with this field to determine if low priority frames should be filtered The RXnFLOWTHRESH value is compared with this field to determine if receive flow control should be issued against incoming packets if enable...

Page 811: ...th word 1 Block all EMAC DMA controller writes to the receive buffer descriptor offset buffer length words during packet processing When this bit is set the EMAC will never write the third word to any receive buffer descriptor 13 RXOWNERSHIP Receive ownership write bit value 0 The EMAC writes the Receive ownership bit to 0 at the end of packet processing 1 The EMAC writes the Receive ownership bit...

Page 812: ...rdless of this bit setting The RXMBPENABLE bits determine whether or not received pause frames are transferred to memory 0 Transmit flow control is disabled Full duplex mode incoming pause frames are not acted upon 1 Transmit flow control is enabled Full duplex mode incoming pause frames are acted upon 3 RXBUFFERFLOWEN Receive buffer flow control enable bit 0 Receive flow control is disabled Half ...

Page 813: ... DMA related host errors The host should read this field after a host error interrupt HOSTPEND to determine the error Host error interrupts require hardware reset in order to recover A 0 packet length is an error but it is not detected 0 No error 1h SOP error the buffer is the first buffer in a packet but the SOP bit is not set in software 2h Ownership bit not set in SOP buffer 3h Zero next buffer...

Page 814: ...ed on receive channel 3 4h The host error occurred on receive channel 4 5h The host error occurred on receive channel 5 6h The host error occurred on receive channel 6 7h The host error occurred on receive channel 7 7 3 Reserved 0 Reserved 2 RXQOSACT Receive Quality of Service QOS active bit When asserted indicates that receive quality of service is enabled and that at least one channel freebuffer...

Page 815: ...d in conjunction with SOFT bit to determine the emulation suspend mode 0 Free running mode is disabled During emulation halt SOFT bit determines operation of EMAC 1 Free running mode is enabled During emulation halt EMAC continues to operate 18 3 3 32 FIFO Control Register FIFOCONTROL The FIFO control register FIFOCONTROL is shown in Figure 18 70 and described in Table 18 69 Figure 18 70 FIFO Cont...

Page 816: ... of cells in the receive FIFO 15 8 ADDRESSTYPE 2h Address type 7 0 MACCFIG 2h MAC configuration value 18 3 3 34 Soft Reset Register SOFTRESET The soft reset register SOFTRESET is shown in Figure 18 72 and described in Table 18 71 Figure 18 72 Soft Reset Register SOFTRESET 31 16 Reserved R 0 15 1 0 Reserved SOFTRESET R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 18 71 Soft R...

Page 817: ...5 8 MACSRCADDR0 0 FFh MAC source address lower 8 0 bits byte 0 7 0 MACSRCADDR1 0 FFh MAC source address bits 15 8 byte 1 18 3 3 36 MAC Source Address High Bytes Register MACSRCADDRHI The MAC source address high bytes register MACSRCADDRHI is shown in Figure 18 74 and described in Table 18 73 Figure 18 74 MAC Source Address High Bytes Register MACSRCADDRHI 31 24 23 16 MACSRCADDR2 MACSRCADDR3 R W 0 ...

Page 818: ...t into a 64 bit hash table stored in MACHASH1 and MACHASH2 that indicates whether a particular address should be accepted or not The MAC hash address register 1 MACHASH1 is shown in Figure 18 75 and described in Table 18 74 Figure 18 75 MAC Hash Address Register 1 MACHASH1 31 0 MACHASH1 R W 0 LEGEND R W Read Write n value after reset Table 18 74 MAC Hash Address Register 1 MACHASH1 Field Descripti...

Page 819: ...unter to be observed for test purposes This field is loaded automatically according to the backoff algorithm and is decremented by one for each slot time after the collision 18 3 3 40 Transmit Pacing Algorithm Test Register TPACETEST The transmit pacing algorithm test register TPACETEST is shown in Figure 18 78 and described in Table 18 77 Figure 18 78 Transmit Pacing Algorithm Test Register TPACE...

Page 820: ...sends an outgoing pause frame with pause time of FFFFh The receive pause timer is decremented at slot time intervals If the receive pause timer decrements to 0 then another outgoing pause frame is sent and the load decrement process is repeated 18 3 3 42 Transmit Pause Timer Register TXPAUSE The transmit pause timer register TXPAUSE is shown in Figure 18 80 and described in Table 18 79 Figure 18 8...

Page 821: ...ytes Register MACADDRLO Field Descriptions Bit Field Value Description 31 21 Reserved 0 Reserved 20 VALID Address valid bit This bit should be cleared to zero for unused address channels 0 Address is not valid and will not be used for matching or filtering incoming packets 1 Address is valid and will be used for matching or filtering incoming packets 19 MATCHFILT Match or filter bit 0 The address ...

Page 822: ...40 byte 5 Bit 40 is the group bit It is forced to 0 and read as 0 Therefore only unicast addresses are represented in the address table 18 3 3 45 MAC Index Register MACINDEX The MAC index register MACINDEX is shown in Figure 18 83 and described in Table 18 82 Figure 18 83 MAC Index Register MACINDEX 31 16 Reserved R 0 15 3 2 0 Reserved MACINDEX R 0 R W 0 LEGEND R W Read Write R Read only n value a...

Page 823: ...perations in the queue for the selected channel Writing to these locations when they are nonzero is an error except at reset Host software must initialize these locations to 0 on reset 18 3 3 47 Receive Channel DMA Head Descriptor Pointer Registers RX0HDP RX7HDP The receive channel 0 7 DMA head descriptor pointer register RXnHDP is shown in Figure 18 85 and described in Table 18 84 Figure 18 85 Re...

Page 824: ...ith the buffer descriptor address for the last buffer processed by the host during interrupt processing The EMAC uses the value written to determine if the interrupt should be deasserted 18 3 3 49 Receive Channel Completion Pointer Registers RX0CP RX7CP The receive channel 0 7 completion pointer register RXnCP is shown in Figure 18 87 and described in Table 18 86 Figure 18 87 Receive Channel n Com...

Page 825: ...GEND R W Read Write WD Write to decrement n value after reset 18 3 3 50 1 Good Receive Frames Register RXGOODFRAMES The total number of good frames received on the EMAC A good frame is defined as having all of the following Any data or MAC control frame that matched a unicast broadcast or multicast address or matched due to promiscuous mode Was of length 64 to RXMAXLEN bytes inclusive Had no CRC e...

Page 826: ...d due to promiscuous mode Was of length 64 to RXMAXLEN bytes inclusive Had no alignment or code error Had a CRC error A CRC error is defined as having all of the following A frame containing an even number of nibbles Fails the frame check sequence test See Section 18 2 5 5 for definitions of alignment code and CRC errors Overruns have no effect on this statistic 18 3 3 50 6 Receive Alignment Code ...

Page 827: ...ived on the EMAC An undersized frame is defined as having all of the following Was any data frame that matched a unicast broadcast or multicast address or matched due to promiscuous mode Was less than 64 bytes long Had no CRC error alignment error or code error See Section 18 2 5 5 for definitions of alignment code and CRC errors Overruns have no effect on this statistic 18 3 3 50 10 Receive Frame...

Page 828: ...frame destination channel flow control threshold register RXnFLOWTHRESH value was greater than or equal to the channel s corresponding free buffer register RXnFREEBUFFER value Was of length 64 to RXMAXLEN RXQOSEN bit is set in RXMBPENABLE Had no CRC error alignment error or code error See Section 18 2 5 5 for definitions of alignment code and CRC errors Overruns have no effect on this statistic 18...

Page 829: ... frames are only transmitted in full duplex mode carrier loss and collisions have no effect on this statistic Transmitted pause frames are always 64 byte multicast frames so appear in the multicast transmit frames register and 64 octect frames register statistics 18 3 3 50 18 Deferred Transmit Frames Register TXDEFERRED The total number of frames transmitted on the EMAC that first experienced defe...

Page 830: ...r of frames when transmission was abandoned due to excessive collisions Such a frame is defined as having all of the following Was any data or MAC control frame destined for any unicast broadcast or multicast address Was any size Had no carrier loss and no underrun Experienced 16 collisions before abandoning all attempts at transmitting the frame None of the collisions were late CRC errors have no...

Page 831: ...ss Did not experience late collisions excessive collisions underrun or carrier sense error Was exactly 64 bytes long If the frame was being transmitted and experienced carrier loss that resulted in a frame of this size being transmitted then the frame is recorded in this statistic CRC errors alignment code errors and overruns do not affect the recording of frames in this statistic 18 3 3 50 28 Tra...

Page 832: ...4 to RXMAXLEN Octet Frames Register FRAME1024TUP The total number of 1024 byte to RXMAXLEN byte frames received and transmitted on the EMAC Such a frame is defined as having all of the following Any data or MAC control frame that was destined for any unicast broadcast or multicast address Did not experience late collisions excessive collisions underrun or carrier sense error Was 1024 bytes to RXMA...

Page 833: ...verrun frame is defined as having all of the following Was any data or MAC control frame that matched a unicast broadcast or multicast address or matched due to promiscuous mode Was of any size including less than 64 byte and greater than RXMAXLEN byte frames The EMAC was unable to receive it because it did not have the resources to receive it cell FIFO full or no DMA buffer available after the fr...

Page 834: ... April 2013 Revised September 2016 External Memory Interface A EMIFA This chapter describes the external memory interface A EMIFA The EMIFA SDRAM interface is not supported on all devices see your device specific data manual to see if the EMIFA SDRAM is supported on your device Topic Page 19 1 Introduction 835 19 2 Architecture 835 19 3 Example Configuration 876 19 4 Registers 898 ...

Page 835: ...9 3 contains an example of operating the EMIFA in this configuration 19 1 2 Features The EMIFA includes many features to enhance the ease and flexibility of connecting to external SDR SDRAM and asynchronous devices For details on features of EMIFA see your device specific data manual 19 1 3 Functional Block Diagram Figure 19 1 illustrates the connections between the EMIFA and its internal requeste...

Page 836: ...ription EMA_D x 0 I O EMIFA data bus The number of available data bus pins varies among devices see your device specific data manual for details EMA_ A x 0 O EMIFA address bus The number of available address pins varies among devices see your device specific data manual for details When interfacing to an SDRAM device these pins are primarily used to provide the row and column address to the SDRAM ...

Page 837: ...2 1 for details on the clock signal Table 19 3 EMIFA Pins Specific to Asynchronous Memory Pin s I O Description EMA_CS 5 2 O Active low chip enable pins for asynchronous devices These pins are meant to be connected to the chip select pins of the attached asynchronous device These pins are active only during accesses to the asynchronous memory EMA_WAIT I Wait input with programmable polarity NAND F...

Page 838: ...r bank for the current access READ Read The READ command outputs the starting column address and signals the SDRAM to begin the burst read operation Address EMA_A 10 is always pulled low to avoid auto precharge This allows for better bank interleaving performance WRT Write The WRT command outputs the starting column address and signals the SDRAM to begin the burst write operation Address EMA_A 10 ...

Page 839: ...or 11 See your device specific data manual for the number of column address bits supported on your device The number of row address bits is 13 14 15 or 16 See your device specific data manual for the number of row address bits supported on your device The number of internal banks is 1 2 or 4 See your device specific data manual for the number of internal banks supported on your device Figure 19 3 ...

Page 840: ...re www ti com 840 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Figure 19 3 EMIFA to 2M 16 4 bank SDRAM Interface Figure 19 4 EMIFA to 512K 16 2 bank SDRAM Interface Table 19 6 16 bit EMIFA Address Pin Connections SDRAM Size Width Banks Device Address Pins 16M bits 16 2 SDRAM A 10 0 EMIF...

Page 841: ...th PD when entering power down mode NM Narrow Mode This bit defines the width of the data bus between the EMIFA and the attached SDRAM device When set to 1 the data bus is set to 16 bits When set to 0 the data bus is set to 32 bits This bit must always be set to 1 CL CAS latency This field defines the number of clock cycles between when an SDRAM issues a READ command and when the first piece of da...

Page 842: ...s to the SDRAM and Asynchronous interfaces are performed until this auto initialization is complete A write is performed to any of the three least significant bytes of the SDRAM configuration register SDCR An SDRAM initialization sequence consists of the following steps 1 If the initialization sequence is activated by a write to SDCR and if any of the SDRAM banks are open the EMIFA issues a PRE co...

Page 843: ... NOT violated 1 Place the SDRAM into Self Refresh Mode by setting the SR bit of SDCR to 1 A byte write to the upper byte of SDCR should be used to avoid restarting the SDRAM Auto Initialization Sequence described in Section 19 2 4 4 The SDRAM should be placed into Self Refresh mode when changing the frequency of EMA_CLK to avoid incurring the 200 μs Power up constraint again 2 Program the CPU s PL...

Page 844: ...inder of this section details the EMIFA s refresh scheme and provides an example for determining the appropriate value to place in the RR field of SDRCR The two counters used to perform auto refresh cycles are a 13 bit refresh interval counter and a 4 bit refresh backlog counter At reset and upon writing to the RR field the refresh interval counter is loaded with the value from RR field and begins...

Page 845: ...by setting the SR bit of SDCR to 1 This will cause the EMIFA to issue the SLFR command after completing any outstanding SDRAM access requests and clearing the refresh backlog counter by performing one or more auto refresh cycles This places the attached SDRAM device into self refresh mode in which it consumes a minimal amount of power while performing its own refresh cycles The SR bit should be se...

Page 846: ...anks of the SDRAM are closed precharged prior to issuing the POWER DOWN command Therefore the EMIFA only supports Precharge Power Down The EMIFA does not support Active Power Down where internal banks of the SDRAM are open active before the POWER DOWN command is issued During the power down state the EMIFA services the SDRAM asynchronous memory and register accesses as normal returning to the powe...

Page 847: ...s configured to 16 bit by setting the NM bit of the SDRAM configuration register SDCR to 1 a burst size of eight is used Figure 19 5 shows a burst size of eight The EMIFA will truncate a series of bursting data if the remaining addresses of the burst are not required to complete the request The EMIFA can truncate the burst in three ways By issuing another READ to the same page in the same bank By ...

Page 848: ...g the NM bit of the SDRAM configuration register SDCR to 1 a burst size of eight is used Figure 19 6 shows a burst size of eight Figure 19 6 Timing Waveform for Basic SDRAM Write Operation The EMIFA will truncate a series of bursting data if the remaining addresses of the burst are not part of the write request The EMIFA can truncate the burst in three ways By issuing another WRT to the same page ...

Page 849: ...close it This method of traversal through the SDRAM banks helps maximize the number of open banks inside of the SDRAM and results in an efficient use of the device There is no limitation on the number of banks that can be open at one time but only one page within a bank can be open at a time The EMIFA uses the EMA_WE_DQM pins during a WRT command to mask out selected bytes or entire words The EMA_...

Page 850: ... only during the strobe period of an access In this mode the EMA_WE_DQM pins of the EMIFA function as standard byte enables for reads and writes A summary of the differences between the two modes of operation are shown in Table 19 14 Refer to Section 19 2 5 4 for the details of asynchronous operations in Normal Mode and to Section 19 2 5 5 for the details of asynchronous operations in Select Strob...

Page 851: ... the least significant bits of the halfword or byte address respectively Additionally when the EMIFA interfaces to a 16 bit asynchronous device the EMA_BA 0 pin can serve as the upper address line EMA_A 22 Note that the width of the address bus varies with devices therefore see your device specific data manual for the EMA_A bus width supported Figure 19 8 and Figure 19 9 show the mapping between t...

Page 852: ...the EMIFA s asynchronous interface can be configured by programming the appropriate register fields The reset value and bit position for each register field can be found in Section 19 4 but the Boot ROM documentation should be consulted to determine if the fields are programmed during boot The following tables list the register fields that can be programmed and describe the purpose of each field T...

Page 853: ...ld time for the data pins EMA_D Refer to the datasheet of the external asynchronous device to determine the appropriate setting for this field TA Minimum turnaround time This field defines the minimum number of EMIFA clock cycles between asynchronous reads and writes minus one cycle The purpose of this feature is to avoid contention on the bus The value written to this field also determines the nu...

Page 854: ...d of an access cycle The maximum number of EMIFA clock cycles it will wait is determined by the following formula Maximum Extended Wait Cycles MAX_EXT_WAIT 1 16 If the EMA_WAIT pin is not deactivated within the time specified by this field the EMIFA resumes the access cycle registering whatever data is on the bus and proceeding to the hold period of the access cycle This situation is referred to a...

Page 855: ...ous Read Operations Normal Mode NOTE During the entirety of an asynchronous read operation the EMA_WE pin is driven high An asynchronous read is performed when any of the requesters mentioned in Section 19 2 2 request a read from the attached asynchronous memory After the request is received a read operation is initiated once it becomes the EMIFA s highest priority task according to the priority s...

Page 856: ...eriod EMA_OE rises The data on the EMA_D bus is sampled by the EMIFA In Figure 19 10 EMA_WAIT is inactive If EMA_WAIT is instead activated the strobe period can be extended by the external device to give it more time to provide the data Section 19 2 5 7 contains more details on using the EMA_WAIT pin End of the hold period At the end of the hold period The address pins EMA_A and EMA_BA become inva...

Page 857: ...MIFA proceeds to the setup period of the operation If it is no longer the highest priority task the EMIFA terminates the operation Start of the setup period The following actions occur at the start of the setup period The setup strobe and hold values are set according to the W_SETUP W_STROBE and W_HOLD values in CEnCFG The address pins EMA_A and EMA_BA and the data pins EMA_D become valid The EMA_...

Page 858: ...ress Data Address Byte enable Architecture www ti com 858 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Figure 19 11 Timing Waveform of an Asynchronous Write Cycle in Normal Mode ...

Page 859: ...ptions to this rule If the current read operation was directly proceeded by another read operation to the same chip select no turn around cycles are inserted After the EMIFA has waited for the turn around cycles to complete it again checks to make sure that the read operation is still its highest priority task If so the EMIFA proceeds to the setup period of the operation If it is no longer the hig...

Page 860: ...e enables Address Data Architecture www ti com 860 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Figure 19 12 Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode ...

Page 861: ...o make sure that the write operation is still its highest priority task If so the EMIFA proceeds to the setup period of the operation If it is no longer the highest priority task the EMIFA terminates the operation Start of the setup period The following actions occur at the start of the setup period The setup strobe and hold values are set according to the W_SETUP W_STROBE and W_HOLD values in CEn...

Page 862: ...e enables Address Data Architecture www ti com 862 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Figure 19 13 Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode ...

Page 863: ...art an ECC calculation for EMA_CS 4 Cleared to 0 when NAND Flash 3 ECC register NANDF3ECC is read CS4NAND NAND Flash mode for EMA_CS 4 Set to 1 to enable NAND Flash mode for EMA_CS 4 CS3ECC NAND Flash ECC state for EMA_CS 3 Set to 1 to start an ECC calculation for EMA_CS 3 Cleared to 0 when NAND Flash 2ECC register NANDF2ECC is read CS3NAND NAND Flash mode for EMA_CS 3 Set to 1 to enable NAND Flas...

Page 864: ...ed to EMIFA base address 0000 0000h to drive CLE and ALE low 0000 0010h to drive CLE high and ALE low 0000 0008h to drive CLE low and ALE high 19 2 5 6 4 NAND Read and Program Operations A NAND Flash access cycle is composed of a command address and data phase The EMIFA will not automatically generate these three phases to complete a NAND access with one transfer request To complete a NAND access ...

Page 865: ...LE and or ALE high To prevent the address from incrementing into a range that drives CLE and or ALE high the EDMA ACNT BCNT SIDX DIDX and synchronization type must be programmed appropriately Following is an example configuration of EDMA controller when EMA_A 2 is connected to CLE and EMA_A 1 is connected to ALE EDMA setup for a NAND Flash data read ACNT 8 bytes this can also be set to less than o...

Page 866: ... ECC start bit 4BITECC_START is cleared upon reading any of the NAND Flash 4 bit ECC 1 4 registers NAND4BITECC 4 1 The NAND Flash 4 bit ECC 1 4 registers are cleared upon writing one to the 4 bit ECC start bit 4BITECC_START The 4 bit ECC algorithm works on a 10 bit data bus but only the lower eight bits of the data bus actually contain data When the EMIFA is used in 16 bit mode the lower and upper...

Page 867: ... value can be broken down into ten 8 bit values 5 Store the parity to spare location in the NAND Flash For reads 1 Set the 4BITECC_START bit in the NAND Flash control register NANDFCR to 1 2 Read 518 bytes of data from the NAND Flash 3 Clear the 4BITECC_START bit in NANDFCR by reading any of the NAND Flash 4 bit ECC registers 4 Read the parity stored in the spare location in the NAND Flash 5 Conve...

Page 868: ...peration has completed the software can then configure the selected GPIO to be high 19 2 5 7 Extended Wait Mode and the EMA_WAIT Pin The EMIFA supports the Extend Wait Mode This is a mode in which the external asynchronous device may assert control over the length of the strobe period The Extended Wait Mode can be entered by setting the EW bit in the asynchronous n configuration register CEnCFG n ...

Page 869: ...al pull ups such as 10kΩ resistors should be placed on the 16 EMIFA data bus pins which do not have internal pull ups if it is required to perform reads in this situation The precise resistor value should be chosen so that the worst case combined off state leakage currents do not cause the voltage levels on the associated pins to drop below the high level input voltage requirement For information ...

Page 870: ...ation register AWCC The asynchronous time out interrupt condition occurs when the attached asynchronous device fails to deassert the EMA_WAIT pin within the number of cycles defined by the MAX_EXT_WAIT bit in AWCC this happens only in extended wait mode EMIFA supports only linear incrementing and cache line wrap addressing modes If an access request for an unsupported addressing mode is received t...

Page 871: ... set only when line trap interrupt occurs and the interrupt has been enabled by writing a 1 to the LT_MASK_SET bit in INTMSKSET EMIFA interrupt mask set register INTMSKSET WR_MASK_SET Writing a 1 to this bit enables the wait rise interrupt AT_MASK_SET Writing a 1 to this bit enables the asynchronous timeout interrupt LT_MASK_SET Writing a 1 to this bit enables the line trap interrupt EMIFA interru...

Page 872: ...s according to the following priority scheme highest priority listed first 1 If the EMIFA s backlog refresh counter is at the Refresh Must urgency level the EMIFA performs multiple SDRAM auto refresh cycles until the Refresh Release urgency level is reached 2 If an SDRAM or asynchronous read has been requested the EMIFA performs a read operation 3 If the EMIFA s backlog refresh counter is at the R...

Page 873: ... the asynchronous request is determined by the programmed setup strobe hold and turnaround values but can also be extended with the assertion of the EMA_WAIT input signal up to a programmed maximum limit It is up to the user to make sure that an entire asynchronous request does not exceed the timing values listed above when also interfacing to an SDRAM device This can be done by limiting the async...

Page 874: ...sh mode If the external memory requires a continuous clock the clock provided by the PLL must not be turned off because this may result in data corruption See the following subsections for the proper procedures to follow when stopping the EMIFA memory controller clocks Figure 19 17 EMIFA PSC Block Diagram 19 2 14 1 Power Management Using Self Refresh Mode The EMIFA can be placed into a self refres...

Page 875: ...e request and returns back to auto sleep state until further requests come On frequent requests EMIFA switches between auto sleep and enable states To bring EMIFA back to the enable state auto wake can be used Following procedure is followed for performing auto wake Program the LPSC of EMIFA for auto wake Bring EMIFA out of self refresh Refer to Section 19 2 4 7 for details on self refresh mode Af...

Page 876: ...de use of to receive the RD BY signal coming from the second flash as shown in Figure 19 18 Finally this example configuration connects the EMA_WE pin to the WE input of the flash and operates the EMIFA in Normal Mode 19 3 2 Software Configuration The following sections describe how to interface the EMIFA to SDRAM Asynchronous SRAM ASRAM or a NAND Flash device 19 3 2 1 Configuring the SDRAM Interf...

Page 877: ...4 bank CE CAS RAS WE CLK CKE BA 1 BA 0 A 11 0 LDQM UDQM DQ 15 0 TC5515100FT 12 A 0 A 19 1 DQ 15 0 CE WE OE RY BY BYTE0 BYTE1 www ti com Example Configuration 877 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Figure 19 18 Example Configuration Interface ...

Page 878: ...tead Samsung specifies tRC as the minimum auto refresh period 2 The Samsung datasheet does not specify a tWR value Instead Samsung specifies tRDL as last data in to row precharge minimum delay Table 19 27 SDTIMR Field Calculations for the EMIFA to K4S641632H TC L 70 Interface Field Name Formula Value from K4S641632H TC L 70 Datasheet Value Calculated for Field T_RFC T_RFC tRFC fEMA_CLK 1 tRC 68 ns...

Page 879: ...rmula Value from K4S641632H TC L 70 Datasheet Value Calculated for Field T_XS T_XS tXSR fEMA_CLK 1 tRC 68 ns min 1 6 Figure 19 20 SDRAM Self Refresh Exit Timing Register SDSRETR 31 16 0000 0000 0000 0000 Reserved 15 5 4 0 000 0000 0000 0 0110 Reserved T_XS 19 3 2 1 4 SDRAM Refresh Control Register SDRCR Settings for the EMIFA to K4S641632H TC L 70 Interface The SDRAM refresh control register SDRCR...

Page 880: ...ld be programmed The EMIFA is now ready to perform read and write accesses to the SDRAM Table 19 30 SDCR Field Values For the EMIFA to K4S641632H TC L 70 Interface Field Value Purpose SR 0 To avoid placing the EMIFA into the self refresh state NM 1 To configure the EMIFA for a 16 bit data bus CL 011b To select a CAS latency of 3 BIT11_9LOCK 1 To allow the CL field to be written IBANK 010b To selec...

Page 881: ...MIFA Input Timing Requirements Parameter Description tSU Data Setup time data valid before EMA_OE high tH Data Hold time data valid after EMA_OE high Table 19 32 ASRAM Output Timing Characteristics Parameter Description tACC Address Access time tOH Output data Hold time for address change tCOD Output Disable time from chip enable Table 19 33 ASRAM Input Timing Requirement for a Read Parameter Desc...

Page 882: ...nst the situation when the output turn off time of the memory is longer than the time it takes to start the next write cycle If this is the case the EMIFA will drive data at the same time as the memory causing contention on the bus By examining Figure 19 23 the equation for TA can be derived as Figure 19 23 Timing Waveform of an ASRAM Read For a write access Table 19 34 lists the AC timing specifi...

Page 883: ...how the EMIFA and ASRAM AC timing requirements work together to define values for W_SETUP W_STROBE and W_HOLD From Figure 19 24 the following equations may be derived tcyc is the period at which the EMIFA operates The W_SETUP W_STROBE and W_HOLD fields are programmed in terms of EMIFA cycles where as the data sheet specifications are typically given is nano seconds This is explains the presence of...

Page 884: ...epresents the delayed signal seen at the ASRAM Table 19 35 ASRAM Timing Requirements With PCB Delays Parameter Description Read Access tEM_CS Delay on EMA_CS from EMIFA to ASRAM EMA_CS is driven by EMIF tEM_A Delay on EMA_A from EMIFA to ASRAM EMA_A is driven by EMIF tEM_OE Delay on EMA_OE from EMIFA to ASRAM EMA_OE is driven by EMIF tEM_D Delay on EMA_D from ASRAM to EMIFA EMA_D is driven by ASRA...

Page 885: ... EMIFA Figure 19 25 Timing Waveform of an ASRAM Read with PCB Delays From Figure 19 26 the following equations may be derived tcyc is the period at which the EMIFA operates The W_SETUP W_STROBE and W_HOLD fields are programmed in terms of EMIFA cycles where as the data sheet specifications are typically given is nano seconds This is explains the presence of tcyc in the denominator of the following...

Page 886: ...STROBE W_HOLD w tWC m tcyc 3 W_HOLD w maxǒǒtEM_WE tWR m tEM_A Ǔ tcyc ǒtEM_WE tDH m tEM_D Ǔ tcyc Ǔ 1 W_SETUP W_STROBE max tEM_A tAW m tEM_WE tcyc tEM_D tDS m tEM_WE tcyc 2 W_STROBE w tWP m tcyc 1 Example Configuration www ti com 886 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Figure 19 ...

Page 887: ...er Description Min Max Units tACC Address Access time 12 nS tOH Output data Hold time for address change 3 nS tRC Read cycle time 12 nS tWP Write Pulse width 8 nS tAW Address valid to end of Write 9 nS tDS Data Setup time 7 nS tWR Write Recovery time 0 nS tDH Data Hold time 0 nS tWC Write Cycle time 12 nS tCOD Output Disable time from chip enable 7 Table 19 38 lists the values of the PCB board del...

Page 888: ... m tEM_A Ǔ tcyc 1 w 0 0 45 3 0 27 10 1 w 1 37 R_SETUP R_STROBE R_HOLD w tRC m tcyc 3 w ǒ12 10 Ǔ 3 w 1 8 R_SETUP R_STROBE tEM_A tACC m tSU tEM_D tcyc 2 0 27 12 5 0 45 10 2 0 23 Example Configuration www ti com 888 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Inserting these values into t...

Page 889: ...TROBE 0 W_HOLD R_HOLD Read Write hold widths W_HOLD 0 R_HOLD 0 TA Minimum turnaround time TA 0 ASIZE Asynchronous Device Bus Width ASIZE 1 select a 16 bit data bus width 19 3 2 3 Interfacing to NAND Flash The following example explains how to interface the EMIFA to the Hynix HY27UA081G1M NAND Flash device 19 3 2 3 1 Margin Requirements The Flash interface is typically a low performance interface c...

Page 890: ...by the EMIFA The command and address phases of a NAND Flash access cycle are asynchronous writes performed by the EMIFA where as the data phase can be either an asynchronous write or a read depending on whether the NAND Flash is being programmed or read Therefore to determine the required EMIFA configuration to interface to the NAND Flash for a read operation Table 19 41 and Table 19 42 list the A...

Page 891: ...re programmed in terms of EMIFA cycles where as the data sheet specifications are typically given is nano seconds This is explains the presence of tcyc in the denominator of the following equations A minus 1 is included in the equations because each field in CEnCFG is programmed in terms of EMIFA clock cycles minus 1 cycle For example R_SETUP is equal to R_SETUP width in EMIFA clock cycles minus 1...

Page 892: ...meter Description tWP Write Pulse width tCLS CLE Setup time tALS ALE Setup time tCS CS Setup time tDS Data Setup time tCLH CLE Hold time tALH ALE Hold time tCH CS Hold time tDH Data Hold time tWC Write Cycle time Figure 19 28 to Figure 19 30 show the command latch address latch and data input latch of the NAND access From Figure 19 28 to Figure 19 30 the following equations may be derived tcyc is ...

Page 893: ..._EM_A 2 EMA_WE EMA_D 7 0 tCS m tALS m tCLS m tDS m tDH m Setup Strobe Hold www ti com Example Configuration 893 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Figure 19 28 Timing Waveform of a NAND Flash Command Write Figure 19 29 Timing Waveform of a NAND Flash Address Write ...

Page 894: ...S m tCLS m tDS m tDH m Setup Strobe Hold Example Configuration www ti com 894 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Figure 19 30 Timing Waveform of a NAND Flash Data Write ...

Page 895: ...ice specific data manual for the value Table 19 44 EMIFA Timing Requirements for HY27UA081G1M Example Parameter Description Min Max Units tSU Data Setup time data valid before EMA_OE high 3 to 7 1 nS tH Data Hold time data valid after EMA_OE high 0 nS Table 19 45 NAND Flash Timing Requirements for HY27UA081G1M Example Parameter Description Min Max Units tRP Read Pulse width 60 nS tREA Read Enable ...

Page 896: ...yc 2 75 5 10 2 6 R_STROBE w maxǒǒtREA m tSU Ǔ tcyc tRP tcyc Ǔ 1 w ǒ65 10 Ǔ 1 w 5 5 R_SETUP w tCLR m tcyc 1 w ǒ10 10 Ǔ 1 w 0 Example Configuration www ti com 896 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated External Memory Interface A EMIFA Inserting these values into the equations defined above allows you to determine t...

Page 897: ...ous device bus width ASIZE 0 select an 8 bit data bus width Since this is a NAND Flash example the EMIFA must be configured for NAND Flash mode This is accomplished by configuring the NAND Flash control register NANDFCR as in Table 19 47 In NANDFCR chip select space 2 must be configured with NAND Flash mode enabled Table 19 47 Configuring NANDFCR for HY27UA081G1M Example Parameter Setting CS5ECC N...

Page 898: ...9 4 5 18h CE4CFG Asynchronous 3 Configuration Register Section 19 4 5 1Ch CE5CFG Asynchronous 4 Configuration Register Section 19 4 5 20h SDTIMR SDRAM Timing Register Section 19 4 6 3Ch SDSRETR SDRAM Self Refresh Exit Timing Register Section 19 4 7 40h INTRAW EMIFA Interrupt Raw Register Section 19 4 8 44h INTMSK EMIFA Interrupt Mask Register Section 19 4 9 48h INTMSKSET EMIFA Interrupt Mask Set R...

Page 899: ...it cycle configuration register AWCC is used to configure the parameters for extended wait cycles Both the polarity of the EMA_WAIT pin s and the maximum allowable number of extended wait cycles can be configured The AWCC is shown in Figure 19 32 and described in Table 19 50 Not all devices support both EMA_WAIT 1 and EMA_WAIT 0 see the device specific data manual to determine support on each devi...

Page 900: ...ternal wait states 2h 3h Reserved 21 20 CS4_WAIT 0 3h Chip Select 4 WAIT signal selection This signal determines which EMA_WAIT n signal will be used for memory accesses to chip select 4 memory space 0 EMA_WAIT 0 pin is used to control external wait states 1h EMA_WAIT 1 pin is used to control external wait states 2h 3h Reserved 19 18 CS3_WAIT 0 3h Chip Select 3 WAIT signal selection This signal de...

Page 901: ...d in Section 19 2 4 7 The field should be written using a byte write to the upper byte of SDCR to avoid triggering the SDRAM initialization sequence 0 Writing a 0 to this bit will cause connected SDRAM devices and the EMIFA to exit the Self Refresh mode 1 Writing a 1 to this bit will cause connected SDRAM devices and the EMIFA to enter the Self Refresh mode 30 PD Power Down bit This bit controls e...

Page 902: ...s read as 0 Writing to this field triggers the SDRAM initialization sequence 0 CL cannot be written 1 CL can be written 7 Reserved 0 Reserved The reserved bit location is always read as 0 If writing to this field always write the default value of 0 6 4 IBANK 0 7h Internal SDRAM Bank size This field defines number of banks inside the connected SDRAM devices Writing to this field triggers the SDRAM ...

Page 903: ...in Figure 19 34 and described in Table 19 52 Figure 19 34 SDRAM Refresh Control Register SDRCR 31 16 Reserved R 0 15 13 12 0 Reserved RR R 0 R W 4E2h LEGEND R W Read Write R Read only n value after reset Table 19 52 SDRAM Refresh Control Register SDRCR Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 If writing to this field alw...

Page 904: ... Configuration Register CEnCFG Field Descriptions Bit Field Value Description 31 SS Select Strobe bit This bit defines whether the asynchronous interface operates in Normal Mode or Select Strobe Mode See Section 19 2 5 for details on the two modes of operation 0 Normal Mode enabled 1 Select Strobe Mode enabled 30 EW Extend Wait bit This bit defines whether extended wait cycles will be enabled See ...

Page 905: ...ion 19 2 5 3 for details 0h Divide by 1 1h Divide by 2 2h 3Fh Divide by 3 to Divide by 64 6 4 R_HOLD 0 7h Read hold width in the format n 1 where n number of EMA_CLK cycles See Section 19 2 5 3 for details 0h Divide by 1 1h Divide by 2 2h 7h Divide by 3 to Divide by 8 3 2 TA 0 3h Minimum Turn Around time This field defines the minimum number of EMA_CLK cycles between reads and writes minus one cyc...

Page 906: ...ved 0 Reserved The reserved bit location is always read as 0 If writing to this field always write the default value of 0 22 20 T_RCD 0 7h Specifies the Trcd value of the SDRAM This defines the minimum number of EMA_CLK cycles from Active ACTV to Read READ or Write WRT minus 1 T_RCD Trcd tEMA_CLK 1 19 Reserved 0 Reserved The reserved bit location is always read as 0 If writing to this field always...

Page 907: ...the EMIFA issues another command The SDSRETR is shown in Figure 19 37 and described in Table 19 55 Figure 19 37 SDRAM Self Refresh Exit Timing Register SDSRETR 31 16 Reserved R 0 15 5 4 0 Reserved T_XS R 0 R W 9h LEGEND R W Read Write R Read only n value after reset Table 19 55 SDRAM Self Refresh Exit Timing Register SDSRETR Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved T...

Page 908: ...3 Reserved 0 Reserved The reserved bit location is always read as 0 If writing to this field always write the default value of 0 2 WR Wait Rise This bit is set to 1 by hardware to indicate that a rising edge on the EMA_WAIT pin has occurred 0 Indicates that a rising edge has not occurred on the EMA_WAIT pin Writing a 0 has no effect 1 Indicates that a rising edge has occurred on the EMA_WAIT pin W...

Page 909: ...ways read as 0 If writing to this field always write the default value of 0 2 WR_MASKED Wait Rise Masked This bit is set to 1 by hardware to indicate a rising edge has occurred on the EMA_WAIT pin provided that the WR_MASK_SET bit is set to 1 in the EMIFA interrupt mask set register INTMSKSET 0 Indicates that a wait rise interrupt has not been generated Writing a 0 has no effect 1 Indicates that a...

Page 910: ...ASK_SET Wait Rise Mask Set This bit determines whether or not the wait rise Interrupt is enabled Writing a 1 to this bit sets this bit sets the WR_MASK_CLR bit in the EMIFA interrupt mask clear register INTMSKCLR and enables the wait rise interrupt To clear this bit a 1 must be written to the WR_MASK_CLR bit in INTMSKCLR 0 Indicates that the wait rise interrupt is disabled Writing a 0 has no effec...

Page 911: ...t clears this bit clears the WR_MASK_SET bit in the EMIFA interrupt mask set register INTMSKSET and disables the wait rise interrupt To set this bit a 1 must be written to the WR_MASK_SET bit in INTMSKSET 0 Indicates that the wait rise interrupt is disabled Writing a 0 has no effect 1 Indicates that the wait rise interrupt is enabled Writing a 1 clears this bit and the WR_MASK_SET bit in the EMIFA...

Page 912: ...START Nand Flash 4 bit ECC start for the selected chip select Set to 1 to start 4_bit ECC calculation on data for NAND Flash on chip select selected by bit 4BITECCSEL This bit is cleared when ay of the NAND Flash 4_bit ECC registers are read 1 start 4_bit ECC calculation on data for NAND Flash on chip select selected by bit 4BITECCSEL 11 CS5ECC NAND Flash ECC start for chip select 5 Set to 1 to st...

Page 913: ...t on which 4 bit ECC will be calculated 0 ECC will be calculated for CS2 1h ECC will be calculated for CS3 2h ECC will be calculated for CS4 3h ECC will be calculated for CS5 3 CS5NAND NAND Flash mode for chip select 5 0 Not using NAND Flash 1 Using NAND Flash on EMA_CS5 2 CS4NAND NAND Flash mode for chip select 4 0 Not using NAND Flash 1 Using NAND Flash on EMA_CS4 1 CS3NAND NAND Flash mode for c...

Page 914: ...4 Bit ECC Error Address and Error Value Calculation 0 1 error found 1h 2 errors found 2h 3 errors found 3h 4 errors found 15 12 Reserved 0 Reserved 11 8 ECC_STATE 0 Fh ECC correction state while performing 4 bit ECC Address and Error Value Calculation 0 No errors detected 1h Errors cannot be corrected 5 or more 2h Error correction complete errors on bit 8 or 9 3h Error correction complete error ex...

Page 915: ...ulated while reading writing NAND Flash 24 P256O 0 1 ECC code calculated while reading writing NAND Flash 23 P128O 0 1 ECC code calculated while reading writing NAND Flash 22 P64O 0 1 ECC code calculated while reading writing NAND Flash 21 P32O 0 1 ECC code calculated while reading writing NAND Flash 20 P16O 0 1 ECC code calculated while reading writing NAND Flash 19 P8O 0 1 ECC code calculated wh...

Page 916: ...s shown in Figure 19 45 and described in Table 19 63 Figure 19 45 NAND Flash 4 Bit ECC LOAD Register NAND4BITECCLOAD 31 16 Reserved R 0 15 10 9 0 Reserved 4BITECCLOAD R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 19 63 NAND Flash 4 Bit ECC LOAD Register NAND4BITECCLOAD Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 0 4BITECCLOAD 0 3FFh 4 bit ECC ...

Page 917: ...ue Description 31 26 Reserved 0 Reserved 25 16 4BITECCVAL2 0 3FFh Calculated 4 bit ECC or Syndrom Value2 15 10 Reserved 0 Reserved 9 0 4BITECCVAL1 0 3FFh Calculated 4 bit ECC or Syndrom Value1 19 4 17 NAND Flash 4 Bit ECC Register 2 NAND4BITECC2 The NAND Flash 4 bit ECC register 2 NAND4BITECC2 is shown in Figure 19 47 and described in Table 19 65 Figure 19 47 NAND Flash 4 Bit ECC Register 2 NAND4B...

Page 918: ...ue Description 31 26 Reserved 0 Reserved 25 16 4BITECCVAL6 0 3FFh Calculated 4 bit ECC or Syndrom Value6 15 10 Reserved 0 Reserved 9 0 4BITECCVAL5 0 3FFh Calculated 4 bit ECC or Syndrom Value5 19 4 19 NAND Flash 4 Bit ECC Register 4 NAND4BITECC4 The NAND Flash 4 bit ECC register 4 NAND4BITECC4 is shown in Figure 19 49 and described in Table 19 67 Figure 19 49 NAND Flash 4 Bit ECC Register 4 NAND4B...

Page 919: ... Description 31 26 Reserved 0 Reserved 25 16 4BITECCERRADD2 0 3FFh Calculated 4 bit ECC Error Address 2 15 10 Reserved 0 Reserved 9 0 4BITECCERRADD1 0 3FFh Calculated 4 bit ECC Error Address 1 19 4 21 NAND Flash 4 Bit ECC Error Address Register 2 NANDERRADD2 The NAND Flash 4 bit ECC error register 2 NANDERRADD2 is shown in Figure 19 51and described in Table 19 69 Figure 19 51 NAND Flash 4 Bit ECC ...

Page 920: ...alue Description 31 26 Reserved 0 Reserved 25 16 4BITECCERRVAL2 0 3FFh Calculated 4 bit ECC Error Value 2 15 10 Reserved 0 Reserved 9 0 4BITECCERRVAL1 0 3FFh Calculated 4 bit ECC Error Value 1 19 4 23 NAND Flash 4 Bit ECC Error Value Register 2 NANDERRVAL2 The NAND Flash 4 bit ECC error value register 2 NANDERRVAL2 is shown in Figure 19 53 and described in Table 19 71 Figure 19 53 NAND Flash 4 Bit...

Page 921: ... GPIO The GPIO peripheral provides dedicated general purpose pins that can be configured as either inputs or outputs When configured as an output you can write to an internal register to control the state driven on the output pin When configured as an input you can detect the state of the input by reading the state of an internal register This chapter describes the GPIO Topic Page 20 1 Introductio...

Page 922: ... through separate data set and clear registers allows multiple software processes to control GPIO signals without critical section protection Set clear functionality through writing to a single output data register is also supported Separate input output registers Output register can be read to reflect output drive status Input register can be read to reflect pin status All GPIO signals can be use...

Page 923: ...d of the GPIO peripheral is limited by system level latencies More specifically how quickly the GPIO registers can be written to or read from 20 2 2 Signal Descriptions The number of GPIO signals supported will vary between devices For information on the number of signals supported and the package pinout of each GPIO signal see your device specific data manual 20 2 3 Pin Multiplexing Extensive pin...

Page 924: ... GPIO pins additional control registers and fields should be appended using the same numbering scheme in the table Detailed information regarding the specific register names for each bank and the contents and function of these registers is presented in Section 20 3 Table 20 1 GPIO Register Bits and Banks Associated With GPIO Signals GPIO Pin Number GPIO Signal Name Bank Number Control Registers Re...

Page 925: ...3 Bit 14 GP2P14 48 GP2 15 2 register_name23 Bit 15 GP2P15 49 GP3 0 3 register_name23 Bit 16 GP3P0 50 GP3 1 3 register_name23 Bit 17 GP3P1 51 GP3 2 3 register_name23 Bit 18 GP3P2 52 GP3 3 3 register_name23 Bit 19 GP3P3 53 GP3 4 3 register_name23 Bit 20 GP3P4 54 GP3 5 3 register_name23 Bit 21 GP3P5 55 GP3 6 3 register_name23 Bit 22 GP3P6 56 GP3 7 3 register_name23 Bit 23 GP3P7 57 GP3 8 3 register_na...

Page 926: ...9 GP5P13 95 GP5 14 5 register_name45 Bit 30 GP5P14 96 GP5 15 5 register_name45 Bit 31 GP5P15 97 GP6 0 6 register_name67 Bit 0 GP6P0 98 GP6 1 6 register_name67 Bit 1 GP6P1 99 GP6 2 6 register_name67 Bit 2 GP6P2 100 GP6 3 6 register_name67 Bit 3 GP6P3 101 GP6 4 6 register_name67 Bit 4 GP6P4 102 GP6 5 6 register_name67 Bit 5 GP6P5 103 GP6 6 6 register_name67 Bit 6 GP6P6 104 GP6 7 6 register_name67 Bi...

Page 927: ...3 GP8 14 8 register_name8 Bit 14 GP8P14 144 GP8 15 8 register_name8 Bit 15 GP8P15 20 2 6 Using a GPIO Signal as an Output GPIO signals are configured to operate as inputs or outputs by writing the appropriate value to the GPIO direction register DIR This section describes using the GPIO signal as an output signal 20 2 6 1 Configuring a GPIO Output Signal To configure a given GPIO signal as an outp...

Page 928: ...ing a GPIO Signal as an Input GPIO signals are configured to operate as inputs or outputs by writing the appropriate value to the GPIO direction register DIR This section describes using the GPIO signal as an input signal 20 2 7 1 Configuring a GPIO Input Signal To configure a given GPIO signal as an input set the bit in DIR that is associated with the desired GPIO signal For detailed information ...

Page 929: ... of 16 by setting the appropriate bit s in the GPIO interrupt per bank enable register BINTEN For example to enable bank 0 interrupts events from GP0 15 0 set bit 0 in BINTEN to enable bank 3 interrupts events from GP3 15 0 set bit 3 in BINTEN For detailed information on BINTEN see Section 20 3 20 2 10 3 Configuring GPIO Interrupt Edge Triggering Each GPIO interrupt source can be configured to gen...

Page 930: ...determine which GPIO interrupt occurred It is the responsibility of software to ensure that all pending GPIO interrupts are appropriately serviced Pending GPIO interrupt flags can be cleared by writing a logic 1 to the associated bit position in INTSTAT For detailed information on INTSTAT see Section 20 3 20 2 10 5 Interrupt Multiplexing GPIO interrupts may be multiplexed with other interrupt func...

Page 931: ...r Section 20 3 10 30h CLR_FAL_TRIG01 GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register Section 20 3 11 34h INTSTAT01 GPIO Banks 0 and 1 Interrupt Status Register Section 20 3 12 GPIO Banks 2 and 3 38h DIR23 GPIO Banks 2 and 3 Direction Register Section 20 3 3 3Ch OUT_DATA23 GPIO Banks 2 and 3 Output Data Register Section 20 3 4 40h SET_DATA23 GPIO Banks 2 and 3 Set Data Register Section 20 ...

Page 932: ...3 11 ACh INTSTAT67 GPIO Banks 6 and 7 Interrupt Status Register Section 20 3 12 GPIO Bank 8 B0h DIR8 GPIO Bank 8 Direction Register Section 20 3 3 B4h OUT_DATA8 GPIO Bank 8 Output Data Register Section 20 3 4 B8h SET_DATA8 GPIO Bank 8 Set Data Register Section 20 3 5 BCh CLR_DATA8 GPIO Bank 8 Clear Data Register Section 20 3 6 C0h IN_DATA8 GPIO Bank 8 Input Data Register Section 20 3 7 C4h SET_RIS...

Page 933: ...isable or enable the bank 7 interrupts events from GP7 15 0 0 Bank 7 interrupts are disabled 1 Bank 7 interrupts are enabled 6 EN6 Bank 6 interrupt enable is used to disable or enable the bank 6 interrupts events from GP6 15 0 0 Bank 6 interrupts are disabled 1 Bank 6 interrupts are enabled 5 EN5 Bank 5 interrupt enable is used to disable or enable the bank 5 interrupts events from GP5 15 0 0 Bank...

Page 934: ...P0P2 GP0P1 GP0P0 R W 1 LEGEND R W Read Write n value after reset Figure 20 5 GPIO Banks 2 and 3 Direction Register DIR23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP2P15 GP2P14 GP2P13 GP2P12 GP2P11 GP2P10 GP2P9 GP2P8 GP2P7 GP2P6 GP2P5 GP2P4 GP2P3 G...

Page 935: ...ed R W 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP8P15 GP8P14 GP8P13 GP8P12 GP8P11 GP8P10 GP8P9 GP8P8 GP8P7 GP8P6 GP8P5 GP8P4 GP8P3 GP8P2 GP8P1 GP8P0 R W 1 LEGEND R W Read Write n value after reset Table 20 5 GPIO Direction Register DIRn Field Descriptions Bit Field Value Description 31 0 GPkPj Direction of pin GPk j The GPkPj bit is used to control the direction output 0 input 1 of pin j in GPIO b...

Page 936: ...11 10 9 8 7 6 5 4 3 2 1 0 GP0P15 GP0P14 GP0P13 GP0P12 GP0P11 GP0P10 GP0P9 GP0P8 GP0P7 GP0P6 GP0P5 GP0P4 GP0P3 GP0P2 GP0P1 GP0P0 R W 0 LEGEND R W Read Write n value after reset Figure 20 10 GPIO Banks 2 and 3 Output Data Register OUT_DATA23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R W 0 15 1...

Page 937: ...7 6 5 4 3 2 1 0 GP8P15 GP8P14 GP8P13 GP8P12 GP8P11 GP8P10 GP8P9 GP8P8 GP8P7 GP8P6 GP8P5 GP8P4 GP8P3 GP8P2 GP8P1 GP8P0 R W 0 LEGEND R W Read Write n value after reset Table 20 6 GPIO Output Data Register OUT_DATAn Field Descriptions Bit Field Value Description 31 0 GPkPj Output drive state of GPk j The GPkPj bit is used to drive the output low 0 high 1 of pin j in GPIO bankk The GPkPj bit is ignore...

Page 938: ... 6 5 4 3 2 1 0 GP0P15 GP0P14 GP0P13 GP0P12 GP0P11 GP0P10 GP0P9 GP0P8 GP0P7 GP0P6 GP0P5 GP0P4 GP0P3 GP0P2 GP0P1 GP0P0 R W 0 LEGEND R W Read Write n value after reset Figure 20 15 GPIO Banks 2 and 3 Set Data Register SET_DATA23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R W 0 15 14 13 12 11 10 ...

Page 939: ...8P12 GP8P11 GP8P10 GP8P9 GP8P8 GP8P7 GP8P6 GP8P5 GP8P4 GP8P3 GP8P2 GP8P1 GP8P0 R W 0 LEGEND R W Read Write n value after reset Table 20 7 GPIO Set Data Register SET_DATAn Field Descriptions Bit Field Value Description 31 0 GPkPj Set the output drive state of GPk j to logic high The GPkPj bit is used to drive the output high on pin j in GPIO bankk The GPkPj bit is ignored when GPk j is configured a...

Page 940: ... 7 6 5 4 3 2 1 0 GP0P15 GP0P14 GP0P13 GP0P12 GP0P11 GP0P10 GP0P9 GP0P8 GP0P7 GP0P6 GP0P5 GP0P4 GP0P3 GP0P2 GP0P1 GP0P0 R W 0 LEGEND R W Read Write n value after reset Figure 20 20 GPIO Banks 2 and 3 Clear Data Register CLR_DATA23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R W 0 15 14 13 12 11...

Page 941: ...8P12 GP8P11 GP8P10 GP8P9 GP8P8 GP8P7 GP8P6 GP8P5 GP8P4 GP8P3 GP8P2 GP8P1 GP8P0 R W 0 LEGEND R W Read Write n value after reset Table 20 8 GPIO Clear Data Register CLR_DATAn Field Descriptions Bit Field Value Description 31 0 GPkPj Clear the output drive state of GPk j to logic low The GPkPj bit is used to drive the output low on pin j in GPIO bankk The GPkPj bit is ignored when GPk j is configured...

Page 942: ...P15 GP0P14 GP0P13 GP0P12 GP0P11 GP0P10 GP0P9 GP0P8 GP0P7 GP0P6 GP0P5 GP0P4 GP0P3 GP0P2 GP0P1 GP0P0 R 0 LEGEND R Read only n value after reset Figure 20 25 GPIO Banks 2 and 3 Input Data Register IN_DATA23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP2P...

Page 943: ...TA8 31 16 Reserved R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP8P15 GP8P14 GP8P13 GP8P12 GP8P11 GP8P10 GP8P9 GP8P8 GP8P7 GP8P6 GP8P5 GP8P4 GP8P3 GP8P2 GP8P1 GP8P0 R 0 LEGEND R Read only n value after reset Table 20 9 GPIO Input Data Register IN_DATAn Field Descriptions Bit Field Value Description 31 0 GPkPj Status of pin GPk j Reading the GPkPj bit returns the state of pin j in GPIO bank k 0 GPk j...

Page 944: ... GP0P1 GP0P0 R W 0 LEGEND R W Read Write n value after reset Figure 20 30 GPIO Banks 2 and 3 Set Rise Trigger Register SET_RIS_TRIG23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP2P15 GP2P14 GP2P13 GP2P12 GP2P11 GP2P10 GP2P9 GP2P8 GP2P7 GP2P6 GP2P5 ...

Page 945: ...R W 0 LEGEND R W Read Write n value after reset Table 20 10 GPIO Set Rising Edge Trigger Interrupt Register SET_RIS_TRIGn Field Descriptions Bit Field Value Description 31 0 GPjPk Enable rising edge trigger interrupt detection on GPk j Reading the GPkPj bit in either SET_RIS_TRIGn or CLR_RIS_TRIGn always returns an indication of whether the rising edge interrupt generation function is enabled for ...

Page 946: ...0P2 GP0P1 GP0P0 R W 0 LEGEND R W Read Write n value after reset Figure 20 35 GPIO Banks 2 and 3 Clear Rise Trigger Register CLR_RIS_TRIG23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP2P15 GP2P14 GP2P13 GP2P12 GP2P11 GP2P10 GP2P9 GP2P8 GP2P7 GP2P6 G...

Page 947: ...1 GP8P0 R W 0 LEGEND R W Read Write n value after reset Table 20 11 GPIO Clear Rising Edge Interrupt Register CLR_RIS_TRIGn Field Descriptions Bit Field Value Description 31 0 GPkPj Disable rising edge interrupt detection on GPk j Reading the GPkPj bit in either SET_RIS_TRIGn or CLR_RIS_TRIGn always returns an indication of whether the rising edge interrupt generation function is enabled for GPk j...

Page 948: ...0P2 GP0P1 GP0P0 R W 0 LEGEND R W Read Write n value after reset Figure 20 40 GPIO Banks 2 and 3 Set Rise Trigger Register SET_FAL_TRIG23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP2P15 GP2P14 GP2P13 GP2P12 GP2P11 GP2P10 GP2P9 GP2P8 GP2P7 GP2P6 GP2...

Page 949: ...W 0 LEGEND R W Read Write n value after reset Table 20 12 GPIO Set Falling Edge Trigger Interrupt Register SET_FAL_TRIGn Field Descriptions Bit Field Value Description 31 0 GPkPj Enable falling edge trigger interrupt detection on GPk j Reading the GPkPj bit in either SET_FAL_TRIGn or CLR_FAL_TRIGn always returns an indication of whether the falling edge interrupt generation function is enabled for...

Page 950: ...GP0P2 GP0P1 GP0P0 R W 0 LEGEND R W Read Write n value after reset Figure 20 45 GPIO Banks 2 and 3 Clear Rise Trigger Register CLR_FAL_TRIG23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R W 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP2P15 GP2P14 GP2P13 GP2P12 GP2P11 GP2P10 GP2P9 GP2P8 GP2P7 GP2P6...

Page 951: ...GP8P0 R W 0 LEGEND R W Read Write n value after reset Table 20 13 GPIO Clear Falling Edge Interrupt Register CLR_FAL_TRIGn Field Descriptions Bit Field Value Description 31 0 GPkPj Disable falling edge interrupt detection on GPk j Reading the GPkPj bit in either SET_FAL_TRIGn or CLR_FAL_TRIGn always returns an indication of whether the falling edge interrupt generation function is enabled for GPk ...

Page 952: ...bit writing 0 has no effect n value after reset Figure 20 50 GPIO Banks 2 and 3 Interrupt Status Register INTSTAT23 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GP3P15 GP3P14 GP3P13 GP3P12 GP3P11 GP3P10 GP3P9 GP3P8 GP3P7 GP3P6 GP3P5 GP3P4 GP3P3 GP3P2 GP3P1 GP3P0 R W1C 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GP2P15 GP2P14 GP2P13 GP2P12 GP2P11 GP2P10 GP2P9 GP2P8 GP2P7 GP2P6 GP2P5 GP2P4 GP2P3 GP2P...

Page 953: ...12 GP8P11 GP8P10 GP8P9 GP8P8 GP8P7 GP8P6 GP8P5 GP8P4 GP8P3 GP8P2 GP8P1 GP8P0 R W1C 0 LEGEND R W Read Write W1C Write 1 to clear bit writing 0 has no effect n value after reset Table 20 14 GPIO Interrupt Status Register INTSTATn Field Descriptions Bit Field Value Description 31 0 GPkPj Interrupt status of GPk j The GPkPj bit is used to monitor pending GPIO interrupts on pin j of GPIO bank k Write a...

Page 954: ... Copyright 2013 2016 Texas Instruments Incorporated Host Port Interface HPI Chapter 21 SPRUH82C April 2013 Revised September 2016 Host Port Interface HPI This chapter describes the host port interface HPI Topic Page 21 1 Introduction 955 21 2 Architecture 958 21 3 Registers 978 ...

Page 955: ...nsfer the host can also use the HPI to bootload the processor by downloading program and data information to the processor s memory after power up 21 1 2 Features The HPI supports the following features Multiplexed address data Dual 16 bit halfword cycle access internal data word is 32 bits wide 16 bit wide host data bus interface Internal data bursting using 8 word read and write first in first o...

Page 956: ... host cycle consists of two consecutive 16 bit transfers When the host drives an address on the bus the address is stored in a 32 bit address register HPIA in the HPI so that the bus can then be used for data The HPI contains two address registers HPIAR and HPIAW which can be used as separate address registers for read accesses and write accesses for details see Section 21 2 6 1 A control register...

Page 957: ...ed by an international organization It is a generic parallel interface that can be configured to gluelessly interface to a variety of parallel devices 21 1 5 Terminology Used in This Document The following is a brief explanation of some terms used in this document Term Meaning host External host device HPI DMA logic Logic used to communicate between the HPI and the DMA system that moves data to an...

Page 958: ...dicates the transfer is a read from the HPI while driving UHPI_HR W low indicates a write to the HPI UHPI_HHWIL I Address or control pins Halfword identification line The host uses UHPI_HHWIL to identify the first and second halfwords of the host cycle UHPI_HHWIL must be driven low for the first halfword and high for the second halfword UHPI_HAS I None Address strobe Connect to logic high UHPI_HIN...

Page 959: ... GPIO Enable Bit s When Enabled as GPIO Treated as Driven UHPI_HD 15 8 GPIOEN8 0 UHPI_HD 7 0 GPIOEN7 0 UHPI_HCNTL0 GPIOEN1 1 UHPI_HCNTL1 GPIOEN1 1 UHPI_HAS GPIOEN2 1 21 2 4 2 General Purpose I O Programmer s Model For each HPI pin there are three bits that control this pin as general purpose I O GPIO Enable GPIO_EN GPIOEN xx Direction GPIO_DIRn DIR yy Data GPIO_DATn DIR yy For example the UHPI_HAS...

Page 960: ...e host can choose how to interact with the two HPI address registers Using the DUALHPIA bit in the HPI control register HPIC the host determines whether HPIAR and HPIAW act as a single 32 bit register single HPIA mode or as two independent 32 bit registers dual HPIA mode Note that the addresses loaded into the HPI address registers must be byte addresses and must be 32 bit word aligned with the le...

Page 961: ...hile HPIASEL 1 only HPIAR is read or updated by the host While HPIASEL 0 only HPIAW is read or updated by the host The HPIASEL bit is only meaningful in the dual HPIA mode NOTE The HPIASEL bit does not affect the HPI DMA logic Regardless of the value of HPIASEL the HPI DMA logic uses HPIAR when reading from memory and HPIAW when writing to memory A host HPID access with autoincrementing UHPI_HCNTL...

Page 962: ...n HPI resources are temporarily busy or unavailable the HPI can communicate this to the host by deasserting the HPI ready UHPI_HRDY output signal When performing an access the HPI first latches the levels on UHPI_HCNTL 1 0 UHPI_HR W and other control signals This latching can occur on the falling edge of the internal strobe signal for details see Section 21 2 6 4 After the control information is l...

Page 963: ..._HDS strobe input can be tied together and driven with a single strobe signal from the host This technique selects the HPI and provides the strobe simultaneously When using this method be aware that UHPI_HRDY is gated by UHPI_HCS as previously described It is not recommended to tie both UHPI_HDS1 and UHPI_HDS2 to static logic levels and use UHPI_HCS as a strobe 1 The UHPI_HR W signal could be driv...

Page 964: ... With the UHPI_HCNTL and UHPI_HR W Signals UHPI_HCNTL1 UHPI_HCNTL0 UHPI_HR W Cycle Type 0 0 0 HPIC write cycle 0 0 1 HPIC read cycle 0 1 0 HPID write cycle with autoincrementing 0 1 1 HPID read cycle with autoincrementing 1 0 0 HPIA write cycle 1 0 1 HPIA read cycle 1 1 0 HPID write cycle without autoincrementing 1 1 1 HPID read cycle without autoincrementing 21 2 6 6 UHPI_HHWIL Identifying the Fi...

Page 965: ... accessed regardless of whether the host performs a single or dual access For an example timing diagram of this case see Section 21 2 6 8 21 2 6 7 Performing a Multiplexed Access Figure 21 2 shows an example of signal connections for multiplexed transfers Figure 21 4 and Figure 21 5 show typical HPI signal activity when performing a read and write transfer respectively In these cases the falling e...

Page 966: ... SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Host Port Interface HPI Figure 21 5 Multiplexed Mode Host Write Cycle NOTE Depending on the type of write operation HPID without autoincrementing HPIA HPIC or HPID with autoincrementing and the state of the FIFO transitions on UHPI_HRDY may or may not occur For more informat...

Page 967: ...ates These wait states indicate to the host that read data is not yet valid read cycle or that the HPI is not ready to latch write data write cycle The number of wait states that must be inserted by the HPI is dependent upon the state of the resource that is being accessed When the HPI is not ready to complete the current cycle UHPI_HRDY is high the host can begin a new host cycle by forcing the H...

Page 968: ...lfword access is performed the same register will be accessed twice Figure 21 7 UHPI_HRDY Behavior During an HPIC or HPIA Read Cycle in the Multiplexed Mode Figure 21 8 includes an HPID read cycle without autoincrementing The host writes the memory address during the HPIA UHPI_HCNTL 1 0 10b write cycle and the host reads the data during the HPID UHPI_HCNTL 1 0 11b read cycle UHPI_HRDY goes high fo...

Page 969: ...HRDY to go high and the state of UHPI_HHWIL is ignored Firmware is not required to perform a dual access to access HPIC Figure 21 10 UHPI_HRDY Behavior During an HPIC Write Cycle in the Multiplexed Mode Figure 21 11 includes a HPID write cycle without autoincrementing The host writes the memory address while UHPI_HCNTL 1 0 10b and writes the data while UHPI_HCNTL 1 0 11b During the HPID write cycl...

Page 970: ...e 21 13 the write FIFO is not empty when the HPIA access is made UHPI_HRDY goes high twice for the first halfword access of the HPIA write cycle The first UHPI_HRDY high period is due to the nonempty FIFO The data currently in the FIFO must first be written to the memory This results in UHPI_HRDY going high immediately after the falling edge of the data strobe HSTRB The second and third UHPI_HRDY ...

Page 971: ...st in first out buffers FIFOs As shown in Figure 21 14 a read FIFO supports host read cycles and a write FIFO supports host write cycles Both read and write FIFOs are 8 words deep each word is 32 bits If the host is performing multiple reads or writes to consecutive memory addresses autoincrement HPID cycles the FIFOs are used for bursting The HPI DMA logic reads or writes a burst of four words at...

Page 972: ... an event that causes a read FIFO flush see Section 21 2 6 10 3 As mentioned the second way that read bursting may begin is with a FETCH command The host should always precede the FETCH command with the initialization of the HPIAR register or a nonautoincrement access so that the read FIFO is flushed beforehand When the host initiates a FETCH command the HPI DMA logic begins to prefetch data to ke...

Page 973: ... waiting in the FIFO the HPI holds off the host by deasserting UHPI_HRDY until at least one empty word location is available in the FIFO Because excessive time might pass between consecutive burst operations the HPI has a time out counter If there are fewer than four words in the write FIFO and the time out counter expires the HPI DMA logic empties the FIFO immediately by performing a 2 word or 3 ...

Page 974: ...cenarios cause both FIFOs to be flushed when DUALHPIA 0 The host performs a write to the HPIA register The host performs an HPID write cycle with autoincrementing while the read FIFO is not empty the read FIFO still contains data from prefetching or an HPID read cycle with autoincrementing The host performs an HPID read cycle with autoincrementing while the write FIFO is not empty there is still p...

Page 975: ...ly updated If the active cycle was a read cycle the fetched value may not be valid The HPI registers are reset to their default values see Section 21 3 The read and write FIFOs and the associated FIFO logic are reset this includes a flush of the FIFOs Host to CPU and CPU to host interrupts are cleared 21 2 8 Initialization The following steps are required to configure the HPI after a hardware rese...

Page 976: ...e 21 15 Figure 21 15 Host to CPU Interrupt State Diagram A When the DSPINT bit transitions from 0 to 1 an interrupt is generated to the CPU No new interrupt can be generated until the CPU has cleared the bit DSPINT 0 To interrupt the CPU the host must 1 Drive both UHPI_HCNTL1 and UHPI_HCNTL0 low to request a write to HPIC 2 Write 1 to the DSPINT bit in HPIC When the host sets the DSPINT bit the HP...

Page 977: ...edge the current interrupt by writing 1 to the HINT bit When the host does this the HPI clears the HINT bit HINT 0 and this drives the UHPI_HINT signal high The CPU should read HPIC and make sure HINT 0 before generating subsequent interrupts Writes of 0 have no effect A hardware reset immediately clears the HINT bit and thus clears an active CPU to host interrupt 21 2 10 EDMA Event Support The HP...

Page 978: ...urs UHPI_HRDY continues to be driven low holding off the host until the emulation suspend condition is over and the FIFOs are serviced by the HPI DMA logic allowing the host cycle to complete When the emulation suspend condition is over the appropriate requests by the HPI DMA logic are made to process any posted host writes in the write FIFO or to fill the read FIFO as necessary HPI operation then...

Page 979: ...ines the emulation mode of the HPI PWREMU_MGMT is shown in Figure 21 18 and described in Table 21 8 Figure 21 18 Power and Emulation Management Register PWREMU_MGMT 31 16 Reserved R 0 15 2 1 0 Reserved SOFT FREE R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 21 8 Power and Emulation Management Register PWREMU_MGMT Field Descriptions Bit Field Value Description 31 2 Res...

Page 980: ... 15 8 pins 0 Disable pins for GPIO Pins functions as HPI signal 1 Enable pins for GPIO 7 GPIOEN7 Enable as GPIO for UHPI_HD 7 0 pins 0 Disable pins for GPIO Pins functions as HPI signal 1 Enable pins for GPIO 6 GPIOEN6 Enable as GPIO for UHPI_HINT pin 0 Disable pin for GPIO Pin functions as HPI signal 1 Enable pin for GPIO 5 GPIOEN5 Enable as GPIO for UHPI_HRDY pin 0 Disable pin for GPIO Pin funct...

Page 981: ...n 0 UHPI_HDn pin is an input 1 UHPI_HDn pin is an output 21 3 5 GPIO Data 1 Register GPIO_DAT1 The GPIO data 1 register GPIO_DAT1 determines the value driven on the corresponding UHPI_HDn pin if the pin is configured as an output GPIO_DIR1 HDn 1 Writes do not affect pins not configured as GPIO outputs The bits in GPIO_DAT1 are set or cleared by writing directly to this register A read of GPIO_DAT1...

Page 982: ...ol for UHPI_HRDY pin 0 UHPI_HRDY pin is an input 1 UHPI_HRDY pin is an output 8 HINTZ Direction control for UHPI_HINT pin 0 UHPI_HINT pin is an input 1 UHPI_HINT pin is an output 7 HCNTL0 Direction control for UHPI_HCNTL0 pin 0 UHPI_HCNTL0 pin is an input 1 UHPI_HCNTL0 pin is an output 6 HCNTL1 Direction control for UHPI_HCNTL1 pin 0 UHPI_HCNTL1 pin is an input 1 UHPI_HCNTL1 pin is an output 5 HHW...

Page 983: ...GPIO Data 2 Register GPIO_DAT2 31 16 Reserved R 0 15 10 9 8 Reserved HRDY HINTZ R 0 R W 0 R W 0 7 6 5 4 3 2 1 0 HCNTL0 HCNTL1 HHWIL HRW HDS2Z HDS1Z HCSZ HASZ R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 21 13 GPIO Data 2 Register GPIO_DAT2 Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 HRDY 0 1 Data read fro...

Page 984: ...errupt to the host Figure 21 24 Host Port Interface Control Register HPIC Host Access Permissions 31 16 Reserved R 0 15 12 11 10 9 8 Reserved HPIASEL Reserved DUALHPIA HWOBSTAT R 0 R W 0 R W 0 R W 0 R 0 7 6 5 4 3 2 1 0 HPIRST Reserved FETCH Reserved HINT DSPINT HWOB R 1 R 2h R W 0 R 1 R W 1 Host R W1C 0 CPU R W 0 R W 0 LEGEND R W Read Write R Read only W1C Write 1 to clear writing 0 has no effect ...

Page 985: ...OB bit is logic 1 7 HPIRST HPI reset Some HPI logic is held in reset when the HPIRST bit is set The HPIRST bit must be cleared to 0 before data transactions can take place 0 HPI is released from reset 1 HPI is held in reset 6 5 Reserved 2h Reserved 4 FETCH Host data fetch request bit Only the host may write to FETCH When a host writes a 1 to FETCH a request is posted in the HPI to prefetch data in...

Page 986: ...nly n value after reset Table 21 15 Host Port Interface Write Address Register HPIAW Field Descriptions Bit Field Value Description 31 0 HPIAW 0 FFFF FFFFh Host port interface write address 21 3 10 Host Port Interface Read Address Register HPIAR The HPI contains two 32 bit address registers one for read operations HPIAR and one for write operations HPIAW The host port interface read address regist...

Page 987: ...Chapter 22 SPRUH82C April 2013 Revised September 2016 Inter Integrated Circuit I2C Module This chapter describes the inter integrated circuit I2C peripheral The scope of this chapter assumes that you are familiar with the Philips Semiconductors Inter IC bus I2C bus specification version 2 1 Topic Page 22 1 Introduction 988 22 2 Architecture 990 22 3 Registers 1002 ...

Page 988: ...mpliance with the Philips Semiconductors I2C bus specification version 2 1 Support for byte format transfer 7 bit and 10 bit addressing modes General call START byte mode Support for multiple master transmitters and slave receivers mode Support for multiple slave transmitters and master receivers mode Combined master transmit receive and receive transmit mode I2C data transfer rate of from 10 kbps...

Page 989: ...16 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Inter Integrated Circuit I2C Module 22 1 3 Functional Block Diagram A block diagram of the I2C peripheral is shown in Figure 24 1 Refer to Section 22 2 for detailed information about the architecture of the I2C peripheral Figure 22 1 I2C Peripheral Block Diagram 22 1 4 Industry Standard s Compliance Statement The I...

Page 990: ... in the EDMA controller can be synchronized to data reception and data transmission in the I2C peripheral Figure 24 1 shows the four registers used for transmission and reception The CPU or the EDMA controller writes data for transmission to ICDXR and reads received data from ICDRR When the I2C peripheral is configured as a transmitter data written to ICDXR is copied to ICXSR and shifted out on th...

Page 991: ...clock The prescaled module clock must be operated within the range of 6 7 to 13 3 MHz The I2C clock dividers divide down the high ICCH bit in ICCLKH and low portions ICCL bit in ICCLKL of the prescaled module clock signal to produce the I2C serial clock which appears on the I2Cx_SCL pin when the I2C module is configured to be a master on the I2C bus The prescaler IPSC bit in ICPSC must only be ini...

Page 992: ...high period If a device pulls down the clock line for a longer time the result is that all clock generators must enter the wait state This way a slave slows down a fast master and the slow device creates enough time to store a received data word or to prepare a data word that you are going to transmit Figure 22 4 Synchronization of Two I2C Clock Generators During Arbitration 22 2 4 Signal Descript...

Page 993: ...ition on the I2Cx_SDA line while I2Cx_SCL is high A master drives this condition to indicate the start of a data transfer The STOP condition is defined as a low to high transition on the I2Cx_SDA line while I2Cx_SCL is high A master drives this condition to indicate the end of a data transfer The I2C bus is considered busy after a START condition and before a subsequent STOP condition The bus busy...

Page 994: ... data values being transferred The I2C peripheral supports the following data formats 7 bit addressing mode 10 bit addressing mode Free data format mode Figure 22 7 I2C Peripheral Data Transfer 22 2 6 1 7 Bit Addressing Format In the 7 bit addressing format Figure 22 8 the first byte after a START condition S consists of a 7 bit slave address followed by a R W bit The R W bit determines the direct...

Page 995: ...g to Slave Receiver FDF 0 XA 1 in ICMDR n The number of data bits from 1 to 8 specified by the bit count BC field of ICMDR 22 2 6 3 Free Data Format In the free data format Figure 22 10 the first bits after a START condition S are a data word An ACK bit is inserted after each data word The data word can be from 1 to 8 bits depending on the bit count BC bits of ICMDR No address or data direction bi...

Page 996: ... master This mode can only be entered from the slave receiver mode the I2C peripheral must first receive a command from the master When you are using any of the 7 bit 10 bit addressing formats the I2C peripheral enters its slave transmitter mode if the slave address is the same as its own address in ICOAR and the master has transmitted R W 1 As a slave transmitter the I2C peripheral then shifts th...

Page 997: ...n Basic Optional Slave receiver mode Disable data transfers STT 0 in ICSTR Allow an overrun condition RSFULL 1 in ICSTR Reset the peripheral IRS 0 in ICMDR Set the NACKMOD bit of ICMDR before the rising edge of the last data bit you intend to receive Master receiver mode AND Repeat mode RM 1 in ICMDR Generate a STOP condition STOP 1 in ICMDR Reset the peripheral IRS 0 in ICMDR Set the NACKMOD bit ...

Page 998: ...master transmitter that drives I2Cx_SDA low The arbitration procedure gives priority to the device that transmits the serial data stream with the lowest binary value Should two or more devices send identical first bytes arbitration continues on the subsequent bytes If the I2C peripheral is the losing master it switches to the slave receiver mode sets the arbitration lost AL flag and generates the ...

Page 999: ...e set to their default values and the I2C peripheral remains disabled until the I2C reset IRS bit in the I2C mode register ICMDR is changed to 1 NOTE The IRS bit must be cleared to 0 while you configure reconfigure the I2C peripheral Forcing IRS to 0 can be used to save power and to clear error conditions 22 2 11 Initialization Proper I2C initialization is required prior to starting communication ...

Page 1000: ...y is between 6 7 and 13 3 MHz 6 Configure I2C master clock frequency Configure the low time divider value ICCLKL Configure the high time divider value ICCLKH 7 Make sure the interrupt status register ICSTR is cleared Read ICSTR and write it back write 1 to clear ICSTR ICSTR Read ICIVR until it is 0 8 Take I2C controller out of reset enable I2C controller set IRS bit 1 in ICMDR 9 Wait until bus bus...

Page 1001: ...p Condition Detection interrupt SCD Generated when a STOP condition has been detected Address as Slave interrupt AAS Generated when the I2C has recognized its own slave address or an address of all 8 zeros 22 2 13 DMA Events Generated by the I2C Peripheral For the EDMA controller to handle transmit and receive data the I2C peripheral generates the following two EDMA events Activity in EDMA channel...

Page 1002: ...ivider Register Section 22 3 4 10h ICCLKH I2C Clock High Time Divider Register Section 22 3 4 14h ICCNT I2C Data Count Register Section 22 3 5 18h ICDRR I2C Data Receive Register Section 22 3 6 1Ch ICSAR I2C Slave Address Register Section 22 3 7 20h ICDXR I2C Data Transmit Register Section 22 3 8 24h ICMDR I2C Mode Register Section 22 3 9 28h ICIVR I2C Interrupt Vector Register Section 22 3 10 2Ch...

Page 1003: ...n in Figure 22 13 and described in Table 22 5 Figure 22 13 I2C Own Address Register ICOAR 31 16 Reserved R 0 15 10 9 0 Reserved OADDR R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 5 I2C Own Address Register ICOAR Field Descriptions Bit Field Value Description 31 10 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effec...

Page 1004: ...cription 31 7 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 6 AAS Address as slave interrupt enable bit 0 Interrupt request is disabled 1 Interrupt request is enabled 5 SCD Stop condition detected interrupt enable bit 0 Interrupt request is disabled 1 Interrupt request is enabled 4 ICXRDY Transmit data ready interrupt enable bit 0 Inte...

Page 1005: ...affected is when the NACK mode is used see the description for NACKMOD in Section 22 3 9 0 NACK is not sent NACKSNT is cleared by one of the following events It is manually cleared To clear this bit write a 1 to it The I2C is reset either when 0 is written to the IRS bit of ICMDR or when the processor is reset 1 NACK is sent A no acknowledge bit was sent during the acknowledge cycle on the I2C bus...

Page 1006: ...en detected 4 ICXRDY Transmit data ready interrupt flag bit ICXRDY indicates that the data transmit register ICDXR is ready to accept new data because the previous data has been copied from ICDXR to the transmit shift register ICXSR The CPU can poll ICXRDY or use the XRDY interrupt request 0 ICDXR is not ready ICXRDY is cleared by one of the following events Data is written to ICDXR ICXRDY is manu...

Page 1007: ...reset 1 NACK bit is received The hardware detects that a no acknowledge NACK bit has been received Note While the I2C performs a general call transfer NACK is 1 even if one or more slaves send acknowledgment 0 AL Arbitration lost interrupt flag bit only applicable when the I2C is a master transmitter AL primarily indicates when the I2C has lost an arbitration contest with another master transmitte...

Page 1008: ... ICCLKL Field Descriptions Bit Field Value Description 31 16 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 15 0 ICCL 0 FFFFh Clock low time divide down value of 1 65536 The period of the module clock is multiplied by ICCL d to produce the low time duration of the I2C serial on the I2Cx_SCL pin 22 3 4 2 I2C Clock High Time Divider Regis...

Page 1009: ...ransfer with a STOP condition when the countdown is complete that is when the last data word has been transferred ICCNT is shown in Figure 22 18 and described in Table 22 10 Figure 22 18 I2C Data Count Register ICCNT 31 16 Reserved R 0 15 0 ICDC R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 10 I2C Data Count Register ICCNT Field Descriptions Bit Field Value Description 31 16...

Page 1010: ... is selected by the bit count bits BC of ICMDR The I2C receive shift register ICRSR shifts in the received data from the I2Cx_SDA pin Once data is complete the I2C copies the contents of ICRSR into ICDRR The CPU and the EDMA controller cannot access ICRSR ICDRR is shown in Figure 22 19 and described in Table 22 11 Figure 22 19 I2C Data Receive Register ICDRR 31 16 Reserved R 0 15 8 7 0 Reserved D ...

Page 1011: ... ICSAR are used bits 9 7 are ignored ICSAR is shown in Figure 22 20 and described in Table 22 12 Figure 22 20 I2C Slave Address Register ICSAR 31 16 Reserved R 0 15 10 9 0 Reserved SADDR R 0 R W 3FFh LEGEND R W Read Write R Read only n value after reset Table 22 12 I2C Slave Address Register ICSAR Field Descriptions Bit Field Value Description 31 10 Reserved 0 These reserved bit locations are alwa...

Page 1012: ... the bit count bits BC of ICMDR Once data is written to ICDXR the I2C copies the contents of ICDXR into the I2C transmit shift register ICXSR The ICXSR shifts out the transmit data from the I2Cx_SDA pin The CPU and the EDMA controller cannot access ICXSR ICDXR is shown in Figure 22 21 and described in Table 22 13 Figure 22 21 I2C Data Transmit Register ICDXR 31 16 Reserved R 0 15 8 7 0 Reserved D ...

Page 1013: ... NACKMOD before the rising edge of the last data bit 14 FREE This emulation mode bit is used to determine the state of the I2C when a breakpoint is encountered in the high level language debugger 0 When I2C is master If I2Cx_SCL is low when the breakpoint occurs the I2C stops immediately and keeps driving I2Cx_SCL low whether the I2C is the transmitter or the receiver If I2Cx_SCL is high the I2C w...

Page 1014: ...P bit is manually set to 1 regardless of the value in ICCNT 6 DLB Digital loopback mode bit only applicable when the I2C is a master transmitter This bit disables or enables the digital loopback mode of the I2C The effects of this bit are shown in Figure 22 23 Note that DLB mode in the free data format mode DLB 1 and FDF 1 is not supported 0 Digital loopback mode is disabled 1 Digital loopback mod...

Page 1015: ...ption 0 0 0 None No activity 0 0 1 P STOP condition 0 1 0 S A D n D START condition slave address n data words n value in ICCNT 0 1 1 S A D n D P START condition slave address n data words STOP condition n value in ICCNT 1 0 0 None No activity 1 0 1 P STOP condition 1 1 0 S A D D D Repeat mode transfer START condition slave address continuous data transfers until STOP condition or next START condi...

Page 1016: ...or EDMA From CPU or EDMA From CPU or EDMA From CPU or EDMA SCLn SDAn I2C peripheral DLB DLB Registers www ti com 1016 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Inter Integrated Circuit I2C Module Figure 22 23 Block Diagram Showing the Effects of the Digital Loopback Mode DLB Bit ...

Page 1017: ...n in Figure 22 24 and described in Table 22 17 Figure 22 24 I2C Interrupt Vector Register ICIVR 31 16 Reserved R 0 15 2 0 Reserved INTCODE R 0 R 0 LEGEND R Read only n value after reset Table 22 17 I2C Interrupt Vector Register ICIVR Field Descriptions Bit Field Value Description 31 3 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 2 0 I...

Page 1018: ...scriptions Bit Field Value Description 31 2 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 1 IGNACK Ignore NACK mode 0 Master transmitter operates normally that is it discontinues the data transfer and sets the ARDY and NACK bits in ICSTR when receiving a NACK from the slave 1 Master transmitter ignores a NACK from the slave 0 BCM Backw...

Page 1019: ...Changing the IPSC value while IRS 1 has no effect ICPSC is shown in Figure 22 26 and described in Table 22 19 Figure 22 26 I2C Prescaler Register ICPSC 31 16 Reserved R 0 15 8 7 0 Reserved IPSC R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 19 I2C Prescaler Register ICPSC Field Descriptions Bit Field Value Description 31 8 Reserved 0 These reserved bit locations are alway...

Page 1020: ...h LEGEND R Read only n value after reset Table 22 20 I2C Revision Identification Register 1 REVID1 Field Descriptions Bit Field Value Description 31 0 REVID1 4415h Peripheral Identification Number 22 3 14 I2C Revision Identification Register REVID2 The I2C revision identification register REVID2 contains identification data for the peripheral REVID2 is shown in Figure 22 28 and described in Table ...

Page 1021: ... R 0 15 1 0 Reserved TXDMAEN RXDMAEN R 0 R W 1 R W 1 LEGEND R W Read Write R Read only n value after reset Table 22 22 I2C DMA Control Register ICDMAC Field Descriptions Bit Field Value Description 31 2 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 1 TXDMAEN Transmit DMA enable This bit controls the transmit DMA event pin to the system...

Page 1022: ...C Pin Function Register ICPFUNC Field Descriptions Bit Field Value Description 31 1 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 0 PFUNC0 Controls the function of the I2Cx_SCL and I2Cx_SDA pins 0 Pins function as I2Cx_SCL and I2Cx_SDA 1 Pins function as GPIO Note No hardware protection is required to disable the I2C function when the ...

Page 1023: ...egister ICPDIR 31 16 Reserved R 0 15 2 1 0 Reserved PDIR1 PDIR0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 24 I2C Pin Direction Register ICPDIR Field Descriptions Bit Field Value Description 31 2 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 1 PDIR1 Controls the direction of the I2Cx_SDA pin when con...

Page 1024: ...In Register ICPDIN 31 16 Reserved R 0 15 2 1 0 Reserved PDIN1 PDIN0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 25 I2C Pin Data In Register ICPDIN Field Descriptions Bit Field Value Description 31 2 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 1 PDIN1 Indicates the logic level present on the I2Cx_SDA...

Page 1025: ...PDOUT 31 16 Reserved R 0 15 2 1 0 Reserved PDOUT1 PDOUT0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 26 I2C Pin Data Out Register ICPDOUT Field Descriptions Bit Field Value Description 31 2 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 1 PDOUT1 Controls the level driven on the I2Cx_SDA pin when config...

Page 1026: ...R 0 15 2 1 0 Reserved PDSET1 PDSET0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 27 I2C Pin Data Set Register ICPDSET Field Descriptions Bit Field Value Description 31 2 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 1 PDSET1 Used to set the PDOUT1 bit in the I2C pin data out register ICPDOUT that corre...

Page 1027: ...0 15 2 1 0 Reserved PDCLR1 PDCLR0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 22 28 I2C Pin Data Clear Register ICPDCLR Field Descriptions Bit Field Value Description 31 2 Reserved 0 These reserved bit locations are always read as zeros A value written to this field has no effect 1 PDCLR1 Used to clear the PDOUT1 bit in the I2C pin data out register ICPDOUT that cor...

Page 1028: ... LCDC Chapter 23 SPRUH82C April 2013 Revised September 2016 Liquid Crystal Display Controller LCDC The liquid crystal display controller LCDC is capable of supporting an asynchronous memory mapped LCD interface and a synchronous raster type LCD interface This chapter describes the LCDC Topic Page 23 1 Introduction 1029 23 2 Architecture 1030 23 3 Registers 1046 ...

Page 1029: ...orts a wide variety of monochrome and full color display types and sizes by use of programmable timing controls a built in palette and a gray scale serializer Graphics data is processed and stored in frame buffers A frame buffer is a contiguous memory block in the system A built in DMA engine supplies the graphics data to the Raster engine which in turn outputs to the external LCD device The LIDD ...

Page 1030: ...sed for each pixel In some documentation this is also referred to as color depth RGB Red Green Blue 23 2 Architecture 23 2 1 Clocking This section details the various clocks and signals Figure 23 2 shows input and output LCD controller clocks Figure 23 2 Input and Output Clocks 23 2 1 1 Pixel Clock The pixel clock LCD_PCLK frequency is derived from LCD_CLK the reference clock to this LCD module se...

Page 1031: ...Vertical Clock LCD_VSYNC LCD_VSYNC toggles after all lines in a frame have been transmitted to the LCD and a programmable number of line clock cycles has elapsed both at the beginning and end of each frame The RASTER_TIMING_1 register fully defines the behavior of this signal LCD_VSYNC can be programmed to be synchronized with the rising or falling edge of LCD_PCLK The configuration field is bits ...

Page 1032: ...passive mode the pixel clock transitions only when valid data is available on the data lines In active mode the pixel clock transitions continuously and the ac bias pin is used as an output enable to signal when data is available on the LCD pin LIDD character not used LIDD graphics 6800 mode enable strobe 8080 mode read strobe LCD_AC_ENB_CS OUT Raster controller ac bias used to signal the LCD to s...

Page 1033: ... buffer is used these two registers will not be used LCDDMA_FB1_CEILING In addition the LIDD_CTRL register for LIDD Controller or the RASTER_CTRL register for Raster Controller should also be configured appropriately along with all the timing registers To enable DMA transfers the LIDD_DMA_EN bit in the LIDD_CTRL register or the LCDEN bit in the RASTER_CTRL register should be written with 1 NOTE If...

Page 1034: ...ounter reloads the value in field ACB_I but does not start to decrement until the ABC bit is cleared by writing 0 to this bit 5 Frame transfer completed When one frame of data is transferred completely the DONE bit in the LCD_STAT register is set This bit is cleared by disabling the Raster Controller i e clearing the LCDEN bit in the RASTER_CTRL register Note that the EOF0 and EOF1 bits in the LCD...

Page 1035: ...acter Display HD44780 Type 8 100 LCD_D 7 0 DATA 7 0 Data Bus length defined by Instruction LCD_HSYNC R W Read Write LCD_VSYNC RS Register Select RS 0 command RS 1 data LCD_AC_ENB_CS E or E0 Enable Strobe first display LCD_MCLK E1 Enable Strobe second display optional Micro Interface Graphic Display 6800 Family Up to 16 001 LCD_D 15 0 DATA 15 0 Data Bus 16 bits always available LCD_PCLK E Enable Cl...

Page 1036: ...gnals when this mode is active Table 23 4 Operation Modes Supported by Raster Controller Interface Data Bus Width Register Bits RASTER_CTRL 9 7 1 Signal Name Description Passive STN Mono 4 bit 4 001 LCD_D 3 0 Data bus LCD_PCLK Pixel clock LCD_HSYNC Horizontal clock Line Clock LCD_VSYNC Vertical clock Frame Clock LCD_AC_ENB_CS AC Bias LCD_MCLK Not used Passive STN Mono 8 bit 8 101 LCD_D 7 0 Data bu...

Page 1037: ... passive STN versus active TFT various BPP size Figure 23 3 shows that The gray scaler serializer and output FIFO blocks are bypassed in active TFT modes The palette is bypassed in both 12 and 16 BPP modes Figure 23 3 Logical Data Path for Raster Controller In summary The display image is stored in frame buffers The built in DMA engine constantly transfers the data stored in the frame buffers to t...

Page 1038: ...ytes are still considered a palette The first entry should be 4000h bit 14 is 1 while the remaining entries must be filled with 0 For details see Table 23 5 Each entry in a palette occupies 2 bytes As a result 8 BPP mode palette has 256 color entries while the other palettes have up to 16 color entries 4 BPP mode uses up the all the 16 entries in a palette 1 BPP mode uses the first 2 entries in a ...

Page 1039: ...39 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Liquid Crystal Display Controller LCDC The equations shown in Table 23 6 are used to calculate the total frame buffer size in bytes based on varying pixel size encoding and screen sizes Figure 23 5 and Figure 23 6 show more detail of the palette entry organization Table 23...

Page 1040: ... Base FEh Unused BPP A Architecture www ti com 1040 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Liquid Crystal Display Controller LCDC Figure 23 6 256 Entry Palette Buffer Format 8 BPP Bits 12 13 and 14 of the first palette entry select the number of bits per pixel to be used in the following frame and thus the number ...

Page 1041: ...3 14 12 bits pixel Bit Pixel 0 Pixel 1 Bit 15 0 Base 2 Unused www ti com Architecture 1041 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Liquid Crystal Display Controller LCDC Figure 23 8 12 BPP Data Memory Organization Little Endian Unused 15 12 bits are filled with zeroes in TFT mode Figure 23 9 8 BPP Data Memory Organ...

Page 1042: ...e supported The PLM field in RASTER_CTRL affects the palette loading If PLM is 00b palette plus data mode or 01b palette only mode the palette is loaded by the DMA engine at the very beginning which is followed by the loading of pixel data If PLM is 10b data only mode the palette is not loaded Instead the DMA engine loads the pixel data immediately 23 2 5 4 Gray Scaler Serializer 23 2 5 4 1 Passiv...

Page 1043: ...0 Active Mode TFT_STN 1 Monochrome MONO_COLOR 1 Color MONO_COLOR 0 Color Only MONO_COLOR 0 1 2 palette entries to select within 15 grayscales 2 palette entries to select within 3375 possible colors 2 palette entries to select within 4096 possible colors 2 4 palette entries to select within 15 grayscales 4 palette entries to select within 3375 possible colors 4 palette entries to select within 4096...

Page 1044: ...re www ti com 1044 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Liquid Crystal Display Controller LCDC 23 2 5 5 Output Format 23 2 5 5 1 Passive STN Mode As shown in Figure 23 3 the pixel data stored in frame buffers go through palette if applicable and gray scaler serializer before reaching the Output FIFO As a result ...

Page 1045: ...e first or last few lines of the LCD panel see Figure 23 14 This is mainly used for power saving This is supported by the Raster Controller via its subpanel feature The RASTER_SUBPANEL register fully defines its behavior that is the following parameters are defined Whether the first or last few lines will be refreshed A line number which is the last or first line to be refreshed The pixel data to ...

Page 1046: ...Write Register Section 23 3 7 28h RASTER_CTRL LCD Raster Control Register Section 23 3 8 2Ch RASTER_TIMING_0 LCD Raster Timing 0 Register Section 23 3 9 30h RASTER_TIMING_1 LCD Raster Timing 1 Register Section 23 3 10 34h RASTER_TIMING_2 LCD Raster Timing 2 Register Section 23 3 11 38h RASTER_SUBPANEL LCD Raster Subpanel Display Register Section 23 3 12 40h LCDDMA_CTRL LCD DMA Control Register Sec...

Page 1047: ...CD Controller in Raster mode The 8 bit clock divider CLKDIV field is used to select the frequency of the pixel clock CLKDIV can generate a range of pixel clock frequencies from LCD_CLK 2 to LCD_CLK 255 The pixel clock frequency must be adjusted to meet the required screen refresh rate The refresh rate depends on The number of pixels for the target display Whether monochrome or color mode is select...

Page 1048: ...limitations shown in Table 23 12 If CLKDIV equals 0 or 1 the effect is undefined Dividing the pixel clock frequency by an odd number distorts the duty cycle Table 23 12 Pixel Clock Frequency Programming Limitations Type of Screen Output In Bits Minimum Pixel Clock Divider TFT 1 2 4 8 BPP 12 1 pixel 2 TFT 16 BPP 16 1 pixel 2 STN monochrome 4 output lines per panel 4 4 pixel 4 STN monochrome 8 outpu...

Page 1049: ...riptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 EOF1 End of Frame 1 0 no end of frame 1 detected 1 end of frame 1 detected 8 EOF0 End of Frame 0 0 no end of frame 0 detected 1 end of frame 0 detected 7 Reserved 0 Reserved 6 PL Loaded Palette 0 The palette is not loaded 1 The palette is loaded 5 FUF FIFO Underflow Status 0 FIFO has not underrun 1 LCD dither logic not supplying data...

Page 1050: ...D FIFO threshold Increase priority for LCD controller DMA Increase burst size setting for LCD controller DMA Run the DDR2 mobile DDR mDDR memory controller if used at maximum clock speed This bit is cleared by disabling the LCD controller RASTER_EN 0 This also resets the input FIFO in the DMA controller SYNC 1 when a frame synchronization lost occurred SYNC 0 as long as no frame synchronization er...

Page 1051: ... is a read only bit that is set after the LCD finished loading the palette into memory PL 1 when the palette is loaded PL 0 as long as the palette is not loaded In data only PL 10 and palette plus data PL 00 modes write 0 to clear the interrupt However in the palette only PL 01 mode LCD must be turned off in order to reset clear the interrupt But in this particular mode make sure not to turn off t...

Page 1052: ...ved 0 Reserved 10 DONE_INT_EN LIDD Frame Done Interrupt Enable 0 Disable LIDD Frame Done interrupt 1 Enable LIDD Frame Done interrupt seen on LCD Status Reg bit 0 9 DMA_CS0_CS1 CS0 CS1 Select for LIDD DMA writes 0 DMA writes to LIDD CS0 1 DMA writes to LIDD CS1 8 LIDD_DMA_EN LIDD DMA Enable 0 Deactivate DMA control of LIDD interface DMA control is released upon completion of transfer of the curren...

Page 1053: ...Description 3 RSPOL Register Select RS Polarity Control 0 Do Not Invert RS 1 Invert RS RS is active low by default 2 0 LIDD_MODE_SEL 0 7h LIDD Mode Select Selects type of LCD interface for the LIDD to drive LIDD_MODE_SEL defines the function of LCD external pins as follows Pin 001b 011b 100b LCD_PCLK E RD N A LCD_HSYNC R W WR R W LCD_VSYNC RS RS RS LCD_AC_ENB_CS CS0 CS0 E0 LCD_MCLK CS1 CS1 E1 0 Sy...

Page 1054: ...ad Output Enable ALE Direction bit and Chip Select 0 have been set up before the Write Strobe is asserted when performing a write access 26 21 W_STROBE 1 3Fh Write Strobe Duration cycles Field value defines number of MCLK cycles that the Write Strobe is held active when performing a write access 20 17 W_HOLD 1 Fh Write Strobe Hold cycles Field value defines number of MCLK cycles that the Data Bus ...

Page 1055: ... ADR_INDX field of this register Similarly writing to LIDD_CS1_ADDR asserts CS1 and Address Latch Enable which loads the ADR_INDX field of this register into the address generator of the peripheral device Likewise reading from LIDD_CS1_ADDR asserts CS1 and Address Latch Enable which loads status information from the peripheral device into the ADR_INDX field of this register The LIDD_CSn_ADDR is sh...

Page 1056: ...ral device into the DATA field of this register Similarly writing to LIDD_CS1_DATA asserts CS1 and deasserts Address Latch Enable which loads the DATA field of this register into the peripheral device Likewise reading from LIDD_CS1_DATA asserts CS1 and deasserts Address Latch Enable which loads data from the peripheral device into the DATA field of this register The LIDD_CSn_DATA is shown in Figur...

Page 1057: ...2 bits of pixel data is processed and output i e X X X X R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 where X is ignored by the Raster Controller 1 Enabled Pixel data in the frame buffer is 16 bit but only 12 of the bits are processed and output i e R3 R2 R1 R0 X G3 G2 G1 G0 X X B3 B2 B1 B0 X where X is ignored by the Raster Controller The data patterns above refer to frame buffer bits not output bits 23 T...

Page 1058: ...word 7 TFT_STN TFT or STN Mode 0 Passive STN display operation enabled 1 Active TFT display operation enabled 6 FUF_EN FIFO Underflow Interrupt Enable 0 Disable the FIFO Underflow interrupt 1 Enable the FIFO Underflow interrupt 5 SL_EN Sync Lost Interrupt Enable 0 Disable the Sync Lost interrupt 1 Enable the Sync Lost interrupt 4 PL_EN Palette Loaded Interrupt Enable 0 Disable the Palette Loaded i...

Page 1059: ...pt request If the LCD controller is disabled the signals on pixel data 15 0 pins are set to 0 and the pixel clock frame clock vertical clock line clock horizontal clock and ac bias signals are set to their inactive state This can be 0 or 1 depending on the inversions programmed in the LCD Raster Timing 2 register 23 3 8 2 LCD Monochrome MONO_COLOR The color monochrome select LcdBW bit is used to d...

Page 1060: ...isplay Controller LCDC 23 3 8 3 TFT_STN TFT_STN The TFT_STN TFT_STN bit selects whether the LCD controller operates in passive STN or active TFT display control mode When TFT_STN 0 passive or STN mode is selected LCD data flows from the frame buffer memory via the LCD dedicated DMA channel to the palette the palette is bypassed for the 12 and 16 BPP modes to the dithering logic and the output FIFO...

Page 1061: ...ic only supports 4 bits to encode each color component R G B that limits the pixel encoding size in passive mode Increasing the size of the pixel representation allows a total of 64K colors to be addressed using an off chip palette in conjunction with the LCD controller 23 3 8 4 Mono 8 Bit Mode MONO8B NOTE MONO8B does not affect any of the color modes or TFT The mono 8 bit mode MONO8B bit selects ...

Page 1062: ...s the palette was previously loaded There is no need to keep loading the palette if it is not changing As a matter of fact in data only mode the BPP is fixed and can not change on the fly since the palette is not loaded at every frame PLM 3h is reserved 23 3 8 7 TFT Alternate Signal Mapping TFT_ALT_MAP This bit is relevant only if TFT_ALT_MAP 1 This bit field controls how the TFT pixel data is out...

Page 1063: ...s as shown in Figure 23 27 Figure 23 27 12 Bit STN Data in Frame Buffer Pins 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data Data Ignored R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 If STN_565 1 the 16 bit STN mode is selected The only difference from the 12 BPP mode is how the pixel data is organized in the frame buffer and which bits are sent to the dither logic The 16 bit STN mode appears in frame buffer me...

Page 1064: ...P 0 FFh Horizontal Front Porch Encoded value HFP 1 is used to specify number of LCD_PCLKs to add to the end of a line transmission before line clock is asserted program to value minus one Note that pixel clock is held in its inactive state during the end of line wait period in STN mode while it is active in TFT mode 15 10 HSW 0 3Fh Horizontal Sync Pulse Width Encoded value HSW 1 is used to specify...

Page 1065: ...orch HFP NOTE The pixel clock does not transition during these dummy pixel clock cycles in passive display mode but it transitions continuously in active display mode The 8 bit horizontal front porch HFP field is used to specify the number of dummy pixel clocks to insert at the end of each line or row of pixels before pulsing the line clock or LCD_HSYNC pin Once a complete line of pixels is transm...

Page 1066: ...ing the insertion of the extra line clock periods 23 16 VFP 0 FFh Vertical Front Porch Encoded value VFP used to specify number of line clock LCD_HSYNC periods to add to the end of each frame Note that the line clock transitions during the insertion of the extra line clock periods 15 10 VSW 0 3Fh Vertical Synchronization Pulse Width In TFT mode encoded value VSW 1 defines the number of line clock ...

Page 1067: ...ulse width ranging from 1 64 line clock periods program to value required minus 1 see Figure 23 32 The following frame starts after LCD_VSYNC is deasserted and a programmable number of line clock delays VBP has elapsed Figure 23 32 Vertical Synchronization Pulse Width VSW Active Mode 23 3 10 2 2 Passive Mode NOTE The pixel clock does not transition during the whole dummy line clock periods that ar...

Page 1068: ...ember that VSW must be programmed to value required minus 1 The 8 bit vertical front porch VFP field is used to specify the number of line clocks to insert at the end of each frame Once a complete frame of pixels is transmitted to the LCD display the value in VFP is used to count the number of line clock periods to wait After the count has elapsed the LCD_VSYNC signal is pulsed in active mode or e...

Page 1069: ...tte to be completely filled via the DMA and allows a sufficient number of encoded pixel values to be input from the frame buffer processed by the dither logic then placed in the output FIFO ready to be output to the LCD data lines The 8 bit vertical back porch VBP field is used to specify the number of line clocks or LCD_HSYNC to insert at the beginning of each frame The VBP count starts just afte...

Page 1070: ... to activate and deactivate LCD_HSYNC and LCD_VSYNC 24 SYNC_EDGE Horizontal and Vertical Sync Edge The activation and deactivation of LCD_HSYNC and LCD_VSYNC will occur on the defined LCD_PCLK edge 0 Rising edge 1 Falling edge SYNC_CTRL must be active in order to use this bit 23 BIAS Invert AC Bias 0 LCD_AC_ENB_CS is an active high pulse 1 LCD_AC_ENB_CS is an active low pulse In STN mode the activ...

Page 1071: ...d minus 1 This line is used by the LCD display to periodically reverse the polarity of the power supplied to the screen to eliminate DC offset 23 3 11 2 AC Bias Line Transitions Per Interrupt ACB_I The 4 bit ac bias line transitions per interrupt ACB_I field is used to specify the number of line transitions to count before setting the ac bias count status ABC bit in the LCD controller status regis...

Page 1072: ...0 the ac bias pin is active high 23 3 11 7 Horizontal and Vertical Sync Edge SYNC_EDGE This bit determines whether the HSYNC VSYNC is driven on the rising or falling edge of the pixel clock see the SYNC_CTRL bit SYNC_CTRL must be turned on first By default the LCD_HSYNC and LCD_VSYNC signals are driven on the falling edge of the pixel clock and the pixel data is driven on the rising edge of pixel ...

Page 1073: ...ck SYNC_CTRL 1 LCD_HSYNC and LCD_VSYNC signals are driven according to the SYNC_EDGE bit SYNC_EDGE 0 LCD_HSYNC and LCD_VSYNC signals are driven on the falling edge of the pixel clock Figure 23 37 SYNC_CTRL 1 SYNC_EDGE 0 and IPC 1 23 3 11 8 Horizontal and Vertical Sync Control SYNC_CTRL This bit enables disables the possibility to make HSYNC and VSYNC programmable When SYNC_CTRL 1 HSYNC and VSYNC a...

Page 1074: ...R Read only n value after reset Table 23 23 LCD Raster Subpanel Display Register RASTER_SUBPANEL Field Descriptions Bit Field Value Description 31 SPEN Subpanel Enable 0 Disabled 1 Enabled 30 Reserved 0 Reserved 29 HOLS High or Low Signal The field indicates the position of subpanel compared to the LPPT value 0 Low below 1 High above 28 26 Reserved 0 Reserved 25 16 LPPT 0 3FFh Line Per Panel Thres...

Page 1075: ... begins to be displayed The rest of the screen is filled with DPD value Figure 23 39 Subpanel Display SPEN 1 HOLS 1 When HOLS 0 the beginning of the screen is filled with DPD value until the LPPT excluded From the LPPT line number the rest of the screen below LPPT displays the image from system memory Figure 23 40 Subpanel Display SPEN 1 HOLS 0 The bottom of the panel is line 0 and top line of the...

Page 1076: ...ds 1 dword is 4 bytes specified by TH_FIFO_READY have been loaded by the DMA from the frame buffer to the input FIFO 0 8 dwords 1h 16 dwords 2h 32 dwords 3h 64 dwords 4h 128 dwords 5h 256 dwords 6h 512 dwords 7h Reserved 7 Reserved 0 Reserved 6 4 BURST_SIZE 0 7h Burst Size setting for DMA transfers all DMA transfers are 32 bits wide 0 Burst size of 1 1h Burst size of 2 2h Burst size of 4 3h Burst ...

Page 1077: ...ddress Register LCDDMA_FBn_BASE Field Descriptions Bit Field Value Description 31 0 FBn_BASE 0 FFFF FFFFh Frame Buffer n Base Address pointer Note The 2 LSBs are hardwired to 00b 23 3 15 LCD DMA Frame Buffer n Ceiling Address Registers LCDDMA_FB0_CEILING and LCDDMA_FB1_CEILING The LCD DMA frame buffer n ceiling address register LCDDMA_FBn_CEILING contains the ending address for frame buffer n spec...

Page 1078: ...orated Multichannel Audio Serial Port McASP Chapter 24 SPRUH82C April 2013 Revised September 2016 Multichannel Audio Serial Port McASP This chapter describes the multichannel audio serial port McASP See your device specific data manual to determine how many McASPs are available on your device Topic Page 24 1 Registers 1134 ...

Page 1079: ...Programmable clock and frame sync generator TDM streams from 2 to 32 and 384 time slots Support for time slot sizes of 8 12 16 20 24 28 and 32 bits Data formatter for bit manipulation Up to 16 individually assignable serial data pins McASP0 can have up to 16 serial data pins Glueless connection to audio analog to digital converters ADC digital to analog converters DAC codec digital audio interface...

Page 1080: ...s on the basic serial protocol Programmable clock and frame sync polarity rising or falling edge ACLKR X AHCLKR X and AFSR X Slot length number of bits per time slot 8 12 16 20 24 28 32 bits supported Word length bits per word 8 12 16 20 24 28 32 bits always less than or equal to the time slot length First bit data delay 0 1 2 bit clocks Left right alignment of word inside slot Bit order MSB first...

Page 1081: ...s Clock check circuit Audio FIFO WFIFO RFIFO FIFO CONTROL STATUS AXEVT AREVT DMA events DMA bus Peripheral configuration bus Pin function control www ti com 1081 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multichannel Audio Serial Port McASP 24 0 18 Functional Block Diagram A block diagram of the McASP is shown in Fig...

Page 1082: ...Amp Stereo I2S www ti com 1082 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multichannel Audio Serial Port McASP 24 0 18 1 System Level Connections Figure 24 2 through Figure 24 5 show examples of McASP usage in digital audio encoder decoder systems Figure 24 2 McASP to Parallel 2 Channel DACs Figure 24 3 McASP to 6 Cha...

Page 1083: ... generator Stereo I2S Digital amp Digital amp Digital Digital amp amp generator PWM generator generator PWM PWM www ti com 1083 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multichannel Audio Serial Port McASP Figure 24 4 McASP to Digital Amplifier Figure 24 5 McASP as Digital Audio Encoder ...

Page 1084: ...erial transfer the clock the data and the frame sync In a TDM transfer all data bits AXR n are synchronous to the serial clock ACLKX or ACLKR The data bits are grouped into words and slots as defined in Section 24 0 19 The slots are also commonly referred to as time slots or channels in TDM terminology A frame consists of multiple slots or channels Each TDM frame is defined by the frame sync signa...

Page 1085: ...el DAC may be designed to transfer over a single serial data pin AXR n as shown in Figure 24 6 In this case the serial clock must run fast enough to transfer a total of 6 channels within each frame period Alternatively a similar six channel DAC may be designed to use three serial data pins AXR 0 1 2 transferring two channels of data on each pin during each sample period Figure 24 8 In the latter c...

Page 1086: ... two logical states form a cell The duration of the cell which equals to the duration of the data bit is called a time interval A logical 1 is represented by two transitions of the signal within a time interval which corresponds to a cell with logical states 01 or 10 A logical 0 is represented by one transition within a time interval which corresponds to a cell with logical states 00 or 11 In addi...

Page 1087: ... may carry any other information Time interval 28 carries the validity bit V associated with the main data field in the subframe Time interval 29 carries the user data channel U associated with the main data field in the subframe Time interval 30 carries the channel status information C associated with the main data field in the subframe The channel status indicates if the data in the subframe is ...

Page 1088: ...hannel operation mode the samples taken from both channels are transmitted by time multiplexing in consecutive subframes Both subframes contain valid data The first subframe left or A channel in stereophonic operation and primary channel in monophonic operation normally starts with preamble M However the preamble of the first subframe changes to preamble B once every 192 frames to identify the sta...

Page 1089: ... is marked by an edge of the serial clock The duration of a bit is a serial clock period A 1 is represented by a logic high on the AXR n pin for the entire duration of the bit A 0 is represented by a logic low on the AXR n pin for the entire duration of the bit Word A word is a group of bits that make up the data being transferred between the CPU and the external device Figure 24 12 shows an 8 bit...

Page 1090: ...eros 87h as 8 bit word 12 bit slot b right align MSB first pad zeros left align LSB first pad zeros 87h as 8 bit word 12 bit slot c right align LSB first pad zeros 87h as 8 bit word 12 bit slot d 87h as 8 bit word 12 bit slot left align MSB first pad with bit 7 e 87h as 8 bit word 12 bit slot right align MSB first pad with bit 4 f 87h as 8 bit word 12 bit slot left align LSB first pad with bit 7 g...

Page 1091: ...inition of the frame sync See Section 24 0 18 1 Section 24 0 18 2 and Section 24 0 21 2 1 for details on the frame sync formats required for the different transfer modes and protocols burst mode TDM mode and I2S format DIT mode and S PDIF format Figure 24 14 Definition of Frame and Frame Sync Width 1 In this example there are two slots in a frame and FS duration of slot length is shown Other terms...

Page 1092: ...n out AMUTEIN McASP mute input from external device AMUTE McASP mute output Data pins AXR n 24 0 21 Clock and Frame Sync Generators The McASP clock generators are able to produce two independent clock zones transmit and receive clock zones The serial clock generators may be programmed independently for the transmit section and the receive section and may be completely asynchronous to each other Th...

Page 1093: ...the rising edge of the internal transmit clock XCLK Figure 24 15 The CLKXP mux determines if ACLKX needs to be inverted to become XCLK If CLKXP 0 the CLKXP mux directly passes ACLKX to XCLK As a result the McASP shifts transmit data at the rising edge of ACLKX If CLKXP 1 the CLKX mux passes the inverted version of ACLKX to XCLK As a result the McASP shifts transmit data at the falling edge of ACLK...

Page 1094: ...ternally generated or externally sourced polarity of the clock may be programmed CLKRP to be either rising or falling edge The receive high frequency master clock AHCLKR may be either externally sourced from the AHCLKR pin or internally generated as selected by the HCLKRM bit If internally generated HCLKRM 1 the clock is divided down by a programmable divider HCLKRDIV from AUXCLK The receive high ...

Page 1095: ...or is shown in Figure 24 17 The frame sync options are programmed by the receive and transmit frame sync control registers AFSRCTL and AFSXCTL The options are Internally generated or externally generated Frame sync polarity rising edge or falling edge Frame sync width single bit or single word Bit delay 0 1 or 2 cycles before the first data bit The transmit frame sync pin is AFSX and the receive f...

Page 1096: ...hifts out data to the serial data pin AXR n When configured as a receiver the serializer shifts in data from the AXR n pin The serializer is clocked from the transmit receive section clock ACLKX ACLKR if configured to transmit receive respectively All serializers that are configured to transmit operate in lock step Similarly all serializers that are configured to receive also operate in lock step ...

Page 1097: ...s or perform sign extension Since all transmitters share the same data formatting unit the McASP only supports one transmit format at a time For example the McASP will not transmit in I2S format on serializer 0 while transmitting Left Justified on serializer 1 Likewise the receiver section of the McASP only supports one data format at a time and this format applies to all receiving serializers How...

Page 1098: ...ve in an LSB first order Finally note that the R X DATDLY bits in R X FMT also determine the data format For example the difference between I2S format and left justified is determined by the delay between the frame sync edge and the first data bit of a given time slot For I2S format R X DATDLY should be set to a 1 bit delay whereas for left justified format it should be set to a 0 bit delay The co...

Page 1099: ...recover from transmit and receive clock failures See Section 24 0 21 6 6 for implementation and programming details 24 0 21 6 Pin Function Control All McASP pins except AMUTEIN are bidirectional input output pins In addition these bidirectional pins function either as McASP or general purpose I O GPIO pins The following registers control the pin functions Pin function register PFUNC selects pin to...

Page 1100: ...parate control of pin direction by PDIR and the choice of internal versus external clocking by CLKRM CLKXM Depending on the specific device and usage you might select an external clock CLKRM 0 while enabling the internal clock divider and the clock pin as an output in the PDIR register PDIR ACLKR 1 In this case the bit clock is an output PDIR ACLKR 1 and therefore routed to the ACLKR pin However b...

Page 1101: ...eral Purpose Output Pin Initialization Using PDOUT All pins default as inputs To initialize a pin as output you should follow this sequence 1 PDIR n 0 default as input 2 PFUNC n 1 GPIO function 3 PDOUT n desired output value 4 PDIR n 1 change to output after desired value is configured in PDOUT n Example 24 3 General Purpose Output Pin Change Data from 0 to 1 Using PDSET If the pin is already conf...

Page 1102: ...lization This section discusses steps necessary to use the McASP module 24 0 21 1 1 Considerations When Using a McASP The following is a list of things to be considered for systems using a McASP 24 0 21 1 1 1 Clocks For each receive and transmit section External or internal generated bit clock and high frequency clock If internally generated what is the bit clock speed and the high frequency clock...

Page 1103: ...FMT AFSRCTL ACLKRCTL AHCLKRCTL RTDM RINTCTL RCLKCHK If external clocks AHCLKR and or ACLKR are used they must be running already for proper synchronization of the GBLCTL register b Transmit registers XMASK XFMT AFSXCTL ACLKXCTL AHCLKXCTL XTDM XINTCTL XCLKCHK If external clocks AHCLKX and or ACLKX are used they must be running already for proper synchronization of the GBLCTL register c Serializer r...

Page 1104: ...4 second waveform As soon as the transmit serializer is taken out of reset XDATA in the XSTAT register is set indicating that XBUF is empty and ready to be serviced The XDATA status causes a DMA event AXEVT to be generated and can cause an interrupt AXINT to be generated if it is enabled in the XINTCTL register a If DMA is used to service the McASP the DMA automatically services the McASP upon rec...

Page 1105: ...ns Also make sure that the initialization or reinitialization sequence follows the guidelines in Bits With Restrictions on When They May be Changed 24 0 21 1 4 Importance of Reading Back GBLCTL In Section 24 0 21 1 2 steps 4b 5b 7c 9b and 10b state that GBLCTL should be read back until the bits that were written are successfully latched This is important because the transmitter and receiver state ...

Page 1106: ...hronously 24 0 21 2 Transfer Modes 24 0 21 2 1 Burst Transfer Mode The McASP supports a burst transfer mode which is useful for nonaudio data such as passing control information between two CPUs Burst transfer mode uses a synchronous serial format similar to the TDM mode The frame sync generation is not periodic or time driven as in TDM mode but data driven and the frame sync is generated for each...

Page 1107: ...eft at default 0 to select non DIT mode Leave the register at default RMASK XMASK Mask desired bits according to Section 24 0 21 2 and Section 24 0 21 4 RFMT XFMT Program all fields according to data format desired See Section 24 0 21 4 AFSRCTL AFSXCTL Clear RMOD XMOD bits to 0 to indicate burst mode Clear FRWID FXWID bits to 0 for single bit frame sync duration Configure other fields as desired A...

Page 1108: ...desired PDOUT PDIN PDSET PDCLR Not applicable Leave at default GBLCTL Follow the initialization sequence in Section 24 0 21 1 2 to configure this register AMUTE Program all fields according to mute control desired DLBCTL If loopback mode is desired configure this register according to Section 24 0 21 7 otherwise leave this register at default DITCTL DITEN must be left at default 0 to select TDM mo...

Page 1109: ...me slot M 1 In this case slot M is the next active time slot The DMA event for time slot M is generated during the first bit time of slot M 1 The receive DMA request generation does not need this capability since the receive DMA event is generated after data is received in the buffer looks back in time If a time slot is disabled then no data is copied to the buffer for that time slot and no DMA ev...

Page 1110: ...at the TDM slot counter counts the DIT subframes To transmit data in the DIT mode the following pins are typically needed AHCLKX transmit high frequency master clock One or more serial data pins AXR n whose serializers have been configured to transmit AHCLKX is optional the internal clock source may be used instead but if used as a reference the CPU provides a clock check circuit that continually ...

Page 1111: ...ter AMUTE Program all fields according to mute control desired DLBCTL Not applicable Loopback is not supported for DIT mode Leave at default DITCTL DITEN bit must be set to 1 to enable DIT mode Configure other bits as desired RMASK Not applicable Leave at default RFMT Not applicable Leave at default AFSRCTL Not applicable Leave at default ACLKRCTL Not applicable Leave at default AHCLKRCTL Not appl...

Page 1112: ...RA5 The 192 bits in these six registers contain the user data information for the LEFT channel within each frame DITUDRB0 to DITUDRB5 The 192 bits in these six registers contain the user data information for the RIGHT channel within each frame The S PDIF block format is shown in Figure 24 11 There are 192 frames within a block frame 0 to frame 191 Within each frame there are two subframes subframe...

Page 1113: ...UDRB1 32 1 L M DITCSRA1 0 DITUDRA1 0 32 2 R W DITCSRB1 0 DITUDRB1 0 63 1 L M DITCSRA1 31 DITUDRA1 31 63 2 R W DITCSRB1 31 DITUDRB1 31 Defined by DITCSRA2 DITCSRB2 DITUDRA2 DITUDRB2 64 1 L M DITCSRA2 0 DITUDRA2 0 64 2 R W DITCSRB2 0 DITUDRB2 0 95 1 L M DITCSRA2 31 DITUDRA2 31 95 2 R W DITCSRB2 31 DITUDRB2 31 Defined by DITCSRA3 DITCSRB3 DITUDRA3 DITUDRB3 96 1 L M DITCSRA3 0 DITUDRA3 0 96 2 R W DITC...

Page 1114: ...rrupt AXINT is also generated if XDATA interrupt is enabled in the XINTCTL register See Section 24 0 21 5 1 for details For DMA requests the McASP does not require XSTAT to be read between DMA events This means that even if XSTAT already has the XDATA flag set to 1 from a previous request the next transfer triggers another DMA request Since all serializers act in lockstep only one DMA event is gen...

Page 1115: ... Figure 24 25 Calculation of McASP system clock cycle CPU uses SYSCLK2 as the McASP system clock It runs at 150 MHz half of device frequency Therefore McASP system clock cycle 1 150 MHz 6 7 ns Calculation of ACLKX clock cycle This example has two 32 bit slots per frame for a total of 64 bits per frame ACLKX clock cycle is 1 192 kHz 64 81 4 ns Time Slot between AXEVT events For I2S format McASP gen...

Page 1116: ... the RINTCTL register See Section 24 0 21 5 2 for details For DMA requests the McASP does not require RSTAT to be read between DMA events This means that even if RSTAT already has the RDATA flag set to 1 from a previous request the next transfer triggers another DMA request Since all serializers act in lockstep only one DMA event is generated to indicate that all active receive serializers are rea...

Page 1117: ...tive receivers the DMA CPU should read from the RBUF DMA port address four times to obtain data for serializers 1 2 3 and 6 in this exact order upon each receive data ready event When transmitting the DMA CPU must write data to each serializer configured as active and transmit within each time slot Failure to do so results in a buffer underrun condition Section 24 0 21 6 2 Similarly when receiving...

Page 1118: ...rough the DMA port or through the peripheral configuration port To use the CPU to service the McASP through interrupts the XSTAT RSTAT bit must be enabled in the respective XINTCTL RINTCTL registers to generate interrupts AXINT ARINT to the CPU upon data ready 24 0 21 3 5 Using the DMA for McASP Servicing The most typical scenario is to use the DMA to service the McASP through the DMA port althoug...

Page 1119: ...ASP Audio FIFO AFIFO Block Diagram AFIFO Data Transmission When the Write FIFO is disabled transmit DMA requests pass through directly from the McASP to the host DMA controller Whether the WFIFO is enabled or disabled the McASP generates transmit DMA requests as needed the AFIFO is invisible to the McASP When the Write FIFO is enabled transmit DMA requests from the McASP are sent to the AFIFO whic...

Page 1120: ...s until this condition has been satisfied at that point it reads RNUMDMA words from the McASP See description for RFIFOCTL RNUMDMA in Section 24 1 47 If the host CPU reads the Read FIFO independent of a receive DMA request and the RFIFO at that time contains less than RNUMEVT words those words will be read correctly emptying the FIFO Receive DMA Event Pacer The AFIFO may be configured to delay mak...

Page 1121: ...word size WORD in Table 24 4 options are multiples of 4 since the transmit rotate right unit only supports rotation by multiples of 4 However the bit mask pad unit does allow for any number of significant digits For example a Q31 number may have 19 significant digits word and be transmitted in a 24 bit slot this would be formatted as a word size of 20 bits and a slot size of 24 bits However it is ...

Page 1122: ...1 M L P P XROT WORD m Out MSB first LEFT aligned M M 1 L P P XRVRS 1 reverse P P L M 1 M DSP REP Integer P L M P M 1 Data flow P P P P M M 1 L XROT SLOT P P n Out MSB first RIGHT aligned XRVRS 1 reverse P P M M 1 L P P L M 1 M DSP REP Integer P L P M M 1 Data flow XROT 0 P L M P M 1 XRVRS 0 no reverse P L P M M 1 o Out LSB first LEFT aligned L M 1 M P P DSP REP Integer P L M P M 1 Data flow P P P ...

Page 1123: ...ions are multiples of 4 since the receive rotate right unit only supports rotation by multiples of 4 However the bit mask pad unit does allow for any number of significant digits For example a Q31 number may have 19 significant digits word and be transmitted in a 24 bit slot this would be formatted as a word size of 20 bits and a slot size of 24 bits However it is possible to set the bit mask unit...

Page 1124: ...2 DSP REP Q31 M L M 1 P P RROT 0 M M 1 L P P M M 1 L P P RRVRS 0 no reverse RROT 0 M 1 P P M L RRVRS 1 reverse f In MSB first RIGHT aligned P P M M 1 L L M 1 M P P Data flow Data flow Data flow Data flow Data flow M 1 P P M L Data flow M 1 P P M RROT 32 SLOT L L M 1 M P P g In LSB first LEFT aligned RRVRS 0 no reverse M 1 P P M P P L RROT 32 WORD M 1 M 1 DSP REP Integer P P M P P M L L Data flow P...

Page 1125: ... Interrupts Upon detection the following error conditions generate interrupt flags In the receive status register RSTAT Receiver overrun ROVRN Unexpected receive frame sync RSYNCERR Receive clock failure RCKFAIL Receive DMA error RDMAERR In the transmit status register XSTAT Transmit underrun XUNDRN Unexpected transmit frame sync XSYNCERR Transmit clock failure XCKFAIL Transmit DMA error XDMAERR E...

Page 1126: ...h GPIO so GPIO function must be set to McASP for automatic mute function www ti com 1126 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multichannel Audio Serial Port McASP When one or more of the errors is detected and enabled the AMUTE device pin is driven to an active state that is selected by MUTEN in AMUTE The active...

Page 1127: ...bust audio system the McASP includes error checking capability for the serial protocol data underrun and data overrun In addition the McASP includes a timer that continually measures the high frequency master clock every 32 AHCLKX AHCLKR clock cycles The timer value can be read to get a measurement of the clock frequency and has a minimum and maximum range setting that can set an error flag if the...

Page 1128: ...et the McASP and start again with the proper initialization In TDM mode during an underrun case a long stream of zeros are shifted out causing the DACs to mute To recover reset the McASP and start again with the proper initialization 24 0 21 6 3 Buffer Overrun Error Receiver A buffer overrun can only occur for serializers programmed to be receivers A buffer overrun occurs when the serializer is in...

Page 1129: ...clock failure check a Configure transmit clock failure detect logic XMIN XMAX XPS in the transmit clock check control register XCLKCHK b Clear transmit clock failure flag XCKFAIL in the transmit status register XSTAT c Wait until first measurement is taken 32 AHCLKX clock periods d Verify no clock failure is detected e Repeat steps b d until clock is running and is no longer issuing clock failure ...

Page 1130: ...n an out of range condition occurs An out of range minimum condition occurs when the count is smaller than XMIN The logic continually compares the current count from the running system clock counter against the maximum allowable boundary XMAX This is in case the external clock completely stops so that the counter value is not copied to XCNT An out of range maximum condition occurs when the count i...

Page 1131: ... minimum allowable boundary RMIN and automatically flags an interrupt RCKFAIL in RSTAT when an out of range condition occurs An out of range minimum condition occurs when the count is smaller than RMIN The logic continually compares the current count from the running system clock counter against the maximum allowable boundary RMAX This is in case the external clock completely stops so that the cou...

Page 1132: ...ack mode applies to TDM mode only 2 to 32 slots in a frame It does not apply to DIT mode XMOD 180h or burst mode XMOD 0 Figure 24 34 shows the basic logical connection of the serializers in loopback mode Two types of loopback connections are possible selected by the ORD bit in the digital loopback control register DLBCTL as follows ORD 0 Outputs of odd serializers are connected to inputs of even s...

Page 1133: ...e McASP may be put in reset through the global control register GBLCTL Note that a valid serial clock must be supplied to the desired portion of the McASP transmit and or receive in order to assert the software reset bits in GBLCTL See Section 24 0 21 1 2 for details on how to ensure reset has occurred The entire McASP module may also be reset through the Power and Sleep Controller PSC Note that f...

Page 1134: ...ction 24 1 11 50h DITCTL DIT mode control register Section 24 1 12 60h RGBLCTL Receiver global control register Alias of GBLCTL only receive bits are affected allows receiver to be reset independently from transmitter Section 24 1 13 64h RMASK Receive format unit bit mask register Section 24 1 14 68h RFMT Receive bit stream format register Section 24 1 15 6Ch AFSRCTL Receive frame sync control reg...

Page 1135: ...hannel user data register DIT mode 2 Section 24 1 40 13Ch DITUDRA3 Left even TDM time slot channel user data register DIT mode 3 Section 24 1 40 140h DITUDRA4 Left even TDM time slot channel user data register DIT mode 4 Section 24 1 40 144h DITUDRA5 Left even TDM time slot channel user data register DIT mode 5 Section 24 1 40 148h DITUDRB0 Right odd TDM time slot channel user data register DIT mo...

Page 1136: ...ster for serializer 10 Section 24 1 42 22Ch XBUF11 1 Transmit buffer register for serializer 11 Section 24 1 42 230h XBUF12 1 Transmit buffer register for serializer 12 Section 24 1 42 234h XBUF13 1 Transmit buffer register for serializer 13 Section 24 1 42 238h XBUF14 1 Transmit buffer register for serializer 14 Section 24 1 42 23Ch XBUF15 1 Transmit buffer register for serializer 15 Section 24 1...

Page 1137: ...IFO Table 24 9 McASP AFIFO Registers Accessed Through Peripheral Configuration Port 1 Offset Acronym Register Description Section 1000h AFIFOREV AFIFO revision identification register Section 24 1 44 1010h WFIFOCTL Write FIFO control register Section 24 1 45 1014h WFIFOSTS Write FIFO status register Section 24 1 46 1018h RFIFOCTL Read FIFO control register Section 24 1 47 101Ch RFIFOSTS Read FIFO ...

Page 1138: ...XP x x x x x AHCLKXCTL HCLKXM x x x x x AHCLKRCTL HCLKRDIV x x x x x AHCLKRCTL HCLKRP x x x x x AHCLKRCTL HCLKRM x x x x x DLBCTL DLBEN x x x x x x DLBCTL ORD x x x x x x DLBCTL MODE x x x x x x 24 1 2 Revision Identification Register REV The revision identification register REV contains revision data for the peripheral The REV is shown in Figure 24 35 and described in Table 24 10 Figure 24 35 Rev...

Page 1139: ...riting to Reserved Bits Writing a value other than 0 to reserved bits in this register may cause improper device operation Figure 24 36 Pin Function Register PFUNC 31 30 29 28 27 26 25 24 AFSR AHCLKR ACLKR AFSX AHCLKX ACLKX AMUTE Reserved A R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R 0 23 16 Reserved A R 0 15 14 13 12 11 10 9 8 AXR15 AXR14 AXR13 AXR12 AXR11 AXR10 AXR9 AXR8 R W 0 R W 0 R W 0 R W 0 ...

Page 1140: ... GPIO pin 28 AFSX Determines if AFSX pin functions as McASP or GPIO 0 Pin functions as McASP pin 1 Pin functions as GPIO pin 27 AHCLKX Determines if AHCLKX pin functions as McASP or GPIO 0 Pin functions as McASP pin 1 Pin functions as GPIO pin 26 ACLKX Determines if ACLKX pin functions as McASP or GPIO 0 Pin functions as McASP pin 1 Pin functions as GPIO pin 25 AMUTE Determines if AMUTE pin functi...

Page 1141: ...P function and the PDIR bit must be set to 1 an output When AXR n is configured to transmit the PFUNC bit must be cleared to 0 McASP function and the PDIR bit must be set to 1 an output Similarly when AXR n is configured to receive the PFUNC bit must be cleared to 0 McASP function and the PDIR bit must be cleared to 0 an input CAUTION Writing to Reserved Bits Writing a value other than 0 to reserv...

Page 1142: ... as output 28 AFSX Determines if AFSX pin functions as an input or output 0 Pin functions as input 1 Pin functions as output 27 AHCLKX Determines if AHCLKX pin functions as an input or output 0 Pin functions as input 1 Pin functions as output 26 ACLKX Determines if ACLKX pin functions as an input or output 0 Pin functions as input 1 Pin functions as output 25 AMUTE Determines if AMUTE pin function...

Page 1143: ...corresponding bit in PDOUT to 1 writing a 0 has no effect and keeps the bits in PDOUT unchanged PDCLR when written to at this address writing a 1 to a bit in PDCLR clears the corresponding bit in PDOUT to 0 writing a 0 has no effect and keeps the bits in PDOUT unchanged There is only one set of data out bits PDOUT 31 0 The other registers PDSET and PDCLR are just different addresses for the same c...

Page 1144: ...mines drive on AFSX output pin when the corresponding PFUNC 28 and PDIR 28 bits are set to 1 0 Pin drives low 1 Pin drives high 27 AHCLKX Determines drive on AHCLKX output pin when the corresponding PFUNC 27 and PDIR 27 bits are set to 1 0 Pin drives low 1 Pin drives high 26 ACLKX Determines drive on ACLKX output pin when the corresponding PFUNC 26 and PDIR 26 bits are set to 1 0 Pin drives low 1 ...

Page 1145: ...in Figure 24 39 and described in Table 24 14 CAUTION Writing to Reserved Bits Writing a value other than 0 to reserved bits in this register may cause improper device operation Figure 24 39 Pin Data Input Register PDIN 31 30 29 28 27 26 25 24 AFSR AHCLKR ACLKR AFSX AHCLKX ACLKX AMUTE Reserved A R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R 0 23 16 Reserved A R 0 15 14 13 12 11 10 9 8 AXR15 AXR14 AXR...

Page 1146: ...el on ACLKR pin 0 Pin is logic low 1 Pin is logic high 28 AFSX Logic level on AFSX pin 0 Pin is logic low 1 Pin is logic high 27 AHCLKX Logic level on AHCLKX pin 0 Pin is logic low 1 Pin is logic high 26 ACLKX Logic level on ACLKX pin 0 Pin is logic low 1 Pin is logic high 25 AMUTE Logic level on AMUTE pin 0 Pin is logic low 1 Pin is logic high 24 16 Reserved 0 Reserved The reserved bit location a...

Page 1147: ...affecting other I O pins controlled by the same McASP The PDSET is shown in Figure 24 40 and described in Table 24 15 CAUTION Writing to Reserved Bits Writing a value other than 0 to reserved bits in this register may cause improper device operation Figure 24 40 Pin Data Set Register PDSET 31 30 29 28 27 26 25 24 AFSR AHCLKR ACLKR AFSX AHCLKX ACLKX AMUTE Reserved A R W 0 R W 0 R W 0 R W 0 R W 0 R ...

Page 1148: ...to be set to a logic high without affecting other I O pins controlled by the same port 0 No effect 1 PDOUT 28 bit is set to 1 27 AHCLKX Allows the corresponding AHCLKX bit in PDOUT to be set to a logic high without affecting other I O pins controlled by the same port 0 No effect 1 PDOUT 27 bit is set to 1 26 ACLKX Allows the corresponding ACLKX bit in PDOUT to be set to a logic high without affect...

Page 1149: ...t affecting other I O pins controlled by the same McASP The PDCLR is shown in Figure 24 41 and described in Table 24 16 CAUTION Writing to Reserved Bits Writing a value other than 0 to reserved bits in this register may cause improper device operation Figure 24 41 Pin Data Clear Register PDCLR 31 30 29 28 27 26 25 24 AFSR AHCLKR ACLKR AFSX AHCLKX ACLKX AMUTE Reserved A R W 0 R W 0 R W 0 R W 0 R W ...

Page 1150: ...cleared to a logic low without affecting other I O pins controlled by the same port 0 No effect 1 PDOUT 28 bit is cleared to 0 27 AHCLKX Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I O pins controlled by the same port 0 No effect 1 PDOUT 27 bit is cleared to 0 26 ACLKX Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low wit...

Page 1151: ...effect If writing to this field always write the default value for future device compatibility 12 XFRST Transmit frame sync generator reset enable bit 0 Transmit frame sync generator is reset 1 Transmit frame sync generator is active When released from reset the transmit frame sync generator begins counting serial clocks and generating frame sync as programmed 11 XSMRST Transmit state machine rese...

Page 1152: ...e sync generator is active When released from reset the receive frame sync generator begins counting serial clocks and generating frame sync as programmed 3 RSMRST Receive state machine reset enable bit 0 Receive state machine is held in reset 1 Receive state machine is released from reset When released from reset the receive state machine immediately begins detecting frame sync and is ready to re...

Page 1153: ...DMA error RDMAERR drive AMUTE active enable bit 0 Drive is disabled Detection of receive DMA error is ignored by AMUTE 1 Drive is enabled active Upon detection of receive DMA error AMUTE is active and is driven according to MUTEN bit 10 XCKFAIL If transmit clock failure XCKFAIL drive AMUTE active enable bit 0 Drive is disabled Detection of transmit clock failure is ignored by AMUTE 1 Drive is enab...

Page 1154: ... MUTEN bit 4 INSTAT Determines drive on AXR n pin when PFUNC n and PDIR n bits are set to 1 0 AMUTEIN pin is inactive 1 AMUTEIN pin is active Audio mute in error is detected 3 INEN Drive AMUTE active when AMUTEIN error is active INSTAT 1 0 Drive is disabled AMUTEIN is ignored by AMUTE 1 Drive is enabled active INSTAT 1 drives AMUTE active 2 INPOL Audio mute in AMUTEIN polarity select bit 0 Polarit...

Page 1155: ... The reserved bit location always returns the default value A value written to this field has no effect If writing to this field always write the default value for future device compatibility 3 2 MODE 0 3h Loopback generator mode bits Applies only when loopback mode is enabled DLBEN 1 0 Default and reserved on loopback mode DLBEN 1 When in non loopback mode DLBEN 0 MODE should be left at default 0...

Page 1156: ...tion always returns the default value A value written to this field has no effect If writing to this field always write the default value for future device compatibility 3 VB Valid bit for odd time slots DIT right subframe 0 V bit is 0 during odd DIT subframes 1 V bit is 1 during odd DIT subframes 2 VA Valid bit for even time slots DIT left subframe 0 V bit is 0 during even DIT subframes 1 V bit i...

Page 1157: ...ST x Transmit state machine reset enable bit A read of this bit returns the XSMRST bit value of GBLCTL Writes have no effect 10 XSRCLR x Transmit serializer clear enable bit A read of this bit returns the XSRCLR bit value of GBLCTL Writes have no effect 9 XHCLKRST x Transmit high frequency clock divider reset enable bit A read of this bit returns the XHCLKRST bit value of GBLCTL Writes have no eff...

Page 1158: ... W 0 23 22 21 20 19 18 17 16 RMASK23 RMASK22 RMASK21 RMASK20 RMASK19 RMASK18 RMASK17 RMASK16 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 RMASK15 RMASK14 RMASK13 RMASK12 RMASK11 RMASK10 RMASK9 RMASK8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 RMASK7 RMASK6 RMASK5 RMASK4 RMASK3 RMASK2 RMASK1 RMASK0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND ...

Page 1159: ...riting to this field always write the default value for future device compatibility 17 16 RDATDLY 0 3h Receive bit delay 0 0 bit delay The first receive data bit AXR n occurs in same ACLKR cycle as the receive frame sync AFSR 1h 1 bit delay The first receive data bit AXR n occurs one ACLKR cycle after the receive frame sync AFSR 2h 2 bit delay The first receive data bit AXR n occurs two ACLKR cycl...

Page 1160: ...Slot size is 32 bits 3 RBUSEL Selects whether reads from serializer buffer XRBUF n by way of RBUFn by the CPU EDMA occur through the peripheral configuration port or the DMA port 0 Reads from XRBUF n originate on the DMA port Reads from XRBUF n on the peripheral configuration port are ignored 1 Reads from XRBUF n originate on the peripheral configuration port Reads from XRBUF n on the DMA port are...

Page 1161: ...ue for future device compatibility 15 7 RMOD 0 1FFh Receive frame sync mode select bits 0 Burst mode 1h Reserved 2h 20h 2 slot TDM I2S mode to 32 slot TDM 21h 17Fh Reserved 180h 384 slot TDM external DIR IC inputting 384 slot DIR frames to McASP over I2S interface 181h 1FFh Reserved 6 5 Reserved 0 Reserved The reserved bit location always returns the default value A value written to this field has...

Page 1162: ... that this bitfield does not have any effect if ACLKXCTL ASYNC 0 see Section 24 1 29 for a description for the ASYNC bit 0 Falling edge Receiver samples data on the falling edge of the serial clock so the external transmitter driving this receiver must shift data out on the rising edge of the serial clock 1 Rising edge Receiver samples data on the rising edge of the serial clock so the external tr...

Page 1163: ...or future device compatibility 15 HCLKRM Receive high frequency clock source bit 0 External receive high frequency clock source from AHCLKR pin 1 Internal receive high frequency clock source from output of programmable high clock divider 14 HCLKRP Receive bitstream high frequency clock polarity select bit 0 Not inverted AHCLKR is not inverted before programmable bit clock divider In the special ca...

Page 1164: ...0 23 22 21 20 19 18 17 16 RTDMS23 RTDMS22 RTDMS21 RTDMS20 RTDMS19 RTDMS18 RTDMS17 RTDMS16 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 RTDMS15 RTDMS14 RTDMS13 RTDMS12 RTDMS11 RTDMS10 RTDMS9 RTDMS8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 RTDMS7 RTDMS6 RTDMS5 RTDMS4 RTDMS3 RTDMS2 RTDMS1 RTDMS0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W...

Page 1165: ...erved The reserved bit location always returns the default value A value written to this field has no effect If writing to this field always write the default value for future device compatibility 5 RDATA Receive data ready interrupt enable bit 0 Interrupt is disabled A receive data ready interrupt does not generate a McASP receive interrupt RINT 1 Interrupt is enabled A receive data ready interru...

Page 1166: ...eceivers Causes a receive interrupt RINT if this bit is set and RDMAERR in RINTCTL is set This bit is cleared by writing a 1 to this bit Writing a 0 to this bit has no effect 0 Receive DMA error did not occur 1 Receive DMA error did occur 6 RSTAFRM Receive start of frame flag Causes a receive interrupt RINT if this bit is set and RSTAFRM in RINTCTL is set This bit is cleared by writing a 1 to this...

Page 1167: ... by writing a 1 to this bit Writing a 0 to this bit has no effect 0 Receiver overrun did not occur 1 Receiver overrun did occur 24 1 22 Current Receive TDM Time Slot Registers RSLOT The current receive TDM time slot register RSLOT indicates the current time slot for the receive data frame The RSLOT is shown in Figure 24 55 and described in Table 24 30 Figure 24 55 Current Receive TDM Time Slot Reg...

Page 1168: ... maximum boundary This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high frequency master clock AHCLKR signals have been received If the current counter value is greater than RMAX after counting 32 AHCLKR signals RCKFAIL in RSTAT is set The comparison is performed using unsigned arithmetic 15 8 RMIN 0 FFh Receive clock minimum boundary This 8 ...

Page 1169: ...r REVTCTL 31 16 Reserved A R 0 15 1 0 Reserved A RDATDMA R 0 R W 0 LEGEND R W Read Write R Read only n value after reset A If writing to this field always write the default value for future device compatibility Table 24 32 Receiver DMA Event Control Register REVTCTL Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit location always returns the default value A ...

Page 1170: ...s reset 1 Transmit frame sync generator is active 11 XSMRST Transmit state machine reset enable bit A write to this bit affects the XSMRST bit of GBLCTL 0 Transmit state machine is held in reset 1 Transmit state machine is released from reset 10 XSRCLR Transmit serializer clear enable bit A write to this bit affects the XSRCLR bit of GBLCTL 0 Transmit serializers are cleared 1 Transmit serializers...

Page 1171: ...23 XMASK22 XMASK21 XMASK20 XMASK19 XMASK18 XMASK17 XMASK16 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 XMASK15 XMASK14 XMASK13 XMASK12 XMASK11 XMASK10 XMASK9 XMASK8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 XMASK7 XMASK6 XMASK5 XMASK4 XMASK3 XMASK2 XMASK1 XMASK0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write n value after reset...

Page 1172: ...d always write the default value for future device compatibility 17 16 XDATDLY 0 3h Transmit sync bit delay 0 0 bit delay The first transmit data bit AXR n occurs in same ACLKX cycle as the transmit frame sync AFSX 1h 1 bit delay The first transmit data bit AXR n occurs one ACLKX cycle after the transmit frame sync AFSX 2h 2 bit delay The first transmit data bit AXR n occurs two ACLKX cycles after...

Page 1173: ... Selects whether writes to serializer buffer XRBUF n by way of XBUFn by the CPU EDMA occur through the peripheral configuration port or the DMA port 0 Writes to XRBUF n originate from the DMA port Writes to XRBUF n from the peripheral configuration port are ignored with no effect to the McASP 1 Writes to XRBUF n originate from the peripheral configuration port Writes to XRBUF n from the DMA port a...

Page 1174: ...eld always write the default value for future device compatibility 15 7 XMOD 0 1FFh Transmit frame sync mode select bits 0 Burst mode 1h Reserved 2h 20h 2 slot TDM I2S mode to 32 slot TDM 21h 17Fh Reserved 180h 384 slot DIT mode 181h 1FFh Reserved 6 5 Reserved 0 Reserved The reserved bit location always returns the default value A value written to this field has no effect If writing to this field ...

Page 1175: ...field always write the default value for future device compatibility 7 CLKXP Transmit bitstream clock polarity select bit 0 Rising edge External receiver samples data on the falling edge of the serial clock so the transmitter must shift data out on the rising edge of the serial clock 1 Falling edge External receiver samples data on the rising edge of the serial clock so the transmitter must shift ...

Page 1176: ...or future device compatibility 15 HCLKXM Transmit high frequency clock source bit 0 External transmit high frequency clock source from AHCLKX pin 1 Internal transmit high frequency clock source from output of programmable high clock divider 14 HCLKXP Transmit bitstream high frequency clock polarity select bit 0 Not inverted AHCLKX is not inverted before programmable bit clock divider In the specia...

Page 1177: ... XTDMS26 XTDMS25 XTDMS24 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 23 22 21 20 19 18 17 16 XTDMS23 XTDMS22 XTDMS21 XTDMS20 XTDMS19 XTDMS18 XTDMS17 XTDMS16 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 XTDMS15 XTDMS14 XTDMS13 XTDMS12 XTDMS11 XTDMS10 XTDMS9 XTDMS8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 XTDMS7 XTDMS6 XTDMS5 XTDMS4 XTDMS3 XTDMS2 X...

Page 1178: ...eserved bit location always returns the default value A value written to this field has no effect If writing to this field always write the default value for future device compatibility 5 XDATA Transmit data ready interrupt enable bit 0 Interrupt is disabled A transmit data ready interrupt does not generate a McASP transmit interrupt XINT 1 Interrupt is enabled A transmit data ready interrupt gene...

Page 1179: ...nsmitters Causes a transmit interrupt XINT if this bit is set and XDMAERR in XINTCTL is set This bit is cleared by writing a 1 to this bit Writing a 0 has no effect 0 Transmit DMA error did not occur 1 Transmit DMA error did occur 6 XSTAFRM Transmit start of frame flag Causes a transmit interrupt XINT if this bit is set and XSTAFRM in XINTCTL is set This bit is cleared by writing a 1 to this bit W...

Page 1180: ...smitter underrun did occur See Section 24 0 21 6 2 for details on McASP action upon underrun conditions 24 1 34 Current Transmit TDM Time Slot Register XSLOT The current transmit TDM time slot register XSLOT indicates the current time slot for the transmit data frame The XSLOT is shown in Figure 24 67 and described in Table 24 42 Figure 24 67 Current Transmit TDM Time Slot Register XSLOT 31 16 Res...

Page 1181: ... maximum boundary This 8 bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high frequency master clock AHCLKX signals have been received If the current counter value is greater than XMAX after counting 32 AHCLKX signals XCKFAIL in XSTAT is set The comparison is performed using unsigned arithmetic 15 8 XMIN 0 FFh Transmit clock minimum boundary This ...

Page 1182: ...ter XEVTCTL 31 16 Reserved A R 0 15 1 0 Reserved A XDATDMA R 0 R W 0 LEGEND R W Read Write R Read only n value after reset A If writing to this field always write the default value for future device compatibility Table 24 44 Transmitter DMA Event Control Register XEVTCTL Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit location always returns the default val...

Page 1183: ...ive buffer state Always reads 0 when programmed as a transmitter or as inactive If SRMOD bit is set to receive 2h RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF 0 Receive buffer RBUF is empty 1 Receive buffer RBUF contains data and needs to be read before the start of the next time slot or a receiver overrun occurs 4 XRDY Transmit buffer ready bit XRDY indicates the curre...

Page 1184: ... register file in time if a different set of data need to be sent Figure 24 71 DIT Left Channel Status Registers DITCSRA0 DITCSRA5 31 0 DITCSRAn R W 0 LEGEND R W Read Write n value after reset 24 1 39 DIT Right Channel Status Registers DITCSRB0 DITCSRB5 The DIT right channel status registers DITCSRB provide the status of each right channel odd TDM time slot Each of the six 32 bit registers Figure ...

Page 1185: ...he register in time if a different set of data need to be sent Figure 24 73 DIT Left Channel User Data Registers DITUDRA0 DITUDRA5 31 0 DITUDRAn R W 0 LEGEND R W Read Write n value after reset 24 1 41 DIT Right Channel User Data Registers DITUDRB0 DITUDRB5 The DIT right channel user data registers DITUDRB provides the user data of each right channel odd TDM time slot Each of the six 32 bit registe...

Page 1186: ...ers not implemented on a specific CPU may cause improper device operation Figure 24 75 Transmit Buffer Registers XBUFn 31 0 XBUFn R W 0 LEGEND R W Read Write n value after reset 24 1 43 Receive Buffer Registers RBUFn The receive buffers for the serializers RBUF hold data from the serializer before the data goes to the receive format unit For receive operations the RBUF Figure 24 76 is an alias of ...

Page 1187: ...o FIFO AFIFO revision identification register AFIFOREV contains revision data for the Audio FIFO AFIFO The AFIFOREV is shown in Figure 24 77 and described in Table 24 46 Figure 24 77 AFIFO Revision Identification Register AFIFOREV 31 0 REV R 4431 1100h LEGEND R Read only n value after reset Table 24 46 AFIFO Revision Identification Register AFIFOREV Field Descriptions Bit Field Value Description 3...

Page 1188: ...e WLVL field in the Write FIFO status register WFIFOSTS is reset to 0 and pointers are initialized that is the Write FIFO is flushed 1 Write FIFO is enabled If Write FIFO is to be enabled it must be enabled prior to taking McASP out of reset 15 8 WNUMEVT 0 FFh Write word count per DMA event 32 bit When the Write FIFO has space for at least WNUMEVT words of data then an AXEVT transmit DMA event is ...

Page 1189: ...e 24 48 Figure 24 79 Write FIFO Status Register WFIFOSTS 31 16 Reserved R 0 15 8 7 0 Reserved WLVL R 0 R 0 LEGEND R Read only n value after reset Table 24 48 Write FIFO Status Register WFIFOSTS Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 WLVL 0 FFh Write level read only Number of 32 bit words currently in the Write FIFO 0 0 words currently in Write FIFO 1h 1 word cu...

Page 1190: ...it 0 Read FIFO is disabled The RLVL bit in the Read FIFO status register RFIFOSTS is reset to 0 and pointers are initialized that is the Read FIFO is flushed 1 Read FIFO is enabled If Read FIFO is to be enabled it must be enabled prior to taking McASP out of reset 15 8 RNUMEVT 0 FFh Read word count per DMA event 32 bit When the Read FIFO contains at least RNUMEVT words of data then an AREVT receiv...

Page 1191: ...able 24 50 Figure 24 81 Read FIFO Status Register RFIFOSTS 31 16 Reserved R 0 15 8 7 0 Reserved RLVL R 0 R 0 LEGEND R Read only n value after reset Table 24 50 Read FIFO Status Register RFIFOSTS Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 RLVL 0 FFh Read level read only Number of 32 bit words currently in the Read FIFO 0 0 words currently in Read FIFO 1h 1 word curr...

Page 1192: ... Serial Port McBSP Chapter 25 SPRUH82C April 2013 Revised September 2016 Multichannel Buffered Serial Port McBSP This chapter describes the multichannel buffered serial port McBSP See your device specific data manual to determine how many McBSPs are available on your device Topic Page 25 1 Introduction 1193 25 2 Architecture 1195 25 3 Registers 1242 ...

Page 1193: ...Independent framing and clocking for receive and transmit Direct interface to industry standard codecs analog interface chips AICs and other serially connected analog to digital A D and digital to analog D A devices External shift clock or an internal programmable frequency shift clock for data transfer In addition the McBSP has the following capabilities Direct interface to T1 E1 framers MVIP swi...

Page 1194: ...s Incorporated Multichannel Buffered Serial Port McBSP 25 1 3 Functional Block Diagram The McBSP consists of a data path and control path as shown in Figure 25 1 25 1 4 Industry Standard Compliance Statement The McBSP supports the following industry standard interfaces AC97 The AC97 standard specifies a 5 wire digital serial link between an audio codec device and its digital controller IIS IIS is ...

Page 1195: ...or receives a reference clock for the receiver or supplies a reference clock to the sample rate generator CLKS I Supplies the input clock of the sample rate generator CLKX I O Z Transmit clock supplies or receives a reference clock for the transmitter or supplies a reference clock to the sample rate generator DR I Received serial data DX O Z Transmitted serial data FSR I O Z Receive frame synchron...

Page 1196: ...in the pin control register PCR FSR is also affected by the GSYNC bit in the sample rate generator register SRGR see Section 25 2 5 4 2 for details When FSR and FSX are inputs FSXM FSRM 0 the McBSP detects them on the internal falling edge of clock CLKR_int and CLKX_int respectively see Figure 25 2 The receive data arriving at the DR pin is also sampled on the falling edge of CLKR_int These intern...

Page 1197: ...rly the receiver can reliably sample data that is clocked by the transmitter with a rising edge clock The receive clock polarity bit CLKRP sets the edge used to sample received data The receive data is always sampled on the falling edge of CLKR_int see Figure 25 4 Therefore if CLKRP 1 and external clocking is selected CLKRM 0 and CLKR is an input pin the external rising edge triggered input clock ...

Page 1198: ...raming FS R X The sample rate generator can be programmed to be driven by an internal clock source or an internal clock derived from an external clock source The sample rate generator is not used when CLKX FSX CLKR and FSR are driven by an external source Therefore the GRST bit in the serial port control register SPCR does not need to be enabled GRST 1 for this setup The three stages of the sample...

Page 1199: ... rate generator register SRGR see Table 25 2 Table 25 2 Choosing an Input Clock for the Sample Rate Generator With the SCLKME and CLKSM Bits SCLKME Bit in PCR CLKSM Bit in SRGR Input Clock for Sample Rate Generator 0 0 Signal on CLKS pin 0 1 McBSP internal input clock 1 0 Signal on CLKR pin 1 1 Signal on CLKX pin 25 2 5 3 2 Sample Rate Generator Data Bit Clock Rate CLKGDV The first divider stage g...

Page 1200: ...ge of CLKS when CLKSP 1 causes the transition on CLKG and FSG 25 2 5 3 4 Bit Clock and Frame Synchronization When the external clock CLKS is selected to drive the sample rate generator CLKSM 0 in SRGR and SCLKME 0 in PCR the GSYNC bit in SRGR can be used to configure the timing of CLKG relative to CLKS GSYNC 1 ensures that the McBSP and the external device to which it is communicating are dividing...

Page 1201: ...rnal FSRP 0 CLKS CLKSP 0 CLKS CLKSP 1 www ti com Architecture 1201 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multichannel Buffered Serial Port McBSP Figure 25 6 CLKG Synchronization and FSG Generation When GSYNC 1 and CLKGDV 1 Figure 25 7 CLKG Synchronization and FSG Generation When GSYNC 1 and CLKGDV 3 ...

Page 1202: ...e internally connected through multiplexers to DX FSX and CLKX respectively as shown in Figure 25 2 and Figure 32 4 DLB mode allows testing of serial port code without using the external interface of the McBSP CLKX and FSX must be enabled as outputs CLKXM FSXM 1 in DLB mode Figure 25 8 Digital Loopback Mode 25 2 5 3 6 Receive Clock Selection DLB CLKRM Table 25 3 shows how the digital loopback bit ...

Page 1203: ...XEMPTY may occur if the DXR is not properly serviced at least three CLKX cycles before the next frame sync Therefore if the serial clock is stopped before DXR is properly serviced the external device needs to restart the clock at least three CLKX cycles before the next frame sync to allow the DXR write to be properly synchronized See Figure 25 29 for a graphical explanation on when DXR needs to be...

Page 1204: ...e 25 5 shows how you can select various sources to provide the receive frame synchronization signal Note that in digital loopback mode DLB 1 in the serial port control register SPCR the transmit frame sync signal is used as the receive frame sync signal and that DR is internally connected to DX NOTE FSR_int and FSX_int are shown in Figure 25 2 Table 25 5 Receive Frame Synchronization Selection DLB...

Page 1205: ...and Frames 25 2 5 5 1 Frame Synchronization Phases Frame synchronization indicates the beginning of a transfer on the McBSP The data stream following frame synchronization can have up to two phases phase 1 and phase 2 The number of phases can be selected by the phase bit R X PHASE in RCR and XCR The number of elements per frame and bits per element can be independently selected for each phase via ...

Page 1206: ... In multichannel selection mode the frame length value is independent of and perhaps different from the actual number of channels that the device is programmed to receive or transmit per frame via the MCR RCEREn and XCEREn registers See Section 25 2 9 for details on multichannel selection mode operation The 7 bit R X FRLEN1 2 bits in R X CR support up to 128 elements per phase in a frame as shown ...

Page 1207: ... in Figure 25 11 In this case R X PHASE 0 indicating a single phase frame R X FRLEN1 000 0011b indicating a 4 element frame R X WDLEN1 000b indicating 8 bit elements In this example four 8 bit data elements are transferred to and from the McBSP by the CPU or the EDMA controller Four reads of DRR and four writes of DXR are necessary for each frame Figure 25 11 Single Phase Frame of Four 8 Bit Eleme...

Page 1208: ...n and transmission respectively The range of programmable data delay is zero to two bit clocks R X DATDLY 00b to10b as shown in Figure 25 13 Typically a 1 bit delay is selected because data often follows a 1 cycle active frame sync pulse Figure 25 13 Data Delay Normally a frame sync pulse is detected or sampled with respect to an edge of serial clock CLK R X Thus on a subsequent cycle depending on...

Page 1209: ...he framing bit is generated by another device Alternatively you may pull up or pull down DX to achieve the desired value Figure 25 14 2 Bit Data Delay Used to Discard Framing Bit 25 2 5 5 6 Receive Data Justification and Sign Extension RJUST The RJUST bit in the serial port control register SPCR selects whether data in RBR is right or left justified with respect to the MSB in the DRR If right just...

Page 1210: ...or convenience the BFIFO is treated here as a block between the McBSP and the host DMA controller see Figure 25 1 Details on configuration of the BFIFO are provided in Section 25 2 7 6 25 2 7 McBSP Standard Operation During a serial transfer there are typically periods of serial port inactivity between packets or transfers The receive and transmit frame synchronization pulse occurs for every seria...

Page 1211: ...tents of RSR is copied to RBR at the end of every element on the rising edge of the clock provided RBR is not full with the previous data Then an RBR to DRR copy activates the RRDY status bit in the serial port control register SPCR to 1 on the following falling edge of CLKR This indicates that the receive data register DRR is ready with the data to be read by the CPU or the EDMA controller RRDY i...

Page 1212: ...ed the inactivity period between the data frames for adjacent transfers decreases to 0 The minimum time between frame synchronization pulses is the number of bits transferred per frame This time also defines the maximum frame frequency which is calculated by the following equation Figure 25 18 shows the McBSP operating at maximum frame frequency The data bits in consecutive frames are transmitted ...

Page 1213: ... bits to 1 causes the serial port to ignore these unexpected frame sync signals In reception if not ignored RFIG 0 an unexpected FSR pulse discards the contents of RSR in favor of the incoming data Therefore if RFIG 0 an unexpected frame synchronization pulse aborts the current data transfer sets RSYNCERR in SPCR to 1 and begins the reception of a new data element When RFIG 1 the unexpected frame ...

Page 1214: ...2 Data Packing using Frame Sync Ignore Bits Section 25 2 5 5 4 describes one method of changing the element length and frame length to simulate 32 bit serial element transfers thus requiring much less bus bandwidth than four 8 bit transfers require This example works when there are multiple elements per frame Now consider the case of the McBSP operating at maximum packet frequency as shown in Figu...

Page 1215: ...and is in an error condition RFULL is set when the following conditions are met DRR has not been read since the last RBR to DRR transfer RBR is full and an RBR to DRR copy has not occurred RSR is full and an RSR to RBR transfer has not occurred The data arriving on DR is continuously shifted into RSR Figure 25 23 Once a complete element is shifted into RSR an RSR to RBR transfer can occur only if ...

Page 1216: ...me synchronization is required to restart the receiver Figure 25 23 shows the receive overrun condition Because element A is not read before the reception of element B is complete B is not transferred to DRR yet Another element C arrives and fills RSR DRR is finally read but not earlier than two and one half cycles before the end of element C New data D overwrites the previous element C in RSR If ...

Page 1217: ...hree reasons for a receive not to be in progress This FSR is the first after RRST 1 This FSR is the first after DRR has been read clearing an RFULL condition The serial port is in the inter packet intervals The programmed data delay RDATDLY for reception may start during these inter packet intervals for the first bit of the next element to be received Thus at maximum frame frequency frame synchron...

Page 1218: ...expected frame synchronization RBR to DRR copy Read of DRR B6 B5 B4 C7 C6 C5 C4 C3 C2 A1 RBR to DRR copy Read of DRR Architecture www ti com 1218 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multichannel Buffered Serial Port McBSP Figure 25 26 Unexpected Receive Frame Synchronization Pulse 25 2 7 5 3 Transmit With Data ...

Page 1219: ...a in DXR for every new frame sync signal FSX generated by an external device or by the internal sample rate generator until a new element is loaded into DXR by the CPU or the EDMA controller XEMPTY is deactivated XEMPTY 1 when this new element in DXR is transferred to XSR In the case when the FSX is generated by a DXR to XSR copy FSXM 1 in PCR and FSGM 0 in SRGR the McBSP does not generate any new...

Page 1220: ...cted FSX pulses with XFIG 1 This case is discussed in Section 25 2 7 4 1 and shown in Figure 25 20 In this case unexpected FSX pulses are ignored and the transmission continues Case 2 FSX pulses with normal serial port transmission This situation is discussed in Section 25 2 7 2 There are two possible reasons for a transmit not to be in progress This FSX pulse is the first one to occur after XRST ...

Page 1221: ...R Abort transfer Ignore frame pulse Transmitter continues running Start new transmit Transmit frame sync pulse occurs Case 1 Case 2 Case 3 www ti com Architecture 1221 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multichannel Buffered Serial Port McBSP Figure 25 30 Decision Tree Response to Transmit Frame Synchronizatio...

Page 1222: ...uffer FIFO BFIFO has a different memory map see your device specific data manual than the McBSP memory mapped registers MMRs hence the BFIFO is accessible by way of a different Configuration Bus 25 2 7 6 1 BFIFO Data Transmission When the Write FIFO is disabled transmit DMA requests pass through directly from the McBSP to the host DMA controller Whether the WFIFO is enabled or disabled the McBSP g...

Page 1223: ...rds If the RFIFO does not have space the RFIFO waits until this condition has been satisfied at this point it reads RNUMDMA words from the McBSP If the host CPU reads the Read FIFO independent of a receive DMA request and the RFIFO at that time contains less than RNUMEVT words those words will be read correctly emptying the RFIFO 25 2 7 6 2 1 Receive DMA Event Pacer The BFIFO may be configured to ...

Page 1224: ...lements Companded data is always 8 bits wide so the appropriate R X WDLEN1 2 must be cleared to 0 indicating an 8 bit serial data stream If companding is enabled and either phase of the frame does not have an 8 bit element length companding continues as if the element length is eight bits When companding is used transmit data is encoded according to the specified companding law and receive data is...

Page 1225: ...me companding format Figure 25 36 shows the method by which the McBSP can compand internal data The data path is indicated by the DLB arrow The McBSP is enabled in digital loopback DLB mode with companding appropriately enabled by the RCOMPAND and XCOMPAND bits Receive and transmit interrupts RINT when RINTM 0 and XINT when XINTM 0 or synchronization events REVT and XEVT allow synchronization of t...

Page 1226: ...time division multiplexed TDM data stream while communicating with other McBSPs or serial devices the McBSP may need to receive and or transmit on only a few channels To save memory and bus bandwidth you can use a multichannel selection mode to prevent data flow in some of the channels The McBSP has one receive multichannel selection mode and three transmit multichannel selection modes Each channe...

Page 1227: ...able time specified in the data manual As shown in Figure 25 37 this disable time is measured from the CLKX active clock edge The next McBSP turns on its DX pin changes from a high impedance state to valid after a delay time Again this delay time is measured from the CLKX active clock edge Bus contention occurs because the dead time between the two devices is not enough You need to apply alternati...

Page 1228: ...annel control register MCR In one of the transmit multichannel selection modes the channels in this partition are controlled by the enhanced transmit channel enable register partition A B XCERE0 Assign an odd numbered block 1 3 5 or 7 to transmit partition B with the XPBBLK bit in MCR In one of the transmit multichannel selection modes the channels in this partition are controlled by the enhanced ...

Page 1229: ...n A and the Channels of Partition B 25 2 9 5 2 Reassigning Blocks During Reception Transmission If you want to use more than 32 channels you can change which channel blocks are assigned to partitions A and B during the course of a data transfer However these changes must be carefully timed While a partition is being transferred it s the associated block assignment bits cannot be modified and its a...

Page 1230: ...5 16 These assignments cannot be changed Table 25 15 and Table 25 16 also show the registers used to control the channels in the partitions Table 25 15 Receive Channel Assignment and Control When Eight Receive Partitions are Used Receive Partition Assigned Block of Receive Channels Register Used For Channel Control A Block 0 channels 0 through 15 RCERE0 B Block 1 channels 16 through 31 RCERE0 C Bl...

Page 1231: ... determines whether all channels or only selected channels are enabled and unmasked for transmission The McBSP has three transmit multichannel selection modes XMCM 1 XMCM 2h and XMCM 3h which are described in Table 25 17 Table 25 17 Selecting a Transmit Multichannel Selection Mode With the XMCM Bits XMCM Bit in MCR Transmit Multichannel Selection Mode 0 No transmit multichannel selection mode is o...

Page 1232: ...ues of XMCM Figure 25 41 shows the activity on the McBSP pins for the various XMCM values In all cases the transmit frame is configured as follows In transmit control register XCR XPHASE 0 Single phase frame required for multichannel selection modes XFRLEN1 3h 4 words per frame XWDLEN1 0 8 bits per word In multichannel control register MCR XMCME 0 2 partition mode only partitions A and B used In t...

Page 1233: ...l FSX Write to DXR W1 DXR to XSR copy W0 DXR to XSR copy W1 Write to DXR W3 DXR to XSR copy W2 DXR to XSR copy W3 Write to DXR W2 W0 W1 W2 W3 www ti com Architecture 1233 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multichannel Buffered Serial Port McBSP Figure 25 41 Activity on McBSP Pins for the Possible Values of XM...

Page 1234: ...XRST 0 and GRST 1 DX O Z High impedance High impedance CLKX I O Z Input Known state if input CLKX if output FSX I O Z Input Known state if input FSXP inactive state if output CLKS I Input Input 25 2 11 1 Software Reset Considerations McBSP reset When the receiver and transmitter reset bits RRST and XRST in SPCR are written with 0 the respective portions of the McBSP are reset and activity in the c...

Page 1235: ...eceiver Clock and Frame Configurations CLKR Source FSR Source Comment on Configuration Internal Internal The McBSP internal sample rate generator and internal frame sync generator are used by the receiver External Internal The McBSP internal sample rate generator and internal frame sync generator are used by the receiver Internal External The McBSP internal sample rate generator is used but the in...

Page 1236: ... 1 CLKGDV 1 of the sample rate generator source clock CLKSRG 6 Skip this step if the transmitter is not used If the transmitter is used a transmit sync error XSYNCERR may occur when it is enabled for the first time after device reset The purpose of this step is to clear any potential XSYNCERR that occurs on the transmitter at this time a Set the XRST bit to 1 to enable the transmitter b Wait for a...

Page 1237: ...iving the second frame sync At this point DXR is already serviced with the first word 25 2 12 2 1 How to Detect First Frame Sync Although the McBSP is capable of generating an interrupt to the CPU upon the detection of frame synchronization XINTM 2h and or RINTM 2h in the serial port control register SPCR the McBSP requires the associated portion receiver transmitter of the McBSP to be out of rese...

Page 1238: ...nc error XSYNCERR may occur when it is enabled for the first time after device reset The purpose of this step is to clear any potential XSYNCERR that occurs on the transmitter at this time a Set the XRST bit in SPCR to 1 to enable the transmitter b Wait for any unexpected frame sync error to occur If the external device provides the bit clock wait for two CLKR or CLKX cycles If the McBSP generates...

Page 1239: ...ization error Note that if any of the other interrupt modes are selected R X SYNCERR may be read when servicing the interrupts to detect this condition See Section 25 2 7 5 2 and Section 25 2 7 5 5 for more details on synchronization error 25 2 13 1 2 Receive Ready Status RINT and RRDY RRDY 1 indicates that the RBR contents have been copied to DRR and that the data can now be read by either the CP...

Page 1240: ...e the Enhanced Direct Memory Access EDMA3 Controller chapter 25 2 14 2 Transmit Ready Status XEVT and XRDY XRDY 1 in the serial port control register SPCR indicates that the DXR contents have been copied to XSR and that DXR is ready to be loaded with a new data word When the transmitter transitions from reset to non reset XRST transitions from 0 to 1 in SPCR XRDY also transitions from 0 to 1 indic...

Page 1241: ...from DXR to XSR the XRDY flag transitions again from 0 to 1 7 Write a second dummy data value to DXR in order to clear the second XRDY flag 8 Check the RRDY flag in SPCR and if set to 1 read the data receive register DRR and discard the data to clear the RRDY flag 9 Place the McBSP in power down mode by issuing the proper PSC commands For detailed information on power management procedures using t...

Page 1242: ... Registers Offset Acronym Register Name Section RBR 1 Receive buffer register RSR 1 Receive shift register XSR 1 Transmit shift register 0h DRR 2 3 Data receive register Section 25 3 1 4h DXR 3 Data transmit register Section 25 3 2 8h SPCR Serial port control register Section 25 3 3 Ch RCR Receive control register Section 25 3 4 10h XCR Transmit control register Section 25 3 5 14h SRGR Sample rate...

Page 1243: ...value after reset Table 25 23 Data Receive Register DRR Field Descriptions Bit Field Value Description 31 0 DR 0 FFFF FFFFh Data receive register value to be written to the data bus 25 3 2 Data Transmit Register DXR The data transmit register DXR contains the value to be loaded into the data transmit shift register XSR The DXR is shown in Figure 25 43 and described in Table 25 24 See the device sp...

Page 1244: ...OFT bit determines operation of McBSP 1 Free running mode is enabled During emulation halt serial clocks continue to run 24 SOFT Soft bit enable mode bit This bit is used in conjunction with FREE bit to determine state of serial port clock during emulation halt This bit has no effect if FREE 1 0 Soft mode is disabled Serial port clock stops immediately during emulation halt thus aborting any trans...

Page 1245: ...ing for non SPI mode 1h 3h Reserved 10 8 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 7 DXENA DX enabler bit See Section 25 2 9 4 for details on the DX enabler bit 0 DX enabler is off 1 DX enabler is on 6 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 5 4 RINTM 0 3h Recei...

Page 1246: ...n phase 2 1h 2 words in phase 2 2h 3 words in phase 2 7Fh 128 words in phase 2 23 21 RWDLEN2 0 7h Specifies the receive word length number of bits in phase 2 0 Receive word length is 8 bits 1h Receive word length is 12 bits 2h Receive word length is 16 bits 3h Receive word length is 20 bits 4h Receive word length is 24 bits 5h Receive word length is 32 bits 6h 7h Reserved 20 19 RCOMPAND 0 3h Recei...

Page 1247: ...ies the receive word length number of bits in phase 1 0 Receive word length is 8 bits 1h Receive word length is 12 bits 2h Receive word length is 16 bits 3h Receive word length is 20 bits 4h Receive word length is 24 bits 5h Receive word length is 32 bits 6h 7h Reserved 4 RWDREVRS Receive 32 bit bit reversal enable bit 0 32 bit bit reversal is disabled 1 32 bit bit reversal is enabled 32 bit data ...

Page 1248: ...hase 2 1h 2 words in phase 2 2h 3 words in phase 2 7Fh 128 words in phase 2 23 21 XWDLEN2 0 7h Specifies the transmit word length number of bits in phase 2 0 Transmit word length is 8 bits 1h Transmit word length is 12 bits 2h Transmit word length is 16 bits 3h Transmit word length is 20 bits 4h Transmit word length is 24 bits 5h Transmit word length is 32 bits 6h 7h Reserved 20 19 XCOMPAND 0 3h T...

Page 1249: ...ransmit word length number of bits in phase 1 0 Transmit word length is 8 bits 1h Transmit word length is 12 bits 2h Transmit word length is 16 bits 3h Transmit word length is 20 bits 4h Transmit word length is 24 bits 5h Transmit word length is 32 bits 6h 7h Reserved 4 XWDREVRS Transmit 32 bit bit reversal feature enable bit 0 32 bit bit reversal is disabled 1 32 bit bit reversal is enabled 32 bi...

Page 1250: ...LKSM Sample rate generator input clock mode bit The sample rate generator can accept an input clock signal and divide it down according to CLKGDV to produce an output clock signal CLKG The frequency of CLKG is CLKG frequency Input clock frequency CLKGDV 1 CLKSM is used in conjunction with the SCLKME bit in the pin control register PCR to determine the source for the input clock A CPU reset selects...

Page 1251: ...r transmission Figure 25 48 Multichannel Control Registers MCR 31 26 25 24 23 22 21 20 18 17 16 Reserved XMCME XPBBLK XPABLK XCBLK XMCM R 0 R W 0 R W 0 R W 0 R 0 R W 0 15 10 9 8 7 6 5 4 2 1 0 Reserved RMCME RPBBLK RPABLK RCBLK Reserved RMCM R 0 R W 0 R W 0 R W 0 R 0 R 0 R W 0 LEGEND R Read only R W Read Write n value after reset Table 25 29 Multichannel Control Register MCR Field Descriptions Bit ...

Page 1252: ...lock is assigned to partition B The XCBLK bit is regularly updated to indicate which block is active When XMCM 3h for symmetric transmission and reception the transmitter uses the receive block bits RPABLK and RPBBLK rather than the transmit block bits XPABLK and XPBBLK 0 Block 1 channels 16 through 31 1h Block 3 channels 48 through 63 2h Block 5 channels 80 through 95 3h Block 7 channels 112 thro...

Page 1253: ...idually selectable 0 2 partition mode Only partitions A and B are used You can control up to 32 channels in the receive multichannel selection mode RMCM 1 Assign 16 channels to partition A with the RPABLK bit and assign 16 channels to partition B with the RPBBLK bit You control the channels with the enhanced receive channel enable register partition A B RCERE0 1 You can control up to 128 channels ...

Page 1254: ...2h Block 4 channels 64 through 79 3h Block 6 channels 96 through 111 4 2 RCBLK 0 7h Receive current block indicator RCBLK indicates which block of 16 channels is involved in the current McBSP reception 0 Block 0 channels 0 through 15 1h Block 1 channels 16 through 31 2h Block 2 channels 32 through 47 3h Block 3 channels 48 through 63 4h Block 4 channels 64 through 79 5h Block 5 channels 80 through...

Page 1255: ...n B The 16 channels in partition A are assigned with the RPABLK bit in MCR and the 16 channels in partition B are assigned with the RPBBLK bit in MCR When RMCME 1 All partitions are used RCERE0 is used to enable any of the 32 elements in channels 0 through 31 for a receive Of the 32 elements channels 0 to 15 belong to a subframe in partition A and channels 16 to 31 belong to a subframe in partitio...

Page 1256: ... block 0 2 4 or 6 m is any odd numbered block 1 3 5 or 7 Table 25 31 Use of the Receive Channel Enable Registers Number of selectable channels Block Assignments Channel Assignments RCEREn Block assigned 1 Bit in RCEREn Channel assigned 1 32 RCERE0 Channels n to n 15 RCE0 Channel n RMCME 0 The block of channels 0 2 4 or 6 is selected with the RPABLK bit in MCR RCE1 Channel n 1 RCE15 Channel n 15 Ch...

Page 1257: ... in partition A and channels 16 to 31 belong to a subframe in partition B The XCE0 XCE15 bits enable elements within the 16 channel elements in partition A and the XCE16 XCE31 bits enable elements within the 16 channel elements in partition B Section 25 3 9 1 shows the 128 channels in a multichannel data stream and their corresponding enable bits in XCEREn Figure 25 50 Enhanced Transmit Channel En...

Page 1258: ...or transmission 1 n is any even numbered block 0 2 4 or 6 m is any odd numbered block 1 3 5 or 7 Table 25 33 Use of the Transmit Channel Enable Registers Number of selectable channels Block Assignments Channel Assignments XCEREn Block assigned 1 Bit in XCEREn Channel assigned 1 32 XCERE0 Channels n to n 15 XCE0 Channel n XMCME 0 When XMCM 1h or 2h the block of channels 0 2 4 or 6 is selected with ...

Page 1259: ...0 R W 0 R W 0 LEGEND R Read only R W Rear Write n value afer reset 1 If writing to this field always write the default value of 0 to ensure proper McBSP operation Table 25 34 Pin Control Register PCR Field Descriptions Bit Field Value Description 31 14 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 13 12 Reserved 0 Reserved The reserve...

Page 1260: ...ock frequency 0 The input clock for the sample rate generator is taken from the CLKS pin or from the McBSP internal input clock depending on the value of the CLKSM bit in SRGR SCLKME CLKSM Input Clock for Sample Rate Generator 0 0 Signal on CLKS pin 0 1 McBSP internal input clock 1 The input clock for the sample rate generator is taken from the CLKR pin or from the CLKX pin depending on the value ...

Page 1261: ...er FIFO BFIFO revision identification register BFIFOREV contains revision data for the Buffer FIFO BFIFO The BFIFOREV is shown in Figure 25 52 and described in Table 25 35 Figure 25 52 BFIFO Revision Identification Register BFIFOREV 31 0 REV R 4431 1100h LEGEND R Read only n value after reset Table 25 35 BFIFO Revision Identification Register BFIFOREV Field Descriptions Bit Field Value Description...

Page 1262: ...scriptions Bit Field Value Description 31 17 Reserved 0 Reserved 16 WENA Write FIFO enable bit 0 Write FIFO is disabled The WLVL bit in the Write FIFO status register WFIFOSTS is reset to 0 and the pointers are initialized that is the Write FIFO is flushed 1 Write FIFO is enabled If the Write FIFO is to be enabled it must be enabled prior to taking the McBSP out of reset 15 8 WNUMEVT 0 FFh Write w...

Page 1263: ...able 25 37 Figure 25 54 Write FIFO Status Register WFIFOSTS 31 16 Reserved R 0 15 8 7 0 Reserved WLVL R 0 R 0 LEGEND R Read only n value after reset Table 25 37 Write FIFO Status Register WFIFOSTS Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 WLVL 0 FFh Write level Number of 32 bit words currently in the Write FIFO 0 0 words currently in the Write FIFO 1h 1 word curre...

Page 1264: ...OCTL Field Descriptions Bit Field Value Description 31 17 Reserved 0 Reserved 16 RENA Read FIFO enable bit 0 Read FIFO is disabled The RLVL bit in the Read FIFO status register RFIFOSTS is reset to 0 and the pointers are initialized that is the Read FIFO is flushed 1 Read FIFO is enabled If the Read FIFO is to be enabled it must be enabled prior to taking the McBSP out of reset 15 8 RNUMEVT 0 FFh ...

Page 1265: ...n Table 25 39 Figure 25 56 Read FIFO Status Register RFIFOSTS 31 16 Reserved R 0 15 8 7 0 Reserved RLVL R 0 R 0 LEGEND R Read only n value after reset Table 25 39 Read FIFO Status Register RFIFOSTS Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 RLVL 0 FFh Read level Number of 32 bit words currently in the Read FIFO 0 0 words currently in the Read FIFO 1h 1 word current...

Page 1266: ...MMC Secure Digital SD Card Controller Chapter 26 SPRUH82C April 2013 Revised September 2016 Multimedia Card MMC Secure Digital SD Card Controller This chapter describes the multimedia card MMC secure digital SD card controller Topic Page 26 1 Introduction 1267 26 2 Architecture 1268 26 3 Procedures for Common Operations 1284 26 4 Registers 1296 ...

Page 1267: ...ween the MMC SD controller and memory card 512 bit read write FIFO to lower system overhead Signaling to support enhanced direct memory access EDMA transfers slave Maximum clock to MMC varies based on core voltage see your device specific data manual Maximum clock to SD varies based on core voltage see your device specific data manual 26 1 3 Functional Block Diagram The MMC SD card controller tran...

Page 1268: ... SD controller to work as an MMC or SD controller based on the type of card the controller is communicating with Figure 26 2 summarizes the MMC SD mode interface Figure 26 3 illustrates how the controller interfaces to the cards in MMC SD mode In the MMC SD mode the MMC controller supports one or more MMC SD cards Regardless of the number of cards connected the MMC SD controller selects one by usi...

Page 1269: ...nd SD 4 bit mode DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 www ti com Architecture 1269 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multimedia Card MMC Secure Digital SD Card Controller Figure 26 3 MMC Configuration and SD Configuration Diagram 26 2 1 Clock Control There are two clocks the function clock and the memory clock ...

Page 1270: ... MMC SD Controller Clocking Diagram 26 2 2 Signal Descriptions Table 26 1 shows the MMC SD controller pins that each mode uses The MMC SD protocol uses the clock command two way communication between the MMC controller and memory card and data MMCSD_DAT0 MMCSD_DAT0 3 or MMCSD_DAT0 7 for MMC card MMCSD_DAT0 or MMCSD_DAT0 3 for SD card pins 1 I input to the MMC controller O output from the MMC contr...

Page 1271: ... sends responses to the command The MMC SD controller requests the card to change states from standby to transfer The card receives the command and sends responses to the command The MMC SD controller sends a write command to the card The card receives the command and sends responses to the command The MMC SD controller sends a block of data to the card The card sends the CRC status to the MMC SD ...

Page 1272: ...nd The MMC SD controller sends a read command to the card The card drives responses to the command The card sends a block of data to the CPU Figure 26 6 MMC SD Mode Read Sequence Timing Diagram Table 26 3 MMC SD Mode Read Sequence Portion of the Sequence Description RD CMD Read command A 6 byte READ_SINGLE_BLOCK command token is sent from the CPU to the card CMD RSP Command response The card sends...

Page 1273: ...ation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multimedia Card MMC Secure Digital SD Card Controller A high level operational description is as follows Data is written to the FIFO through the MMC data transmit register MMCDXR Data is read from the FIFO through the MMC data receive register MMCDRR This is true for both the CPU and EDMA driven transactions however for the EDMA tra...

Page 1274: ...a Card MMC Secure Digital SD Card Controller 26 2 5 Data Flow in the Data Registers MMCDRR and MMCDXR The CPU or EDMA controller can read 32 bits at a time from the FIFO by reading the MMC data receive register MMCDRR and write 32 bits at a time to the FIFO by writing to the MMC data transmit register MMCDXR However since the memory card is an 8 bit device it transmits or receives one byte at a ti...

Page 1275: ...e FIFO fills up the FIFO controller stops the MMC SD controller from reading any more data until the FIFO is no longer full An EDMA read event generates when the last data arrives as determined by the MMC block length register MMCBLEN and the MMC number of blocks register MMCNBLK settings This EDMA event flushes all of the data that was read from the card to the FIFO Each time an EDMA read event g...

Page 1276: ...ter Increment counter DMA Capture data done DMA No Yes Yes Yes Generate DMA Reset counter Idle DMA pending DMA No done Architecture www ti com 1276 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multimedia Card MMC Secure Digital SD Card Controller Figure 26 9 FIFO Operation During Card Read Diagram ...

Page 1277: ...T generates and the DXRDY bit in the MMC status register 0 MMCST0 is also set 26 2 7 2 CPU Writes The system CPU can also directly write the card data by writing the MMC data transmit register MMCDXR The MMC SD peripheral supports writes that are 1 2 3 or 4 bytes wide as shown in Figure 26 8 The CPU makes use of the FIFO to transfer data to the card via the MMC SD controller The CPU writes the dat...

Page 1278: ... Increment counter DMA pending Send data done DMA No Yes Yes Yes Generate DMA Reset counter Idle DMA pending DMA No done Architecture www ti com 1278 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multimedia Card MMC Secure Digital SD Card Controller Figure 26 10 FIFO Operation During Card Write Diagram ...

Page 1279: ...MC SD controller The subsections that follow help you decide how to initialize each of control register bits In the MMC SD mode the MMC SD controller must know how wide the data bus must be for the memory card that is connected If an MMC card is connected specify a 1 bit data bus WIDTH 0 in MMCCTL if an SD card is connected specify a 4 bit data bus WIDTH 1 in MMCCTL To place the MMC SD controller ...

Page 1280: ...the size for each block of data transferred between the MMC SD controller and a memory card in MMCBLEN The valid size depends on the type of read write operations A length of 0 bytes is prohibited For multiple block transfers you must specify how many blocks of data are to be transferred between the MMC SD controller and a memory card You can specify an infinite number of blocks by loading 0 into ...

Page 1281: ...to stop reading from the data receive register for a read operation The CPU is also notified of the time out event by an interrupt if the interrupt request is enabled EDATDNE 1 in MMCIM 26 2 9 7 8 Determining When Last Data has Been Written to Card SanDisk SD cards Some SanDisk brand SD cards exhibit a behavior that requires a multiple block write command to terminate with a STOP CMD12 command bef...

Page 1282: ...bit transfer depending on the MMC FIFO control register MMCFIFOCTL setting Performing a write and a read in response to the interrupt generated by the FIFO automatically clears the corresponding interrupt bit flag NOTE You must be aware that an emulation read of the status register clears the interrupt status flags To avoid inadvertently clearing the flag be careful while monitoring MMCST0 via the...

Page 1283: ...A controller Based on the FIFO threshold setting the EDMA event signals generate every time 256 bit or 512 bit data is transferred from the FIFO 26 2 12 Power Management You can put the MMC SD peripheral in reduced power modes to conserve power during periods of low activity The processor power and sleep controller PSC controls the power management of the MMC SD peripheral The PSC acts as a master...

Page 1284: ...e and no response from the cards is expected 2 Use MMCCMD to issue the SEND_OP_CMD CMD1 command with the voltage range supported R3 response if it is successful R1b response if the card is expected to be busy Using MMCCMD to issue the CMD1 command allows the host to identify and reject cards that do not match the VDD range that the host supports 3 If the response in Step 2 is R1b that is the card ...

Page 1285: ...MD0 command puts all cards MMC and SD in the idle state and no response from the cards is expected 2 Use MMCCMD to issue the APP_CMD CMD55 command R1 response is expected to indicate that the command that follows is an application command 3 Use MMCCMD to send the SD_SEND_OP_COND ACMD41 command with the voltage range supported R3 response is expected to SD cards Using MMCCMD to send the ACMD41 comm...

Page 1286: ... CMD3 RCA in R6 Response Command CMD2 CID in R2 ALL_SEND_CID Response Command Procedures for Common Operations www ti com 1286 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multimedia Card MMC Secure Digital SD Card Controller 6 Repeat Step 4 and Step 5 to identify and retrieve relative addresses from all remaining SD ca...

Page 1287: ... s maximum block length 5 Use MMCCMD to send the SET_BLOCKLEN command if the block length is different than the length used in the previous operation The block length must be a multiple of 512 bytes and less then the maximum block length specified in the CSD 6 Reset the FIFO FIFORST bit in MMCFIFOCTL 7 Set the FIFO direction to transmit FIFODIR bit in MMCFIFOCTL 8 Set the access width ACCWD bits i...

Page 1288: ... the transfer Start writing one block of data Only 512 byte block length is permitted Is CRCWR 1 Is DATDNE 1 Is DXRDY 1 Check CRCWR bit for any write CRC errors Check DATDNE bit to see if the transfer is done If not then Check DXRDY bit to see the data transmit register is ready for the next byte Load the data transmit register with the next byte Procedures for Common Operations www ti com 1288 SP...

Page 1289: ...or errors 26 3 4 MMC SD Mode Single Block Read Operation Using the CPU To perform a single block read the same block length must be set in both the MMC SD controller and the card The procedure for this operation is as follows 1 Write the card s relative address to the MMC argument registers MMCARGH and MMCARGL Load the high part of the address to MCARGH and the low part of the address to MMCARGL 2...

Page 1290: ...CRCRD 1 Is DRRDY 1 Is DATDNE 1 Is TOUTRD 1 Check TOUTRD bit to verify that read operation has not timed out Check CRCRD bit for any read CRC errors Check DATDNE bit to see if transfer is done If not then Check DRRDY bit to see the data receive register has received a new byte Read the new byte from the data receiver register Procedures for Common Operations www ti com 1290 SPRUH82C April 2013 Revi...

Page 1291: ...ation Using CPU NOTE This procedure uses a STOP_TRANSMISSION command to end the block transfer This assumes that the value in the MMC number of blocks counter register MMCNBLK is 0 A multiple block operation terminates itself if you load MMCNBLK with the exact number of blocks you want transferred To perform a multiple block write the same block length needs to be set in both the MMC SD controller...

Page 1292: ...ommand register Check CRCWR bit for any write CRC errors Check DXRDY to see if a new byte can be put in MMCDXR register STOP_TRANSMISSION COMMAND Terminate the multiple block write operation Procedures for Common Operations www ti com 1292 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Multimedia Card MMC Secure Digital S...

Page 1293: ...k for errors 13 Use MMCCMD to send the STOP_TRANSMISSION command 26 3 8 MMC SD Mode Multiple Block Read Operation Using CPU NOTE This procedure uses a STOP_TRANSMISSION command to end the block transfer This assumes that the value in the MMC number of blocks counter register MMCNBLK is 0 A multiple block operation terminates itself if you load MMCNBLK with the exact number of blocks you want trans...

Page 1294: ...o verify that the read operation has not timed out Check CRCRD bit for any read CRC errors Check DRRDY to see if a new byte is in the data STOP_TRANSMISSION COMMAND Terminate the multiple block read operation Is TOUTRD 1 receive register Procedures for Common Operations www ti com 1294 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments In...

Page 1295: ...e DMATRIG bit in MMCCMD to trigger the first data transfer 11 Wait for DMA sequence to complete 12 Use the MMC status register 0 MMCST0 to check for errors 13 Use MMCCMD to send the STOP_TRANSMISSION command 26 3 10 SDIO Card Function To support the SDIO card the following features are available in the MMC SD controller Read wait operation request Interrupt to CPU at the start of read wait operati...

Page 1296: ...gister Section 26 4 1 4h MMCCLK MMC Memory Clock Control Register Section 26 4 2 8h MMCST0 MMC Status Register 0 Section 26 4 3 Ch MMCST1 MMC Status Register 1 Section 26 4 4 10h MMCIM MMC Interrupt Mask Register Section 26 4 5 14h MMCTOR MMC Response Time Out Register Section 26 4 6 18h MMCTOD MMC Data Read Time Out Register Section 26 4 7 1Ch MMCBLEN MMC Block Length Register Section 26 4 8 20h ...

Page 1297: ...t Field Value Description 31 11 Reserved 0 Reserved 10 PERMDX Endian select when writing 0 Little endian is selected 1 Big endian is selected 9 PERMDR Endian select when reading 0 Little endian is selected 1 Big endian is selected 8 WIDTH1 0 3h Data bus width 1 MMC mode only Used in conjunction with the WIDTH0 bit 0 Data bus has 1 bit only MMCSD_DAT0 is used 1h Data bus has 4 bits only MMCSD_DAT0 ...

Page 1298: ... 26 2 1 The MMC memory clock control register MMCCLK is shown in Figure 26 18 and described in Table 26 7 Figure 26 18 MMC Memory Clock Control Register MMCCLK 31 16 Reserved R 0 15 10 9 8 7 0 Reserved DIV4 CLKEN CLKRT R 0 R W 0 R W 0 R W FFh LEGEND R W Read Write R Read only n value after reset Table 26 7 MMC Memory Clock Control Register MMCCLK Field Descriptions Bit Field Value Description 31 1...

Page 1299: ... command with BSYEXP bit otherwise it continues transferring data 2 Bit 12 TRNDNE indicates that the last byte of a transfer has been completed Bit 0 DATDNE occurs at end of a transfer but not until the CRC check and programming has completed Figure 26 19 MMC Status Register 0 MMCST0 31 16 Reserved R 0 15 14 13 12 11 10 9 8 Reserved CCS TRNDNE DATED DRRDY DXRDY Reserved R 0 R 0 R 0 RC 0 R 0 R 1 R ...

Page 1300: ...en detected 1 A response CRC error has been detected 6 CRCRD Read data CRC error 0 A read data CRC error has not been detected 1 A read data CRC error has been detected 5 CRCWR Write data CRC error 0 A write data CRC error has not been detected 1 A write data CRC error has been detected 4 TOUTRS Response time out event 0 A response time out event has not occurred 1 A time out event has occurred wh...

Page 1301: ...1 FIFO is empty 4 DAT3ST MMCSD_DAT3 status 0 The signal level on the MMCSD_DAT3 pin is a logic low level 1 The signal level on the MMCSD_DAT3 pin is a logic high level 3 DRFUL Data receive register MMCDRR is full 0 A data receive register full condition is not detected The data receive shift register is not full 1 A data receive register full condition is detected The data receive shift register i...

Page 1302: ...eld Value Description 31 14 Reserved 0 Reserved 13 ECCS Command completion signal interrupt enable 0 Command completion signal interrupt is disabled 1 Command completion signal interrupt is enabled 12 ETRNDNE Transfer done TRNDNE interrupt enable 0 Transfer done interrupt is disabled 1 Transfer done interrupt is enabled 11 EDATED MMCSD_DAT3 edge detect DATED interrupt enable 0 MMCSD_DAT3 edge dete...

Page 1303: ...interrupt is disabled 1 Response time out event interrupt is enabled 3 ETOUTRD Read data time out event TOUTRD interrupt enable 0 Read data time out event interrupt is disabled 1 Read data time out event interrupt is enabled 2 ERSPDNE Command response done RSPDNE interrupt enable 0 Command response done interrupt is disabled 1 Command response done interrupt is enabled 1 EBSYDNE Busy done BSYDNE i...

Page 1304: ...an MMCTOR can provide a software time out mechanism can be implemented The MMC response time out register MMCTOR is shown in Figure 26 22 and described in Table 26 11 Figure 26 22 MMC Response Time Out Register MMCTOR 31 18 17 16 Reserved TOD_25_16 R 0 R W 0 15 8 7 0 TOD_25_16 TOR R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 26 11 MMC Response Time Out Register MMCTOR Fi...

Page 1305: ...is set in MMCST0 If a memory card should require a longer time out period than MMCTOD can provide a software time out mechanism can be implemented The MMC data read time out register MMCTOD is shown in Figure 26 23 and described in Table 26 12 Figure 26 23 MMC Data Read Time Out Register MMCTOD 31 16 Reserved R 0 15 0 TOD_15_0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 26 12...

Page 1306: ... 26 24 and described in Table 26 13 NOTE The BLEN bits value must be the same as the CSD register settings in the MMC SD card To be precise it should match the value of the READ_BL_LEN field for read or WRITE_BL_LEN field for write Figure 26 24 MMC Block Length Register MMCBLEN 31 16 Reserved R 0 15 12 11 0 Reserved BLEN R 0 R W 200h LEGEND R W Read Write R Read only n value after reset Table 26 1...

Page 1307: ...0 Infinite number of blocks The MMC controller reads writes blocks of data until a STOP_TRANSMISSION command is written to the MMC command register MMCCMD 1h FFFFh n blocks The MMC controller reads writes only n blocks of data even if the STOP_TRANSMISSION command has not been written to the MMC command register MMCCMD 26 4 10 MMC Number of Blocks Counter Register MMCNBLC The MMC number of blocks ...

Page 1308: ...RR R W 0 LEGEND R W Read Write n value after reset Table 26 16 MMC Data Receive Register MMCDRR Field Descriptions Bit Field Value Description 31 0 DRR 0 FFFF FFFFh Data receive 26 4 12 MMC Data Transmit Register MMCDXR The MMC data transmit register MMCDXR is used for storing the data to be transmitted from the MMC controller to the memory card The CPU or the DMA controller can write data to this...

Page 1309: ...ommand Register MMCCMD 31 24 Reserved R 0 23 17 16 Reserved DMATRIG R 0 R W 0 15 14 13 12 11 10 9 8 DCLR INITCK WDATX STRMTP DTRW RSPFMT BSYEXP R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 0 PPLEN Reserved CMD R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 26 18 MMC Command Register MMCCMD Field Descriptions Bit Field Value Description 31 17 Reserved 0 Reserved 16 D...

Page 1310: ...ansfer is a write operation 10 9 RSPFMT 0 3h Response format expected type of response to the command 0 No response 1h R1 R4 R5 or R6 response 48 bits with CRC 2h R2 response 136 bits with CRC 3h R3 response 48 bits with no CRC 8 BSYEXP Busy expected If an R1b R1 with busy response is expected set RSPFMT 1h and BSYEXP 1 0 A busy signal is not expected 1 A busy signal is expected 7 PPLEN Push pull ...

Page 1311: ... causes the MMC controller to send a command therefore MMCARGHL must be configured before writing to MMCCMD The content of MMCARGHL is kept after the transfer to the shift register however modification to MMCARGHL is not allowed during a sending operation For the format of a command see Figure 26 30 and Table 26 19 The MMC argument register MMCARGHL is shown in Figure 26 31 and described in Table ...

Page 1312: ...se registers holds up to 16 bits Table 26 21 and Table 26 22 show the format for each type of response and which MMC response registers are used for the bits of the response The first byte of the response is a command index byte and is stored in the MMC command index register MMCCIDX Figure 26 32 MMC Response Register 0 and 1 MMCRSP01 31 16 MMCRSP1 R W 0 15 0 MMCRSP0 R W 0 LEGEND R W Read Write n ...

Page 1313: ... 1 Bits 7 0 of the response are stored to bits 7 0 of MMCRSP5 Table 26 21 R1 R3 R4 R5 or R6 Response 48 Bits Bit Position of Response Register 47 40 MMCCIDX 39 24 MMCRSP7 23 8 MMCRSP6 7 0 MMCRSP5 1 MMCRSP4 0 Table 26 22 R2 Response 136 Bits Bit Position of Response Register 135 128 MMCCIDX 127 112 MMCRSP7 111 96 MMCRSP6 95 80 MMCRSP5 79 64 MMCRSP4 63 48 MMCRSP3 47 32 MMCRSP2 31 16 MMCRSP1 15 0 MMC...

Page 1314: ...rite operation see Section 26 2 3 1 the CRC status token is stored in DRSP 26 4 17 MMC Command Index Register MMCCIDX The MMC command index register MMCCIDX stores the first byte of a response from a memory card Table 26 21 and Table 26 22 show the format for each type of response The MMC command index register MMCCIDX is shown in Figure 26 37 and described in Table 26 24 Figure 26 37 MMC Command ...

Page 1315: ...e 26 25 SDIO Control Register SDIOCTL Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 RDWTCR Read wait enable for CRC error To end the read wait operation write 0 to RDWTRQ No need to clear RDWTCR 0 Read wait is disabled 1 Automatically start read wait on CRC error detection during multiple block read access and not the last block to be transferred RDWTRQ is automatically...

Page 1316: ... SDIOST0 31 16 Reserved R 0 15 3 2 1 0 Reserved RDWTST INTPRD DAT1 R 0 R 0 R 0 R 1 LEGEND R W Read Write R Read only n value after reset Table 26 26 SDIO Status Register 0 SDIOST0 Field Descriptions Bit Field Value Description 31 3 Reserved 0 Reserved 2 RDWTST Read wait status 0 Read wait operation not in progress 1 Read wait operation in progress 1 INTPRD Interrupt period 0 Interrupt not in progr...

Page 1317: ...le 0 SDIO card interrupt is disabled 1 SDIO card interrupt is enabled 26 4 21 SDIO Interrupt Status Register SDIOIST The SDIO interrupt status register SDIOIST is shown in Figure 26 41 and described in Table 26 28 Figure 26 41 SDIO Interrupt Status Register SDIOIST 31 16 Reserved R 0 15 2 1 0 Reserved RWS IOINT R 0 R W1C 0 R W1C 0 LEGEND R W Read Write R Read only W1C Write 1 to clear writing 0 ha...

Page 1318: ...trol Register MMCFIFOCTL Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 3 ACCWD 0 3h Access width Used by FIFO control to determine full empty flag 0 CPU EDMA access width of 4 bytes 1h CPU EDMA access width of 3 bytes 2h CPU EDMA access width of 2 bytes 3h CPU EDMA access width of 1 byte 2 FIFOLEV FIFO level Sets the threshold level that determines when the EDMA request...

Page 1319: ...dback Copyright 2013 2016 Texas Instruments Incorporated Real Time Clock RTC Chapter 27 SPRUH82C April 2013 Revised September 2016 Real Time Clock RTC This chapter describes the real time clock RTC Topic Page 27 1 Introduction 1320 27 2 Architecture 1321 27 3 Registers 1327 ...

Page 1320: ...ot interfere with the accuracy of the time and date Alarms are available to interrupt the CPU at a particular time or at periodic time intervals such as once per minute or once per day In addition the RTC can interrupt the CPU every time the calendar and time registers are updated or at programmable periodic intervals 27 1 2 Features The real time clock RTC provides the following features 100 year...

Page 1321: ...riven with a 32 768 kHz reference clock or RTC_XI and RTC_XO can be connected to an external crystal This signal is the input to the RTC internal oscillator RTC_XO O RTC time base output signal RTC_XO is the output from the RTC internal oscillator If a crystal is not used as the time base for RTC_XI RTC_XO should be left unconnected 27 2 3 Isolated Power Supply The RTC has a power supply that is i...

Page 1322: ...When HOURMODE 1 12 hour mode is selected The hours are represented as 00 through 12 MERIDIEM 0 indicates ante meridiem AM and MERIDIEM 1 indicates post meridiem PM 27 2 4 1 3 Reading from Time Calendar Registers The time calendar registers are updated every second as the time changes During a read of the SECOND register the RTC copies the current values of the time date registers into shadow read ...

Page 1323: ...following registers while RTC is running SECOND MINUTE HOUR DAY MONTH YEAR DOTW ALARMSECOND when ALARM interrupt is enabled ALARMMINUTE when ALARM interrupt is enabled ALARMHOUR when ALARM interrupt is enabled ALARMDAY when ALARM interrupt is enabled ALARMMONTH when ALARM interrupt is enabled ALARMYEAR when ALARM interrupt is enabled CTRL SET32COUNTER field only the other fields in CTRL do not req...

Page 1324: ...upt request to the CPU When the device is initially powered on the RTC may issue spurious interrupt signals to the CPU To avoid issues a software reset should be performed on the RTC module before the CPU interrupt controller is initialized See Section 27 2 10 for more information on reset considerations 27 2 5 1 Alarm Interrupt Enable and Status Bits The ALARM bit in the interrupt register INTERR...

Page 1325: ...MM SS format transitions from 23 59 59 to 00 00 00 the STATUS register sets all four periodic status bits DAYEVT HREVT MINEVT and SECEVT because all four time periods were incremented These bits all remain high until 1 The TIME bit is cleared and all four status bits clear to zero until TIME is set again OR 2 The current time reaches 00 00 01 At that point the SECEVT remains set while the DAYEVT H...

Page 1326: ...igured and enabled If the RTC is unintentionally powered down the value written to the SCRATCH register is cleared 27 2 8 Real Time Clock Response to Low Power Modes Idle Configurations The device is divided into idle domains that can be programmed to be idle or active The state of all domains is called the idle configuration The RTC runs on its own external clock source and is not affected by any...

Page 1327: ... 20h ALARMSECOND Alarm Seconds Register Section 27 3 8 24h ALARMMINUTE Alarm Minutes Register Section 27 3 9 28h ALARMHOUR Alarm Hours Register Section 27 3 10 2Ch ALARMDAY Alarm Days Register Section 27 3 11 30h ALARMMONTH Alarm Months Register Section 27 3 12 34h ALARMYEAR Alarm Years Register Section 27 3 13 40h CTRL Control Register Section 27 3 14 44h STATUS Status Register Section 27 3 15 48...

Page 1328: ... Reserved 0 Reserved 6 4 SEC1 0 5h Most significant digit of second value Range for SEC1 SEC0 is 00 59 3 0 SEC0 0 9h Least significant digit of second value Range for SEC1 SEC0 is 00 59 27 3 2 Minute Register MINUTE NOTE Out of reset the minute register MINUTE is write protected To disable write protection correct keys must be written to the KICKnR registers see Section 27 2 6 The minute register ...

Page 1329: ...are encoded with their binary equivalent The HOUR register is shown in Figure 27 6 and described in Table 27 5 Figure 27 6 Hour Register HOUR 31 16 Reserved R 0 15 8 7 6 5 4 3 0 Reserved MERIDIEM Rsvd HOUR1 HOUR0 R 0 R W 0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 27 5 Hour Register HOUR Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 MER...

Page 1330: ...Reserved 5 4 DAY1 0 3h Most significant digit of day of the month value Range for DAY1 DAY0 is 01 31 3 0 DAY0 0 9h Least significant digit of day of the month value Range for DAY1 DAY0 is 01 31 27 3 5 Month Register MONTH NOTE Out of reset the month register MONTH is write protected To disable write protection correct keys must be written to the KICKnR registers see Section 27 2 6 The month regist...

Page 1331: ...d Value Description 31 8 Reserved 0 Reserved 7 4 YEAR1 0 9h Most significant digit of years value Range for YEAR1 YEAR0 is 00 99 3 0 YEAR0 0 9h Least significant digit of years value Range for YEAR1 YEAR0 is 00 99 27 3 7 Day of the Week Register DOTW NOTE Out of reset the day of the week register DOTW is write protected To disable write protection correct keys must be written to the KICKnR registe...

Page 1332: ...served 6 4 SEC1 0 5h Most significant digit of alarm seconds value Range for SEC1 SEC0 is 00 59 3 0 SEC0 0 9h Least significant digit of alarm seconds value Range for SEC1 SEC0 is 00 59 27 3 9 Alarm Minute Register ALARMMINUTE NOTE Out of reset the alarm minute register ALARMMINUTE is write protected To disable write protection correct keys must be written to the KICKnR registers see Section 27 2 ...

Page 1333: ... 9 are encoded with their binary equivalent The ALARMHOUR register is shown in Figure 27 13 and described in Table 27 12 Figure 27 13 Alarm Hour Register ALARMHOUR 31 16 Reserved R 0 15 8 7 6 5 4 3 0 Reserved MERIDIEM Rsvd HOUR1 HOUR0 R 0 R W 0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 27 12 Alarm Hour Register ALARMHOUR Field Descriptions Bit Field Value Descript...

Page 1334: ...larm interrupt Days are stored as binary coded decimal BCD format In BCD format the decimal numbers 0 through 9 are encoded with their binary equivalent The ALARMDAYS register is shown in Figure 27 14 and described in Table 27 13 Figure 27 14 Alarm Day Register ALARMDAY 31 16 Reserved R 0 15 6 5 4 3 0 Reserved DAY1 DAY0 R 0 R W 0 R W 1 LEGEND R W Read Write R Read only n value after reset Table 27...

Page 1335: ... 31 5 Reserved 0 Reserved 4 MONTH1 0 1h Most significant digit of months value For MONTH1 MONTH0 JAN 01 and DEC 12 3 0 MONTH0 0 9h Least significant digit of months value For MONTH1 MONTH0 JAN 01 and DEC 12 27 3 13 Alarm Year Register ALARMYEAR NOTE Out of reset the alarm year register ALARMYEAR is write protected To disable write protection correct keys must be written to the KICKnR registers see...

Page 1336: ...split power 1 Enable split power 6 RTCDISABLE Disable RTC module and gate 32 kHz reference clock RTC should only be disabled using this bit if the module will never be used and saving power is desired 0 RTC is functional 1 RTC is disabled and 32 kHz reference clock is gated 5 SET32COUNTER Set the 32 kHz counter with the value stored in the compensation registers when the SET32COUNTER bit is set RT...

Page 1337: ...time update 0 DAYS register did not increment during the last time update 1 DAYS register incremented during the last time update 4 HREVT When the TIMER 1 in the INTERRUPTS register HREVT indicates if the HOURS register incremented during the most recent time update 0 HOURS register did not increment during the last time update 1 HOURS register incremented during the last time update 3 MINEVT When...

Page 1338: ... R 0 15 4 3 2 1 0 Reserved ALARM TIMER EVERY R 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 27 18 Interrupt Register INTERRUPT Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 ALARM Enable interrupt generation for when the alarm time and date match the current time and date 0 Alarm interrupt is disabled 1 Alarm interrupt is enabled 2 TIME...

Page 1339: ...llator compensation value The AUTOCOMP bit in the control register CTRL must be enabled for compensation to take place The COMPLSB register is shown in Figure 27 20 and described in Table 27 19 Figure 27 20 Compensation LSB Register COMPLSB 31 16 Reserved R 0 15 8 7 0 Reserved COMPLSB R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 27 19 Compensations Register COMPLSB Field D...

Page 1340: ...llator compensation value The AUTOCOMP bit in the control register CTRL must be enabled for compensation to take place The COMPMSB register is shown in Figure 27 21 and described in Table 27 20 Figure 27 21 Compensation MSB Register COMPMSB 31 16 Reserved R 0 15 8 7 0 Reserved COMPMSB R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 27 20 Compensations Register COMPMSB Field D...

Page 1341: ...d described in Table 27 21 Figure 27 22 Oscillator Register OSC 31 16 Reserved R 0 15 6 5 4 0 Reserved SWRESET Reserved R 0 W 0 R W 7h LEGEND R W Read Write R Read only W Write only n value after reset Table 27 21 Oscillator Register OSC Field Descriptions Bit Field Value Description 31 6 Reserved 0 Reserved 5 SWRESET Software reset Always reads back 0 0 No action 1 Reset RTC module and registers ...

Page 1342: ...ers SCRATCHn Field Descriptions Bit Field Value Description 31 0 SCRATCHn 0 FFFF FFFFh General purpose 32 bit registers that have no effect on RTC functionality 27 3 21 Kick Registers KICK0R KICK1R The kick registers KICKnR are used to enable and disable write protection on the RTC registers Out of reset the RTC registers are write protected To disable write protection correct keys must be written...

Page 1343: ...2016 Texas Instruments Incorporated Serial ATA SATA Controller Chapter 28 SPRUH82C April 2013 Revised September 2016 Serial ATA SATA Controller This chapter describes the serial ATA SATA controller Topic Page 28 1 Introduction 1344 28 2 Architecture 1348 28 3 Use Cases 1353 28 4 Registers 1373 ...

Page 1344: ... PATA as well as extending PATAs capabilities The SATA controller that is supported by this device supports AHCI mode of operation only AHCI is a PCI class device that acts as a data movement engine between system memory and serial ATA devices However the AHCI controller on this device is integrated within the core chipset a common attribute for embedded devices The AHCI controller supported has n...

Page 1345: ...res not supported in this SATA controller are Legacy mode of operation Master slave type of configuration Far end analog loopback Message signaled interrupts 64 bit addressing 28 1 4 Functional Block Diagram The SATA subsystem SATASS is a fully contained serial ATA host with built in DMA It uses the AHCI standard for communication with a SATA device It has no support for the Legacy mode of operati...

Page 1346: ...packet interface CF Compact Flash device External SATA or ATAPI device attached to the SATA controller DMA DMA within the ATA controller not the processor EDMA system DWORD DWORD is 32 bits of data command list A memory buffer for as much as 32 commands Each command is entered in a command slot This is a required feature when supporting command queuing command slot A subset of the command list It ...

Page 1347: ...rd The PRD describes memory regions to be used as the source or destination of data during DMA transfers A PRD table is often referred to as a scatter gather list PM Port Multiplier A Port Multiplier allows extending an HBA port connection capability to connect to multiple SATA devices a maximum of 15 devices Note that the operating bandwidth is shared amongst all the Devices when using this type ...

Page 1348: ...to the SATA controller is gated by the PSC and is required to be enabled prior to accessing the SATA controller SYCLK4 PLL0 output frequency divided by 4 is the keep alive clock and is always ON A high quality low jitter external differential clock is required as a source clock input for the PHY and the frequency of the input clock should be between 75MHz and 375 MHz depending upon the supported m...

Page 1349: ...VSS Ground SATA PHY ground reference 28 2 3 Pin Multiplexing Extensive pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings Refer to the device specific data manual to determine how pin multiplexing a...

Page 1350: ...transaction size is the minimum amount of data that the DMA works on For example if there is a FIS coming from the device to the host the DMA does not begin transferring data into system memory until there is at least rx_transaction_size RXTS data in the receive FIFO During transmit the DMA reads data from system memory in tx_transaction_size TXTS increments to put into the transmit FIFO Note that...

Page 1351: ...ontroller PHY initialization structures and memories for Command Slots FIS and Data Memories are configured and the FIS DMAs is enabled The software will then spin up the device and ensure that a proper Device Detection and Speed Negotiation has completed prior to enabling the Command DMA Note that DMA Configuration Initialization should take place after Device Detection and Speed Negotiation If d...

Page 1352: ...mpletion coalescing ports register CCC_PORTS should be programmed with 1 to indicate that the single available port Port0 is selected For a detailed explanation of the CCC initialization and usage see the AHCI Specification 1 1 Section 11 6 28 2 11 1 1 CCC Interrupt Based on Timer Expiration When CCC is enabled and the desired method to receive an interrupt is based on a timer elapse condition the...

Page 1353: ...ocedures using the PSC see the Power and Sleep Controller PSC chapter During times of the SATA peripheral use the SATASS supports the industry standard power down modes both Partial and Slumber low power modes as provided within the SATA specification These modes allow for power savings through powering down part of the SERDES PHY and the ability to gate off the clocks to the link layer The Port P...

Page 1354: ...H PRDLENGTH DATABUFFERLEN define NUMOFPORTS 1 Freon Supports A Single HBA Port However it can support up to 16 additional Ports with the use of an external Port Multiplier So keep this value to 1 define LISTLENGTH 2 Max Command Header Per Port is 32 define WRITE_CMD_SLOT 0 Value used here should be LISTLENGTH 1 define READ_CMD_SLOT 1 Value used here should be LISTLENGTH 1 WARNING PRDLENGTH can not...

Page 1355: ...st Base Address should be 1K Byte Aligned typedef struct Uint32 CmdLen 5 bits 4 0 Uint32 Atapi 1 bit 5 Uint32 Write 1 bit 6 Uint32 Prefetch 1 bit 7 Uint32 Reset 1 bit 8 Uint32 Bist 1 bit 9 Uint32 Rok 1 bit 10 Uint32 Rsv 1 bit 11 Uint32 Pmp 4 bits 15 12 Uint32 Prdtl 16 bits 31 16 CmdListHeaderW0 typedef struct Uint32 PrdByteCnt bits 31 0 CmdListHeaderW1 typedef struct Uint32 CmdTableAddLowRsv 7 bit...

Page 1356: ...B2Rsv 8 bits 23 16 Uint32 B3Control 8 bits 31 24 CmdFisWord3 typedef struct Uint32 DWResv bits 31 0 CmdFisWord4 typedef struct CmdFisWord0 DW0 CmdFisWord1 DW1 CmdFisWord2 DW2 CmdFisWord3 DW3 CmdFisWord4 DW4 Uint32 DW5 Uint32 DW6 Uint32 DW7 Uint32 DW8 Uint32 DW9 Uint32 DW10 Uint32 DW11 Uint32 DW12 Uint32 DW13 Uint32 DW14 Uint32 DW15 CommandFIS Command FIS end ATAPI Command ATAPI Command Data Struct...

Page 1357: ...S cfis Atapi atapi Uint32 Rsv 12 PRDT prdTable 16 Have forced this size to 8 in order to meet the minimum required size for Command Table CommandTable Command Table Data Structure end Receive FIS requires the Receive FIS to be 256 byte aligned P0FB should be programmed with this restriction RECEIVE FIS Data Structure Members DMA Setup FIS DSFIS PIO Setup FIS PSFIS D2H Register FIS RFIS Set Device ...

Page 1358: ...p 8 bits 15 8 Uint32 B2Rsv 8 bits 23 16 Uint32 B3Estatus 8 bits 31 24 PioSetupDW3 typedef struct Uint32 HW0XferCnt 16 bits 15 0 Uint32 HW1Rsv 16 bits 31 16 PioSetupDW4 typedef struct PioSetupDW0 DW0 PioSetupDW1 DW1 PioSetupDW2 DW2 PioSetupDW3 DW3 PioSetupDW4 DW4 PIOSetupFis PIO Setup FIS end D2H Reg FIS typedef struct Uint32 B0FisType 8 bits 7 0 Uint32 BYTE1 8 bits 15 8 Uint32 B2Status 8 bits 23 1...

Page 1359: ...This second word is the SACTVE register and the AHCI takes care of updating SACTIVE register at its location typedef struct Uint32 B0FisType 8 bits 7 0 Uint32 BYTE1 8 bits 15 8 Uint32 B2Status 8 bits 23 16 Uint32 B3Errror 8 bits 31 24 SetDevBitsDW0 typedef struct Uint32 W1Rsv bits 31 0 SetDevBitsDW1 typedef struct SetDevBitsDW0 DW0 SetDevBitsDW1 DW1 SetDevBitsFis Set Device Bits FIS end Unkonwn FI...

Page 1360: ...8 dsfisType Uint8 dsfisByte1 Uint32 dsfisDw1DmaBuffLow Uint32 dsfisDw2DmaBuffHigh Uint32 dsfisDw4DmaBuffOffset Uint32 dsfisDw5DmaXferCnt dsFis typedef struct Uint8 psfisType Uint8 psfisByte1 Uint8 psfisStatus Uint8 psfisError Uint8 psfisDw1SecNumLbaLow Uint8 psfisDw1CylLowLbaMid Uint8 psfisDw1CylHighLbahigh Uint8 psfisDw1Dev Uint8 psfisDw3SecCnt Uint8 psfisDw3Estatus Uint16 psfisDw4XferCnt piosFis...

Page 1361: ...FIS 4 sizeof Atapi 4 0 0 Clear PRD Descriptor Locations for Command Header X LISTLENGTH X 0 initMemory Uint32 Uint32 CmdTable cmdSlot 0x80 sata_input_filePageSize sizeof PRDT 4 sata_input_prdLength 0 0 void clearRcvFis clear Receive DMA Setup FIS Space initMemory Uint32 RcvFis sizeof DMASetupFis 4 0 0 clear Receive PIO Setup FIS Space initMemory Uint32 Uint32 RcvFis 0x20 sizeof PIOSetupFis 4 0 0 c...

Page 1362: ... W needs to initialize this variable prior to calling _INT_DRIVEN_TEST_ is defined within the Project File ifdef _INT_DRIVEN_TEST_ intHandlingMethod USE_INT_HANDLER else intHandlingMethod USE_POLLING endif char spinUpDeviceAndWaitForInitToComplete void Make sure that the HBA is in a Listen Mode prior to Spinning Up Device Following Configuration is not allowed P0SCTL DET P0CMD SUD 1 1 NOT Allowed ...

Page 1363: ...ot affected To Do Check if the Global Registers are affected Spec mentions not affected Note COMRESET OOB will not be sent to attached Device because Freon supports Staggered Spinup capability and P0CMD SUD is cleared to Zero when HBA Reset takes place Software needs to invoke this if needed Most likely user want to ensure HBA comes up in its default operation state or has hung and is unable to id...

Page 1364: ...th Command Header 0 PRD Descriptors 0 1 are Initialized CmdTable cmdSlot prdTable sata_input_prdLength fileSIZE prdLength DW0 DbaLow unsigned int prdTableDataBuff cmdSlot prdLength CmdTable cmdSlot prdTable sata_input_prdLength fileSIZE prdLength DW1 DbaHigh 0x0 CmdTable cmdSlot prdTable sata_input_prdLength fileSIZE prdLength DW3 DataBC sata_input_prd_da taBuffLen 1 void setSataSpeed unsigned cha...

Page 1365: ...the alloted data buffers Strucutre type cmdFis holds 8 of the 20 bytes of the FIS These seven elements of the cfis are good enough for majority of command building tasks If need to access other cfis members need to access the cfis member directly Example of how to access the FIS Type cfis Byte0 CmdTable n cfis DW0 B0FisType 0x27 FIS Type is hard coded within buildCmdFis function and Reserved Locat...

Page 1366: ...use Dev28bitLbaAddress 0xFFFFFFFF return 0 void buildCmdFis CommandTable CmdSlotNum DW0 FEATURE COMMAND c r r r port FISTYPE 27h DW1 DEVICE LBA HIGH LBA MID LBA LOW DW2 FETURESexp LBAHIGHexp LBAMIDexp LBALOWexp DW3 CONTROL RESERVED SEC CNTexp SEC CNT DW4 RESERVED RESERVED RESERVED RESERVED CmdSlotNum cfis DW0 B0FisType 0x27 CmdSlotNum cfis DW0 BYTE1 myCmdFis cfisByte1 Make Sure the C bit field is ...

Page 1367: ...PxCMD_FRE AHCI_PxCMD_FRE AHCI_PxCMD_FRE return 1 Enable the Cmd List DMA Engine sataRegs P0CMD AHCI_PxCMD_ST Wait here a bit until the Command List DMA Engine has started to run while sataRegs P0CMD AHCI_PxCMD_CR 0 waitForXms 1 return 0 char submitCmd Uint8 commandType Uint8 commandSlot Make sure both the Command List and Receive FIS DMAs are eanbled and running prior to submiting command Uint16 I...

Page 1368: ...ecord arg NULL CSL_intcPlugEventHandler hIntc myIntcEventHandlerRecord endif Used by both ARM and GEM Processors void sataIsr void intIsrCnt Count interrupt intIsrFlag 1 Ensure all pending Port Interrupts and The Single Global Interrupt are cleared clearIntOrErrorDiag INTFIELDS sataRegs P0IS Clear P0IS and IS Regs 28 3 2 Example on Initialization and Spinning Up Device char hetero_doTest void char...

Page 1369: ...RESET cfgDmaSetting initIntAndClearFlags Disable CCC Initialize 1ms Time Clear Int and Flags if intHandlingMethod USE_INT_HANDLER USE_POLLING or USE_INT_HANDLER Setup Interrupt Handler intIsrFlag 0 sata_intc_setup Configure Interrupt Handler enableDisableInt PORTint ENABLE 0xFFC000FF enableDisableInt int type intState specificField int type GLOBALint or PORTint intState DISABLE or ENABLE enableDis...

Page 1370: ...s not enabled GHC IE is set Interrupt will not be sent to CPU just from Port Level only Write to Disk cmdSlot2Use 0 associateSysMem2Hba cmdSlot2Use Associate Sys Memory to CmdList and PRDs to Cmd Table Initialize PRD Data Buffer Memory initMemory Uint32 prdTableDataBuff cmdSlot2Use sata_input_prdLength DATABUFFERLEN 4 0x12345678 0x01010101 Configure Device 28 bit LBA Address Start Address for Rd W...

Page 1371: ...e1 bit6 is set If need to generate Interrupt at Global Level enable interrupt by setting GHC IE bit field and P0IE xxx should be set to enable particular interrupt Port Level interrupt handling is a subset of Global Level Port Level So long as Global Level interrupt is not enabled GHC IE is set Interrupt will not be sent to CPU just from Port Level only Read from Disk cmdSlot2Use 1 associateSysMem...

Page 1372: ...the I bit set has transferred all of its data This bitfield might not bit set for Non Queued DMA Applicable for Queued DMA while getRegStatus Uint32 sataRegs P0IS AHCI_P0IS_DPS 0 getRegStatus ptr2int field Mask while getRegStatus Uint32 sataRegs P0CI 1 cmdSlot2Use 1 cmdSlot2Use Wait Until P0CI ChHeader to be cleared by HBA Clears both P0IS and IS register Only Clears RWC bit fields So it is OK for...

Page 1373: ...calls for the support of multiple Host ports and the register space partitioning comes from this perspective All registers that start below offset address 100h are global and meant to apply to the entire HBA The port control registers are the same for all ports and there are as many register banks as there are ports for hosts with multiple ports This device supports only one HBA port and has a sin...

Page 1374: ...obal Parameter 1 Register Section 28 4 14 ECh GPARAM2R Global Parameter 2 Register Section 28 4 15 F0h PPARAMR Port Parameter Register Section 28 4 16 F4h TESTR Test Register Section 28 4 17 F8h VERSIONR Version Register Section 28 4 18 FCh IDR ID Register Section 28 4 19 100h P0CLB Port Command List Base Address Register Section 28 4 20 108h P0FB Port FIS Base Address Register Section 28 4 21 110...

Page 1375: ...ritable once after power up 26 SALP 1 Supports Aggressive Link Power Management SATASS supports auto generating Port initiated Link Layer requests to the PARTIAL or SLUMBER power management states when there are no commands to process 25 SAL 1 Supports Activity LED 24 SCLO 1 Supports Command List Override Supports the P0CMD CLO bit functionality for Port Multiplier devices enumeration 23 20 ISS 2h...

Page 1376: ...0 2 Reserved 0 Reserved 1 IE Interrupt Enable This global bit enables interrupts from the SATASS This field is reset on Global reset GHC HR 1 0 All interrupt sources from all the Ports are disabled masked 1 Interrupts are enabled and any SATASS interrupt event causes interrupt output assertion 0 HR 0 HBA Reset When set by the software this bit causes an internal Global reset of the SATASS All stat...

Page 1377: ...0 R W1C 0 LEGEND R W Read Write R Read only W1C Write 1 to clear n value after reset Table 28 7 Interrupt Status Register IS Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 IPS n 0 1 Interrupt Pending Status If a bit n is set to 1 If set the corresponding Port has an interrupt pending Software can use this information to determine which Ports require service after an in...

Page 1378: ...set by firmware then remain as read only n value after reset Table 28 8 Ports Implemented Register PI Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 0 PI n 0 1 Ports Implemented This register is bit significant If a bit n is set to 1 the corresponding Port is available for software to use If a bit n is cleared to 0 the Port is not available for software to use The maximu...

Page 1379: ... prior to enabling CCC This bit field is Read Write R W when EN 0 Read only R when EN 1 A time out value of 0 is reserved and should not be used 15 8 CC 0 FFh Command Completions This bit field specifies the number of command completions that are necessary to cause a CCC interrupt Software loads this value prior to enabling CCC This bit field is Read Write R W when EN 0 Read only R when EN 1 A val...

Page 1380: ...set The CCC_PORTS is shown in Figure 28 7 and described in Table 28 11 Figure 28 7 Command Completion Coalescing Ports Register CCC_PORTS 31 0 PRT n R W 0 LEGEND R W Read Write n value after reset Table 28 11 Command Completion Coalescing Ports Register CCC_PORTS Field Description Bit Field Value Description 31 0 PRT n Ports This field is bit significant Each bit n corresponds to a particular Port...

Page 1381: ... Reserved 78h Mid frequency test pattern MFTP 79h 7Dh Reserved 7Eh Low frequency test pattern LFTP 7Fh Simultaneous switching outputs pattern SSOP 80h 8Ah Reserved 8Bh Lone Bit pattern LBP 8Ch AAh Reserved ABh Low frequency spectral component pattern LFSCP ACh B4h Reserved B5h High transition density pattern HTDP B6h F0h Reserved F1h Low transition density pattern LTDP F2h FFh Reserved 7 0 PD 0 FF...

Page 1382: ... PHY Link NOCOMM state BIST Activate FIS is not sent to the device in this mode 15 11 Reserved 0 Reserved 10 8 LLC 0 7h Link Layer Control This bit field controls the Port Link Layer functions scrambler descrambler and repeat primitive drop RPD In normal mode the functions scrambler descrambler or RPD are changed only during Port reset P0SCTL DET 1 Note the different meanings for normal and BIST m...

Page 1383: ...ong pattern version 3 0 PATTERN 0 Fh Defines one of the following SATA compliant patterns for far end retimed far end analog near end analog initiator modes or non compliant patterns for transmit only responder mode when initiated by software writing to the BISTCR TXO bit 0 Simultaneous switching outputs pattern SSOP 1h High transition density pattern 2h Low transition density pattern 3h Low frequ...

Page 1384: ...ST status register BISTSR contains errors detected in the received BIST FIS in the loopback initiator far end retimed far end analog and near end analog modes It is updated each time a new BIST FIS is received It is reset by Global reset Port reset COMRESET or by setting the BISTCR CNTCLR bit The BISTSR is shown in Figure 28 11 and described in Table 28 15 Figure 28 11 BIST Status Register BISTSR ...

Page 1385: ...It is accumulated new value is added to the old value each time a new BIST frame is received The DWERR value does not roll over and freezes if it exceeds FFFF F000h 28 4 13 BIST DWORD Error Count Register TIMER1MS The BIST DWORD error count register TIMER1MS is used to generate 1ms tick for the command completion coalescing CCC logic based on the VBUS clock frequency sourced to the SATA Controller...

Page 1386: ...riptions Bit Field Value Description 31 ALIGN_M 1 Rx Data Alignment Data is always aligned 30 RX_BUFFER 1 Rx Data Buffer Core includes an Rx Data Buffer 29 28 PHY_DATA 0 PHY Data Width Indicates width 0 8 bits 27 PHY_RST 0 PHY Reset Mode Indicates that the phy reset output is active low 26 21 PHY_CTRL 20h PHY Control Width Indicates that there are 32 bits of phy control 20 15 PHY_STAT 2h PHY Statu...

Page 1387: ...1 R 1 R 0 R 0 R 1 8 0 RXOOB_CLK R 96h LEGEND R Read only n value after reset Table 28 19 Global Parameter 2 Register GPARAM2R Field Descriptions Bit Field Value Description 31 15 Reserved 0 Reserved 14 DEV_CP 1 Cold Presence Detect CPD is supported in SATASS 13 DEV_MP 1 Mechanical Presence Switch MP is supported in SATASS 12 ENCODE_M 1 8b 10b Encoding Decoding Indicates 8 bit 10 bit encoding and d...

Page 1388: ... 2 0 RX_MEM_M RX_MEM_S X_FIFO_DEPTH RX_FIFO_DEPTH R 0 R 0 R 0 R 1 LEGEND R Read only n value after reset Table 28 20 Port Parameter Register PPARAMR Field Descriptions Bit Field Value Description 31 10 Reserved 0 Reserved 9 TX_MEM_M 0 Tx FIFO Memory Read Port Type Indicates that the Tx FIFO memory is asynchronous read 8 TX_MEM_S 0 Tx FIFO Memory Type Indicates that the Tx FIFO memory is outside of...

Page 1389: ...function of the DWC SATA AHCI state and does not match the value written 1 Test mode the read back value of the registers matches the value written Normal operation is disabled The following registers are accessed in this mode GHC register IE bit BISTAFR register NCP and PD bits become read write BISTCR register LLC ERREN FLIP PV PATTERN BISTFCTR BISTSR BISTDECR registers become read write P0CLB C...

Page 1390: ...8 18 Version Register VERSIONR 31 0 VERSION R 3133 302Ah LEGEND R Read only n value after reset Table 28 22 Version Register VERSIONR Field Description Bit Field Value Description 31 0 VERSION 3133 302Ah Version of SATASS 28 4 19 ID Register IDR The ID register IDR contains the 32 bit SATASS ID The IDR is shown in Figure 28 19 and described in Table 28 23 Figure 28 19 ID Register IDR 31 0 ID R 4E4...

Page 1391: ... for this port This base is used when fetching commands to execute The structure pointed to by this address range is 1Kbyte in length This address must be 1Kbyte aligned as indicated by bits 9 0 being read only 9 0 Reserved 0 Reserved 28 4 21 Port FIS Base Address Register P0FB The port FIS base address register P0FB contains the 32 bit base address of the destination for incoming received FISes T...

Page 1392: ...transmission One or more of the following errors are detected during Data FIS transfer Protocol P0SERR ERR_P CRC P0SERR DIAG_C Handshake P0SERR DIAG_H PHY Not Ready P0SERR ERR_C Unknown FIS is received with good CRC but the length exceeds 64 bytes PRD table byte count is zero Port DMA transitions to a fatal state until software clears P0CMD ST bit or resets the interface by way of Port or Global r...

Page 1393: ...time together such that the second interrupt is missed when the first PRD interrupt is being cleared 4 UFS 0 1 Unknown FIS Interrupt When set to 1 indicates that an unknown FIS was received and has been copied into system memory This bit is cleared to 0 by software clearing the P0SERR DIAG_F bit to 0 Note The UFS bit does not directly reflect the P0SERR DIAG_F bit P0SERR DIAG_F bit is set immediat...

Page 1394: ...C IE 1 and P0IS HBFS 1 the interq output is asserted 28 HBDE 0 1 Host Bus Data Error Enable When set to 1 GHC IE 1 and P0IS HBDS 1 the intrq output is asserted 27 IFE 0 1 Interface Fatal Error Enable When set to 1 GHC IE 1 and P0IS IFS 1 the intrq output is asserted 26 INFE 0 1 Interface Non fatal Error Enable When set to 1 GHC IE 1 and P0IS INFS 1 the intrq output is asserted 25 Reserved 0 Reserv...

Page 1395: ...ust first bring the link to active and then initiate the transition to the desired low power state 0 No Op Idle When software reads this value it indicates the Port is ready to accept a new interface control command although the transition to the previously selected state may not yet have occurred 1h Active Causes the Port to request a transition of the interface into the active state 2h Partial C...

Page 1396: ...MPS and P0CMD MPSP are set to 1 Note The reset of this bit may change based on the SATA_MP_SWITCH state at reset 0 Switch is closed 1 Switch is open 12 8 CCS 0 1Fh Current Command Slot This bit field is valid when P0CMD ST is set to 1 and is set to the command slot value of the command that is currently being issued by the Port When P0CMD ST transitions from 1 to 0 this bit field is reset to 0 Aft...

Page 1397: ...dge detect from 0 to 1 the Port starts a COMRESET initialization sequence to the device Clearing this bit causes no action on the interface Note the SUD bit is read only 0 on power up until CAP SSS bit is written with the required value 0 ST 0 1 Start When set to 1 the Port processes the command list When cleared the Port does not process the command list Whenever this bit is changed from a 0 to a...

Page 1398: ...task file status register Note the HBA updates the entire 8 bit field 0 ERR Indicates an error during the transfer 1h 2h Reserved 3h DRQ Indicates a data transfer is requested 4h 6h Reserved 7h BSY Indicates the interface is busy 8h FFh Reserved 28 4 26 Port Signature Register P0SIG The port signature register P0SIG contains the Device Signature information The P0SIG is shown in Figure 28 26 and d...

Page 1399: ... Field Value Description 31 12 Reserved 0 Reserved 11 8 IPM 0 Fh Interface Power Management Indicates the current interface state 0 Device is not present or communication is not established 1h Interface in active state 2h Interface in Partial power management state 3h 5h Reserved 6h Interface in Slumber power management state 7h Fh Reserved 7 4 SPD 0 Fh Current Interface Speed Indicates the negoti...

Page 1400: ...transition to If an interface power management state is disabled the Port does not initiate that state and any request from the device to enter that state is rejected via PMNAKp 0 No interface power management state restrictions 1h Transitions to the Partial state are disabled 2h Transitions to the Slumber state are disabled 3h Transitions to both Partial and Slumber states are disabled 4h Fh Rese...

Page 1401: ...0 1 Unknown FIS Type Indicates that one or more FISes were received by the Transport layer with good CRC but had a type field that was not recognized known and the length was less than or equal to 64 bytes Note If the Unknown FIS length exceeds 64 bytes the DIAG_F bit is not set and the DIAG_T bit is set instead 24 DIAG_T 0 1 Transport State Transition Error Indicates that a Transport Layer protoc...

Page 1402: ...nication Error This bit is set to 1 when the PHY Ready signal is negated due to the loss of communication with the device or problems with the interface but not after transition from active to Partial or Slumber power management state 8 ERR_T 0 1 Non recovered Transient Data Integrity Error This bit is set if any of the following P0SERR register bits is set during Data FIS transfer ERR_P Protocol ...

Page 1403: ...n the SActive field of the Set Device Bits FIS The Port only clears bits that correspond to native queued commands that have completed successfully Software should only write to this bit field when P0CMD ST bit is set to 1 This bit field is cleared when P0CMD ST is written from a 1 to a 0 by software This bit field is not cleared by a Port reset COMRESET or a software reset 28 4 31 Port Command Is...

Page 1404: ... 32 Port Serial ATA Notification Register POSNTF 31 16 Reserved R 0 15 0 PMN n R W1C 0 LEGEND R W Read Write R Read only W1C Write 1 to clear n value after reset Table 28 36 Port Serial ATA Notification Register POSNTF Field Description Bit Field Value Description 31 16 Reserved 0 Reserved 15 0 PMN n 0 1 PM Notify Indicates whether a particular device with the corresponding PM Port number issued a...

Page 1405: ...ST 0 and read only when P0CMD ST 1 Note SATASS master breaks the burst at 1Kbyte address boundaries regardless of the RXABL value 0 Limit VBUSP burst size to 256 DWORDS 1h Limit VBUSP Burst size to 1 DWORD 2h Limit VBUSP Burst size to 2 DWORDs 3h Limit VBUSP Burst size to 4 DWORDs 4h Limit VBUSP Burst size to 8 DWORDs 5h Limit VBUSP Burst size to 16 DWORDs 6h Limit VBUSP Burst size to 32 DWORDs 7h...

Page 1406: ...8 7h 128 DWORDs maximum value if P0_RXFIFO_DEPTH 256 8h 256 DWORDs maximum value if P0_RXFIFO_DEPTH 512 9h 512 DWORDs maximum value if P0_RXFIFO_DEPTH 1024 Ah 1024 DWORDs maximum value if P0_RXFIFO_DEPTH 2048 Bh Fh Reserved 3 0 TXTS 0 Fh Transmit Transaction Size TX_TRANSACTION_SIZE This field defines the DMA transaction size in DWORDs for transmit system bus read device write operation This bit f...

Page 1407: ...d Write R Read only n value after reset Table 28 38 Port PHY Control Register P0PHYCR Field Descriptions Bit Field Value Description 31 ENPLL Enable Phy PLL This must be enabled by software before initialization is started on the device This bit should not be enabled unless the MPY field has been previously set or is being set in the same write Changing the MPY field while the PLL is enabled disru...

Page 1408: ...the OVERRIDE bit is used if the functional clock is stopped when the link is not in a low power state may ruin the link and cause undetermined behavior A port reset or full SATASS reset may be required to recover 0 Normal 1 Override 29 26 Reserved 0 Reserved 25 22 TXDE 0 Fh Transmitter De Emphasis Selects 1 of 16 output de emphasis settings from 0 to 71 42 Reduction dB 0 0 0 1 4 76 0 42 2h 9 52 0 ...

Page 1409: ...ic variation 4h Second order low precision threshold of 1 Best response to changes in frequency offset and fastest lock time but lowest precision frequency offset matching Suitable for use in systems with spread spectrum clocking 5h Second order low precision threshold of 16 Good response to changes in frequency offset and fast lock time but low precision frequency offset matching Suitable for use...

Page 1410: ...no effect 0 Medium Bandwidth The PLL bandwidth is set to a twelfth of the frequency of REFCLKP N 1h Ultra High Bandwidth The PLL bandwidth is set to one eighth of the frequency of REFCLKP N 2h Low Bandwidth The PLL bandwidth is set to one twentieth of the frequency of RECLKP N or 3 MHz whichever is larger 3h High Bandwidth The PLL bandwidth is set to one tenth of the frequency of REFCLKP N or 3 MH...

Page 1411: ... description is only valid for the configuration GS60 See the corresponding P0PHYSR Register description for each configuration The P0PHYSR is shown in Figure 28 35 and described in Table 28 39 Figure 28 35 Port PHY Status Register P0PHYSR 31 16 Reserved R 0 15 1 0 Reserved SIGDET LOCK R 0 R 0 R 0 LEGEND R Read only n value after reset Table 28 39 Port PHY Status Register P0PHYSR Field Description...

Page 1412: ...pheral Interface SPI Chapter 29 SPRUH82C April 2013 Revised September 2016 Serial Peripheral Interface SPI This chapter describes the serial peripheral interface SPI module See your device specific data manual to determine how many SPIs are available on your device Topic Page 29 1 Introduction 1413 29 2 Architecture 1415 29 3 Registers 1441 ...

Page 1413: ... SPIEMU 16 bit Transmit data register SPIDAT0 and 16 bit Transmit data and format selection register SPIDAT1 8 bit baud clock generator Serial clock SPIx_CLK I O pin Slave in master out SPIx_SIMO I O pin Slave out master in SPIx_SOMI I O pin SPI enable SPIx_ENA I O pin 4 pin or 5 pin mode only Multiple slave chip select SPIx_SCS n I O pins 4 pin or 5 pin mode only Programmable SPI clock frequency ...

Page 1414: ... the SPI block diagram Figure 29 1 SPI Block Diagram NOTE The value x indicates the applicable SPI that is SPI0 SPI1 etc See your device specific data manual to determine how many SPIs are available on your device The value n indicates the SPI pins available See your device specific data manual to determine how many SPI pins are available on your device A Indicates the log controlled by SPI regist...

Page 1415: ...Ix_SIMO Input Output Serial data input in slave mode serial data output in master mode SPIx_SOMI Input Output Serial data output in slave mode serial data input in master mode SPIx_CLK Input Output Serial clock input in slave mode serial clock output in master mode SPIx_SCS n 2 Input Output Slave chip select output in master mode input in slave mode SPIx_ENA Input Output Input in master mode outpu...

Page 1416: ...tion of data on the I O pins Section 29 3 7 1Ch SPIPC2 Pin control register 2 Reflects the values on the I O pins Section 29 3 8 20h SPIPC3 Pin control register 3 Controls the values sent to the I O pins Section 29 3 9 24h SPIPC4 Pin control register 4 Sets data values in the SPIPC3 register Section 29 3 10 28h SPIPC5 Pin control register 5 Clears values in the SPIPC3 register Section 29 3 11 38h ...

Page 1417: ... 0 0 0 0 SPIGCR1 CLKMOD 1 1 1 1 SPIGCR1 MASTER 1 1 1 1 SPIPC0 SOMIFUN 1 1 1 1 SPIPC0 SIMOFUN 1 1 1 1 SPIPC0 CLKFUN 1 1 1 1 SPIPC0 ENAFUN 0 0 1 1 SPIPC0 SCS0FUN 0 1 0 1 Table 29 4 Allowed SPI Register Settings in Master Modes Register Bit s Master 3 pin Master 4 pin Chip Select Master 4 pin Enable Master 5 pin SPIINT0 ENABLEHIGHZ 0 1 0 1 0 1 0 1 SPIFMTn WDELAY 0 to 3Fh 0 to 3Fh 0 to 3Fh 0 to 3Fh SP...

Page 1418: ...that if SPIDELAY T2CDELAY 0 then the T2CDELAY period 0 If the PHASE bit in the SPI data format register n SPIFMTn is 0 then the T2CDELAY period lasts for an additional 1 2 SPIx_CLK time over that specified by the above equation The current value of the CSHOLD bit in the SPI transmit data register SPIDAT1 must be cleared to 0 for T2C delay to be enabled NOTE If the SPIDAT1 CSHOLD bit is set within ...

Page 1419: ...n certain cases the allowed values may still be ignored For complete details on each mode see the following sections that explain the SPI operation for each of the slave modes Table 29 5 SPI Register Settings Defining Slave Modes Register Bit s Slave 3 pin Slave 4 pin Chip Select Slave 4 pin Enable Slave 5 pin SPIGCR0 RESET 1 1 1 1 SPIGCR1 ENABLE 1 1 1 1 SPIGCR1 LOOPBACK 0 0 0 0 SPIGCR1 CLKMOD 0 0...

Page 1420: ...both must be programmed to 1 to configure the SPI for master mode or to 0 to configure the SPI for slave mode The SPI bus master is the device that drives the SPIx_CLK signal and initiates SPI bus transfers In SPI master mode the SPIx_SOMI pin output buffer is in a high impedance state and the SPIx_CLK and the SPIx_SIMO pin output buffer is enabled In SPI slave mode the SPIx_SIMO and SPIx_CLK pin ...

Page 1421: ...x_SIMO and SPIx_SCS n pin output buffer is in a high impedance state and the SPIx_SOMI pin output buffer is enabled when SPIx_SCS n is asserted and in a high impedance state when SPIx_SCS n is deasserted In slave mode with the chip select option enabled the SPI ignores all transactions on the bus unless SPIx_SCS n is asserted by the bus master It also 3 states its output pin when SPIx_SCS n is dea...

Page 1422: ...it Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Serial Peripheral Interface SPI Figure 29 3 SPI 4 Pin Option with SPIx_SCS n NOTE During an SPI transfer if the slave mode SPI detects a deassertion of its chip select even before its internal character length counter overflows then it 3 states its SPIx_SOMI pin Once this condition has occurred if a SPIx_CLK edge is detec...

Page 1423: ...orks this way After a transfer completes both the master and slave SPI modules need to be serviced The slave SPI deasserts SPIx_ENA after the transfer indicating it requires servicing and is not ready The slave should begin servicing its SPI by first reading receive data from the SPI receive buffer register SPIBUF Next the slave device should write transmit data to the SPI transmit data registers ...

Page 1424: ...IMO Master MASTER 1 CLKMOD 1 SPIBUF SPIDAT1 CPU DMA write CPU DMA read SPIDAT1 SPIBUF CPU DMA read CPU DMA write SPIx_ENA SPIx_ENA Architecture www ti com 1424 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Serial Peripheral Interface SPI Figure 29 4 SPI 4 Pin Option with SPIx_ENA ...

Page 1425: ...ends upon the status of the transmit buffer and the state of the SPIx_SCS n input In SPI slave mode the assertion of the SPIx_ENA pin by the slave is delayed until the master asserts SPIx_SCS n thereby allowing multiple SPI slaves on a single SPI bus each slave with its own enable pin If the SPIx_ENA pin is in high impedance mode ENABLEHIGHZ 1 in the SPI interrupt register SPIINT0 the slave SPI wi...

Page 1426: ... 5 Pin Option with SPIx_ENA and SPIx_SCS n NOTE Push Pull mode of the SPIx_ENA pin can be used only when there is a single slave in the system When there are multiple SPI slave devices connected to the common SPIx_ENA pin all the slaves should configure their SPIx_ENA pins in high impedance mode During an SPI transfer if slave mode SPI detects a deassertion of its chip select even before its inter...

Page 1427: ...by the SPIFMTn CHARLEN bit Legal values are 2 bits 2h to 16 bits 10h The character length is independently configured for each of the four data formats and it must be programmed in both master mode and slave mode Transmit data is written to SPIDAT1 The transmit data must be written right justified irrespective of the character length The SPI automatically sends out the data correctly based on the ...

Page 1428: ...SPIDAT1 is written and before the first edge of SPIx_CLK The data input and output edges depend on the values of both the POLARITY and PHASE bits as shown in Table 29 7 Table 29 7 Clocking Modes POLARITY PHASE Action 0 0 Data is output on the rising edge of SPIx_CLK Input data is latched on the falling edge 0 1 Data is output one half cycle before the first rising edge of SPIx_CLK and on subsequen...

Page 1429: ...SPIx_CLK A write to the SPIDAT register starts SPIx_CLK Clock polarity 1 Clock phase 0 1 2 3 4 5 6 7 8 LSB D1 D2 D3 D4 D5 D6 MSB D0 D1 D2 D3 D4 D5 D6 D7 Write SPIDAT SPIx CLK _ SPIx SIMO _ SPIx_SOMI Sample in reception Clock phase 1 SPIx_CLK with delay Data is output one half cycle before the first rising of SPI CLK and on subsequent falling edges of SPI CLK Input data is latched on the rising edg...

Page 1430: ... a character length of five bits Figure 29 12 Five Bits per Character 5 Pin Option 29 2 12 Interrupt Support The SPI interrupt system is controlled by three registers The SPI interrupt level register SPILVL controls the interrrupt level The interrupt level must be set to select the level one interrupt INT1 The SPI interrupt register SPIINT contains bits to selectively enable disable each interrupt...

Page 1431: ...y the SPI master continually monitors the bus for faults on its data line The handshaking between master and slave can be monitored as well and appropriate actions can be taken interrupt timeout when the handshake breaks down The following sections describe these robustness features in more detail 29 2 14 1 SPI Internal Loopback Test Mode Master Only CAUTION The internal loop back self test mode s...

Page 1432: ...lave device does not deassert the SPIx_ENA signal before the T2EDELAY timeout value expires the SPIFLG DESYNC flag is set and a desynchronization interrupt is asserted if enabled The T2E delay period does not always complete sometimes it is skipped or terminated early The T2E delay period terminates immediately after the SPIx_ENA input is sampled using the SPI module clock at intervals of SPIFMTn ...

Page 1433: ...will be generated only if the SPIx_SCS n pin is configured as a functional pin 29 2 15 Reset Considerations This section describes the software and hardware reset considerations 29 2 15 1 Software Reset Considerations The SPI module contains a software reset RESET bit in the SPI global control register 0 SPIGCR0 that is used to reset the SPI module As a result of a reset the SPI module register va...

Page 1434: ...dule does not support soft or hard stop during emulation breakpoints The SPI module will continue to run if an emulation breakpoint is encountered In addition any status registers that are cleared after reading will be affected if viewed in a memory or watch window of the debugger since the emulator will read these registers to update the value displayed in the window 29 2 19 Initialization Perfor...

Page 1435: ...lustrating the C2TDELAY C2EDELAY T2CDELAY T2EDELAY and WDELAY delays and their interaction with the SPIx_SCS n and SPIx_ENA pins for all SPI modes 29 2 20 1 SPI 3 Pin Mode Figure 29 13 illustrates the WDELAY option in SPI 3 pin master mode This is the only delay available in this mode In CASE1 a new transfer is initiated during the WDELAY period and the transfer begins immediately after the WDELAY...

Page 1436: ...erted during the T2EDELAY period Consequently the T2EDELAY period is terminated early a and the WDELAY period begins immediately b if enabled The next transfer is initiated as soon as the slave asserts SPIx_ENA again In CASE2 the T2EDELAY period c completes before the SPIx_ENA is deasserted As a result the DESYNC error is set However since the SPIx_ENA is deasserted during the WDELAY period d the ...

Page 1437: ... error set SPI CLK i x_ SPI CLK ii x_ SPI CLK iii x_ SPI CLK iv x_ SPI ENA x_ e T2EDELAY f WDELAY Deasserted Case 3 Desync error set Deasserted www ti com Architecture 1437 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Serial Peripheral Interface SPI Figure 29 15 SPI 4 Pin with SPIx_ENA Mode Demonstrating T2EDELAY and WD...

Page 1438: ...d then the DESYNC error is not set The SPI master behavior in this case depends on whether the SPIx_ENA gets deasserted during the T2CDELAY period CASE1 WDELAY period CASE3 or after the WDELAY period completes CASE4 If the slave deasserts the SPIx_ENA signal before the completion of the configured master delays T2CDELAY T2EDELAY WDELAY then the master delays the next transfer until the slave asser...

Page 1439: ...PIx_ENA f T2CDELAY g T2EDELAY Case 3 Deasserted SPIx_SCS n h WDELAY Desync error set SPIx_CLK i SPIx_CLK ii SPIx_CLK iii SPIx_CLK iv SPIx_ENA j T2CDELAY k T2EDELAY Case 4 Deasserted SPIx_SCS n m WDELAY Desync error set www ti com Architecture 1439 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Serial Peripheral Interface ...

Page 1440: ...SCS n x_ SPI ENA x_ d C2EDELAY f C2TDELAY Deasserted Pol 0 Ph 0 Pol 0 Ph 1 Pol 1 Ph 0 Pol 1 Ph 1 SPI CLK x_ Case 3 SPI CLK x_ SPI CLK x_ SPI CLK x_ SPI SCS n x_ SPI ENA x_ g C2EDELAY Deasserted Timeout error set Architecture www ti com 1440 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Serial Peripheral Interface SPI Fig...

Page 1441: ...r 5 Clear SPIPC3 Section 29 3 11 38h SPIDAT0 SPI Data Transmit Register 0 Section 29 3 12 3Ch SPIDAT1 SPI Data Transmit Register 1 Data Transmit and Format Select Section 29 3 13 40h SPIBUF SPI Receive Buffer Register Section 29 3 14 44h SPIEMU SPI Receive Emulation Register Section 29 3 15 48h SPIDELAY SPI Delay Register Section 29 3 16 4Ch SPIDEF SPI Default Chip Select Register Section 29 3 17 ...

Page 1442: ... get dropped When ENABLE bit is cleared to 0 the following SPI registers get forced to their default states to 0s except for RXEMPTY bit in SPIBUF Both TX and RX shift registers The TXDATA fields of SPIDAT0 and SPIDAT1 registers All the fields of the SPIFLG register Contents of SPIBUF and the internal RXBUF registers 0 SPI is not activated for transfers 1 Activates SPI 23 17 Reserved 0 Reads retur...

Page 1443: ... 0 SLAVE MODE SPIx_CLK is an input from the master who initiates the transfers Data is transmitted on the SPIx_SOMI pin and received on the SPIx_SIMO pin The SPIx_SCS n pin is an input pin if configured as SPI slave chip select The SPIx_ENA pin is an output pin if configured as the SPI enable pin 1h 2h Reserved 3h MASTER MODE SPIx_CLK is an output and the SPI initiates transfers Data is transmitte...

Page 1444: ...Enables the DMA request signal to be generated for both receive and transmit channels Set DMAREQEN only after setting the SPIGCR1 ENABLE bit to 1 0 DMA is not used 1 DMA requests will be generated Note A transmit DMA request will be generated each time a transmit data is copied to the shift register either from TXBUF or directly from SPIDAT0 SPIDAT1 Note A receive DMA request will be generated eac...

Page 1445: ...e SPIFLG PARERRFLG is set 0 No interrupt asserted upon parity error 1 Enables an interrupt on a parity error 1 TIMEOUTENA Enables interrupt on SPIx_ENA signal time out An interrupt is to be generated when SPIFLG TIMEOUTFLG is set 0 No interrupt asserted upon SPIx_ENA signal time out 1 Enables an interrupt on a time out of the SPIx_ENA signal 0 DLENERRENA Data length error interrupt enable A data l...

Page 1446: ...erved 1 Receive interrupt is mapped to interrupt line INT1 7 Reserved 0 Reads return zero and writes have no effect 6 OVRNINTLVL Receive overrun interrupt level The overrun interrupt is not useful if receive data is serviced with CPU interrupts because the overrun and receive events share a common level interrupt signal 0 Reserved 1 Receive overrun interrupt is mapped to interrupt line INT1 5 Rese...

Page 1447: ...C1 register when there is a receive buffer full interrupt Writing a 1 to this bit Writing a 0 to SPIGCR1 ENABLE System reset 0 No new received data pending Receive buffer is empty 1 A newly received data is ready to be read Receive buffer is full Note Clearing RXINTFLG bit by writing a 1 before reading the SPIBUF sets the RXEMPTY bit of the SPIBUF register too This way one can ignore a received da...

Page 1448: ...f this error under some circumstances it is possible for a desynchronized error detected for the previous buffer to be visible in the current buffer This is due to the fact that receive completion flag interrupt will be generated when the buffer transfer is completed But decence will be detected after the buffer transfer is completed So if CPU DMA reads the received data quickly when an receive in...

Page 1449: ...ral purpose I O pin or as a SPI functional pin 0 SPIx_SOMI pin is a GPIO pin 1 SPIx_SOMI pin is a SPI functional pin 10 SIMOFUN Slave in master out pin function This bit determines whether the SPIx_SIMO pin is to be used as a general purpose I O pin or as a SPI functional pin 0 SPIx_SIMO pin is a GPIO pin 1 SPIx_SIMO pin is a SPI functional pin 9 CLKFUN SPI clock pin function This bit determines w...

Page 1450: ...tion Controls the direction of the SPIx_SIMO pin when it is used as a general purpose I O pin If the SPIx_SIMO pin is used as a SPI functional pin the I O direction is determined by whether the SPI is configured as master or slave 0 SPIx_SIMO pin is an input 1 SPIx_SIMO pin is an output 9 CLKDIR SPIx_CLK pin direction Controls the direction of the SPIx_CLK pin when it is used as a general purpose ...

Page 1451: ... zero and writes have no effect 11 SOMIDIN SPIx_SOMI data in This bit reflects the value of the SPIx_SOMI pin 0 Current value of SPIx_SOMI pin is logic 0 1 Current value of SPIx_SOMI pin is logic 1 10 SIMODIN SPIx_SIMO data in This bit reflects the value of the SPIx_SIMO pin 0 Current value of SPIx_SIMO pin is logic 0 1 Current value of SPIx_SIMO pin is logic 1 9 CLKDIN Clock data in This bit refl...

Page 1452: ...logic 1 10 SIMODOUT SPIx_SIMO data out write This bit is only active when the SPIx_SIMO pin is configured as a general purpose I O pin and configured as an output pin The value of this bit indicates the value sent to the pin 0 Current value of SPIx_SIMO pin is logic 0 1 Current value of SPIx_SIMO pin is logic 1 9 CLKDOUT SPIx_CLK data out write This bit is only active when the SPIx_CLK pin is conf...

Page 1453: ...pose output pin Reads return the value of the SPIx_SOMI pin Write 0 No effect Write 1 SPIPC3 SOMIDOUT is set to 1 10 SIMOSET SPIx_SIMO data out set This bit is only active when the SPIx_SIMO pin is configured as a general purpose output pin Reads return the value of the SPIx_SIMO pin Write 0 No effect Write 1 SPIPC3 SIMODOUT is set to 1 9 CLKSET SPIx_CLK data out set This bit is only active when t...

Page 1454: ...in Reads return the value of the SPIx_SOMI pin Write 0 No effect Write 1 SPIPC3 SOMIDOUT is cleared to 0 10 SIMOCLR SPIx_SIMO data out clear This bit is only active when the SPIx_SIMO pin is configured as a general purpose output pin Reads return the value of the SPIx_SIMO pin Write 0 No effect Write 1 SPIPC3 SIMODOUT is cleared to 0 9 CLKCLR SPIx_CLK data out clear This bit is only active when th...

Page 1455: ...Field Value Description 31 16 Reserved 0 Reads return zero and writes have no effect 15 0 TXDATA 0 FFFFh SPI transmit data When written these bits will be copied to the shift register if it is empty If the shift register is not empty the TXBUF will hold the written values SPIGCR1 ENABLE must be set to 1 before this register can be written to Writing a 0 to the SPIGCR1 ENABLE forces the TXDATA fiel...

Page 1456: ...bit is supported in master mode only In slave mode this bit is ignored 0 No delay will be inserted However SPIx_SCS n pin will still be deactivated for at least 2 SPI module clock cycles if CSHOLD 0 1 After a transaction SPIFMTn WDELAY of the selected data format will be loaded into the delay counter No transaction will be performed until the SPIFMTn WDELAY counter overflows The SPIx_SCS n pin wil...

Page 1457: ...is flag gets set to 1 under following conditions Reading the RXDATA field of the SPIBUF register Writing 1 to clear the RXINTFLG bit in the SPIFLG register 0 New data has been received and copied into the SPIBUF register 1 No data received since last reading of the SPIBUF register Write Clearing the SPIFLG RXINTFLG bit before reading the SPIBUF register indicates the received data is being ignored...

Page 1458: ...ces it is possible for a desync error detected for the previous buffer to be visible in the current buffer This is because the receive completion flag interrupt will be generated when the buffer transfer is completed But desync will be detected after the buffer transfer is completed So if CPU DMA reads the received data quickly when an RXINT is detected then the status flag may not reflect the cor...

Page 1459: ...scribed in Table 29 23 Figure 29 32 SPI Emulation Register SPIEMU 31 16 Reserved R 0 15 0 RXDATA R 0 LEGEND R Read only n value after reset Table 29 23 SPI Emulation Register SPIEMU Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reads return zero and writes have no effect 15 0 RXDATA 0 FFFFh SPI receive data SPI emulation is a mirror of the SPIBUF register The only difference betw...

Page 1460: ...ditional 0 5 SPIx_CLK period delay This delay is as per the SPI protocol 23 16 T2CDELAY 0 FFh Transmit end to chip select inactive delay T2CDELAY is used in master mode only It defines a hold time for the slave device that delays the chip select deactivation by a multiple of SPI module clock cycles after the last bit is transferred T2CDELAY can be configured between 2 and 256 SPI module clock cycl...

Page 1461: ... SPI detects a deassertion of the SPIx_ENA pin even before the end of the transmission See Figure 29 36 The time out value is calculated as follows tT2EDELAY T2EDELAY SPIclock Example SPIclock 8 Mbit s T2EDELAY 10h tT2EDELAY 2 μs The slave device has to disable the SPIx_ENA signal within 2 μs otherwise the DESYNC flag in SPIFLG is set and an interrupt is asserted if enabled 7 0 C2EDELAY 0 FFh Chip...

Page 1462: ...ers www ti com 1462 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Serial Peripheral Interface SPI Figure 29 35 Example tT2CDELAY 4 SPI Module Clock Cycles Figure 29 36 Transmit Data Finished to SPIx_ENA Inactive Timeout Figure 29 37 Chip Select Active to SPIx_ENA Signal Active Timeout ...

Page 1463: ...able 29 25 SPI Default Chip Select Register SPIDEF Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reads return zero and writes have no effect 7 0 CSDEF n Chip select default pattern The CSDEF field defines the state of the the SPIx_SCS n pins when no transmissions are performed The value of the CSDEF field is driven directly on the SPIx_SCS n pins Each bit in the CSDEF field corres...

Page 1464: ...smit data stream At the end of a transfer the parity generator compares the received parity bit with the locally calculated parity flag If the parity bits do not match the PARERR flag is set in the corresponding control field The parity type even or odd can be selected via the PARPOL bit 21 WAITENA The master waits for SPIx_ENA signal from slave WAITENA is considered in master mode only In slave m...

Page 1465: ...econd inverse clock edge 1 SPI clock signal is delayed by a half SPI clock cycle versus the transmit receive data stream The first transmit bit has to output prior to the first clock edge The master and slave receive the first bit with the first edge 15 8 PRESCALE 2h FFh SPI prescaler It determines the bit transfer rate if the SPI is the network master and is directly derived from the SPI module c...

Page 1466: ...The INTVECT1 field just reflects the status of SPIFLG in a vectorized format So any updates to SPIFLG will automatically reflect in the vector value in this register Vectors for each of these interrupts will be reflected on the INTVECT1 bits when they occur Reading the vectors for the receive buffer overrun and receive buffer full interrupts will automatically clear the respective flags in the SPI...

Page 1467: ... 64 Bit Timer Plus Chapter 30 SPRUH82C April 2013 Revised September 2016 64 Bit Timer Plus This chapter describes the operation of the software programmable 64 bit Timer Plus See your device specific data manual to determine how many Timer modules are available on your device Topic Page 30 1 Introduction 1468 30 2 Registers 1486 ...

Page 1468: ...y mechanism for the device in the event of a fault condition such as a non exiting code loop 30 1 2 Features The 64 bit timer consists of the following features some features may not be supported on all timer instantiations see your device specific data manual for supported features 64 bit count up counter Timer modes 64 bit general purpose timer mode Dual 32 bit unchained general purpose timer mo...

Page 1469: ...ard Compatibility Statement This peripheral is not intended to conform to any specific industry standard Architecture 30 1 5 Architecture General Purpose Timer Mode This section describes the timer in the general purpose GP timer mode 30 1 5 1 Backward Compatible Mode The Timer Plus supports the following additional features over the other timers External clock event input Period reload External e...

Page 1470: ...clock cycles For details on the generation of the on chip clocks see the Phase Locked Loop Controller PLLC chapter The CLKSRC12 parameter in the timer control register TCR determines whether an internal or external clock is used as the clock source for the timer If the timer is configured in 64 bit mode or 32 bit chained mode CLKSRC12 controls the clock source for the entire timer If the timer is ...

Page 1471: ... 5 4 Timer Modes The following section describes the general purpose GP timer modes 30 1 5 4 1 64 Bit Timer Mode The timer can be configured as a 64 bit timer by clearing the TIMMODE bit in the timer global control register TGCR to 0 At reset 0 is the default setting for the TIMMODE bit In this mode the timer operates as a single 64 bit up counter Figure 30 3 The counter registers TIM12 and TIM34 ...

Page 1472: ...o disable the 64 bit timer out of reset 1h 1h 0 To enable the 64 bit timer for one time operation 1h 1h 1h To enable the 64 bit timer for continuous operation 1h 1h 2h To enable the 64 bit timer for continuous operation with period reload 1h 1h 3h Once the timer stops if an external clock is used as the timer clock the timer must remain disabled for at least one external clock period or the timer ...

Page 1473: ...ale counter register and one period register PRD34 to form a 32 bit prescale period register When the timer is enabled the prescale counter starts incrementing by 1 at every timer input clock cycle One cycle after the prescale counter matches the prescale period a clock signal is generated and the prescale counter register is reset to 0 see the example in Figure 30 5 The other 32 bit timer timer 1...

Page 1474: ...uality comparator PRD12 TIM34 PRD34 Input clock 32 bit prescaler Timer 3 4 Pulse generator CLKSRC12 Timer interrupt TINT12 to CPU interrupt controller Timer event TEVT12 to DMA controller 0 1 Reload period PRD34 Output event to TM64P_OUT12 32 bit timer Timer 1 2 Reload period REL12 Introduction www ti com 1474 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 ...

Page 1475: ...counting again Table 30 3 shows the bit values in TGCR to configure the 32 bit timer in chained mode Table 30 3 32 Bit Timer Chained Mode Configurations 32 Bit Timer Configuration TGCR Bit TCR Bit TIM12RS TIM34RS ENAMODE12 To place the 32 bit timer chained mode in reset 0 0 0 To disable the 32 bit timer chained mode out of reset 1h 1h 0 To enable the 32 bit timer chained mode for one time operatio...

Page 1476: ...truments Incorporated 64 Bit Timer Plus 30 1 5 4 2 2 Unchained Mode The general purpose timers can be configured as a dual 32 bit unchained timers by setting the TIMMODE bit to 1 in TGCR In the unchained mode Figure 30 6 the timer operates as two independent 32 bit timers One 32 bit timer timer 3 4 operates as a 32 bit timer being clocked by a 4 bit prescaler The other 32 bit timer timer 1 2 opera...

Page 1477: ...m the 4 bit prescaler see the example in Figure 30 7 The timer counter increments by 1 at every prescaler output clock cycle When the timer counter matches the period a maskable timer interrupt TINT34 and a timer DMA event TEVT34 are generated When the timer is configured in continuous mode the timer counter is reset to 0 on the cycle after the timer counter reaches the timer period The timer can ...

Page 1478: ...g again Table 30 4 shows the bit values in TGCR to configure the 32 bit timer in unchained mode Once the timer stops if an external clock is used as the timer clock the timer must remain disabled for at least one external clock period or the timer will not start counting again When using the external clock the count value is synchronized to the internal clock Note that when both the timer counter ...

Page 1479: ...the timer cycle is restarted when an external input event occurs on pin TM64P_IN12 In particular when an external input event occurs the timer stops counting generates output events TINT12 TEVT12 and TM64P_OUT12 copies values from the timer counter register TIM12 to the timer capture register CAP12 reloads the timer period register PRD12 if in continuous mode with period reload ENAMODE 3h and then...

Page 1480: ...4 bit general purpose TIM34 TIM12 PRD34 PRD12 Dual 32 bit chained Prescaler Timer 3 4 TIM34 PRD34 Timer Timer 1 2 TIM12 PRD12 Dual 32 bit unchained Timer Timer 1 2 TIM12 PRD12 Timer with prescaler Timer 3 4 TDDR34 bits and TIM34 PSC34 bits and PRD34 30 1 5 5 Timer Operation Boundary Conditions The following boundary conditions affect the timer operation 30 1 5 5 1 Timer Counter Overflow Timer coun...

Page 1481: ...his periodic servicing the timer counter increments until it matches the timer period and causes a watchdog timeout event When the timeout event occurs the watchdog timer resets the entire processor 30 1 6 2 Watchdog Timer Mode Restrictions The watchdog timer mode has the following restrictions No external clock source No one time enabling 30 1 6 3 Watchdog Timer Mode Operation The watchdog timer ...

Page 1482: ...ounts up waiting for DA7Eh A5C6h to WDKEY DA7Eh to WDKEY counter cleared Time out WDFLAG set WDTINT triggered Other than DA7Eh or A5C6h to WDKEY WDFLAG set WDTINT triggered A5C6h to WDKEY Disabled state Internal clock Input clock 64 bit timer counter 64 bit tmer period Equality comparator TIM34 PRD34 TIM12 PRD12 Watchdog logic and pulse generator CLKSRC12 0 WDEN WDKEY Device level reset Introducti...

Page 1483: ...ns The timer has two reset sources hardware reset and the timer reset TIM12RS and TIM34RS bits in the timer global control register TGCR 30 1 7 1 Software Reset Considerations When the TIM12RS bit in TGCR is cleared to 0 the TIM12 register is held with the current value When the TIM34RS bit in TGCR is cleared to 0 the TIM34 register is held with the current value 30 1 7 2 Hardware Reset Considerat...

Page 1484: ... value specified in the period registers TSTAT12 drives the TM64P_OUT12 pin Table 30 6 gives equations for various TSTAT12 timing parameters in pulse and clock modes The output mode is selected with the clock pulse bit CPn in the timer control register TCR In pulse mode the PWID12 bit in TCR sets the pulse width between 1 to 4 timer clock periods The TM64P_OUT12 pin may be inverted using the INVOU...

Page 1485: ...he timer period registers set the period compare interrupt enable bit PRDINTENn in the interrupt control and status register INTCTLSTAT The event status for this case is reflected in the period compare interrupt status bit PRDINTSTATn which is also in INTCTLSTAT The PRDINTSTATn bit is cleared by writing a 1 to the bit Similarly to generate events in Event Capture Mode set the event interrupt enabl...

Page 1486: ...e Register Section 30 2 3 Ch GPDATGPDIR GPIO Data and GPIO Direction Register Section 30 2 4 10h TIM12 Timer Counter Register 12 Section 30 2 5 14h TIM34 Timer Counter Register 34 Section 30 2 5 18h PRD12 Timer Period Register 12 Section 30 2 6 1Ch PRD34 Timer Period Register 34 Section 30 2 6 20h TCR Timer Control Register Section 30 2 7 24h TGCR Timer Global Control Register Section 30 2 8 28h W...

Page 1487: ...September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated 64 Bit Timer Plus Table 30 8 Timer Registers continued Offset Acronym Register Description Section 7Ch CMP7 Compare Register 7 Timer Compare Registers CMP0 CMP7 ...

Page 1488: ...ister EMUMGT is shown in Figure 30 14 and described in Table 30 10 Figure 30 14 Emulation Management Register EMUMGT 31 16 Reserved R 0 15 2 1 0 Reserved SOFT FREE R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 30 10 Emulation Management Register EMUMGT Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved 1 SOFT Determines emulation mode functionalit...

Page 1489: ... 0 TM64P_OUT12 is used as a TIMER output pin 1 TM64P_OUT12 is used as a GPIO pin 16 GPENI12 Enable TM64P_IN12 to function in GPIO mode 0 TM64P_IN12 is used as a TIMER input pin 1 TM64P_IN12 is used as a GPIO pin 15 6 Reserved 0 Reserved 5 GPINT12INVO Invert interrupt event signal from TM64P_OUT12 when GPINT12ENO 1 0 Rising signal edge on TM64P_OUT12 generates the interrupt event 1 Falling signal e...

Page 1490: ...T12 functions as an input pin in GPIO mode 1 TM64P_OUT12 functions as an output pin in GPIO mode TM64P_OUT12 cannot capture GPIO interrupt events when configured as output 16 GPDIRI12 Select direction of TM64P_IN12 in GPIO mode 0 TM64P_IN12 functions as an input pin in GPIO mode 1 TM64P_IN12 functions as an output pin in GPIO mode TM64P_IN12 cannot capture GPIO interrupt events when configured as ...

Page 1491: ... TIM12 is shown in Figure 30 17 and described in Table 30 13 Figure 30 17 Timer Counter Register 12 TIM12 31 0 TIM12 R W 0 LEGEND R W Read Write R Read only n value after reset Table 30 13 Timer Counter Register 12 TIM12 Field Descriptions Bit Field Value Description 31 0 TIM12 0 FFFF FFFFh TIM12 count bits This 32 bit value is the current count of the main counter 30 2 5 2 Timer Counter Register ...

Page 1492: ...register 12 PRD12 is shown in Figure 30 19 and described in Table 30 15 Figure 30 19 Timer Period Register 12 PRD12 31 0 PRD12 R W 0 LEGEND R W Read Write R Read only n value after reset Table 30 15 Timer Period Register PRD12 Field Descriptions Bit Field Value Description 31 0 PRD12 0 FFFF FFFFh PRD12 period bits This 32 bit value is the number of timer input clock cycles to count 30 2 6 2 Timer ...

Page 1493: ...ins current value 1h The timer is enabled one time The timer stops after the counter reaches the period 2h The timer is enabled continuously TIM34 increments until the timer counter matches the period resets the timer counter to 0 on the cycle after matching and continues 3h The timer is enabled continuously with period reload TIMn increments until the timer counter matches the period resets the t...

Page 1494: ...the cycle after matching reloads the period register with the values in the reload registers RELn and continues counting 5 4 PWID12 0 3h Pulse width Determines the pulse width on the TSTAT12 bit and the TM64P_OUT12 pin when the clock pulse mode is set to pulse 0 TSTAT12 stays active for one timer clock cycle when the timer counter reaches the period 1h TSTAT12 stays active for two timer clock cycl...

Page 1495: ...cycle after matching PRD34 and timer 3 4 continues if timer 3 4 is enabled continuously 11 8 PSC34 0 Fh TIM34 pre scalar counter specifies the count for timer 3 4 7 5 Reserved 0 Reserved 4 PLUSEN Enable new timer plus features 0 Enable backward compatibility New timer features are unavailable 1 Disable backward compatibility New timer features are available 3 2 TIMMODE 0 3h TIMMODE determines the ...

Page 1496: ...ad only n value after reset Table 30 19 Watchdog Timer Control Register WDTCR Field Descriptions Bit Field Value Description 31 16 WDKEY 0 FFFFh 16 bit watchdog timer service key Only the sequence of an A5C6h followed by a DA7Eh services the watchdog Not applicable in regular timer mode 15 WDFLAG Watchdog flag bit WDFLAG can be cleared by enabling the watchdog timer by device reset or being writte...

Page 1497: ...GEND R W Read Write R Read only n value after reset Table 30 20 Timer Reload Register 12 REL12 Field Descriptions Bit Field Value Description 31 0 REL12 0 FFFF FFFFh Period reload bits 30 2 11 Timer Reload Register 34 REL34 The timer reload register 34 REL34 is shown in Figure 30 25 and described in Table 30 21 Figure 30 25 Timer Reload Register 34 REL34 31 0 REL34 R W 0 LEGEND R W Read Write R Re...

Page 1498: ...ead Write R Read only n value after reset Table 30 22 Timer Capture Register 12 CAP12 Field Descriptions Bit Field Value Description 31 0 CAP12 0 FFFF FFFFh Captured timer counter bits 30 2 13 Timer Capture Register 34 CAP34 The timer capture register 34 CAP34 is shown in Figure 30 27 and described in Table 30 23 Figure 30 27 Timer Capture Register 34 CAP34 31 0 CAP34 R W 0 LEGEND R W Read Write R...

Page 1499: ...clear this bit 0 Interrupt has not occurred 1 Interrupt has occurred 18 EVTINTEN34 Enables the interrupt generation when timer is in capture mode 0 Disable interrupt when in event capture mode 1 Enable interrupt when in event capture mode 17 PRDINTSTAT34 Interrupt status which reflects the condition that timer counter matched the period register when timer is enabled Write a 1 to clear this bit 0 ...

Page 1500: ...imer Compare Registers CMP0 CMP7 The timer compare register CMPn is shown in Figure 30 29 and described in Table 30 25 Figure 30 29 Timer Compare Register CMPn 31 0 CMPn R W 0 LEGEND R W Read Write n value after reset Table 30 25 Timer Compare Register CMPn Field Descriptions Bit Field Value Description 31 0 CMPn 0 FFFF FFFFh Timer compare register When PLUSEN 1 in the timer global control registe...

Page 1501: ...ART Chapter 31 SPRUH82C April 2013 Revised September 2016 Universal Asynchronous Receiver Transmitter UART This chapter describes the universal asynchronous receiver transmitter UART peripheral See your device specific data manual to determine how many UARTs are available on your device Topic Page 31 1 Introduction 1502 31 2 Peripheral Architecture 1504 31 3 Registers 1515 ...

Page 1502: ...rallel to serial conversion on data received from the CPU The CPU can read the UART status at any time The UART includes control capability and a processor interrupt system that can be tailored to minimize software management of the communications link The UART includes a programmable baud generator capable of dividing the UART input clock by divisors from 1 to 65535 and producing a 16 reference c...

Page 1503: ...pheral Bus S e l e c t Receiver Shift Register Receiver Timing and Control Transmitter Timing and Control Transmitter Shift Register Control Logic 16 8 8 8 8 8 Interrupt to CPU 16 8 pin pin 8 8 8 8 Power and Emulation Control Register Event to DMA controller www ti com Introduction 1503 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments I...

Page 1504: ...s 16 BCLK cycles or thirteen times 13 the baud rate each received or transmitted bit lasts 13 BCLK cycles When the UART is receiving the bit is sampled in the 8th BCLK cycle for 16 over sampling mode and on the 6th BCLK cycle for 13 over sampling mode The 16 or 13 reference clock is selected by configuring the OSM_SEL bit in the mode definition register MDR The formula to calculate the divisor is ...

Page 1505: ...ships Between Data Bit BCLK and UART Input Clock Table 31 1 Baud Rate Examples for 150 MHZ UART Input Clock and 16 Over sampling Mode Baud Rate Divisor Value Actual Baud Rate Error 2400 3906 2400 154 0 01 4800 1953 4800 372 0 01 9600 977 9595 701 0 04 19200 488 19211 066 0 06 38400 244 38422 131 0 06 56000 167 56137 725 0 25 128000 73 129807 7 0 33 3000000 3 3125000 4 00 Table 31 2 Baud Rate Examp...

Page 1506: ...of peripheral functions in the smallest possible package Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings See your device specific data manual to determine how pin multiplexing affects the UART 31 2 4 Protocol Description 31 2 4 1 Transmission The UART transmitter section includes a transmitter hold register TH...

Page 1507: ...on the STOP bit selection The UART receives in the following format 1 START bit data bits 5 6 7 8 1 PARITY bit optional 1 STOP bit It receives 1 START bit 5 6 7 or 8 data bits depending on the data width selection 1 PARITY bit if parity is selected and 1 STOP bit The protocol formats are shown in Figure 31 4 Figure 31 4 UART Protocol Formats Transmit Receive for 5 bit data parity Enable 1 STOP bit...

Page 1508: ...hen the transmitter FIFO is empty and it is cleared when at least one byte is loaded into the FIFO or IIR is read 31 2 5 2 Reception The UART receiver section includes a receiver shift register RSR and a receiver buffer register RBR When the UART is in the FIFO mode RBR is a 16 byte FIFO Timing is supplied by the 16 receiver clock Receiver section control is a function of the UART line control reg...

Page 1509: ...et when a character is transferred from the receiver shift register RSR to the empty receiver FIFO The DR bit remains set until the FIFO is empty again A receiver time out interrupt occurs if all of the following conditions exist At least one character is in the FIFO The most recent character was received more than four continuous character times ago A character time is the time allotted for 1 STA...

Page 1510: ...itter holding register THR and the transmitter shift register TSR are empty The THRE bit indicates when THR is empty The BI break FE framing error PE parity error and OE overrun error bits specify which error or errors have occurred The DR data ready bit is set as long as there is at least one byte in the receiver FIFO Also in the FIFO poll mode The interrupt identification register IIR is not aff...

Page 1511: ... where an additional byte is sent 31 2 5 4 2 UARTn_CTS Behavior The transmitter checks UARTn_CTS before sending the next data byte If UARTn_CTS is active the transmitter sends the next byte To stop the transmitter from sending the following byte UARTn_CTS must be released before the middle of the last STOP bit that is currently being sent see Figure 31 7 When flow control is enabled UARTn_CTS leve...

Page 1512: ...LL and DLH 3 If the FIFOs will be used select the desired trigger level and enable the FIFOs by writing the appropriate values to the FIFO control register FCR The FIFOEN bit in FCR must be set first before the other bits in FCR are configured 4 Choose the desired protocol settings by writing the appropriate values to the line control register LCR 5 If autoflow control is desired write appropriate...

Page 1513: ...o using RDAINT the CPU can poll the DR bit in the line status register LSR In the FIFO mode this is not a functionally equivalent alternative because the DR bit does not respond to the FIFO trigger level The DR bit only indicates the presence or absence of unread characters RTOINT Receiver time out condition in the FIFO mode only No characters have been removed from or input to the receiver FIFO d...

Page 1514: ...Power and Sleep Controller PSC The PSC acts as a master controller for power management for all of the peripherals on the device For detailed information on power management procedures using the PSC see the Power and Sleep Controller PSC chapter 31 2 11 Emulation Considerations The FREE bit in the power and emulation management register PWREMU_MGMT determines how the UART responds to an emulation ...

Page 1515: ...ify DLH DLH can also be accessed with address offset 24h IIR and FCR share one address Regardless of the value of the DLAB bit reading from the address gives the content of IIR and writing modifies FCR Table 31 6 UART Registers Offset Acronym Register Description Section 0h RBR Receiver Buffer Register read only Section 31 3 1 0h THR Transmitter Holding Register write only Section 31 3 2 4h IER In...

Page 1516: ...aced in RBR and the receiver data ready interrupt is enabled DR 1 in IER an interrupt is generated This interrupt is cleared when the character is read from RBR In the FIFO mode the interrupt is generated when the FIFO is filled to the trigger level selected in the FIFO control register FCR and it is cleared when the FIFO contents drop below the trigger level Access considerations RBR THR and DLL ...

Page 1517: ...nabled ETBEI 1 in IER an interrupt is generated This interrupt is cleared when a character is loaded into THR or the interrupt identification register IIR is read In the FIFO mode the interrupt is generated when the transmitter FIFO is empty and it is cleared when at least one byte is loaded into the FIFO or IIR is read Access considerations RBR THR and DLL share one address To load THR write 0 to...

Page 1518: ...t IER is always selected at the shared address Figure 31 11 Interrupt Enable Register IER 31 16 Reserved R 0 15 4 3 2 1 0 Reserved Rsvd ELSI ETBEI ERBI R 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 31 9 Interrupt Enable Register IER Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 EDSSI 0 Enable Modem Status Interrupt 2 ELSI Receiv...

Page 1519: ...etermine whether the UART is in the FIFO mode or the non FIFO mode Access consideration IIR and FCR share one address Regardless of the value of the DLAB bit in LCR reading from the address gives the content of IIR and writing to the address modifies FCR Figure 31 12 Interrupt Identification Register IIR 31 16 Reserved R 0 15 8 7 6 5 4 3 1 0 Reserved FIFOEN Reserved INTID IPEND R 0 R 0 R 0 R 0 R 1...

Page 1520: ...from or input to the receiver FIFO during the last four character times see Table 31 4 and there is at least one character in the receiver FIFO during this time One of the following events A character is read from the receiver FIFO 1 A new character arrives in the receiver FIFO The URRST bit in the power and emulation management register PWREMU_MGMT is loaded with 0 3 0 0 1 0 Transmitter holding r...

Page 1521: ...d if the interrupt request is enabled Once the FIFO drops below the trigger level the interrupt is cleared 0 1 byte 1h 4 bytes 2h 8 bytes 3h 14 bytes 5 4 Reserved 0 Reserved 3 DMAMODE1 DMA MODE1 enable if FIFOs are enabled Always write 1 to DMAMODE1 After a hardware reset change DMAMODE1 from 0 to 1 DMAMOD1 1 is a requirement for proper communication between the UART and the EDMA controller 0 DMA ...

Page 1522: ...ed by IER and DLH the CPU can read from and write to IER 1 Allows access to the divisor latches of the baud generator during a read or write operation DLL and DLH At the address shared by RBR THR and DLL the CPU can read from and write to DLL At the address shared by IER and DLH the CPU can read from and write to DLH 6 BC Break control 0 Break condition is disabled 1 Break condition is transmitted...

Page 1523: ...e generated When WLS 1h 2h or 3h 2 STOP bits are generated 1 0 WLS 0 3h Word length select Number of bits in each transmitted or received serial character When STB 1 the WLS bit determines the number of STOP bits 0 5 bits 1h 6 bits 2h 7 bits 3h 8 bits Table 31 14 Relationship Between ST EPS and PEN Bits in LCR ST Bit EPS Bit PEN Bit Parity Option x x 0 Parity disabled No PARITY bit is transmitted ...

Page 1524: ...gnals to provide handshaking between UARTs during data transfer When AFE 1 the RTS bit determines the autoflow control enabled Note that all UARTs do not support this feature see your device specific data manual for supported features If this feature is not available this bit is reserved and should be cleared to 0 0 Autoflow control is disabled 1 Autoflow control is enabled When RTS 0 UARTn_CTS is...

Page 1525: ...XFIFOE was cleared because the CPU read the erroneous character from the receiver FIFO and there are no more errors in the receiver FIFO 1 At least one parity error framing error or break indicator in the receiver FIFO 6 TEMT Transmitter empty TEMT indicator In non FIFO mode 0 Either the transmitter holding register THR or the transmitter shift register TSR contains a data character 1 Both the tra...

Page 1526: ...cleared because the CPU read the erroneous data from the receiver FIFO and the next character to be read from the FIFO has no framing error 1 A framing error has been detected with the character at the top of the receiver FIFO 2 PE Parity error PE indicator A parity error occurs when the parity of the received character does not match the parity selected with the EPS bit in the line control regist...

Page 1527: ... is generated In non FIFO mode 0 Data is not ready or the DR bit was cleared because the character was read from the receiver buffer register RBR 1 Data is ready A complete incoming character has been received and transferred into the receiver buffer register RBR In FIFO mode 0 Data is not ready or the DR bit was cleared because all of the characters in the receiver FIFO have been read 1 Data is r...

Page 1528: ...SR 0 Complement of the Data Set Ready input When the UART is in the diagnostic test mode loopback mode MCR 4 1 this bit is equal to the MCR bit 0 DTR 4 CTS 0 Complement of the Clear To Send input When the UART is in the diagnostic test mode loopback mode MCR 4 1 this bit is equal to the MCR bit 1 RTS 3 DCD 0 Change in DCD indicator bit DCD indicates that the DCD input has changed state since the l...

Page 1529: ... baud clock in the baud generator The latches are in DLH and DLL DLH holds the most significant bits of the divisor and DLL holds the least significant bits of the divisor These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator Writing to the divisor latches results in two wait states being inserted during the write access w...

Page 1530: ...ield Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 DLL 0 FFh The 8 least significant bits LSBs of the 16 bit divisor for generation of the baud clock in the baud rate generator Figure 31 20 Divisor MSB Latch DLH 31 16 Reserved R 0 15 8 7 0 Reserved DLH R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 31 21 Divisor MSB Latch DLH Field Descriptions Bit Fi...

Page 1531: ... shown in Figure 31 22 and described in Table 31 23 Figure 31 21 Revision Identification Register 1 REVID1 31 0 REVID1 R 1102 0002h LEGEND R Read only n value after reset Table 31 22 Revision Identification Register 1 REVID1 Field Descriptions Bit Field Value Description 31 0 REVID1 1102 0002h Peripheral Identification Number Figure 31 22 Revision Identification Register 2 REVID2 31 16 Reserved R ...

Page 1532: ...ons Bit Field Value Description 31 16 Reserved 0 Reserved 15 Reserved 0 Reserved This bit must always be written with a 0 14 UTRST UART transmitter reset Resets and enables the transmitter 0 Transmitter is disabled and in reset state 1 Transmitter is enabled 13 URRST UART receiver reset Resets and enables the receiver 0 Receiver is disabled and in reset state 1 Receiver is enabled 12 1 Reserved 1 ...

Page 1533: ...n register MDR determines the over sampling mode for the UART MDR is shown in Figure 31 24 and described in Table 31 25 Figure 31 24 Mode Definition Register MDR 31 16 Reserved R 0 15 1 0 Reserved OSM_SEL R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 31 25 Mode Definition Register MDR Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 OSM_SEL Over Sam...

Page 1534: ...ght 2013 2016 Texas Instruments Incorporated Universal Parallel Port uPP Chapter 32 SPRUH82C April 2013 Revised September 2016 Universal Parallel Port uPP This chapter describes the universal parallel port uPP Topic Page 32 1 Introduction 1535 32 2 Architecture 1538 32 3 Registers 1555 ...

Page 1535: ... overhead during high speed data transmission All uPP transactions use the internal DMA to feed data to or retrieve data from the I O channels The DMA controller includes two DMA channels which typically service separate I O channels The uPP peripheral also supports data interleave mode in which all DMA resources service a single I O channel In this mode only one I O channel may be used 32 1 2 Fea...

Page 1536: ...bit Configuration bus Interrupt to CPU Transmit clock uPP Internal External CLOCK pin ENABLE pin START pin WAIT pin DATA pins DMA Introduction www ti com 1536 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Universal Parallel Port uPP Figure 32 1 uPP Functional Block Diagram Figure 32 2 Data Flow for Single Channel Receive...

Page 1537: ...a pins Data pins www ti com Introduction 1537 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Universal Parallel Port uPP Figure 32 4 Data Flow for Digital Loopback DLB Mode Duplex Mode 0 Figure 32 5 Data Flow for Single Channel Transmit with Data Interleave ...

Page 1538: ...tained independently based on its operating direction 32 2 1 1 Transmit Mode Single Data Rate The channel drives a clock signal on its CLOCK pin The uPP transmit clock is divided by a fixed value of 2 then divided again by a user specified value between 1 and 16 UPICR CLKDIVn 1 The resulting signal then drives the CLOCK pin The following formula determines the final I O clock speed I O Clock Trans...

Page 1539: ... 2 Signal Description Each uPP channel has its own set of control and data signals Table 32 2 lists every signal and briefly describes their functions Section 32 2 5 explains the uPP protocol 1 This clock can only be used in transmit mode and must be twice the speed of your desired I O clock See Section 32 2 1 and the Device Clocking chapter for more information Table 32 2 uPP Signal Descriptions ...

Page 1540: ...ing Concepts The uPP internal DMA controller uses a simplified programming model similar to 2D transfers performed by the EDMA see the Enhanced Direct Memory Access EDMA3 Controller chapter for more information Each DMA channel may be configured with four parameters window address byte count line count and line offset address Figure 32 8 shows a typical DMA window defined by these parameters Windo...

Page 1541: ...s immediately Section 32 2 6 describes a step by step process for configuring the I O and DMA channels and starting a uPP transfer Each DMA channel allows a second descriptor to be queued while the previously programmed DMA transfer is still running The UPxS2 PEND bit reports whether a new set of DMA parameters may be written to the DMA descriptor registers Each DMA channel can have at most one ac...

Page 1542: ... the differences between single data rate SDR and double data rate DDR In data interleave mode only I O Channel A is used This single channel is associated with two data buffers each serviced by its own DMA channel I and Q In SDR interleave mode the START signal is used as a buffer selection line START 1 indicates that the current word comes from DMA Channel I START 0 indicates that the current wo...

Page 1543: ...n UPICR These pins can be configured to drive an idle value TRISx 0 VALx field in the uPP interface idle value register UPIVR or be in a high impedance state while idle TRISx 1 In receive mode these pins are inputs that provide data to the channel s associated DMA channel Note that the DATA signals map differently to the DATA and XDATA pins for various uPP configurations see Section 32 2 2 for mor...

Page 1544: ...2 10 shows WAIT signal timing The WAIT signal is active high by default but its polarity is controlled by the WAITPOLx bit in UPICR In transmit mode WAIT is an input signal and may be disabled using the WAITx bit in UPICR in receive mode WAIT is an output signal 32 2 5 6 CLOCK Signal The uPP transmitter drives the CLOCK signal to align all other uPP signals By default other signals align on the ri...

Page 1545: ... 1545 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Universal Parallel Port uPP Figure 32 10 Signal Timing for uPP Channel in Transmit Mode with Single Data Rate Figure 32 11 Signal Timing for uPP Channel in Receive Mode with Double Data Rate Figure 32 12 Signal Timing for uPP Channel in Transmit Mode with Double Data Ra...

Page 1546: ...Texas Instruments Incorporated Universal Parallel Port uPP Figure 32 13 Signal Timing for uPP Channel in Receive Mode with Double Data Rate and Data Interleave Enabled via UPCTL DDRDEMUX Figure 32 14 Signal Timing for uPP Channel in Transmit Mode with Double Data Rate and Data Interleave Enabled via UPCTL DDRDEMUX Figure 32 15 Signal Timing for uPP Channel in Transmit Mode with Single Data Rate an...

Page 1547: ... are three selectable data packing modes Right Justify Zero Extend Data occupies N LSBs The 16 N MSBs are cleared to 0 Right Justify Sign Extend Data occupies N LSBs The 16 N MSBs are the same value as the N 1 bit Left Justify Zero Fill Data occupies N MSBs The 16 N LSBs are cleared to 0 Table 32 6 lists some example data for N 12 that is 12 bit operation In transmit mode the packed version of eac...

Page 1548: ...ule out of reset 5 Program the uPP configuration registers UPCTL UPICR UPIVR UPTCR and UPDLB The basic function of each register is summarized here for more information see Section 32 3 a UPCTL Transmit receive selection see Table 32 7 data width data format data rate data interleave enable b UPICR Signal enable signal inversion clock divisor transmit only c UPIVR Idle value transmit only d UPTCR ...

Page 1549: ...al connections between channels The standard uPP pin multiplexing must be applied however even though the pins are not used Table 32 7 Basic Operating Mode Selection Operating Mode uPP Channel Control Register UPCTL Bit uPP Digital Loopback Register UPDLB Bit CHN MODE AB BA 1 Channel Transmit 0 1 0 0 1 Channel Receive 0 0 0 0 2 Channel Transmit 1 1 0 0 2 Channel Receive 1 0 0 0 2 Channel Duplex 0 ...

Page 1550: ...2 8 Sample uPP Parameters for Duplex Mode 0 Register Register Field 1 Setting Description UPCTL DPFB 2h Data packing left justified zero fill DPWB 4h 12 bit data format IWB 1 16 bit DRB 0 Single data rate DPFA Unused DPWA 0 16 bit data format IWA 1 16 bit DRA 0 Single data rate CHN 1 2 Channel MODE 2h Duplex 0 A receive B transmit UPICR CLKDIVB 1 Divide by 2 total division of transmit clock 4 CLKD...

Page 1551: ...clock division is the most straight forward way to decrease system loading This is a coarse adjustment the difference between CLKDIVx 0 and 1 is the same in terms of data rate as the difference between single and double data rate CLKDIVA DMA Read Burst Size UPTCR RDSIZEQ 0 3h Increasing the DMA read threshold decreases system loading by generating fewer larger DMA events This is a fine adjustment ...

Page 1552: ...I 1 clear ERRI Handle ERRI if interrupt_status UORI UPIER UORI 1 clear UORI Handle UORI if interrupt_status DPEI UPIER DPEI 1 clear DPEI Handle DPEI if interrupt_status EOLQ UPIER EOLQ 1 clear EOLQ Handle EOLQ if interrupt_status EOWQ UPIER EOWQ 1 clear EOWQ Handle EOWQ if interrupt_status ERRQ UPIER ERRQ 1 clear ERRQ Handle ERRQ if interrupt_status UORQ UPIER UORQ 1 clear UORQ Handle UORQ if inte...

Page 1553: ... in close proximity to one another a single CPU interrupt and a single call to the ISR may represent multiple interrupt events Thus the uPP ISR must meet certain structural requirements The ISR must be able to handle multiple events before returning The ISR must handle any subsequent events that occur after it is called but before it returns The ISR must write 00h to the uPP end of interrupt regis...

Page 1554: ...mation on power management see the Power Management chapter 32 2 10 Emulation Considerations The uPP peripheral stops running if any of three conditions are met Peripheral Disable EN bit in the uPP peripheral control register UPPCR is 0 Clock Stop uPP acknowledges a clock stop request from the device power management module Emulation Suspend JTAG emulator halts chip while FREE 0 and SOFT 1 in UPPC...

Page 1555: ...UPIEC uPP Interrupt Enable Clear Register Section 32 3 11 30h UPEOI uPP End of Interrupt Register Section 32 3 12 40h UPID0 uPP DMA Channel I Descriptor 0 Register Section 32 3 13 44h UPID1 uPP DMA Channel I Descriptor 1 Register Section 32 3 14 48h UPID2 uPP DMA Channel I Descriptor 2 Register Section 32 3 15 50h UPIS0 uPP DMA Channel I Status 0 Register Section 32 3 16 54h UPIS1 uPP DMA Channel ...

Page 1556: ...poll whether internal DMA is currently active Writes to this field have no effect 0 Internal DMA is idle 1 Internal DMA is active 6 5 Reserved 0 Reserved 4 SWRST Software reset control Asserting reset clears internal state machines and prevents device from running For graceful reset you should first clear the EN bit and poll the DB bit to make sure the DMA is idle then assert the SWRST bit 0 Perip...

Page 1557: ...uPP Digital Loopback Register UPDLB 31 16 Reserved R 0 15 14 13 12 11 0 Reserved BA AB Reserved R 0 R W 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 32 13 uPP Digital Loopback Register UPDLB Field Descriptions Bit Field Value Description 31 14 Reserved 0 Reserved 13 BA B to A digital loopback control Assert to enable digital loopback transmitting from Channel B to Channe...

Page 1558: ...erved R 0 7 5 4 3 2 1 0 Reserved DDRDEMUX SDRTXIL CHN MODE R 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 32 14 uPP Channel Control Register UPCTL Field Descriptions Bit Field Value Description 31 Reserved 0 Reserved 30 29 DPFB 0 3h Channel B data packing format Applies only to 9 bit to 15 bit modes IWB 1 and DPWB 0 0 Right justified zero extended 1h Right ...

Page 1559: ...le data rate 15 5 Reserved 0 Reserved 4 DDRDEMUX Double data rate demultiplexing mode Only applies when DRA 1 0 Disable Each peripheral channel is associated with its own DMA channel 1 Enable Both DMA channels service peripheral Channel A Requires CHN 0 and MODE 0 or 1 3 SDRTXIL Single data rate transmit interleave mode Only applies when DRA 0 0 Disable Each peripheral channel is associated with i...

Page 1560: ... impedance state Controls interface Channel B while idle in transmit mode Only applies when Channel B is configured in transmit mode using the MODE bit in the uPP channel control register UPCTL 0 Channel B drives value from the VALB bit in the uPP interface idle value register UPIVR while idle 1 Channel B data pins are in a high impedance state while idle 28 CLKINVB Channel B clock inversion Contr...

Page 1561: ...1 Clock is inverted Channel A signals align on falling edge of clock 11 8 CLKDIVA 0 Fh Clock divisor for Channel A Only used when interface Channel A is configured in transmit mode using the MODE bit in the uPP channel control register UPCTL Applied divisor equals CLKDIVA 1 7 6 Reserved 0 Reserved 5 WAITA Channel A WAIT signal enable Controls use of WAIT signal for interface Channel A Only applied...

Page 1562: ...ribed in Table 32 16 Figure 32 21 uPP Interface Idle Value Register UPIVR 31 16 VALB R W 0 15 0 VALA R W 0 LEGEND R W Read Write n value after reset Table 32 16 uPP Interface Idle Value Register UPIVR Field Descriptions Bit Field Value Description 31 16 VALB 0 FFFFh Channel B idle value Sets idle value for interface Channel B This value is output on the Channel B data pins when the channel is idle...

Page 1563: ...5 24 TXSIZEB 0 3h Transmit threshold for Channel B Controls the number of bytes that interface Channel B waits before beginning transmission Only applies when Channel B is configured in transmit mode using the MODE bit in the uPP channel control register UPCTL 0 64 bytes 1 128 bytes requires DMA descriptor byte count greater than 64 2h Reserved 3h 256 bytes requires DMA descriptor byte count great...

Page 1564: ...31 13 Reserved 0 Reserved 12 EOLQ Reports raw interrupt status for end of line condition EOL on DMA Channel Q 0 No EOL occurred 1 EOL occurred 11 EOWQ Reports raw interrupt status for end of window condition EOW on DMA Channel Q 0 No EOW occurred 1 EOW occurred 10 ERRQ Reports raw interrupt status for internal bus error condition ERR on DMA Channel Q 0 No error occurred 1 Error occurred 9 UORQ Rep...

Page 1565: ...ght 2013 2016 Texas Instruments Incorporated Universal Parallel Port uPP Table 32 18 uPP Interrupt Raw Status Register UPISR Field Descriptions continued Bit Field Value Description 0 DPEI Reports raw interrupt status for programming error condition DPE on DMA Channel I 0 No error occurred 1 Error occurred ...

Page 1566: ...Table 32 19 uPP Interrupt Enabled Status Register UPIER Field Descriptions Bit Field Value Description 31 13 Reserved 0 Reserved 12 EOLQ Interrupt Status for Channel Q End of Line Reports enabled interrupt status for end of line condition EOL on DMA Channel Q 0 No EOL 1 EOL occurred 11 EOWQ Interrupt Status for Channel Q End of Window Reports enabled interrupt status for end of window condition EO...

Page 1567: ...tatus for Channel I Error Reports enabled interrupt status for internal bus error condition on DMA Channel I 0 No error 1 Error occurred 1 UORI Interrupt Status for Channel I Underrun Overflow condition Reports enabled interrupt status for underrun or overflow condition on DMA Channel I 0 No underrun or overflow 1 Underrun or overflow occurred 0 DPEI Interrupt Status for Channel I Programming Erro...

Page 1568: ...le EOL interrupt 11 EOWQ Interrupt Enable Set for Channel Q End of Window Reports interrupt enable for end of window condition EOW on DMA Channel Q 0 Read EOW interrupt is disabled Write no effect 1 Read EOW interrupt is enabled Write enable EOW interrupt 10 ERRQ Interrupt Enable Set for Channel Q Error Reports interrupt enable for internal bus error condition on DMA Channel Q 0 Read Error interru...

Page 1569: ...abled Write no effect 1 Read Error interrupt is enabled Write enable ERR interrupt 1 UORI Interrupt Enable Set for Channel I Underrun Overflow condition Reports interrupt enable for underrun or overflow condition on DMA Channel I 0 Read Underrun or overflow interrupt is disabled Write no effect 1 Read Underrun or overflow interrupt is enabled Write enable UOR interrupt 0 DPEI Interrupt Enable Set ...

Page 1570: ...OL interrupt 11 EOWQ Interrupt Enable Clear for Channel Q End of Window Reports interrupt enable for end of window condition EOW on DMA Channel Q 0 Read EOW interrupt is disabled Write no effect 1 Read EOW interrupt is enabled Write disable EOW interrupt 10 ERRQ Interrupt Enable Clear for Channel Q Error Reports interrupt enable for internal bus error condition on DMA Channel Q 0 Read Error interr...

Page 1571: ...led Write no effect 1 Read Error interrupt is enabled Write disable ERR interrupt 1 UORI Interrupt Enable Clear for Channel I Underrun Overflow condition Reports interrupt enable for underrun or overflow condition on DMA Channel I 0 Read Underrun or overflow interrupt is disabled Write no effect 1 Read Underrun or overflow interrupt is enabled Write disable UOR interrupt 0 DPEI Interrupt Enable Cl...

Page 1572: ...d 7 0 EOI 0 FFh End of interrupt value Write 00h after uPP interrupt to allow interrupt generation from subsequent uPP events 32 3 13 uPP DMA Channel I Descriptor 0 Register UPID0 The uPP DMA channel I descriptor 0 register UPID0 programs the starting address of the data buffer or window for DMA Channel I The address is programmed by writing a 32 bit value to the entire register Note that the 3 lo...

Page 1573: ...ue 15 1 BCNTH 1 7FFFh Byte Count MSBs Sets the 15 most significant bits of the number of bytes per line in the DMA Channel I window 0 Invalid value 0 BCNT 0 Byte Count LSB Forces the number of bytes per line to an even value multiple of 2 bytes 32 3 15 uPP DMA Channel I Descriptor 2 Register UPID2 The uPP DMA channel I descriptor 2 register UPID2 programs the offset address between lines within th...

Page 1574: ...DR 0 FFFF FFFFh DMA Current Address Reports the current address of the DMA Channel I transfer 32 3 17 uPP DMA Channel I Status 1 Register UPIS1 The uPP DMA channel I status 1 register UPIS1 reports the current line number and the byte position within the current line of the DMA Channel I transfer The UPIS1 is shown in Figure 32 32 and described in Table 32 27 Figure 32 32 uPP DMA Channel I Status ...

Page 1575: ...2 Register UPIS2 Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 4 WM 0 Fh DMA Watermark When the associated interface channel operates in receive mode this field records the maximum FIFO block occupancy reached during any transaction When the associated interface channel operates in transmit mode this field records the FIFO block emptiness and is overwritten every uPP in...

Page 1576: ...align to multiple of 8 bytes 64 bit buffer alignment 32 3 20 uPP DMA Channel Q Descriptor 1 Register UPQD1 The uPP DMA channel Q descriptor 1 register UPQD1 programs the line count per window and byte count per line for DMA Channel Q The line count LNCNT may be set to any number from 1 to 65 535 FFFFh but must not be cleared to 0 The byte count BCNT may only be set to an even number For a simple t...

Page 1577: ...to UPQD2 effectively repeats the same first line UPQD1 LNCNT times The UPQD2 is shown in Figure 32 36 and described in Table 32 31 Figure 32 36 uPP DMA Channel Q Descriptor 2 Register UPID2 31 16 Reserved R 0 15 3 2 0 LNOFFSETH LNOFFSET R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 32 31 uPP DMA Channel Q Descriptor 2 Register UPID2 Field Descriptions Bit Field Value Descri...

Page 1578: ...DR 0 FFFF FFFFh DMA Current Address Reports the current address of the DMA Channel Q transfer 32 3 23 uPP DMA Channel Q Status 1 Register UPQS1 The uPP DMA channel Q status 1 register UPQS1 reports the current line number and the byte position within the current line of the DMA Channel Q transfer The UPQS1 is shown in Figure 32 38 and described in Table 32 33 Figure 32 38 uPP DMA Channel Q Status ...

Page 1579: ...atus 2 Register UPQS2 Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 4 WM 0 Fh DMA Watermark When the associated interface channel operates in receive mode this field records the maximum FIFO block occupancy reached during any transaction When the associated interface channel operates in transmit mode this field records the FIFO block emptiness and is overwritten every u...

Page 1580: ...nstruments Incorporated Universal Serial Bus OHCI Host Controller Chapter 33 SPRUH82C April 2013 Revised September 2016 Universal Serial Bus OHCI Host Controller This chapter describes the universal serial bus OHCI host controller Topic Page 33 1 Introduction 1581 33 2 Architecture 1582 33 3 Registers 1586 ...

Page 1581: ...re already familiar with the USB Specification and OHCI Specification for USB The USB1 1 host controller implements the register set and makes use of the memory data structures defined in the OHCI Specification for USB These registers and data structures are the mechanisms by which a USB host controller driver software package can control the USB1 1 host controller The OHCI Specification for USB a...

Page 1582: ... of the device level power sleep controller 1 PSC1 module This module controls many local power sleep controller modules and local power sleep controller 2 LPSC2 of PSC1 controls the USB1 1 OHCI host controller 33 2 1 3 48 MHz Reference Clock This device includes an integrated USB 1 1 Phy for the OHCI Host Controller s Root Hub Port 0 This Phy requires a 48 MHz reference clock for proper operation...

Page 1583: ...scussions of USB requirements and OHCI controller operation 33 2 3 Differences From OHCI Specification for USB The USB1 1 module OHCI compatible host controller implementation does not implement every aspect of the functionality defined in the OHCI Specification for USB The differences focus on power switching overcurrent reporting and the OHCI ownership change interrupt Other restrictions are imp...

Page 1584: ...RSMRCY after a bus segment transitions from resume signaling to normal operational mode During that time only start of frame packets are to be sent on the bus segment The system software should disable all list enable bits HCCONTROL PLE HCCONTROL IE HCCONTROL CLE and HCCONTROL BLE and then wait for at least 1 ms before setting the host controller into USB suspend state via HCCONTROL HCFS When rest...

Page 1585: ...fabric allows the USB1 1 host controller to access system memory 33 2 7 Physical Addressing Transactions on the internal bus use physical addresses so all system memory accesses initiated by the USB1 1 host controller must use physical addresses The CPU can be configured to use virtual addressing In this case software manipulates virtual addresses that may or may not be identical to physical addre...

Page 1586: ... 01E2 5004h HCCONTROL HC Operating Mode Register Section 33 3 2 01E2 5008h HCCOMMANDSTATUS HC Command and Status Register Section 33 3 3 01E2 500Ch HCINTERRUPTSTATUS HC Interrupt and Status Register Section 33 3 4 01E2 5010h HCINTERRUPTENABLE HC Interrupt Enable Register Section 33 3 5 01E2 5014h HCINTERRUPTDISABLE HC Interrupt Disable Register Section 33 3 6 01E2 5018h HCHCCA HC HCAA Address Regi...

Page 1587: ... R Read only n value after reset Table 33 2 OHCI Revision Number Register HCREVISION Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 REV 10h OHCI revision number 33 3 2 HC Operating Mode Register HCCONTROL The HC operating mode register HCCONTROL controls the operating mode of the USB1 1 host controller HCCONTROL is shown in Figure 33 3 and described in Table 33 3 Figur...

Page 1588: ...a current ED before it reenables the bulk list 1 Enables processing of the bulk ED list The HC head bulk register HCBULKHEADED must be 0 or point to a valid ED before setting this bit The HC current bulk register HCBULKCURRENTED must be 0 or point to a valid ED before setting this bit 4 CLE Control list enable 0 The control ED list is not processed in the next 1 ms frame The host controller driver...

Page 1589: ...iver sets this bit to gain ownership of the host controller The processor does not support SMI interrupts so no ownership change interrupt occurs 2 BLF 0 1 Bulk list filled The host controller driver must set this bit if it modifies the bulk list to include new TDs If the HC current bulk register HCBULKCURRENTED is 0 the USB1 1 host controller does not begin processing bulk list EDs unless this bi...

Page 1590: ... FNO Frame number overflow A write of 1 clears this bit a write of 0 has no effect 0 A frame number overflow has not occurred 1 A frame number overflow has occurred 4 UE Unrecoverable error A write of 1 clears this bit a write of 0 has no effect 0 An unrecoverable error has not occurred 1 An unrecoverable error has occurred on the OCPI bus or that an isochronous TD PSW field condition code was not...

Page 1591: ... a write of 0 has no effect A write of 1 to the corresponding bit in the HC interrupt disable register HCINTERRUPTDISABLE clears this bit 0 Frame number overflow interrupts do not propagate 1 When MIE is 1 allows frame number overflow interrupts to propagate to the level 2 interrupt controller 4 UE Unrecoverable error A write of 1 sets this bit a write of 0 has no effect A write of 1 to the corres...

Page 1592: ... No effect 1 Clears the MIE bit in the HC interrupt enable register HCINTERRUPTENABLE 30 OC 0 1 Ownership change 29 7 Reserved 0 Reserved 6 RHSC Root hub status change Read always returns 0 0 No effect 1 Clears the RHSC bit in the HC interrupt enable register HCINTERRUPTENABLE 5 FNO Frame number overflow Read always returns 0 0 No effect 1 Clears the FNO bit in the HC interrupt enable register HCI...

Page 1593: ...Reserved 0 Reserved 33 3 8 HC Current Periodic Register HCPERIODCURRENTED The HC current periodic register HCPERIODCURRENTED defines the physical address of the next endpoint descriptor ED on the periodic ED list HCPERIODCURRENTED is shown in Figure 33 9 and described in Table 33 9 Figure 33 9 HC Current Periodic Register HCPERIODCURRENTED 31 16 PCED R 0 15 4 3 0 PCED Reserved R 0 R 0 LEGEND R Rea...

Page 1594: ...restrictions on physical addresses see Section 33 2 7 3 0 Reserved 0 Reserved 33 3 10 HC Current Control Register HCCONTROLCURRENTED The HC current control register HCCONTROLCURRENTED defines the physical address of the next endpoint descriptor ED on the control ED list HCCONTROLCURRENTED is shown in Figure 33 11 and described in Table 33 11 Figure 33 11 HC Current Control Register HCCONTROLCURREN...

Page 1595: ...e restrictions on physical addresses see Section 33 2 7 3 0 Reserved 0 Reserved 33 3 12 HC Current Bulk Register HCBULKCURRENTED The HC current bulk register HCBULKCURRENTED defines the physical address of the next endpoint descriptor ED on the bulk ED list HCBULKCURRENTED is shown in Figure 33 13 and described in Table 33 13 Figure 33 13 HC Current Bulk Register HCBULKCURRENTED 31 16 BCED R W 0 1...

Page 1596: ...Ds on the done queue This register is automatically updated by the USB1 1 host controller 3 0 Reserved 0 Reserved 33 3 14 HC Frame Interval Register HCFMINTERVAL The HC frame interval register HCFMINTERVAL defines the number of 12 MHz clock pulses in each USB frame HCFMINTERVAL is shown in Figure 33 15 and described in Table 33 15 Figure 33 15 HC Frame Interval Register HCFMINTERVAL 31 30 16 FIT F...

Page 1597: ... 0 3FFFh Frame remaining The number of full speed bit times remaining in the current frame This field is automatically reloaded with the frame interval FI value in the HC frame interval register HCFMINTERVAL at the beginning of every frame 33 3 16 HC Frame Number Register HCFMNUMBER The HC frame number register HCFMNUMBER reports the current USB frame number HCFMNUMBER is shown in Figure 33 17 and...

Page 1598: ... the first 10 of the frame then periodic EDs have priority for the remaining 90 of the frame 33 3 18 HC Low Speed Threshold Register HCLSTHRESHOLD The HC low speed threshold register HCLSTHRESHOLD defines the latest time in a frame that the USB1 1 host controller can begin a low speed packet HCLSTHRESHOLD is shown in Figure 33 19 and described in Table 33 19 Figure 33 19 HC Low Speed Threshold Reg...

Page 1599: ...elationship to the OTG controller register bits that relate to VBUS System software can update this register to simplify host controller driver and or OTG driver coding 23 13 Reserved 0 Reserved 12 NOCP 1 No overcurrent protection Because the device does not provide signals to allow connection of external overcurrent indication signals to the USB1 1 host controller this bit defaults to 1 that indi...

Page 1600: ... is the port power control mask for downstream port 2 Defines whether downstream port 2 has port power controlled by the global power control System software can update these bits to simplify host controller driver and or OTG driver coding 0 Global power control is implemented for downstream port 2 1 Per port power control is implemented for downstream port 2 17 PPCM 1 Port power control mask PPCM...

Page 1601: ...status change Because the root hub does not support the local power status feature this bit defaults to 0 and has no effect This bit has no relationship to the OTG controller register bits that relate to VBUS System software can update this register to simplify host controller driver and or OTG driver coding 15 DRWE Device remote wake up enable When 1 this bit enables a connect status change event...

Page 1602: ...pend status change A write of 1 clears this bit a write of 0 has no effect 0 Port 1 port suspend status has not changed 1 Port 1 port suspend status has changed Suspend status is considered to have changed only after the resume pulse low speed EOP and 3 ms synchronization delays have been completed 17 PESC Port 1 enable status change A write of 1 clears this bit a write of 0 has no effect 0 Port 1...

Page 1603: ... The device does not provide inputs for signaling external overcurrent indication to the USB1 1 host controller Overcurrent monitoring if required must be handled through some other mechanism 0 Port 1 port overcurrent condition has not occurred 1 Port 1 port overcurrent condition has occurred 2 PSS SPS Port 1 port suspend status set port suspend A write of 1 to this bit when port 1 current connect...

Page 1604: ... controller register bits that relate to VBUS 18 PSSC Port 2 suspend status changed A write of 1 clears this bit a write of 0 has no effect 0 Port 2 port suspend status has not changed 1 Port 2 port suspend status has changed Suspend status is considered to have changed only after the resume pulse low speed EOP and 3 ms synchronization delays have been completed 17 PESC Port 2 enable status change...

Page 1605: ...uired must be handled through some other mechanism This bit has no relationship to the OTG controller register bits that relate to VBUS 0 A write of 0 has no effect 1 A write of 1 to this bit when port 2 port suspend status is 1 causes resume signaling on port 2 A write of 1 when port 2 port suspend status is 0 has no effect 2 PSS SPS Port 2 port suspend status set port suspend When read as 1 indi...

Page 1606: ...ments Incorporated Universal Serial Bus 2 0 USB Controller Chapter 34 SPRUH82C April 2013 Revised September 2016 Universal Serial Bus 2 0 USB Controller This chapter describes the universal serial bus USB controller Topic Page 34 1 Introduction 1607 34 2 Architecture 1608 34 3 Use Cases 1675 34 4 Registers 1687 ...

Page 1607: ...for additional versatility supporting operation capability as a host or peripheral 34 1 2 Features The USB has the following features Operating as a host it complies with the USB 2 0 standard for high speed 480 Mbps full speed 12 Mbps and low speed 1 5 Mbps operations with a peripheral Operating as a peripheral it complies with the USB 2 0 standard for high speed 480 Mbps and full speed 12 Mbps op...

Page 1608: ... in the chip configuration 2 register CFGCHIP2 of the System Configuration Module The USB_REFCLKIN source should be selected when it is not possible such as when specific audio rates are required to operate the device at one of the allowed input frequencies to the USB2 0 subsystem The USB2 0 subsystem peripheral bus clock is sourced from SYSCLK2 Table 34 1 determines the source origination as well...

Page 1609: ...ncies 0 1 USB_REFCLKIN USB_REFCLKIN USB_REFCLKIN must be 48 MHz The PLL inside the USB2 0 PHY can be configured to accept this input clock frequency 1 0 PLL0_AUXCLK CLK48MHz output from USB2 0 PHY PLL0_AUXCLK must be 12 24 48 19 2 38 4 13 26 20 or 40 MHz The PLL inside the USB2 0 PHY can be configured to accept any of these input clock frequencies 1 1 PLL0_AUXCLK USB_REFCLKIN PLL0_AUXCLK must be 1...

Page 1610: ...this signal for HNP and SRP For device or host only mode of operation pull up this pin to 5V For host mode of operation also pull up the USB power signal on the USB connector to 5V For mixed host device mode of operation tie this to the charge pump USB0_DRVVBUS I O Z Digital output to control external 5 V supply USB0_VDDA33 I O Z USB0 PHY 3 3V supply USB0_VDDA18 I O Z USB0 PHY 1 8V supply input US...

Page 1611: ...The final task is to turn on the PHY PLL and wait until it locks You should wait for the PHY clock good status to be set prior to ending the PHY initialization process 34 2 5 VBUS Voltage Sourcing Control When the USB controller assumes the role of a host it is required to supply 5V power to an attached device through its VBUS line In order to achieve this task the USB controller requires the use ...

Page 1612: ...o that it start sourcing the required 5V power must be 4 75V The USB2 0 controller will then wait to for the voltage of the USB0_VBUS goes high If it does not see the power on the USB0_VBUS pin greater than Vbus Valid 4 4V it will generate an interrupt to the user indicating the existence of a problem Assuming that the voltage level of the USB0_VBUS is found to be above Vbus Valid then the USB 2 0...

Page 1613: ... routine Yes interrupt Receive Host Tx routine No Yes Transmit interrupt interrupt EP0 Yes Peripheral EP0 routine No interrupt Receive No Rx routine Peripheral Yes Transmit interrupt Tx routine Peripheral Yes interrupt SOF routine Resume Yes interrupt Disconn Disconnect Yes routine Suspend interrupt Suspend Yes routine www ti com Architecture 1613 SPRUH82C April 2013 Revised September 2016 Submit ...

Page 1614: ...e controller will not then be able to detect Resume signaling on the USB As a result some external hardware will be needed to detect Resume signaling by monitoring the DM and DP signals so that the clock to the controller can be restarted Resume Signaling When resume signaling occurs on the bus first the clock to the controller must be restarted if necessary Then the controller will automatically ...

Page 1615: ...requests when the software receives an endpoint 0 interrupt The RXPKTRDY bit of PERI_CSR0 bit 0 will also have been set The 8 byte command should then be read from the endpoint 0 FIFO decoded and the appropriate action taken For example if the command is SET_ADDRESS the 7 bit address value contained in the command should be written to the FADDR register The PERI_CSR0 register should then be writte...

Page 1616: ...ad from the endpoint 0 FIFO If the length of the data associated with the request indicated by the wLength field in the command is greater than the maximum packet size for endpoint 0 further data packets will be sent In this case PERI_CSR0 should be written to set the SERV_RXPKTRDY bit but the DATAEND bit should not be set When all the expected data packets have been received the PERI_CSR0 registe...

Page 1617: ...software the interrupt is just a confirmation that the request completed successfully If the command is an unrecognized command or for some other reason cannot be executed then when it has been decoded the PERI_CSR0 register should be written to set the SERV_RXPKTRDY bit bit 6 and to set the SENDSTALL bit bit 5 When the host requests data the controller will send a STALL to tell the host that the ...

Page 1618: ...a Int Int phase clear RxPktRdy Unload FIFO and and set DataEnd Int OUT data phase Int IN Int RX state Idle Unload device req and clear RxPktRdy Setup Int Sequence 3 Status phase IN Int No data phase DataEnd clear RxPktRdy and set Unload device req and Idle CPU actions Idle Tx state Rx state Sequence 1 Sequence 2 Sequence 3 Architecture www ti com 1618 SPRUH82C April 2013 Revised September 2016 Sub...

Page 1619: ...ontroller receiving data from the bus The service routine must check for this by testing the RXPKTRDY bit of PERI_CSR0 bit 0 If this bit is set then the controller has received a SETUP packet This must be unloaded from the FIFO and decoded to determine the action the controller must take Depending on the command contained within the SETUP packet endpoint 0 will enter one of three states If the com...

Page 1620: ...p end Yes State Yes No IDLE IDLE mode TX mode No TX State Yes RX mode RX State Yes By default Architecture www ti com 1620 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Universal Serial Bus 2 0 USB Controller Figure 34 6 Service Endpoint 0 Flow Chart ...

Page 1621: ...ed September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Universal Serial Bus 2 0 USB Controller 34 2 7 1 1 5 1 IDLE Mode IDLE mode is the mode the endpoint 0 control must select at power on or reset and is the mode to which the endpoint 0 control should return when the RX and TX modes are terminated It is also the mode in which the SETUP phase of control ...

Page 1622: ...IN tokens See Figure 34 8 Three events can cause TX mode to be terminated before the expected amount of data has been sent 1 The host sends an invalid token causing a SETUPEND condition bit 4 of PERI_CSR0 set 2 The software sends a packet containing less than the maximum packet size for endpoint 0 3 The software sends an empty data packet Until the transaction is terminated the software simply nee...

Page 1623: ... RX mode to be terminated before the expected amount of data has been received as shown in Figure 34 9 1 The host sends an invalid token causing a SETUPEND condition setting bit 4 of PERI_CSR0 2 The host sends a packet which contains less than the maximum packet size for endpoint 0 3 The host sends an empty data packet Until the transaction is terminated the software unloads the FIFO when it recei...

Page 1624: ... this indicates that the host has sent another SETUP packet and the software should then process this command If the software wants to abort the current transfer because it cannot process the command or has some other internal error then it should set the SENDSTALL bit bit 5 of PERI_CSR0 The controller will then send a STALL packet to the host set the SENTSTALL bit bit 2 of PERI_CSR0 and generate ...

Page 1625: ... must be enabled Bit 11 FRCDATATOG Cleared to 0 to allow normal data toggle operations Bit 10 DMAMODE Set to 1 when DMA is enabled When the endpoint is first configured following a SET_CONFIGURATION or SET_INTERFACE command on Endpoint 0 the lower byte of PERI_TXCSR should be written to set the CLRDATATOG bit bit 6 This will ensure that the data toggle which is handled automatically by the control...

Page 1626: ...d the data toggle sequence should be restarted by setting the CLRDATATOG bit in the PERI_TXCSR register bit 6 34 2 7 1 2 2 Bulk OUT Transactions A Bulk OUT transaction is used to transfer non periodic data from the host to the function controller The following optional features are available for use with an Rx endpoint used in peripheral mode for Bulk OUT transactions Double packet buffering When ...

Page 1627: ...ze of the data block is a multiple of wMaxPacketSize a null data packet will be sent after the data to signify that the transfer is complete In the general case the application software will need to read each packet from the FIFO individually If large blocks of data are being transferred the overhead of calling an interrupt service routine to unload each packet can be avoided by using DMA 34 2 7 1...

Page 1628: ...nabled for the endpoint a DMA request will be generated whenever the endpoint is able to accept another packet in its FIFO This feature allows the DMA controller to load packets into the FIFO without processor intervention However this feature is not particularly useful with Isochronous endpoints because the packets transferred are often not maximum packet size and the PERI_TXCSR register needs to...

Page 1629: ...enerate a SOF_PULSE when the SOF packet has been lost The interrupts may still be used to set the TXPKTRDY bit in PERI_TXCSR bit 0 and to check for data overruns underruns Starting up a double buffered Isochronous IN pipe can be a source of problems Double buffering requires that a data packet is not transmitted until the frame microframe after it is loaded There is no problem if the function load...

Page 1630: ...e PERI_RXCSR register should be set as shown in Table 34 7 Table 34 7 PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions Bit Position Bit Field Name Configuration Bit 14 ISO Set to 1 to enable isochronous protocol Bit 13 DMAEN Set to 1 if a DMA request is required for this endpoint Bit 12 DISNYET Ignored in isochronous transfers Bit 11 DMAMODE Always clear this bit to 0 34 2 7 ...

Page 1631: ...then exit Suspend mode and automatically set the RESUME bit in the POWER register bit 2 to take over generating the Resume signaling from the target If the Resume interrupt is enabled an interrupt will be generated Reset Signaling If the RESET bit in the POWER register bit 3 is set while the controller is in Host mode it will generate Reset signaling on the bus If the HSENAB bit in the POWER regis...

Page 1632: ...o establish whether the RXSTALL bit bit 2 the ERROR bit bit 4 or the NAK_TIMEOUT bit bit 7 has been set If RXSTALL is set it indicates that the target did not accept the command for example because it is not supported by the target device and so has issued a STALL response If ERROR is set it means that the controller has tried to send the SETUP Packet and the following data packet three times with...

Page 1633: ...K limit reached No Yes Error count cleared incremented Error count NAK Timeout set Endpoint halted Interrupt generated Error count 3 No Error bit set TxPktRdy cleared Error Count cleared interrupt generated Yes Implies problem at peripheral end of connection Transaction deemed complete www ti com Architecture 1633 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2...

Page 1634: ...it indicates that the target has issued a STALL response If ERROR is set it means that the controller has tried to send the required IN token three times without getting any response If NAK_TIMEOUT bit is set it means that the controller has received a NAK response to each attempt to send the IN token for longer than the time set in HOST_NAKLIMIT0 The controller can then be directed either to cont...

Page 1635: ...unt 3 No Error bit set ReqPkt cleared Error Count cleared Interrupt generated Yes Implies problem at peripheral end of connection Transaction deemed complete For each IN packet requested in SETUP phase ReqPkt set No ACK sent RxPktRdy set ReqPkt cleared Error Count cleared Interrupt generated www ti com Architecture 1635 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyr...

Page 1636: ...OR bit bit 4 or the NAK_TIMEOUT bit bit 7 has been set If RXSTALL bit is set it indicates that the target has issued a STALL response If ERROR bit is set it means that the controller has tried to send the OUT token and the following data packet three times without getting any response If NAK_TIMEOUT is set it means that the controller has received a NAK response to each attempt to send the OUT tok...

Page 1637: ...ceived Yes NAK limit reached No Yes Error count cleared incremented Error count NAK Timeout set Endpoint halted Interrupt generated Error count 3 No Error bit set TxPktRdy cleared Error Count cleared interrupt generated Yes Implies problem at peripheral end of connection Transaction deemed complete www ti com Architecture 1637 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedbac...

Page 1638: ...hether the RXSTALL bit bit 2 the ERROR bit bit 4 the NAK_TIMEOUT bit bit 7 or RXPKTRDY bit bit 0 has been set If RXSTALL bit is set it indicates that the target could not complete the command and so has issued a STALL response If ERROR bit is set it means that the controller has tried to send the required IN token three times without getting any response If NAK_TIMEOUT bit is set it means that the...

Page 1639: ...eared Interrupt generated Yes Implies problem at peripheral end of connection Transaction deemed complete Completion of either SETUP phase or OUT data phase No ACK sent RxPktRdy set ReqPkt cleared Error Count cleared Interrupt generated ReqPkt and StatusPkt both set Command could not be completed www ti com Architecture 1639 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback ...

Page 1640: ..._CSR0 to establish whether the RXSTALL bit bit 2 the ERROR bit bit 4 or the NAK_TIMEOUT bit bit 7 has been set If RXSTALL bit is set it indicates that the target could not complete the command and so has issued a STALL response If ERROR bit is set it means that the controller has tried to send the STATUS Packet and the following data packet three times without getting any response If NAK_TIMEOUT b...

Page 1641: ...nted Error count NAK Timeout set Endpoint halted Interrupt generated Error count 3 No Error bit set TxPktRdy cleared Error Count cleared interrupt generated Yes Implies problem at peripheral end of connection Transaction deemed complete TxPktRdy and StatusPkt both set Zero length DATA1 packet sent www ti com Architecture 1641 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback...

Page 1642: ...ST_RXTYPE register for the endpoint that is to be used needs to be programmed as Operating speed in the SPEED bit field bits 7 and 6 Set 10 binary value in the PROT field for bulk transfer Endpoint Number of the target device in RENDPN field This is the endpoint number contained in the Rx endpoint descriptor returned by the target device during enumeration The RXMAXP register for the controller en...

Page 1643: ...reports an error by setting the ERROR bit of HOST_RXCSR bit 2 The controller then generates the appropriate endpoint interrupt whereupon the software should read the corresponding HOST_RXCSR register to determine whether the RXPKTRDY RXSTALL ERROR or DATAERR_NAKTIMEOUT bit is set and act accordingly If the DATAERR_NAKTIMEOUT bit is set the controller can be directed either to continue trying this ...

Page 1644: ... transfer Endpoint Number of the target device in TENDPN field This is the endpoint number contained in the OUT Tx endpoint descriptor returned by the target device during enumeration The TXMAXP register for the controller endpoint must be written with the maximum packet size in bytes for the transfer This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for...

Page 1645: ... then generates the appropriate endpoint interrupt whereupon the software should read the corresponding HOST_TXCSR register to determine whether the RXSTALL bit 5 ERROR bit 2 or NAK_TIMEOUT bit 7 bit is set and act accordingly If the NAK_TIMEOUT bit is set the controller can be directed either to continue trying this transaction until it times out again by clearing the NAK_TIMEOUT bit or to abort ...

Page 1646: ...endpoint 34 2 7 2 4 1 1 Setup Before initiating an Isochronous IN Transactions in Host mode The target function address needs to be set in the RXFUNCADDR register for the selected controller endpoint RXFUNCADDR register is available for all endpoints from EP0 to EP4 The HOST_RXTYPE register for the endpoint that is to be used needs to be programmed as Operating speed in the SPEED bit field bits 7 ...

Page 1647: ...ted whenever the endpoint is able to accept another packet in its FIFO This feature can be used to allow the DMA controller to load packets into the FIFO without processor intervention However this feature is not particularly useful with isochronous endpoints because the packets transferred are often not maximum packet size When DMA is enabled and DMAMODE bit in HOST_TXCSR register is set endpoint...

Page 1648: ... additional buffering This can be done by using the SOF_PULSE signal from the controller to trigger the loading of the next data packet The SOF_PULSE is generated once per frame microframe The interrupts may still be used to set the TXPKTRDY bit in HOST_TXCSR 34 2 8 Communications Port Programming Interface CPPI 4 1 DMA Overview The CPPI DMA module supports the transmission and reception of USB pa...

Page 1649: ...it operations and between the Endpoint FIFOs and the CPPI FIFO for receive operations Mentor USB 2 0 Core This controller is responsible for processing USB bus transfers control bulk interrupt and isochronous It supports 4 transmit and 4 receive endpoints in addition to endpoint 0 control 34 2 8 1 CPPI Terminology The following terms are important in the discussion of DMA CPPI Port A port is the c...

Page 1650: ...d for forwarding a packet from one entity to another for any number of purposes Queue Manager The queue manager is a hardware module that is responsible for accelerating management of the packet queues Packets are added to a packet queue by writing the 32 bit descriptor address to a particular memory mapped location in the Queue Manager module Packets are de queued by reading the same location for...

Page 1651: ...it words in the protocol specific region The CPU initializes this field This is encoded in increments of 4 bytes as 0 0 byte 1 4 bytes 16 64 bytes 17 31 Reserved 21 0 Packet Length The length of the packet in bytes If the Packet Length is less than the sum of the buffer lengths then the packet data will be truncated A Packet Length greater than the sum of the buffers is an error The valid range fo...

Page 1652: ...ve descriptors The Tx DMA will return each buffer in sequence 14 On chip This field indicates whether or not this descriptor is in a region which is in on chip memory space 1 or in external memory 0 13 12 Packet Return Queue Mgr This field indicates which queue manager in the system the descriptor is to be returned to after transmission is complete This field is not altered by the DMA during trans...

Page 1653: ...he Host Buffer Descriptor is identical in size and organization to a Host Packet Descriptor but does not include valid information in the packet level fields and does not include a populated region for protocol specific information The packet level fields is not needed since the SOP descriptor contain this information and additional copy of this data is not needed necessary Host Buffer Descriptors...

Page 1654: ...rved Reserved 14 On chip This field indicates whether or not this descriptor is in a region which is in on chip memory space 1 or in external memory 0 13 12 Packet Return Queue Mgr This field indicates which queue manager in the system the descriptor is to be returned to after transmission is complete This field is not altered by the DMA during transmission or reception and is initialized by the C...

Page 1655: ...n 31 0 Original Buffer 0 Pointer The Buffer Pointer is the byte aligned memory address of the buffer associated with the buffer descriptor This value is not overwritten during reception This value is read by the Rx DMA to determine the actual buffer location as allocated by the CPU at initialization Since the buffer pointer in Word 4 is overwritten by the Rx port during reception this field is nec...

Page 1656: ... operations The teardown register in the CPPI DMA must be written the corresponding endpoint bit in TEARDOWN of the USB module must be set and the FlushFIFO bit in the Mentor USB controller Tx RxCSR register must be set The following is the Transmit teardown procedure highlighting the steps required to be followed 1 Set the TX_TEARDOWN bit in the CPPI DMA TX channel n global configuration register...

Page 1657: ...int 4 TX submit queues 24 2 TX Completion return queues 26 2 RX Completion return queues 28 36 Unassigned application defined queues 34 2 8 5 1 Queuing Packets Prior to queuing packets the host firmware should construct data buffer as well host packet buffer descriptors within memory that is external to the CPPI 4 1 DMA module Queuing of packets onto a packet queue is accomplished by writing a poi...

Page 1658: ...pletes 34 2 8 5 3 4 Receive Completion Queue Receive ports also use packet queues referred to as receive completion queues to return packets to the port after they have been received Even though non allocated queues can be used for this purpose a total of two dedicated queues Queue 26 and Queue 27 that is to be shared amongst all four transmit ports have been reserved for returning received packet...

Page 1659: ...ned within all memory regions A minimum of four bytes of memory needs to be allocated for each Descriptor defined within all 16 Memory Regions The Queue Manager has the capability of managing up to 16 Memory Regions These Memory Regions are used to store descriptors of variable sizes The total number of Descriptors that can be managed by the Queue Manager should not exceed 16K Each Memory Region h...

Page 1660: ...he more entries that are present for a given channel the bigger the slice of the bandwidth that channel will be given Larger tables can be accommodated to allow for more precision This array can only be written by the Host it cannot be read 2 If the application does not need to use the entire 256 entries firmware can initialize the portion of the 256 entries and indicate the size of the entries us...

Page 1661: ...ed or a valid block on Rx FIFO empty signal is not asserted 3 If the DMA channel is capable of processing a credit to transfer a block the DMA scheduler will issue that credit via the DMA scheduling interface These are the steps a The DMA controller may not be ready to accept the credit immediately and is provided a sched_ready signal which is used to stall the scheduler until it can accept the cr...

Page 1662: ...ues Each queue has a one head descriptor pointer and one completion pointer There are four Tx DMA State registers one for each port channel The following information is stored in the Tx DMA State Tx Queue Head Descriptor Pointer s Tx Completion Pointer s Protocol specific control status port scratchpad 34 2 8 10 2 Receive DMA State Registers The Rx DMA State is a combination of control fields and ...

Page 1663: ...e larger packet into smaller packets where each packet size being USB MaxPktSize except the last packet where its size is less than USB MaxPktSize including zero bytes This implies that multiple USB packets of MaxPktSize will be received and transferred together as a single large DMA transfer and the DMA interrupt is generated only at the end of the complete reception of DMA transfer The protocol ...

Page 1664: ...t size of any Generic RNDIS mode enabled endpoints must be a multiple of 64 bytes Generic RNDIS acceleration should not be enabled for endpoints where the max packet size is not a multiple of 64 bytes Only transparent mode should be used for such endpoints Generic RNDIS DMA Transfer Setup The following will configure all four ports channels for Generic RNDIS DMA Transfer type Disable RNDIS Mode gl...

Page 1665: ...xample Example assumptions The CPPI data buffers are 256 bytes in length The USB endpoint 1 Tx and Rx endpoint 1 size are 512 bytes A single transfer length is 608 bytes The SOP offset is 0 This translates to the following Transmit Case 1 Host Packet Descriptor with Packet Length field of 608 bytes and a Data Buffer of size 256 Bytes linked to the 1st Host Buffer Descriptor First Host Buffer Descr...

Page 1666: ...ated Universal Serial Bus 2 0 USB Controller PPD Pointer to Host Packet Descriptor RXCQ Receive Completion Queue or Receive Return Queue for all Rx EPs use 26 or 27 RXSQ Receive Free Packet Buffer Descriptor Queue or Receive Submit Queue for all Rx EPs use 0 to 15 TXCQ Transmit Completion Queue or Transmit Return Queue for all Tx EPs use 24 or 25 TXSQ Transmit Queue or Transmit Submit Queue for EP...

Page 1667: ... NOTE You can create more BD DB pairs and push them on one of the unassigned queues The firmware can pop a BD DP pair from this chosen queue and can create its HPD or HBDs and pre link them prior to submitting the pointers to the HPD and HBD on to the TXSQ Step 2 CDMA and XDMA transfers packet data into Endpoint FIFO for Tx 1 The Queue Manager informs the CDMAS that the TXSQ is not empty 2 CDMAS c...

Page 1668: ... remaining 32 byte from the data to be transferred in main memory to the CPPI FIFO d The XDMA sees FIFO_empty not asserted and transfers 32 byte block from CPPI FIFO to Endpoint FIFO Step 3 Mentor USB 2 0 Core transmits USB packets for Tx 1 Once the XDMA has transferred enough 64 byte blocks of data from the CPPI FIFO to fill the Endpoint FIFO it signals the Mentor USB 2 0 Core that a TX packet is...

Page 1669: ...BD 1 PBD 2 PBD 0 Head Tail Queue 0 RXSQ Head Tail Queue 26 RXCQ www ti com Architecture 1669 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Universal Serial Bus 2 0 USB Controller 2 The Queue Manager then indicates the status of the TXSQ empty to the CDMAS and the TXCQ to the CPU via an interrupt 34 2 8 12 2 Receive USB D...

Page 1670: ...e 1 The Mentor USB 2 0 Core receives a USB packet from the USB Host and stores it in the Endpoint FIFO 2 It then asserts a DMA_req to the XDMA informing it that data is available in the Endpoint FIFO 3 The XDMA verifies the corresponding CPPI FIFO is not full via the FIFO_full signal then starts transferring 64 byte data blocks from the Endpoint FIFO into the CPPI FIFO Step 3 CDMA transfers data f...

Page 1671: ...pt conditions are generated the host processor is interrupted The software needs to read the different interrupt status registers discussed in later section to determine the source of the interrupt The nine USB interrupt conditions are listed in Table 34 28 Table 34 28 USB Interrupt Conditions Interrupt Description USB 8 DRVVBUS level change USB 7 VBus voltage VBus Valid Threshold VBus error USB 6...

Page 1672: ...de in which it responds to any valid IN token with a NAK 34 2 9 2 TEST_J To enter the Test_J test mode the software should set the TEST_J bit in the TESTMODE register to 1 The USB controller will then go into a mode in which it transmits a continuous J on the bus 34 2 9 3 TEST_K To enter the Test_K test mode the software should set the TEST_K bit in the TESTMODE register to 1 The USB controller wi...

Page 1673: ...er that records the number of bytes received 2 The Endpoint 0 CPU pointer is reset 3 CSR0 TxPktRdy is cleared 4 CSR0 RxPktRdy is set 5 An Endpoint 0 interrupt is generated if enabled The effect of these steps is to make the Endpoint 0 controller act as if the packet loaded into the Tx FIFO has flushed and the same packet received over the USB The data that was loaded in the Tx FIFO can now be read...

Page 1674: ...upt Support The USB peripheral provides the interrupts listed in Table 34 29 to the interrupt distributor module INTD For information on the mapping of interrupts see your device specific data manual Table 34 29 USB Interrupts Event Acronym Source ARM Event 58 USB0_INT USB 2 0 Controller 34 2 12 DMA Event Support The USB is an internal bus master peripheral and does not utilize EDMA events The USB...

Page 1675: ...s CTRLR 0x00000001 Wait until controller is finished with Reset When done it will clear the RESET bit field while usbRegs CTRLR 0x1 1 RESET Hold PHY in Reset BootCfg CFGCHIP2 0x00008000 Hold PHY in Reset Drive Reset for few clock cycles for I 0 i 50 I RESET Release PHY from Reset BootCfg CFGCHIP2 0xFFFF7FFF Release PHY from Reset Configure PHY with the Desired Operation OTGMODE BootCfg CFGCHIP2 0x...

Page 1676: ... interrupts in OTG block usbRegs CTRLR 0xFFFFFFF7 Enable PDR2 0 Interrupt usbRegs INTRTXE 0x1F Enable All Core Tx Endpoints Interrupts EP0 Tx Rx interrupt usbRegs INTRRXE 0x1E Enable All Core Rx Endpoints Interrupts Enable all interrupts in OTG block usbRegs INTMSKSETR 0x01FF1E1F Enable all USB interrupts in MUSBMHDRC usbRegs INTRUSBE 0xFF Enable SUSPENDM so that suspend can be seen UTMI signal CS...

Page 1677: ...s Program Link Ram0 and Link Ram1 Base Size No Link Ram1 Size Register exists Most likely is using the same Size Register used Link Ram1 Base usbRegs QMGR LRAM0BASE Uint32 queueMgrLinkRam0 usbRegs QMGR LRAM0SIZE LINKRAM0SIZE 4 usbRegs QMGR LRAM1BASE Uint32 queueMgrLinkRam1 Allocate Resource to Region 0 can use any of the 16 available memory location for Host Packet Descriptors DESC_SIZE value shou...

Page 1678: ...to be programmed Since Queues 0 to 15 are alloted for Receive operations and there exist no dedicated queue assignments for each channel a user can associate any Queue with any Channel and this association is not fixed for the Receive Operations Queue 15 0 Any Rx Channel However for Tx Operations Dedicated Submit Queues have been assigned for Each Channel Endpoints Queue 17 16 TxCh 0 Queue 19 18 T...

Page 1679: ...buffer 1 Double buffer For maximum packet size this formula will usually work but it can also be set to another value if needed If non power of 2 value is needed such as 1023 set it explicitly define FIFO_MAXP 8 1 fifosize Set the following variable to the device address int device_address 0 The following code should be run after receiving a USB reset from the host Initialize the endpoint FIFO RX ...

Page 1680: ... If double buffer is selected actual FIFO space will be twice the value listed above for fifosize This example uses single buffer int double_buffer 0 Single buffer int double_buffer 1 Double buffer Set the following variable to the device endpoint type CONTROL ISO BULK or IN int device_protocol BULK int device_protocol ISO int device_protocol INT USB speeds define LOW_SPEED 0 define FULL_SPEED 1 d...

Page 1681: ...ED type 3 6 device_protocol 3 4 device_ep 0xf break case FULL_SPEED type 2 6 device_protocol 3 4 device_ep 0xf break case HIGH_SPEED type 1 6 device_protocol 3 4 device_ep 0xf break default error usbRegs EPCSR CHAN_NUM 1 HOST_TYPE0 type TXTYPE usbRegs EPCSR CHAN_NUM 1 HOST_RXTYPE type Set NAK limit Polling interval Interrupt Iso protocols if device_protocol INT device_protocol ISO usbRegs EPCSR CH...

Page 1682: ...t32 Rsv 6 bits 25 20 Uint32 PktType 5 bits 30 26 Uint32 PktErr 1 bit 31 HPDWord2 typedef struct hostPacketDesc HPDWord0 HPDword0 HPDWord1 HPDword1 HPDWord2 HPDword2 Uint32 HPDword3buffLength Uint32 HPDword4buffAdd Uint32 HPDword5nextHBDptr Uint32 HPDword6orgBuffLength Uint32 HPDword7orgBuffAdd HostPacketDesc The following sample code uses region 0 for all of the ports Ports Channels EPs are not li...

Page 1683: ...stTag 0 Always programmed to ZERO region0DescriptorSpace descNum HPDword1 SrcSubChNum 0 Always programmed to ZERO region0DescriptorSpace descNum HPDword1 SrcChNum 0 Always programmed to ZERO if desc BUFFER_DESC region0DescriptorSpace descNum HPDword1 SrcPrtNum 0 Word1 is Reserved for Buffer DESC else region0DescriptorSpace descNum HPDword1 SrcPrtNum chan_num 1 Ports 1 2 3 4 is associated with Endp...

Page 1684: ...Length prevDescRxNum if dir TRANSMIT prevDescTxNum 1 0 region0DescriptorSpace descNum 1 HPDword5nextHBDptr Uint32 region0DescriptorSpace descNum Modify Previous Link Address region0DescriptorSpace descNum HPDword5nextHBDptr 0 Current Descriptor is the Last Descriptor Null Value is used as the Next Buffer Descriptor Address region0DescriptorSpace descNum HPDword6orgBuffLength region0DescriptorSpace...

Page 1685: ... txSubmitQ etc wait_for_reset wait here until host performs a reset cppiDmaInit Init CPPI 4 1 DMA Initialize Receive Buffer Descriptors Host is performing a transfer and the device is going to loop it back out The example below non commented part of the code applies for a data transfer made of two 64 bytes packet These two packets are treated as part of a single transfer for Non Transparent DMA mo...

Page 1686: ...initSingleHPDorHBD 19 TRANSMIT PACKET_DESC txCompQ Usage initSingleHPDorHBD descNum dir TypeOfDesc returnQueue else initSingleHPDorHBD 17 TRANSMIT BUFFER_DESC txCompQ Usage initSingleHPDorHBD descNum dir TypeOfDesc returnQueue initSingleHPDorHBD 18 TRANSMIT BUFFER_DESC txCompQ Usage initSingleHPDorHBD descNum dir TypeOfDesc returnQueue initSingleHPDorHBD 19 TRANSMIT BUFFER_DESC txCompQ Usage initS...

Page 1687: ...ter Section 34 4 10 28h INTCLRR USB Interrupt Source Clear Register Section 34 4 11 2Ch INTMSKR USB Interrupt Mask Register Section 34 4 12 30h INTMSKSETR USB Interrupt Mask Set Register Section 34 4 13 34h INTMSKCLRR USB Interrupt Mask Clear Register Section 34 4 14 38h INTMASKEDR USB Interrupt Source Masked Register Section 34 4 15 3Ch EOIR USB End of Interrupt Register Section 34 4 16 50h GENRN...

Page 1688: ...t Endpoint 0 Section 34 4 40 RXCOUNT Number of Bytes in Host Receive Endpoint FIFO Index register set to select Endpoints 1 4 Section 34 4 41 41Ah HOST_TYPE0 Defines the speed of Endpoint 0 Section 34 4 42 HOST_TXTYPE Sets the operating speed transaction protocol and peripheral endpoint number for the host Transmit endpoint Index register set to select Endpoints 1 4 only Section 34 4 43 41Bh HOST_...

Page 1689: ...s of the target function that has to be accessed through the associated Receive Endpoint Section 34 4 63 486h RXHUBADDR Address of the hub that has to be accessed through the associated Receive Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub Section 34 4 64 487h RXHUBPORT Port of the hub that has to be accessed through the associated Receive ...

Page 1690: ...that has to be accessed through the associated Transmit Endpoint Section 34 4 60 49Ah TXHUBADDR Address of the hub that has to be accessed through the associated Transmit Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub Section 34 4 61 49Bh TXHUBPORT Port of the hub that has to be accessed through the associated Transmit Endpoint This is used ...

Page 1691: ...m Packet Size for Peripheral Host Receive Endpoint Section 34 4 37 516h PERI_RXCSR Control Status Register for Peripheral Receive Endpoint peripheral mode Section 34 4 38 HOST_RXCSR Control Status Register for Host Receive Endpoint host mode Section 34 4 39 518h RXCOUNT Number of Bytes in Host Receive endpoint FIFO Section 34 4 41 51Ah HOST_TXTYPE Sets the operating speed transaction protocol and ...

Page 1692: ...t Section 34 4 43 53Bh HOST_TXINTERVAL Sets the polling interval for Interrupt ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint Section 34 4 45 53Ch HOST_RXTYPE Sets the operating speed transaction protocol and peripheral endpoint number for the host Receive endpoint Section 34 4 46 53Dh HOST_RXINTERVAL Sets the polling interval for Interrupt ISOC trans...

Page 1693: ...nfiguration Register Section 34 4 69 1868h RXGCR 3 Receive Channel 3 Global Configuration Register Section 34 4 70 186Ch RXHPCRA 3 Receive Channel 3 Host Packet Configuration Register A Section 34 4 71 1870h RXHPCRB 3 Receive Channel 3 Host Packet Configuration Register B Section 34 4 72 2000h DMA_SCHED_CTRL CDMA Scheduler Control Register Section 34 4 73 2800h 28FCh WORD 0 WORD 63 CDMA Scheduler ...

Page 1694: ...CTRLR allows the CPU to control various aspects of the module The CTRLR is shown in Figure 34 28 and described in Table 34 32 Figure 34 28 Control Register CTRLR 31 16 Reserved R 0 15 5 4 3 2 1 0 Reserved RNDIS UINT Reserved CLKFACK RESET R 0 R W 0 R W 0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 34 32 Control Register CTRLR Field Descriptions Bit Field Value Descr...

Page 1695: ...it Field Value Description 31 1 Reserved 0 Reserved 0 DRVVBUS Current DRVVBUS value 0 DRVVBUS value is logic 0 1 DRVVBUS value is logic 1 34 4 4 Emulation Register EMUR The emulation register EMUR allows the CPU to configure the CBA 3 0 emulation interface The EMUR is shown in Figure 34 30 and described in Table 34 34 Figure 34 30 Emulation Register EMUR 31 16 Reserved R 0 15 3 2 1 0 Reserved RT_S...

Page 1696: ...served 0 Reserved 29 28 RX4_MODE 0 3h Receive endpoint 4 mode control 0 Transparent mode on Receive endpoint 4 1h RNDIS mode on Receive endpoint 4 2h CDC mode on Receive endpoint 4 3h Generic RNDIS mode on Receive endpoint 4 27 26 Reserved 0 Reserved 25 24 RX3_MODE 0 3h Receive endpoint 3 mode control 0 Transparent mode on Receive endpoint 3 1h RNDIS mode on Receive endpoint 3 2h CDC mode on Recei...

Page 1697: ...IS mode on Transmit endpoint 3 2h CDC mode on Transmit endpoint 3 3h Generic RNDIS mode on Transmit endpoint 3 7 6 Reserved 0 Reserved 5 4 TX2_MODE 0 3h Transmit endpoint 2 mode control 0 Transparent mode on Transmit endpoint 2 1h RNDIS mode on Transmit endpoint 2 2h CDC mode on Transmit endpoint 2 3h Generic RNDIS mode on Transmit endpoint 2 3 2 Reserved 0 Reserved 1 0 TX1_MODE 0 3h Transmit endp...

Page 1698: ...n the CPPI descriptor For RNDIS CDC and Generic RNDIS modes the auto request stops when the EOP is received either via a short packet for RNDIS CDC and Generic RNDIS or the count is reached for Generic RNDIS making it useful for starting a large RNDIS packet and having it auto generate IN tokens until the end of the RNDIS packet For transparent mode every USB packet is an EOP CPPI packet so the au...

Page 1699: ...rols the tearing down of receive and transmit FIFOs in the USB controller When a 1 is written to a valid bit in TEARDOWN the CPPI FIFO pointers for that endpoint are cleared TEARDOWN must be used in conjunction with the CPPI DMA teardown mechanism The Host should also write the FLUSHFIFO bits in the TXCSR and RXCSR registers to ensure a complete teardown of the endpoint The TEARDOWN is shown in Fi...

Page 1700: ...ved USB R 0 R 0 15 13 12 9 8 5 4 1 0 Reserved RXEP n Reserved TXEP n EP0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 34 39 USB Interrupt Source Register INTSRCR Field Descriptions Bit Field Value Description 31 25 Reserved 0 Reserved 24 16 USB 0 1FFh USB interrupt sources Generated by the USB core not by the DMA Note INTRUSB core interrupts are mapped onto bits 23 16 and bit 2...

Page 1701: ...ETR 31 25 24 16 Reserved USB R 0 R W 0 15 13 12 9 8 5 4 1 0 Reserved RXEP n Reserved TXEP n EP0 R 0 R W 0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 34 40 USB Interrupt Source Set Register INTSETR Field Descriptions Bit Field Value Description 31 25 Reserved 0 Reserved 24 16 USB 0 1FFh Write a 1 to set equivalent USB interrupt source Allows the USB interrupt source...

Page 1702: ... W 0 15 13 12 9 8 5 4 1 0 Reserved RXEP n Reserved TXEP n EP0 R 0 R W 0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 34 41 USB Interrupt Source Clear Register INTCLRR Field Descriptions Bit Field Value Description 31 25 Reserved 0 Reserved 24 16 USB 0 1FFh Write a 1 to clear equivalent USB interrupt source Allows the CPU to acknowledge a USB interrupt source and turn...

Page 1703: ...in CTRLR is set to 1 you need to use the interrupt status flag from the core register space Figure 34 38 USB Interrupt Mask Register INTMSKR 31 25 24 16 Reserved USB R 0 R 0 15 13 12 9 8 5 4 1 0 Reserved RXEP n Reserved TXEP n EP0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 34 42 USB Interrupt Mask Register INTMSKR Field Descriptions Bit Field Value Description 31 25 Reserved ...

Page 1704: ...12 9 8 5 4 1 0 Reserved RXEP n Reserved TXEP n EP0 R 0 R W 0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 34 43 USB Interrupt Mask Set Register INTMSKSETR Field Descriptions Bit Field Value Description 31 25 Reserved 0 Reserved 24 16 USB 0 1FFh Write a 1 to set equivalent USB interrupt source mask Allows the USB interrupt source masks to be manually enabled 15 13 Res...

Page 1705: ... 9 8 5 4 1 0 Reserved RXEP n Reserved TXEP n EP0 R 0 R W 0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 34 44 USB Interrupt Mask Clear Register INTMSKCLRR Field Descriptions Bit Field Value Description 31 25 Reserved 0 Reserved 24 16 USB 0 1FFh Write a 1 to clear equivalent USB interrupt source mask Allows the USB interrupt source masks to be manually disabled 15 13 ...

Page 1706: ... you need to use the interrupt status flag from the core register space Figure 34 41 USB Interrupt Source Masked Register INTMASKEDR 31 25 24 16 Reserved USB R 0 R 0 15 13 12 9 8 5 4 1 0 Reserved RXEP n Reserved TXEP n EP0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 34 45 USB Interrupt Source Masked Register INTMASKEDR Field Descriptions Bit Field Value Description 31 25 Reser...

Page 1707: ...or 34 4 17 Generic RNDIS EP1 Size Register GENRNDISSZ1 The generic RNDIS EP1 size register GENRNDISSZ1 is programmed with a RNDIS packet size in bytes When EP1 is in Generic RNDIS mode the received USB packets are collected into a single CPPI packet that is completed when the number of bytes equal to the value of this register have been received or a short packet is received This register must be ...

Page 1708: ... value after reset Table 34 48 Generic RNDIS EP2 Size Register GENRNDISSZ2 Field Descriptions Bit Field Value Description 31 17 Reserved 0 Reserved 16 0 EP2_SIZE 0 10000h Generic RNDIS packet size 34 4 19 Generic RNDIS EP3 Size Register GENRNDISSZ3 The generic RNDIS EP3 size register GENRNDISSZ3 is programmed with a RNDIS packet size in bytes When EP3 is in Generic RNDIS mode the received USB pack...

Page 1709: ...ed EP4_SIZE R 0 R W 0 15 0 EP4_SIZE R W 0 LEGEND R W Read Write R Read only n value after reset Table 34 50 Generic RNDIS EP4 Size Register GENRNDISSZ4 Field Descriptions Bit Field Value Description 31 17 Reserved 0 Reserved 16 0 EP4_SIZE 0 10000h Generic RNDIS packet size 34 4 21 Function Address Register FADDR The function address register FADDR is shown in Figure 34 47 and described in Table 34...

Page 1710: ...ONN 0 1 If Soft Connect Disconnect feature is enabled then the USB D D lines are enabled when this bit is set and tri stated when this bit is cleared Note this is only valid in Peripheral Mode 5 HSEN 0 1 When set the USB controller will negotiate for high speed mode when the device is reset by the hub If not set the device will only operate in full speed mode 4 HSMODE 0 1 This bit is set when the ...

Page 1711: ...read clears the pending interrupt Use INTRTX only when in the non PDR interrupt mode that is when handling the interrupt directly from the controller Figure 34 49 Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 INTRTX 15 8 Reserved R 0 7 5 4 3 2 1 0 Reserved EP4TX EP3TX EP2TX EP1TX EP0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 34 53 Interrupt Register for Endp...

Page 1712: ...ming a read clears the pending interrupt Use INTRRX only when in the non PDR interrupt mode that is when handling the interrupt directly from the controller Figure 34 50 Interrupt Register for Receive Endpoints 1 to 4 INTRRX 15 8 Reserved R 0 7 5 4 3 2 1 0 Reserved EP4RX EP3RX EP2RX EP1RX Rsvd R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 34 54 Interrupt Register for Receive...

Page 1713: ... 4 interrupt active 3 EP3TX 0 1 Transmit Endpoint 3 interrupt active 2 EP2TX 0 1 Transmit Endpoint 2 interrupt active 1 EP1TX 0 1 Transmit Endpoint 1 interrupt active 0 EP0 0 1 Endpoint 0 interrupt active 34 4 26 Interrupt Enable Register for INTRRX INTRRXE The interrupt enable register for INTRRX INTRRXE is shown in Figure 34 52 and described in Table 34 56 Figure 34 52 Interrupt Enable Register ...

Page 1714: ...R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 34 57 Interrupt Register for Common USB Interrupts INTRUSB Field Descriptions Bit Field Value Description 7 VBUSERR 0 1 Set when VBus drops below the VBus valid threshold during a session Only valid when the USB controller is A device All active interrupts will be cleared when this register is read 6 SESSREQ 0 1 Set when session request ...

Page 1715: ...egister for INTRUSB INTRUSBE Field Descriptions Bit Field Value Description 7 VBUSERR 0 1 Vbus error interrupt enable 6 SESSREQ 0 1 Session request interrupt enable 5 DISCON 0 1 Disconnect interrupt enable 4 CONN 0 1 Connect interrupt enable 3 SOF 0 1 Start of frame interrupt enable 2 RESET_BABBLE 0 1 Reset interrupt enable 1 RESUME 0 1 Resume interrupt enable 0 SUSPEND 0 1 Suspend interrupt enabl...

Page 1716: ...EGEND R W Read Write W Write only n value after reset Table 34 61 Register to Enable the USB 2 0 Test Modes TESTMODE Field Descriptions Bit Field Value Description 7 FORCE_HOST 0 1 Set this bit to forcibly put the USB controller into Host mode when SESSION bit is set regardless of whether it is connected to any peripheral The controller remains in Host mode until the Session bit is cleared even if...

Page 1717: ...AXPAYLOAD R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 34 62 Maximum Packet Size for Peripheral Host Transmit Endpoint TXMAXP Field Descriptions Bit Field Value Description 15 11 Reserved 0 Reserved 10 0 MAXPAYLOAD 0 400h The maximum payload transmitted in a single transaction The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specifi...

Page 1718: ... RXPKTRDY is set 7 SERV_SETUPEND 0 1 Set this bit to clear the SETUPEND bit It is cleared automatically 6 SERV_RXPKTRDY 0 1 Set this bit to clear the RXPKTRDY bit It is cleared automatically 5 SENDSTALL 0 1 Set this bit to terminate the current transaction The STALL handshake will be transmitted and then this bit will be cleared automatically 4 SETUPEND 0 1 This bit will be set when a control tran...

Page 1719: ...OGWREN is low any value written to this bit is ignored 8 FLUSHFIFO 0 1 Write 1 to this bit to flush the next packet to be transmitted read from the Endpoint 0 FIFO The FIFO pointer is reset and the TXPKTRDY RXPKTRDY bit is cleared Note FLUSHFIFO has no effect unless TXPKTRDY RXPKTRDY is set 7 NAK_TIMEOUT 0 1 This bit will be set when Endpoint 0 is halted following the receipt of NAK responses for ...

Page 1720: ...ly where the same endpoint FIFO is used for both Transmit and Receive transactions 12 DMAEN 0 1 Set this bit to enable the DMA request for the Tx endpoint 11 FRCDATATOG 0 1 Set this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO regardless of whether an ACK was received This can be used by Interrupt Tx endpoints that are used to communicate rate fee...

Page 1721: ...MODE 0 1 This bit should always be set to 1 when the DMA is enabled 9 DATATOGWREN 0 1 Write 1 to this bit to enable the DATATOG bit to be written This bit is automatically cleared once the new value is written to DATATOG 8 DATATOG 0 1 When read this bit indicates the current state of the Tx EP data toggle If DATATOGWREN is high this bit can be written with the required setting of the data toggle I...

Page 1722: ...ad only n value after reset Table 34 67 Maximum Packet Size for Peripheral Host Receive Endpoint RXMAXP Field Descriptions Bit Field Value Description 15 11 Reserved 0 Reserved 10 0 MAXPAYLOAD 0 400h Defines the maximum amount of data that can be transferred through the selected Receive endpoint in a single frame microframe high speed transfers The value set can be up to 1024 bytes but is subject ...

Page 1723: ... are ACK d including at the point at which the FIFO becomes full Note This bit only has any effect in high speed mode in which mode it should be set for all Interrupt endpoints 1 PID_ERROR Applies only for ISO Transactions The core sets this bit to indicate a PID error in the received packet 11 DMAMODE 0 1 Always clear this bit to 0 10 8 Reserved 0 Reserved 7 CLRDATATOG 0 1 Write a 1 to this bit t...

Page 1724: ... which mode it should be set for all Interrupt endpoints 11 DMAMODE 0 1 Always clear this bit to 0 10 DATATOGWREN 0 1 Write 1 to this bit to enable the DATATOG bit to be written This bit is automatically cleared once the new value is written to DATATOG 9 DATATOG 0 1 When read this bit indicates the current state of the Receive EP data toggle If DATATOGWREN is high this bit can be written with the ...

Page 1725: ...ue after reset Table 34 70 Count 0 Register COUNT0 Field Descriptions Bit Field Value Description 15 7 Reserved 0 Reserved 6 0 EP0RXCOUNT 0 7Fh Indicates the number of received data bytes in the Endpoint 0 FIFO The value returned changes as the contents of the FIFO change and is only valid while RXPKTRDY of PERI_CSR0 or HOST_CSR0 is set 34 4 41 Receive Count Register RXCOUNT The receive count regi...

Page 1726: ... High 2h Full 3h Low 5 0 Reserved 0 Reserved 34 4 43 Transmit Type Register Host mode only HOST_TXTYPE The transmit type register Host mode only HOST_TXTYPE is shown in Figure 34 69 and described in Table 34 73 Figure 34 69 Transmit Type Register Host mode only HOST_TXTYPE 7 6 5 4 3 0 SPEED PROT TENDPN R W 0 R W 0 R W 0 LEGEND R W Read Write n value after reset Table 34 73 Transmit Type Register H...

Page 1727: ...t function 34 4 45 Transmit Interval Register Host mode only HOST_TXINTERVAL The transmit interval register Host mode only HOST_TXINTERVAL is shown in Figure 34 71 and described in Table 34 75 Figure 34 71 Transmit Interval Register Host mode only HOST_TXINTERVAL 7 0 POLINTVL_NAKLIMIT R W 0 LEGEND R W Read Write n value after reset Table 34 75 Transmit Interval Register Host mode only HOST_TXINTER...

Page 1728: ... Host mode only HOST_RXTYPE 7 6 5 4 3 0 SPEED PROT RENDPN R W 0 R W 0 R W 0 LEGEND R W Read Write n value after reset Table 34 76 Receive Type Register Host mode only HOST_RXTYPE Field Descriptions Bit Field Value Description 7 6 SPEED 0 3h Operating Speed of Target Device 0 Illegal 1h High 2h Full 3h Low 5 4 PROT 0 3h Set this to select the required protocol for the transmit endpoint 0 Control 1h...

Page 1729: ...IMIT 0 FFh For Interrupt and Isochronous transfers defines the polling interval for the currently selected transmit endpoint For Bulk endpoints sets the number of frames microframes after which the endpoint should timeout on receiving a stream of NAK responses There is a transmit interval register for each configured transmit endpoint except Endpoint 0 In each case the value that is set defines a ...

Page 1730: ...mation of bulk packets is selected 6 MPTXE Indicates automatic splitting of bulk packets 0 Automatic splitting of bulk packets is not selected 1 Automatic splitting of bulk packets is selected 5 BIGENDIAN Indicates endian ordering 0 Little endian ordering is selected 1 Big endian ordering is selected 4 HBRXE Indicates high bandwidth Rx ISO endpoint support 0 High bandwidth Rx ISO endpoint support ...

Page 1731: ...FFF FFFFh Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint Reading from these addresses unloads data from the Receive FIFO for the corresponding endpoint 34 4 50 Transmit and Receive FIFO Register for Endpoint 1 FIFO1 The transmit and receive FIFO register for endpoint 1 FIFO1 is shown in Figure 34 76 and described in Table 34 80 Figure 34 76 Transmit and...

Page 1732: ...FF FFFFh Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint Reading from these addresses unloads data from the Receive FIFO for the corresponding endpoint 34 4 52 Transmit and Receive FIFO Register for Endpoint 3 FIFO3 The transmit and receive FIFO register for endpoint 3 FIFO3 is shown in Figure 34 78 and described in Table 34 82 Figure 34 78 Transmit and ...

Page 1733: ...ption 7 BDEVICE This read only bit indicates whether the USB controller is operating as the A device or the B device 0 A device 1 B device Only valid while a session is in progress 6 FSDEV 0 1 This read only bit is set when a full speed or high speed device has been detected being connected to the port high speed devices are distinguished from full speed by checking for high speed chirps when the ...

Page 1734: ...to be allowed before any splitting within the FIFO of Bulk packets prior to transmission If m SZ the FIFO size is calculated as 2 m 3 for single packet buffering and 2 m 4 for dual packet buffering 34 4 56 Receive Endpoint FIFO Size RXFIFOSZ Section 34 2 6 describes dynamically setting endpoint FIFO sizes The option of dynamically setting endpoint FIFO sizes only applies to Endpoints 1 4 The Endpo...

Page 1735: ...ress TXFIFOADDR Field Descriptions Bit Field Value Description 15 13 Reserved 0 Reserved 12 0 ADDR 0 1FFFh Start Address of endpoint FIFO in units of 8 bytes If m ADDR then the start address is 8 m 34 4 58 Receive Endpoint FIFO Address RXFIFOADDR Section 34 2 6 describes dynamically setting endpoint FIFO sizes The receive endpoint FIFO address RXFIFOADDR is shown in Figure 34 84 and described in T...

Page 1736: ...ler module The RTL version number is REVMAJ REVMIN The HWVERS is shown in Figure 34 85 and described in Table 34 89 Figure 34 85 Hardware Version Register HWVERS 15 14 10 9 0 RC REVMAJ REVMIN R 0 R 0 R 0 LEGEND R Read only n value after reset Table 34 89 Hardware Version Register HWVERS Field Descriptions Bit Field Value Description 15 RC 0 1 Set to 1 if RTL is used from a Release Candidate rather...

Page 1737: ...transmit hub address TXHUBADDR is shown in Figure 34 87 and described in Table 34 91 Figure 34 87 Transmit Hub Address TXHUBADDR 7 6 0 MULT_TRANS HUBADDR R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 34 91 Transmit Hub Address TXHUBADDR Field Descriptions Bit Field Value Description 7 MULT_TRANS 0 1 Set to 1 if hub has multiple transaction translators Cleared to 0 if only...

Page 1738: ...he receive hub address RXHUBADDR is shown in Figure 34 90 and described in Table 34 94 Figure 34 90 Receive Hub Address RXHUBADDR 7 6 0 MULT_TRANS HUBADDR R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 34 94 Receive Hub Address RXHUBADDR Field Descriptions Bit Field Value Description 7 MULT_TRANS 0 1 Set to 1 if hub has multiple transaction translators Cleared to 0 if only...

Page 1739: ...iptor queue control register TDFDQ is used to inform the DMA of the location in memory or descriptor array which is to be used for signaling of a teardown complete for each transmit and receive channel The CDMA teardown free descriptor queue control register TDFDQ is shown in Figure 34 93 and described in Table 34 97 Figure 34 93 CDMA Teardown Free Descriptor Queue Control Register TDFDQ 31 16 Res...

Page 1740: ... Transmit Channel n Global Configuration Registers TXGCR 0 TXGCR 3 The transmit channel n configuration registers TXGCR n initialize the behavior of each of the transmit DMA channels There are four configuration registers one for each transmit DMA channels The transmit channel n configuration registers TXGCR n are shown in Figure 34 95 and described in Table 34 99 Figure 34 95 CDMA Transmit Channe...

Page 1741: ...after a channel teardown is complete 29 25 Reserved 0 Reserved 24 RX_ERROR_HANDLING Controls the error handling mode for the channel and is only used when channel errors i e descriptor or buffer starvation occur 0 Starvation errors result in dropping packet and reclaiming any used descriptor or buffer resources back to the original queues pools they were allocated to 1 Starvation errors result in ...

Page 1742: ..._FDQ1_QNUM R 0 W 0 W 0 15 14 13 12 11 0 Reserved RX_HOST_FDQ0_QMGR RX_HOST_FDQ0_QNUM R 0 W 0 W 0 LEGEND R Read only W Write only n value after reset Table 34 101 Receive Channel n Host Packet Configuration Registers A RXHPCRA n Field Descriptions Bit Field Value Description 31 30 Reserved 0 Reserved 29 28 RX_HOST_FDQ1_QMGR 0 3h Specifies which buffer manager should be used for the second receive b...

Page 1743: ... 0 W 0 15 14 13 12 11 0 Reserved RX_HOST_FDQ2_QMGR RX_HOST_FDQ2_QNUM R 0 W 0 W 0 LEGEND R Read only W Write only n value after reset Table 34 102 Receive Channel n Host Packet Configuration Registers B RXHPCRB n Field Descriptions Bit Field Value Description 31 30 Reserved 0 Reserved 29 28 RX_HOST_FDQ3_QMGR 0 3h Specifies which buffer manager should be used for the fourth or later receive buffer i...

Page 1744: ...tialized 30 8 Reserved 0 Reserved 7 0 LAST_ENTRY 0 FFh Indicates the last valid entry in the scheduler table There are 64 words in the table and there are 4 entries in each word The table can be programmed with any integer number of entries from 1 to 256 The corresponding encoding for this field is as follows 0 1 entry 1h 2 entries 2h FFh 3 entries to 256 entries 34 4 74 CDMA Scheduler Table Word ...

Page 1745: ... in the receive credit will actually be the channel number which is currently on the head element of that Rx FIFO which is not necessarily the channel number given in the scheduler table entry 15 ENTRY1_RXTX This entry is for a transmit or a receive channel 0 Transmit channel 1 Receive channel 14 12 Reserved 0 Reserved 11 8 ENTRY1_CHANNEL 0 Fh Indicates the channel number that is to be given an op...

Page 1746: ... of the queue manager 34 4 76 Queue Manager Queue Diversion Register DIVERSION The queue manager queue diversion register DIVERSION is used to transfer the contents of one queue onto another queue It does not support byte accesses The queue manager queue diversion register DIVERSION is shown in Figure 34 102and described in Table 34 106 Figure 34 102 Queue Manager Queue Diversion Register DIVERSIO...

Page 1747: ...4 23 16 FDBQ3_STARVE_CNT FDBQ2_STARVE_CNT RC 0 RC 0 15 8 7 0 FDBQ1_STARVE_CNT FDBQ0_STARVE_CNT RC 0 RC 0 LEGEND RC Cleared on read n value after reset Table 34 107 Queue Manager Free Descriptor Buffer Starvation Count Register 0 FDBSC0 Field Descriptions Bit Field Value Description 31 24 FDBQ3_STARVE_CNT 0 FFh This field increments each time the Free Descriptor Buffer Queue 3 is read while it is e...

Page 1748: ... 24 23 16 FDBQ7_STARVE_CNT FDBQ6_STARVE_CNT RC 0 RC 0 15 8 7 0 FDBQ5_STARVE_CNT FDBQ4_STARVE_CNT RC 0 RC 0 LEGEND RC Cleared on read n value after reset Table 34 108 Queue Manager Free Descriptor Buffer Starvation Count Register 1 FDBSC1 Field Descriptions Bit Field Value Description 31 24 FDBQ7_STARVE_CNT 0 FFh This field increments each time the Free Descriptor Buffer Queue 7 is read while it is...

Page 1749: ...4 23 16 FDBQ11_STARVE_CNT FDB10_STARVE_CNT RC 0 RC 0 15 8 7 0 FDBQ9_STARVE_CNT FDBQ8_STARVE_CNT RC 0 RC 0 LEGEND RC Cleared on read n value after reset Table 34 109 Queue Manager Free Descriptor Buffer Starvation Count Register 2 FDBSC2 Field Descriptions Bit Field Value Description 31 24 FDBQ11_STARVE_CNT 0 FFh This field increments each time the Free Descriptor Buffer Queue 11 is read while it i...

Page 1750: ...each time the Free Descriptor Buffer Queue 14 is read while it is empty This field is cleared when read 15 8 FDBQ13_STARVE_CNT 0 FFh This field increments each time the Free Descriptor Buffer Queue 13 is read while it is empty This field is cleared when read 7 0 FDBQ12_STARVE_CNT 0 FFh This field increments each time the Free Descriptor Buffer Queue 12 is read while it is empty This field is clear...

Page 1751: ...with index less than region0_size value has its linking location in region 0 A descriptor with index greater than region0_size has its linking location in region 1 The queue manager will add the index left shifted by 2 bits to the appropriate regionX_base_addr to get the absolute 32 bit address to the linking location for a descriptor 34 4 83 Queue Manager Linking RAM Region 1 Base Address Registe...

Page 1752: ...et Table 34 114 Queue Manager Queue Pending Register 0 PEND0 Field Descriptions Bit Field Value Description 31 0 QPEND0 0 FFFF FFFFh This field indicates the queue pending status for queues 31 0 34 4 85 Queue Manager Queue Pending Register 1 PEND1 The queue pending register 1 PEND1 can be read to find the pending status for queues 63 to 32 It does not support byte accesses The queue pending regist...

Page 1753: ...his memory region will store a number of descriptors of a particular size as determined by the memory region R control register It does not support byte accesses The memory region R base address register QMEMRBASE R is shown in Figure 34 112 and described in Table 34 116 Figure 34 112 Queue Manager Memory Region R Base Address Registers QMEMRBASE R 31 0 REG R W 0 LEGEND R W Read Write n value afte...

Page 1754: ...1 30 29 16 Reserved START_INDEX R 0 R W 0 15 12 11 8 7 3 2 0 Reserved DESC_SIZE Reserved REG_SIZE R 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 34 117 Queue Manager Memory Region R Control Registers QMEMRCTRL R Field Descriptions Bit Field Value Description 31 30 Reserved 0 Reserved 29 16 START_INDEX 0 3FFFh This field indicates where in linking RAM the descriptor...

Page 1755: ...not support byte accesses The queue manager queue N control register D CTRLD N is shown in Figure 34 114 and described in Table 34 118 Figure 34 114 Queue Manager Queue N Control Register D CTRLD N 31 16 DESC_PTR R W 0 15 5 4 0 DESC_PTR DESC_SIZE R W 0 R W 0 LEGEND R W Read Write n value after reset Table 34 118 Queue Manager Queue N Control Register D CTRLD N Field Descriptions Bit Field Value De...

Page 1756: ...Bit Field Value Description 31 14 Reserved 0 Reserved 13 0 QUEUE_ENTRY_COUNT 0 3FFFh This field indicates how many packets are currently queued on the queue 34 4 90 Queue Manager Queue N Status Register B QSTATB 0 QSTATB 63 The queue manager queue N status register B QSTATB N is an optional register that is only implemented for a queue if the queue supports a total byte count feature The total byt...

Page 1757: ...ement of a queue It does not support byte accesses The queue manager queue N status register C QSTATC N is shown in Figure 34 117 and described in Table 34 121 Figure 34 117 Queue Manager Queue N Status Register C QSTATC N 31 16 Reserved R 0 15 14 13 0 Reserved PACKET_SIZE R 0 R 0 LEGEND R Read only n value after reset Table 34 121 Queue Manager Queue N Status Register C QSTATC N Field Description...

Page 1758: ...yright 2013 2016 Texas Instruments Incorporated Video Port Interface VPIF Chapter 35 SPRUH82C April 2013 Revised September 2016 Video Port Interface VPIF This chapter describes the video port interface VPIF Topic Page 35 1 Introduction 1759 35 2 Architecture 1763 35 3 Registers 1784 ...

Page 1759: ...ry 8 Raw capture mode www ti com Introduction 1759 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Video Port Interface VPIF 35 1 Introduction 35 1 1 Overview The video port interface VPIF has two video input channels and two video output channels Channels 0 and 1 share the same receive architecture and channels 2 and 3 sh...

Page 1760: ...orporated Video Port Interface VPIF 35 1 2 Features The VPIF is designed to support the following features note that some device designs may support reduced features because of system level performance limitations ITU BT 656 format ITU BT 1120 and SMTPE 296 formats Raw data capture VBI data storage Clipping of output data to eliminate FFh and 00h values 35 1 3 Features Not Supported The following ...

Page 1761: ... Format conv 3 Reg I F 3 Cache manager Each 512 byte 64 bit x64 word x2 as ping pong buffer Vbus Pic I F 8 VBUSP DMA I F VBUSP DMA I F bi directional VBUSP DMA I F bi directional Domain conv 0 Domain conv 1 Domain conv 2 Domain conv 3 Video clock domain DMA clock domain Video port interface module www ti com Introduction 1761 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback...

Page 1762: ...ed The supported VBI format is be based on ITU BT 1364 Table 35 2 describes the usage combinations that are supported in the VPIF Table 35 1 Supported Formats on VPIF TV System Format TV Definition Format HDTV rec 1120 no support of ancillary data SDTV rec 656 ancillary data is based on BT 1364 NTSC 1125 line 60 field vertical 525 line 60 field vertical 2200 pixel horizontal 858 pixel horizontal P...

Page 1763: ...n Name Rec 656 Rec 1120 Raw Data Capture DIN 0 data0 0 luma 0 raw_data 0 DIN 8 data1 0 chroma 0 raw_data 8 DIN 1 data0 1 luma 1 raw_data 1 DIN 9 data1 1 chroma 1 raw_data 9 DIN 2 data0 2 luma 2 raw_data 2 DIN 10 data1 2 chroma 2 raw_data 10 DIN 3 data0 3 luma 3 raw_data 3 DIN 11 data1 3 chroma 3 raw_data 11 DIN 4 data0 4 luma 4 raw_data 4 DIN 12 data1 4 chroma 4 not used DIN 5 data0 5 luma 5 raw_d...

Page 1764: ...ield 602 669 L9 First line of bottom field for active video area 603 670 L10 Last line of bottom field for active video area 1120 1245 L11 First line of digital field blanking for top field 1121 1246 L12 Last line of bottom field 1125 1250 263 310 20 23 19 22 4 1 SDTV case 264 311 265 312 266 313 282 335 283 336 525 623 1 624 3 625 0 0 0 0 F 0 0 1 1 1 1 1 1 0 0 1 1 V 1 1 1 1 0 0 1 1 Bottom field h...

Page 1765: ...Figure 35 5 Figure 35 5 Progressive Video The buffer register configurations are latched at L1 in progressive format Data on L5 to L6 is stored into a different memory buffer from data on L1 to L2 because the base address is changed at timing of L1 All parameters L1 to L6 for progressive video are configured through VPIF register settings Progressive video is divided into four buffer spaces 1 VBI ...

Page 1766: ...ored in isolated buffers Top and bottom field buffer start addresses are independent Address offset per line of data in each top and bottom field buffer is equal to hofst CnIMGOFFSET hofst Frame format Top and bottom field data sets are interlaced in memory Top field buffer start address is coupled with bottom field buffer start address Top Start Bottom Start hofst Bottom field buffer start addres...

Page 1767: ...l uses a reference input clock CLKINn and a video output clock CLKOUTn When transmit is enabled VPIF will generate CLKOUTn with the same frequency as CLKINn and video data will be transmitted synchronously with CLKOUTn The CLKOUTn output signal is enabled by setting the CLKEN bit in the channel control register CnCTRL the signal can also be inverted by setting the CLKEDGE bit in the CnCTRL registe...

Page 1768: ...receive channel uses an input clock CLKINn When receive is enabled video data is latched synchronously with the rising edge of CLKINn The VPIF can be reconfigured to latch on the falling edge of CLKINn by setting the CLKEDGE bit in the CnCTRL register When receiving BT 1120 video data the two receive channels operate as a pair To ensure that video data is received at the same time across both chan...

Page 1769: ... the FRAME1 signal and the other is asserted at the end of the capture area frame_interrupt through the FRAME0 signal See Figure 35 7 Note that line_interrupt is only supported in raw mode In other modes BT 656 BT 1120 and SMPTE 296M line_interrupt is not supported The following functions are not supported No support of color space conversion from RGB to YCbCr No CFA interpolation for each raw dat...

Page 1770: ...Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Video Port Interface VPIF 35 2 6 1 1 Progressive CCD Raw Capture Mode The CCD Raw Capture mode is illustrated in Figure 35 8 In this mode data within the active periods of both raw_v_valid and raw_h_valid is captured by VPIF The falling edges of the two valid signals serve as the vertical and horizontal synchronizatio...

Page 1771: ... falling edge of the vertical valid signal raw_v_valid and the horizontal valid signal raw_h_valid is regarded as the normal vertical and horizontal synchronization signals respectively The field ID raw_fid is detected at the rising edge of the raw_v_valid signal The description of the detail value in Figure 35 8 is based on the description on the Micron Image sensor device specification sheet In ...

Page 1772: ...ween SAV and EAV horizontal active video area Transmit and receive of ancillary data is enabled by setting the HANC and VANC bits in the C0CTRL and C2CTRL control registers 35 2 7 1 VBI Ancillary Data Transmit The ancillary data to be transmitted is prepared by the user outside of VPIF Ancillary register settings determine the origin position of the ancillary data within the VBI and how much ancil...

Page 1773: ...st cases video ancillary data is inserted in the blanking interval for either the horizontal or vertical direction But in some cases such as CGMS or closed caption that is in Japanese and US applications the line number where these kinds of ancillary data is inserted is in the active video area In the case that ancillary data is inserted in the active video area the VPIF regards the incoming or st...

Page 1774: ...words SAV 4words Top Field Blanking Area Bottom Field Blanking Area Top Field Blanking Area Bottom Field Blanking Area Bottom Field Active Video Area Top Field Active Video Area Never Clipped Architecture www ti com 1774 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Video Port Interface VPIF Data Areas and Clipping Funct...

Page 1775: ...d be taken when VPIF interrupts are combined at the system level In a combined interrupt configuration the CPU may be busy servicing a VPIF interrupt when another VPIF interrupt arrives If the interrupt controller has no means to count VPIF interrupts the CPU will drop subsequent VPIF interrupts until servicing of the first VPIF interrupt is complete Field Frame Interrupts to CPU This section desc...

Page 1776: ... from the VPIF is asserted when the vertical synchronization signal is received So no incoming data is written in memory when the first interrupt is asserted from the VPIF Relationship Between the First Interrupt and Incoming Data If the CPU uses this interrupt signal not only for the time interval between each video frame but also for the timing to read the stored data from the defined area in me...

Page 1777: ...Line Interrupts to CPU In raw data capture mode CCD CMOS capture VPIF will issue line interval triggered interrupts using the field frame interrupt signals The line interval is programmable in the C0CTRL register and it uses the FRAME1 interrupt signal Emulation Considerations 35 2 10 1 Emulation Suspend Mode Support The VPIF supports the emulation suspend signal from the CPU The emulation suspend...

Page 1778: ...ansmits output data to an external video device Source data for this output data is stored in SDRAM The VPIF needs information about the start address of the source data stored in SDRAM The output format is BT 656 or BT 1120 In this mode any suspend function should not be activated because you would like to see a displayed picture taking usage of this signal into consideration From a system s stan...

Page 1779: ...gister CnCTRL Writing to CnCTRL takes effect exactly at the same time you write to it it does not wait to be latched by the VSYNC Figure 35 14 Method for Turning off Module Channel Standard Video Modes BT 656 Mode The input clock source of 27 MHZ is used for the source clock of the video output see Figure 35 15 In BT 656 mode either channel of the input port on the VPIF is used as the actual input...

Page 1780: ...2 Video Output Clock 27 MHz DOUT 7 0 Video Output Data 7 0 Memory FIFO FIFO Memory Interface Memory Architecture www ti com 1780 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Video Port Interface VPIF Figure 35 15 Clock Control on Video Input and Output with SDTV Encoding ...

Page 1781: ...ster Configuration on BT 1120 1125 60 2 1 and 1250 50 2 1 System Input Output Unit Size Byte in unsigned Register Configuration on BT 1120 1125 60 2 1 and 1250 50 2 1 System Input Output Unit Size Byte in unsigned Parameter Register Bit Name NTSC PAL EAV2SAV CnHCFG EAV2SAV 272 376 SAV2EAV CnHCFG SAV2EAV 1920 1920 Vertical frame size CnVSIZE VSIZE 1125 1250 L1 CnVCFG0 L1 1 1 L3 CnVCFG0 L3 41 45 L5 ...

Page 1782: ...N 15 8 DOUT 15 8 Video Output Data C 7 0 CLKIN1 CLKIN3 CLKOUT3 Video Output Clock 74 25 MHz Video Reference Clock 74 25 MHz Memory Interface Memory Memory Interface Architecture www ti com 1782 SPRUH82C April 2013 Revised September 2016 Submit Documentation Feedback Copyright 2013 2016 Texas Instruments Incorporated Video Port Interface VPIF Figure 35 16 Clock Control on Video Input and Output wit...

Page 1783: ...module as in BT 656 and BT 1120 modes The video input clock source is 74 25 MHZ Two VPIFs are necessary to receive an input image and to display the output image The functional image and clock control is shown in Figure 35 17 In this case VPIF channels 0 and 1 are used for input and VPIF channels 2 and 3 are used for output Parameter Configuration for SMPTE 296M Mode The configuration for each reg...

Page 1784: ...n vertical image size register CnVSIZE However you still need to configure the storage memory address control related registers 35 3 Registers All register values should be configured before you set the CnEN bit in the channel n control register CnCTRL to 1 Also note that all register values except the CnEN bit in CnCTRL are detected by the first falling edge of the vertical synchronization signal...

Page 1785: ...tion 35 3 15 8Ch C1BCHROMA Channel 1 bottom field chrominance address register Section 35 3 16 90h C1THANC Channel 1 top field horizontal ancillary address register Section 35 3 17 94h C1BANC Channel 1 bottom field horizontal ancillary address register Section 35 3 18 98h C1TVANC Channel 1 top field vertical ancillary address register Section 35 3 19 9Ch C1BVANC Channel 1 bottom field vertical anc...

Page 1786: ...35 3 15 14Ch C3BCHROMA Channel 3 bottom field chrominance address register Section 35 3 16 150h C3THANC Channel 3 top field horizontal ancillary address register Section 35 3 17 154h C3BHANC Channel 3 bottom field horizontal ancillary address register Section 35 3 18 158h C3TVANC Channel 3 top field vertical ancillary address register Section 35 3 19 15Ch C3BVANC Channel 3 bottom field vertical an...

Page 1787: ...7 6 5 4 3 2 1 0 INTFRAME FID Reserved YCMUX CAPMODE Reserved CHANEN R W 0 R 0 R 0 R W 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 35 7 Channel 0 Control Register C0CTRL Field Descriptions Bit Field Value Description 31 CLKEDGE Clock edge control 0 Data is captured on rising edge of input clock 1 Data is captured on falling edge of input clock 30 Reserved 0 Reserve...

Page 1788: ...9 VANC Channel 0 vertical ancillary data enable Ancillary data is only supported for BT byte streams 0 Vertical ancillary data is disabled 1 Vertical ancillary data is enabled 8 HANC Channel 0 horizontal ancillary data enable Ancillary data is only supported for BT byte streams 0 Horizontal ancillary data is disabled 1 Horizontal ancillary data is enabled 7 6 INTFRAME 0 3h Channel 0 frame interrup...

Page 1789: ...Interlaced 1 Progressive 9 VANC Channel 1 vertical ancillary data enable Ancillary data is only supported for BT byte streams 0 Vertical ancillary data is disabled 1 Vertical ancillary data is enabled 8 HANC Channel 1 horizontal ancillary data enable Ancillary data is only supported for BT byte streams 0 Horizontal ancillary data is disabled 1 Horizontal ancillary data is enabled 7 6 INTFRAME 0 3h...

Page 1790: ...g edge of output clock The output clock controlled by the CLKEN bit will be inverted 30 15 Reserved 0 Reserved 14 CLIPANC Activates clipping function of output data in the blanking region for channel 2 0 Clipping in the blanking region for channel 2 is disabled 1 Clipping in the blanking region for channel 2 is enabled 0 is clipped to 1 FFh is clipped to FEh 13 CLIPVID Activates clipping function ...

Page 1791: ... V sync only 1h Bottom field V sync 2h Top and bottom field 3h Reserved 5 FID Channel 2 field identification This bit indicates the active field ID when the FRAME2 interrupt is asserted from the VPIF to CPU 0 Top field 1 Bottom field 4 Reserved 0 Reserved 3 YCMUX Channel 2 output data format 0 Channel 2 Y C non multiplexed mode 1 Channel 2 Y C multiplexed mode both Y and C are in the byte stream 2...

Page 1792: ...n of output data in the blanking region for channel 3 0 Clipping in the blanking region for channel 3 is disabled 1 Clipping in the blanking region for channel 3 is enabled 0 is clipped to 1 FFh is clipped to FEh 13 CLIPVID Activates clipping function of output data in the active region for channel 3 0 Clipping in the active region for channel 3 is disabled 1 Clipping in the active region for chan...

Page 1793: ...ME3 interrupt is asserted from the VPIF to CPU 0 Top field 1 Bottom field 4 Reserved 0 Reserved 3 YCMUX Channel 3 output data format 0 Channel 3 Y C non multiplexed mode 1 Channel 3 Y C multiplexed mode both Y and C are in the byte stream 2 Reserved 0 Reserved 1 CLKEN Clock output enable control for VPIF channel 3 This bit should be set before enabling the channel and it should be cleared after de...

Page 1794: ...FRAME3 Channel 3 frame interrupt enable Enables the frame interrupt from the VPIF to CPU 0 Channel 3 frame interrupt is disabled 1 Channel 3 frame interrupt is enabled The FRAME3 bit in the INTSET register must also be set to activate the FRAME3 interrupt 2 FRAME2 Channel 2 frame interrupt enable Enables the frame interrupt from the VPIF to CPU 0 Channel 2 frame interrupt is disabled 1 Channel 2 f...

Page 1795: ...5 12 Interrupt Enable Set Register INTSET Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 ERROR Error interrupt enable set 0 Interrupt on ERROR is masked write 0 has no effect 1 Interrupt on ERROR is activated 3 FRAME3 Channel 3 frame interrupt enable set 0 Interrupt on FRAME3 is masked write 0 has no effect 1 Interrupt on FRAME3 is activated 2 FRAME2 Channel 2 frame inte...

Page 1796: ...C Write 1 to Clear n value after reset Table 35 13 Interrupt Enable Clear Register INTCLR Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 ERROR Error interrupt enable clear 0 No change write 0 has no effect 1 Interrupt on ERROR is masked 3 FRAME3 Channel 3 frame interrupt enable clear 0 No change write 0 has no effect 1 Interrupt on FRAME3 is masked 2 FRAME2 Channel 2 fra...

Page 1797: ...ME3 Channel 3 frame interrupt status This bit is effective even if the FRAME3 bit in INTEN is disabled Use the INTSTATCLR register to clear the status 0 Frame sync on channel 3 not detected 1 Frame sync on channel 3 detected 2 FRAME2 Channel 2 frame interrupt status This bit is effective even if the FRAME2 bit in INTEN is disabled Use the INTSTATCLR register to clear the status 0 Frame sync on cha...

Page 1798: ... 0 W1C 0 W1C 0 W1C 0 W1C 0 LEGEND R Read only W1C Write 1 to Clear n value after reset Table 35 15 Interrupt Status Clear Register INTSTATCLR Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 ERROR Error interrupt status clear 0 No change 1 Clear ERROR bit in INTSTAT 3 FRAME3 Channel 3 frame interrupt status clear 0 No change 1 Clear FRAME3 bit in INTSTAT 2 FRAME2 Channel 2...

Page 1799: ...ved 0 Reserved 0 FREE Controls whether the peripheral responds to the emulation suspend signal 0 Respond to monitoring emulation suspend signal 1 Ignores any emulation suspend signal non stop 35 3 12 DMA Size Control Register REQSIZE The DMA size control register REQSIZE is shown in Figure 35 29 and described in Table 35 17 Figure 35 29 DMA Size Control Register REQSIZE 31 16 Reserved R 0 15 9 8 0...

Page 1800: ...ddress of the top field luminance buffer The register value points to the beginning of the buffer and the address must be a multiple of 8 CnTLUMA 2 0 0 35 3 14 Channel n Bottom Field Luminance Address Register CnBLUMA The Channel n Bottom Field Luminance Address Register CnBLUMA is shown in Figure 35 31 and described in Table 35 19 NOTE CnBLUMA registers are not used in progressive video mode C1BL...

Page 1801: ...ss of the top field chrominance buffer The register value points to the beginning of the buffer and the address must be a multiple of 8 CnTCHROMA 2 0 0 35 3 16 Channel n Bottom Field Chrominance Address Register CnBCHROMA The Channel n Bottom Field Chrominance Address Register CnBCHROMA is shown in Figure 35 33 and described in Table 35 21 NOTE CnBCHROMA registers are not used in progressive video...

Page 1802: ...e top field horizontal ancillary buffer The register value points to the beginning of the buffer and the address must be a multiple of 8 CnTHANC 2 0 0 35 3 18 Channel n Bottom Field Horizontal Ancillary Address Register CnBHANC The Channel n Bottom Field Horizontal Ancillary Address Register CnBHANC is shown in Figure 35 35 and described in Table 35 23 NOTE CnBHANC registers are not used in progre...

Page 1803: ...ical ancillary buffer The register value points to the beginning of the buffer and the address must be a multiple of 8 CnTVANC 2 0 0 35 3 20 Channel n Bottom Field Vertical Ancillary Address Register CnBVANC The Channel n Bottom Field Vertical Ancillary Address Register CnBVANC is shown in Figure 35 37 and described in Table 35 25 NOTE CnBVANC registers are not used in progressive video mode Figur...

Page 1804: ...if SDRAM storage mode is raster scanning format In sub picture mode this value is ignored For vertical ancillary data the address line offset value is automatically calculated by hardware with the configuration of the CnYC_MUX bit in CnCTRL In Y C mux mode the actual address offset is CnIMGOFFSET 2 In Y C separate mode the actual address offset is CnIMGOFFSET See Storage Format for more informatio...

Page 1805: ...umber of bytes in the active SAV2EAV and inactive EAV2SAV video regions In the BT YC mode Horizontal Distance in Y C Mode the video regions are delimited by the embedded EAV and SAV codes the region size does not include the 4 byte EAV and SAV codes In the CCD CMOS mode Horizontal Distance in CCD CMOS Mode the regions are delimited by the synchronous raw_h_valid capture signal Horizontal Distance ...

Page 1806: ...terlaced and Progressive Video 15 12 Reserved 0 Reserved 11 0 L3 0 FFFh Enumerated line number for the L3 field position see Interlaced and Progressive Video 35 3 25 Channel n Vertical Size Configuration 1 Register C0VCFG1 and C1VCFG1 The Channel n Vertical Size Configuration 1 Register CnVCFG1 is shown in Figure 35 42 and described in Table 35 30 Figure 35 42 Channel n Vertical Data Size Configur...

Page 1807: ...onfiguration 2 Register CnVCFG2 Field Descriptions Bit Field Value Description 31 28 Reserved 0 Reserved 27 16 L9 0 FFFh Enumerated line number for the L9 field position see Interlaced and Progressive Video 15 12 Reserved 0 Reserved 11 0 L11 0 FFFh Enumerated line number for the L11 field position see Interlaced and Progressive Video 35 3 27 Channel n Vertical Image Size Register C0VSIZE and C1VSI...

Page 1808: ...nd SAV codes the region size does not include the 4 byte EAV and SAV codes In the CCD CMOS mode Horizontal Distance in CCD CMOS Mode the regions are delimited by the synchronous raw_h_valid capture signal Figure 35 45 Channel n Horizontal Size Configuration Register CnHCFG 31 27 26 16 Reserved EAV2SAV R 0 R W 0 15 11 10 0 Reserved SAV2EAV R 0 R W 0 LEGEND R W Read Write R Read only n value after r...

Page 1809: ... Interlaced and Progressive Video 15 11 Reserved 0 Reserved 10 0 L3 0 7FFh Enumerated line number for the L3 field position see Interlaced and Progressive Video 35 3 30 Channel n Vertical Size Configuration 1 Register C2VCFG1 and C3VCFG1 The Channel n Vertical Size Configuration 1 Register CnVCFG1 is shown in Figure 35 47 and described in Table 35 35 Figure 35 47 Channel n Vertical Size Configurat...

Page 1810: ...figuration 2 Register CnVCFG2 Field Descriptions Bit Field Value Description 31 27 Reserved 0 Reserved 26 16 L9 0 7FFh Enumerated line number for the L9 field position see Interlaced and Progressive Video 15 11 Reserved 0 Reserved 10 0 L11 0 7FFh Enumerated line number for the L11 field position see Interlaced and Progressive Video 35 3 32 Channel n Vertical Image Size Register C2VSIZE and C3VSIZE...

Page 1811: ... 26 16 Reserved VPOS R 0 R W 0 15 11 10 0 Reserved HPOS R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 35 38 Channel n Top Field Horizontal Ancillary Position Register CnTHANCPOS Field Descriptions Bit Field Value Description 31 27 Reserved 0 Reserved 26 16 VPOS 0 7FFh Vertical position line count of valid data within the top field horizontal ancillary blanking region Line p...

Page 1812: ...e Register CnTHANCSIZE 31 27 26 16 Reserved VSIZE R 0 R W 0 15 11 10 0 Reserved HSIZE R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 35 39 Channel n Top Field Horizontal Ancillary Size Register CnTHANCSIZE Field Descriptions Bit Field Value Description 31 27 Reserved 0 Reserved 26 16 VSIZE 0 7FFh Vertical size line count of valid top field horizontal ancillary data beginning...

Page 1813: ... 26 16 Reserved VPOS R 0 R W 0 15 11 10 0 Reserved HPOS R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 35 40 Channel n Bottom Field Horizontal Ancillary Position Register CnBHANCPOS Field Descriptions Bit Field Value Description 31 27 Reserved 0 Reserved 26 16 VPOS 0 7FFh Vertical position line count of valid data within the bottom field horizontal ancillary blanking region ...

Page 1814: ...e Register CnBHANCSIZE 31 27 26 16 Reserved VSIZE R 0 R W 0 15 11 10 0 Reserved HSIZE R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 35 41 Channel n Bottom Field Horizontal Ancillary Size Register CnBHANCSIZE Field Descriptions Bit Field Value Description 31 27 Reserved 0 Reserved 26 16 VSIZE 0 7FFh Vertical size line count of valid bottom field horizontal ancillary data beg...

Page 1815: ... 26 16 Reserved VPOS R 0 R W 0 15 11 10 0 Reserved HPOS R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 35 42 Channel n Top Field Vertical Ancillary Position Register CnTVANCPOS Field Descriptions Bit Field Value Description 31 27 Reserved 0 Reserved 26 16 VPOS 0 7FFh Vertical position line count of valid data within the top field vertical ancillary blanking region Line posit...

Page 1816: ... Register CnTVANCSIZE 31 27 26 16 Reserved VSIZE R 0 R W 0 15 11 10 0 Reserved HSIZE R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 35 43 Channel n Top Field Vertical Ancillary Size Register CnTVANCSIZE Field Descriptions Bit Field Value Description 31 27 Reserved 0 Reserved 26 16 VSIZE 0 7FFh Vertical size line count of valid top field verticall ancillary data beginning at ...

Page 1817: ... 26 16 Reserved VPOS R 0 R W 0 15 11 10 0 Reserved HPOS R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 35 44 Channel n Bottom Field Vertical Ancillary Position Register CnBVANCPOS Field Descriptions Bit Field Value Description 31 27 Reserved 0 Reserved 26 16 VPOS 0 7FFh Vertical position line count of valid data within the bottom field vertical ancillary blanking region Line...

Page 1818: ... Register CnBVANCSIZE 31 27 26 16 Reserved VSIZE R 0 R W 0 15 11 10 0 Reserved HSIZE R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 35 45 Channel n Bottom Field Vertical Ancillary Size Register CnBVANCSIZE Field Descriptions Bit Field Value Description 31 27 Reserved 0 Reserved 26 16 VSIZE 0 7FFh Vertical size line count of valid bottom field verticall ancillary data beginni...

Page 1819: ... Texas Instruments Incorporated Revision History Revision History NOTE Page numbers for previous revisions may differ from page numbers in the current version Changes from July 10 2016 to September 12 2016 from B Revision July 2016 to C Revision Page Updated Chapter 13 entirely 315 Updated GMIIEN bit in Section 18 3 3 29 812 ...

Page 1820: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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